Solid-state imaging device and imaging apparatus

Abstract

A solid-state imaging device (200) according to the present application includes a light-receiving substrate (201), a circuit board (202), and a plurality of first connection portions (270). The light-receiving substrate (201) includes a plurality of light-receiving circuits (211) provided with photoelectric conversion elements. The circuit board (202) is directly joined with the light-receiving substrate (201) and includes a plurality of address event detection circuits (231) that respectively detect changes in voltage output from the photoelectric conversion elements of the plurality of light-receiving circuits (211). The plurality of first connection portions (270) are provided at a joining portion (203) between the light-receiving substrate (201) and the circuit board (202) to electrically connect the light-receiving circuits (211) and the address event detection circuits (231) corresponding to each other.

Description

Technical Field

[0001] This invention relates to solid-state imaging devices and imaging equipment. Background Technology

[0002] In recent years, an asynchronous solid-state imaging device has been proposed, in which an address event detection circuit is set in each pixel to detect in real time whether the light amount of the pixel has exceeded a threshold as an address event (for example, see Patent Document 1).

[0003] List of cited references

[0004] Patent documents

[0005] Patent Document 1: JP 2016-533140 W Summary of the Invention

[0006] The technical problem to be solved by the present invention

[0007] However, the aforementioned traditional technologies are insufficient to improve the resolution of such asynchronous solid-state imaging devices.

[0008] Therefore, the present invention proposes a solid-state imaging device and imaging equipment that can improve resolution.

[0009] Technical solutions to solve technical problems

[0010] According to the present invention, a solid-state imaging device is provided. The solid-state imaging device includes a light-receiving substrate, a circuit board, and a plurality of first connection portions. The light-receiving substrate includes a plurality of light-receiving circuits having photoelectric conversion elements disposed thereon. The circuit board is directly bonded to the light-receiving substrate and includes a plurality of address event detection circuits that respectively detect voltage changes output from the photoelectric conversion elements of the plurality of light-receiving circuits. The plurality of first connection portions are disposed at a joint between the light-receiving substrate and the circuit board to electrically connect corresponding light-receiving circuits and address event detection circuits. Attached Figure Description

[0011] Figure 1 This is a block diagram illustrating a construction example of a camera device according to an embodiment of the present invention.

[0012] Figure 2 This is a diagram illustrating the stacked structure of a solid-state imaging device according to an embodiment of the present invention.

[0013] Figure 3 This is a diagram illustrating the planar structure of a light-receiving substrate according to an embodiment of the present invention.

[0014] Figure 4 This is a diagram illustrating the planar structure of a circuit board according to an embodiment of the present invention.

[0015] Figure 5 This is a diagram illustrating the construction of effective pixels according to an embodiment of the present invention.

[0016] Figure 6 This is a diagram illustrating the circuit construction of an effective pixel according to an embodiment of the present invention.

[0017] Figure 7 This is a diagram illustrating the construction of effective pixels according to an embodiment of the present invention.

[0018] Figure 8 This is a diagram showing the cross-sectional structure of a solid-state imaging device according to an embodiment of the present invention.

[0019] Figure 9 This is a diagram illustrating the planar structure of a solid-state imaging device according to an embodiment of the present invention.

[0020] Figure 10 This is a plan view illustrating an example arrangement of the first connecting portion in the effective pixels according to an embodiment of the present invention.

[0021] Figure 11 This is a plan view showing another arrangement example of the first connecting portion in the effective pixels according to an embodiment of the present invention.

[0022] Figure 12 This is a plan view showing another arrangement example of the first connecting portion in the effective pixels according to an embodiment of the present invention.

[0023] Figure 13 This is a plan view showing an example of the arrangement of the through hole relative to the first connecting portion according to an embodiment of the present invention.

[0024] Figure 14 This is a plan view showing an example arrangement of a through hole relative to another first connection portion according to an embodiment of the present invention.

[0025] Figure 15 This is a plan view showing an example arrangement of a through hole relative to another first connection portion according to an embodiment of the present invention.

[0026] Figure 16 This is a plan view showing an example arrangement of a through hole relative to another first connection portion according to an embodiment of the present invention.

[0027] Figure 17 This is a plan view showing another example of the arrangement of the through hole relative to the first connecting portion according to an embodiment of the present invention.

[0028] Figure 18 A plan view is shown of another arrangement example of the through hole relative to the first connecting portion according to an embodiment of the present invention.

[0029] Figure 19 A plan view is shown of another arrangement example of the through hole relative to the first connecting portion according to an embodiment of the present invention.

[0030] Figure 20 A plan view is shown of another arrangement example of the through hole relative to the first connecting portion according to an embodiment of the present invention.

[0031] Figure 21 This is a diagram illustrating the circuit configuration of an effective pixel according to a first variation of an embodiment of the present invention.

[0032] Figure 22 This is a plan view showing an example of the arrangement of the first connecting portion and the second connecting portion in the effective pixels of a first modified embodiment of the present invention.

[0033] Figure 23 This is a plan view showing another arrangement example of the first connecting portion and the second connecting portion in the effective pixels of a first modified example according to an embodiment of the present invention.

[0034] Figure 24 This is a plan view showing another arrangement example of the first connecting portion and the second connecting portion in the effective pixels of a first modified example according to an embodiment of the present invention.

[0035] Figure 25 This is a diagram illustrating the circuit configuration of an effective pixel according to a second variation of an embodiment of the present invention.

[0036] Figure 26 This is a diagram illustrating the circuit structure of an effective pixel according to a third variation of an embodiment of the present invention.

[0037] Figure 27 This is a block diagram showing a second construction example of the address event detection unit.

[0038] Figure 28 This is a block diagram illustrating a construction example of a camera device according to a second construction example (i.e., a scanning camera device used as a camera device in a camera system employing the technology according to the invention).

[0039] Figure 29 This is a schematic diagram illustrating a construction example of a ranging system according to an embodiment of the present invention.

[0040] Figure 30 This is a block diagram illustrating an example of circuit construction. Detailed Implementation

[0041] In the following description, embodiments of the present invention will be detailed with reference to the accompanying drawings. Note that in the following embodiments, the same parts are indicated by the same reference numerals to omit repeated descriptions.

[0042] Synchronous solid-state cameras, which capture image data (frames) in sync with synchronization signals such as vertical sync signals, are already used in imaging equipment. Typical synchronous solid-state cameras can only acquire image data in each cycle of the synchronization signal (e.g., 1 / 60th of a second), making it difficult to respond to the high-speed processing requirements of related fields such as transportation and robotics.

[0043] Therefore, an asynchronous solid-state imaging device is proposed, wherein an address event detection circuit is set in each pixel to detect in real time whether the light intensity of the pixel has exceeded a threshold as an address event. In this solid-state imaging device, a photodiode and multiple transistors for detecting address events are arranged in each pixel.

[0044] However, the aforementioned conventional technology electrically connects each pixel and each address event detection circuit by forming through silicon vias (TSVs) around the pixel array, causing the area of ​​the TSV region to increase with the increase of the number of pixels.

[0045] In other words, while increasing the number of pixels in the pixel array section to improve the resolution of a solid-state imaging device, the area of ​​the TSV region in the device also increases, reducing the area where the pixel array section can be configured. Therefore, it is difficult to improve the resolution of the solid-state imaging device.

[0046] Therefore, it is desirable to develop a technology that can overcome the above problems and improve the resolution of solid-state imaging devices.

[0047] [Structure of camera equipment]

[0048] First, refer to Figure 1 The structure of the camera device 100 according to this embodiment is described. Figure 1 This is a block diagram illustrating a construction example of a camera device 100 according to an embodiment of the present invention.

[0049] The camera device 100 according to this embodiment includes a lens 110, a solid-state imaging device 200, a recording unit 120, and a control unit 130. The camera device 100 may be a camera mounted on a wearable device or a vehicle-mounted camera, etc.

[0050] Lens 110 captures incident light from the subject to form an image on the imaging surface of solid-state imaging device 200.

[0051] The solid-state imaging device 200, also known as a dynamic vision sensor (DVS), detects an address event as the absolute value of the brightness change of each pixel in a plurality of pixels exceeding a threshold. For example, address events include an on event indicating that the increase in brightness has exceeded an upper threshold and an off event indicating that the decrease in brightness has fallen below a lower threshold, where the lower threshold is less than the upper threshold.

[0052] Then, the solid-state imaging device 200 generates a detection signal for each pixel that indicates the detection result of an address event. Each detection signal includes a conduction event detection signal V indicating whether a conduction event exists. CH (Refer to Figure 6 ) and the cutoff event detection signal V indicating whether a cutoff event exists. CL (Refer to Figure 6 ).

[0053] The solid-state imaging device 200 performs predetermined signal processing, such as image recognition processing, on image data including detection signals in a signal processing unit (not shown), and outputs the processed data to the recording unit 120 via signal line 209.

[0054] Recording unit 120 records data from solid-state imaging device 200. Control unit 130 controls solid-state imaging device 200 to capture image data.

[0055] [Structure of solid-state imaging devices]

[0056] Next, we will refer to Figures 2 to 20 The structure of the solid-state imaging device 200 according to this embodiment is explained. Figure 2 This is a diagram illustrating the stacked structure of a solid-state imaging device 200 according to an embodiment of the present invention.

[0057] The solid-state imaging device 200 according to this embodiment includes a circuit board 202 and a light-receiving substrate 201 stacked on the circuit board 202. The light-receiving substrate 201 and the circuit board 202 are electrically connected by a connection such as a through-hole, Cu-Cu joint, or bump.

[0058] Figure 3 This is a diagram illustrating the planar structure of the light-receiving substrate 201 according to an embodiment of the present invention. Figure 3 As shown, the light receiving substrate 201 includes a light receiving part 210, a through hole placement part 221, and a through hole placement part 222.

[0059] In the light receiving unit 210, multiple light receiving circuits 211 are arranged in a two-dimensional grid pattern. Each light receiving circuit 211 performs photoelectric conversion on the incident light to generate a photocurrent, and converts the photocurrent current-voltage signal into an output voltage signal. Each light receiving circuit 211 is assigned a pixel address, including a row address and a column address.

[0060] A connection to the circuit board 202 is disposed in the through-hole mounting section 221 and through-hole mounting section 222 (see reference). Figure 4 ) through holes.

[0061] Figure 4 This is a diagram illustrating the planar structure of the circuit board 202 according to an embodiment of the present invention. (See diagram for example.) Figure 4 As shown, the circuit board 202 includes an address event detection unit 230, a signal processing circuit 240, a row driving circuit 251, a column driving circuit 252, a through-hole mounting portion 261, and a through-hole mounting portion 262.

[0062] In the address event detection unit 230, multiple address event detection circuits 231 are arranged in a two-dimensional grid pattern. The address event detection circuits 231 quantize the voltage signal from the optical receiving circuit 211 and output the quantized voltage signal as a detection signal.

[0063] Each address event detection circuit 231 is assigned a pixel address and is electrically connected to the light receiving circuit 211 with the same address. Furthermore, in this embodiment, the light receiving circuit 211 and the address event detection circuit 231 with the same address are arranged at the same location in the plan view.

[0064] The signal processing circuit 240 performs predetermined signal processing on the detection signal from the address event detection unit 230. For example, the signal processing circuit 240 arranges the detection signal as pixel signals into a two-dimensional grid pattern and acquires image data with two bits of information about each pixel. Then, the signal processing circuit 240 performs signal processing such as image recognition processing on the acquired image data.

[0065] Row driving circuit 251 selects a row address and causes address event detection unit 230 to output a detection signal corresponding to the selected row address. Column driving circuit 252 selects a column address and causes address event detection unit 230 to output a detection signal corresponding to the selected column address. Via mounting portions 261 and 262 are configured with connections to the light receiving substrate 201 (see reference 201). Figure 3 ) through holes.

[0066] Figure 5 This is a diagram illustrating the construction of the effective pixel 310 according to an embodiment of the present invention. (See diagram for example.) Figure 5As shown, each effective pixel 310 includes a light receiving circuit 211 in a light receiving substrate 201 with the same pixel address and an address event detection circuit 231 in a circuit board 202.

[0067] As described above, in the light receiving substrate 201 and the circuit board 202, a plurality of light receiving circuits 211 and a plurality of address event detection circuits 231 are arranged in a two-dimensional grid pattern. Furthermore, light receiving circuits 211 and address event detection circuits 231 with the same address are positioned at the same location in the plan view.

[0068] That is, in the solid-state imaging device 200 according to this embodiment, each of the effective pixels 310 including a pair of light receiving circuits 211 and an address event detection circuit 231 is arranged in a two-dimensional grid pattern.

[0069] Then, each pair of light receiving circuits 211 and address event detection circuits 231 are electrically connected through the first connection portion 270 provided at the joint portion 203 between the light receiving substrate 201 and the circuit board 202.

[0070] Figure 6 This is a diagram illustrating the circuit configuration of an effective pixel 310 according to an embodiment of the present invention. Figure 6 As shown, the effective pixel 310 includes a photodiode 311, a current-to-voltage conversion circuit 320, a buffer 330, a subtractor 340, a quantizer 350, and a transmission circuit 360.

[0071] In an embodiment of the present invention, the photodiode 311 in the effective pixel 310 component and the N-type transistors 321 and 322 in the current-to-voltage conversion circuit 320 are included in the light receiving circuit 211. Furthermore, the buffer 330, subtractor 340, quantizer 350, and transmission circuit 360 in the effective pixel 310 component are included in the address event detection circuit 231.

[0072] That is, in the embodiments of the present invention, the effective pixel 310 includes a photodiode 311, a current-to-voltage conversion circuit 320 and an address event detection circuit 231.

[0073] Photodiode 311 performs photoelectric conversion on incident light to generate photocurrent. Then, photodiode 311 provides the generated photocurrent to current-to-voltage conversion circuit 320.

[0074] The current-to-voltage conversion circuit 320 converts the photocurrent from the photodiode 311 into its logarithmic voltage signal. The current-to-voltage conversion circuit 320 then provides the converted voltage signal to the buffer 330.

[0075] The buffer 330 corrects the voltage signal sent from the current-to-voltage conversion circuit 320 and outputs the corrected signal to the subtractor 340. In the effective pixel 310 according to this embodiment, the buffer 330 can increase the driving force for driving subsequent stages and also enables noise isolation accompanying switching operations in subsequent stages.

[0076] Subtractor 340 calculates the change in the correction signal sent from buffer 330 through subtraction. Then, subtractor 340 provides the calculated change as a differential signal to quantizer 350.

[0077] The quantizer 350 converts (i.e., quantizes) the analog differential signal into a digital detection signal by comparing the differential signal with a predetermined threshold. According to this embodiment, the quantizer 350 compares the differential signal with each of an upper threshold and a lower threshold, and provides the comparison result as a two-bit detection signal to the transmission circuit 360.

[0078] The transmission circuit 360 transmits the detection signal to the signal processing circuit 240 based on the column drive signal from the column drive circuit 252.

[0079] The specific circuit structure of each component will be described below. The current-to-voltage conversion circuit 320 includes an N-type transistor 321, an N-type transistor 322, and a P-type transistor 323. For example, metal-oxide-semiconductor (MOS) transistors are used as the N-type transistor 321, N-type transistor 322, and P-type transistor 323.

[0080] The source of N-type transistor 321 is connected to the cathode of photodiode 311, and its drain is connected to the power supply voltage VDD terminal. The anode of photodiode 311 is connected to the ground potential terminal. P-type transistor 323 and N-type transistor 322 are connected in series between the power supply voltage VDD terminal and the ground potential terminal in this order.

[0081] The connection point between P-type transistor 323 and N-type transistor 322 is connected to the gate of N-type transistor 321 and the input terminal of buffer 330. The connection point between N-type transistor 321 and photodiode 311 is connected to the gate of N-type transistor 322. A predetermined bias voltage V is applied to the gate of P-type transistor 323. blog .

[0082] Then, the N-type transistor 321 converts the photocurrent generated by the photodiode 311 into a voltage between the gate and the source. The N-type transistor 322 amplifies the voltage between the gate, which is at a potential corresponding to the photocurrent, and the source, which is at a potential of ground, and outputs the amplified voltage from the drain.

[0083] In addition, the P-type transistor 323 will be based on the bias voltage V blog A constant current is supplied to the N-type transistor 322. Using this configuration, the current-to-voltage conversion circuit 320 converts the photocurrent from the photodiode 311 into a voltage signal.

[0084] Note that in the solid-state imaging device 200 according to this embodiment, photodiode 311, N-type transistor 321 and N-type transistor 322 are disposed in light receiving substrate 201, and P-type transistor 323 and its downstream circuitry are disposed in circuit board 202.

[0085] Figure 7 This is a diagram illustrating the construction of the effective pixel 310 according to an embodiment of the present invention. (See diagram for example.) Figure 7 As shown, photodiode 311 is embedded in the P-well region of light receiving substrate 201, and has the back gate of N-type transistor 321 and the back gate of N-type transistor 322 formed thereon.

[0086] A power supply voltage VDD is supplied to the drain of the N-type transistor 321. The potential of the P-well region (i.e., the anode of the photodiode 311) and the potential of the source of the N-type transistor 322 are ground potentials. Furthermore, a pixel separation section 410 (see reference) is formed in the dotted line portion. Figure 8 Separate the individual P-well regions of adjacent valid pixels 310.

[0087] Return to Figure 6 The buffer 330 includes P-type transistors 331 and 332. For example, MOS transistors may be used as P-type transistors 331 and 332.

[0088] P-type transistors 331 and 332 are connected in series between the power supply voltage VDD terminal and the ground potential terminal in this order. A predetermined bias voltage V is applied to the gate of P-type transistor 331. bsf The gate of the P-type transistor 332 is connected to the output terminal of the current-to-voltage conversion circuit 320.

[0089] Using this configuration, the buffer 330 outputs the corrected voltage signal from the connection point between P-type transistors 331 and 332 to the subtractor 340.

[0090] Subtractor 340 includes capacitor 341, P-type transistor 342, capacitor 343, P-type transistor 344, and N-type transistor 345. For example, MOS transistors are used as P-type transistor 342, P-type transistor 344, and N-type transistor 345.

[0091] P-type transistor 344 and N-type transistor 345 are connected in series between the power supply voltage VDD terminal and the reference potential terminal in this order. A predetermined bias voltage V is applied to the gate of N-type transistor 345. ba .

[0092] When the gate of the P-type transistor 344 is used as the input terminal and the connection point between the P-type transistor 344 and the N-type transistor 345 is used as the output terminal, the P-type transistor 344 and the N-type transistor 345 are used as an inverter to invert the input signal and output it.

[0093] One end of capacitor 341 is connected to the output terminal of buffer 330, and the other end is connected to the input terminal of inverter (i.e., the gate of P-type transistor 344). One end of capacitor 343 is connected to the input terminal of inverter, and the other end is connected to the output terminal of inverter (i.e., the connection point between P-type transistor 344 and N-type transistor 345).

[0094] P-type transistor 342 opens and closes the path connecting the two ends of capacitor 343 according to the row drive signal output from row drive circuit 251.

[0095] When the P-type transistor 342 is turned on, the voltage signal V init The input is given to the buffer 330 side of capacitor 341, and its opposite side becomes a virtual ground terminal. For convenience, the potential of the virtual ground terminal is taken as zero.

[0096] At this time, the charge Q accumulated in capacitor 341 init It is represented by the following equation (1), where C1 is the capacitance of capacitor 341. On the other hand, the two ends of capacitor 343 are short-circuited, so its accumulated charge is zero.

[0097] Q init =C1×V init …(1)

[0098] Next, consider that P-type transistor 342 is turned off and the voltage on the buffer 330 side of capacitor 341 becomes V. after In this case, the charge Q accumulated in capacitor 341 after It is represented by the following formula (2).

[0099] Q after =C1×V after ...(2)

[0100] On the other hand, the charge Q2 accumulated in capacitor 343 is represented by the following equation (3), where C2 is the capacitance of capacitor 343, and V out It is the output voltage.

[0101] Q2=-C2×V out ...(3)

[0102] At this time, since the total charge in capacitors 341 and 343 remains unchanged, the following equation (4) holds true.

[0103] Q init =Q after +Q2...(4)

[0104] Then, by substituting equations (1) to (3) into equation (4) to transform the equation, we obtain equation (5).

[0105] V out =-(C1 / C2)×(V) after -V init (5)

[0106] Equation (5) above represents the voltage signal subtraction operation. The gain of the subtraction result is C1 / C2. It is generally desirable to maximize the gain. Therefore, it is preferable to design capacitor C1 to be larger and capacitor C2 to be smaller. On the other hand, if capacitor C2 is too small, it will increase kTC noise and degrade the noise characteristics. Therefore, the capacitance of capacitor C2 is limited to within an acceptable range for noise.

[0107] Furthermore, since the subtractor 340 is installed in each effective pixel 310, capacitors C1 and C2 have area limitations. In view of these limitations, for example, capacitor C1 is set to a value of 20 to 200 nanofarads (fF), and capacitor C2 is set to a value of 1 to 20 nanofarads (fF).

[0108] The quantizer 350 includes a P-type transistor 351, an N-type transistor 352, a P-type transistor 353, and an N-type transistor 354. For example, MOS transistors can be used as P-type transistor 351, N-type transistor 352, P-type transistor 353, and N-type transistor 354.

[0109] P-type transistor 351 and N-type transistor 352 are connected in series in this order between the power supply voltage VDD terminal and the ground potential terminal. P-type transistor 353 and N-type transistor 354 are connected in series in this order between the power supply voltage VDD terminal and the reference potential terminal.

[0110] Furthermore, the gates of P-type transistor 351 and P-type transistor 353 are connected to the output terminal of subtractor 340. A bias voltage V representing the upper threshold is applied to the gate of N-type transistor 352. bon A bias voltage V representing the lower threshold is applied to the gate of the N-type transistor 354. boff .

[0111] The connection point between P-type transistor 351 and N-type transistor 352 is connected to the transmission circuit 360. In the quantizer 350, the voltage at this connection point is used as the conduction event detection signal V. CH Output to transmission circuit 360.

[0112] The connection point between P-type transistor 353 and N-type transistor 354 is connected to the transmission circuit 360. In the quantizer 350, the voltage at this connection point is used as the cutoff event detection signal V. CL Output.

[0113] Using this configuration, the quantizer 350 outputs a high-level conduction event detection signal V when the differential signal has exceeded the upper threshold. CH Furthermore, it outputs a low-level cutoff event detection signal V when the differential signal has fallen below the lower threshold. CL That is, the solid-state imaging device 200 according to this embodiment can simultaneously detect the presence of both a conduction event and a cutoff event.

[0114] Figure 8 This is a diagram showing the cross-sectional structure of a solid-state imaging device 200 according to an embodiment of the present invention, and mainly showing the cross-sectional structure of the peripheral portion of the solid-state imaging device 200. Figure 8 As shown, the solid-state imaging device 200 includes an effective pixel area R1, a dummy pixel area R2, a power supply area R3, and a pad area R4.

[0115] The effective pixel region R1 is the area where stacked light receiving units 210 and address event detection units 230 are provided. In the effective pixel region R1, a plurality of effective pixels 310 are arranged in a two-dimensional grid pattern.

[0116] like Figure 9 As shown, the dummy pixel region R2 is the region set around the effective pixel region R1. Figure 9 This is a diagram showing the planar structure of a solid-state imaging device 200 according to an embodiment of the present invention.

[0117] In addition, such as Figure 8 As shown, multiple dummy pixels 310A are arranged side by side in the dummy pixel region R2. The dummy pixels 310A have the same basic structure as the active pixels 310, but are pixels that do not output signals to the outside.

[0118] Therefore, the solid-state imaging device 200 according to this embodiment, which forms a dummy pixel region R2 around the effective pixel region R1, can provide regularity in processing from the center to the edge of the effective pixel region R1. Thus, this embodiment can improve the manufacturing yield of the solid-state imaging device 200.

[0119] like Figure 9As shown, the power supply region R3 is the area surrounding the dummy pixel region R2. The power supply region R3 includes a grounding line 421 for which a ground potential is applied from the outside, a power supply line 422 for which a power supply voltage VDD is applied from the outside, and a substrate voltage VDD for which a substrate voltage VDD is applied from the outside. SUB Power supply wiring 423. For example, ground wiring 421, power supply wiring 422 and power supply wiring 423 are formed in a ring shape around the dummy pixel area R2.

[0120] Grounding wiring 421 supplies ground potential to multiple effective pixels 310, etc. Power wiring 422 supplies power supply voltage VDD to multiple effective pixels 310, etc. Power wiring 423 supplies substrate voltage V having the same potential as the power supply voltage VDD. SUB The area supplied to the solid-state imaging device 200 excluding the effective pixel area R1 and the dummy pixel area R2.

[0121] Therefore, for example, even when the power supply voltage VDD changes during the operation of the effective pixel 310, the solid-state imaging device 200, in which the power supply lines 423 and 422 are separately arranged according to this embodiment, can still supply a stable substrate voltage V to the peripheral portion of the solid-state imaging device 200. SUB Therefore, this implementation scheme enables the solid-state camera device 200 to operate stably.

[0122] Return to Figure 8 The following explanation is provided. The pad area R4 is the area surrounding the power supply area R3 and includes a contact hole 424 and a bonding pad 425. The contact hole 424 is formed along the thickness direction of the light receiving substrate 201 and the circuit board 202 from the light incident side surface of the light receiving substrate 201 to the middle of the circuit board 202.

[0123] A bonding pad 425 is provided at the bottom of the contact hole 424. In this embodiment, bonding wires, etc., are bonded to the bonding pad 425 through the contact hole 424 to connect the recording unit 120 (see reference 124). Figure 1 ) or control unit 130 (refer to Figure 1 It is electrically connected to the components of the solid-state camera device 200.

[0124] Reference Figure 8 The structure of the effective pixel 310 arranged in the effective pixel region R1 is further explained. The solid-state imaging device 200 includes a stacked light receiving substrate 201 and a circuit board 202, and a joint portion 203 is provided at the interface between the light receiving substrate 201 and the circuit board 202.

[0125] The light-receiving substrate 201 includes a semiconductor layer 201a and an insulating layer 201b. The semiconductor layer 201a contains a semiconductor material such as silicon. In the semiconductor layer 201a, photodiodes 311 and N-type transistors 321 (see reference 201b) are formed in each effective pixel 310 and each dummy pixel 310A. Figure 7 ), N-type transistor 322 (reference) Figure 7 )wait.

[0126] Furthermore, in semiconductor layer 201a, pixel separation section 410 is formed to separate adjacent active pixels 310 and dummy pixels 310A. Pixel separation section 410 electrically and optically separates adjacent active pixels 310 and dummy pixels 310A.

[0127] For example, the pixel separation portion 410 is formed to surround the effective pixel 310 and the dummy pixel 310A respectively and penetrate the semiconductor layer 201a.

[0128] A planarization film 411 is formed on the light-incident side surface of the semiconductor layer 201a. An on-chip lens 412 is formed on the light-incident side surface of the planarization film 411. The planarization film 411 planarizes the surface on which the on-chip lens 412 is mounted.

[0129] For example, on-chip lenses 412 are respectively disposed in effective pixels 310 and dummy pixels 310A to concentrate incident light onto effective pixels 310 and dummy pixels 310A.

[0130] Insulating layer 201b contains materials such as silicon oxide (SiO2). x Insulating materials such as silicon nitride (SiN) or silicon oxynitride (SiON) are disposed on the surface of the semiconductor layer 201a opposite to the light incident side.

[0131] Furthermore, a wiring portion 401, including a wiring layer and through holes, is formed in the insulating layer 201b. Figure 6 In the wiring configuration shown, each wiring section 401 is electrically connected to a photodiode 311, an N-type transistor 321, and an N-type transistor 322 disposed in the semiconductor layer 201a.

[0132] Wiring section 401 is electrically connected to first pad 403 through through hole 402. First pad 403 is configured to be exposed on the surface of light receiving substrate 201 opposite to the light incident side surface (i.e., the interface with circuit board 202) and contains copper or copper alloy.

[0133] The circuit board 202 has an insulating layer 202a at the interface with the light receiving substrate 201. The insulating layer 202a contains an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0134] Furthermore, the insulating layer 202a includes a second pad 404. The second pad 404 is configured to be exposed on the light incident side surface of the circuit board 202 (i.e., the interface with the light receiving substrate 201) and comprises copper or a copper alloy.

[0135] The second pad 404 is electrically connected to the wiring section 406 via a through-hole 405. Each wiring section 406 is electrically connected to a P-type transistor 332 (see reference). Figure 6 The gate of the P-type transistor 323 (see reference) Figure 6 The source pole of ).

[0136] Here, in this implementation scheme, as Figure 8 As shown, the first pad 403 and the second pad 404 are directly bonded together via Cu-Cu bonding. That is, each effective pixel 310 according to this embodiment includes a first connection portion 270 having a first pad 403 and a second pad 404. Therefore, in this embodiment, each effective pixel 310 is provided with a first connection portion 270.

[0137] Similarly, Figure 5 As shown, each first connection portion 270 is disposed at the joint portion 203 between the light receiving substrate 201 and the circuit board 202, and electrically connects the light receiving circuit 211 and the address event detection circuit 231 belonging to the same effective pixel 310.

[0138] As described above, in this embodiment, all the light receiving circuits 211 and the address event detection circuits 231 are electrically connected through the first connection portion 270 formed by Cu-Cu bonding.

[0139] This can reduce the need for through-hole mounting sections 221, 222, 261 and 262 (see reference). Figure 3 and Figure 4 The number of wiring connections required at the location can be reduced, thus reducing the area of ​​the through-hole mounting sections 221, 222, 261, and 262.

[0140] Therefore, this embodiment enables additional effective pixels 310 to be configured in the area created by reducing the size of the through-hole mounting portions 221, 222, 261 and 262, thereby improving the resolution of the solid-state imaging device 200.

[0141] Furthermore, the embodiment in which the light receiving circuit 211 and the address event detection circuit 231 are electrically connected by a first connection portion 270 formed by Cu-Cu bonding can thus reduce the resistance between the light receiving circuit 211 and the address event detection circuit 231.

[0142] Therefore, the signal related to the brightness change of the light incident on the photodiode 311 of the light receiving circuit 211 can be transmitted to the address event detection circuit 231 at high speed. Thus, this embodiment enables the asynchronous solid-state imaging device 200 to perform faster processing.

[0143] Furthermore, in this implementation scheme, such as Figure 8 As shown, each of the first connection portions 270 is preferably located between the corresponding optical receiving circuit 211 and address event detection circuit 231. Therefore, the optical receiving circuit 211 and address event detection circuit 231 can be electrically connected by the first connection portions 270 over a shorter distance.

[0144] That is, the embodiment in which the first connection portion 270 is arranged between the corresponding optical receiving circuit 211 and address event detection circuit 231 can thus reduce the resistance between the optical receiving circuit 211 and address event detection circuit 231.

[0145] Therefore, according to this embodiment, the signal detected by the photodiode 311 of the light receiving circuit 211 can be transmitted to the address event detection circuit 231 at high speed, so the asynchronous solid-state imaging device 200 can perform faster processing.

[0146] Furthermore, in this embodiment, the first pad 403 and the second pad 404 constituting the first connection portion 270 preferably contain the same material (e.g., Cu or Cu alloy). This makes it possible to form the first connection portion 270 by direct bonding such as Cu-Cu bonding, thus enabling the formation of multiple first connection portions 270 in the solid-state imaging device 200 in a single process step.

[0147] Therefore, this implementation scheme enables a shorter manufacturing process for the solid-state camera device 200.

[0148] Figure 10 This is a plan view illustrating an example arrangement of the first connecting portion 270 in the effective pixels 310 according to an embodiment of the present invention. Note that, for ease of understanding, in Figures 10 to 12 The first connecting part 270 is shown in a circular shape.

[0149] like Figure 10 As shown, the pixel separation section 410 is configured to separate adjacent valid pixels 310 from each other. Then, in Figure 10 In the example, the first connecting portion 270-1 belonging to the effective pixel 310-1 is placed on the effective pixel 310-1 in the plan view, without overlapping with the pixel separation portion 410 that contacts the effective pixel 310-1.

[0150] Furthermore, the N-type transistor 321-1 belonging to the effective pixel 310-1 is positioned in the plan view at the location where the effective pixel 310-1 and the first connecting portion 270-1 overlap. Additionally, the N-type transistor 322-1 belonging to the effective pixel 310-1 is positioned in the plan view from the location where the effective pixel 310-1 and the first connecting portion 270-1 overlap to the location where only the effective pixel 310-1 is located.

[0151] Similarly, in Figure 10 In the example, the first connecting portion 270-2 belonging to the effective pixel 310-2 is placed on the effective pixel 310-2 in the plan view, without overlapping with the pixel separation portion 410 that contacts the effective pixel 310-2.

[0152] Furthermore, the N-type transistor 321-2 belonging to the effective pixel 310-2 is positioned in the plan view at the location where the effective pixel 310-2 and the first connecting portion 270-2 overlap. Additionally, the N-type transistor 322-2 belonging to the effective pixel 310-2 is positioned in the plan view from the location where the effective pixel 310-2 and the first connecting portion 270-2 overlap to the location where only the effective pixel 310-2 is located.

[0153] Furthermore, the first connecting portion 270-3 belonging to the effective pixel 310-3 is placed on the effective pixel 310-3 in the plan view, without overlapping with the pixel separation portion 410 that contacts the effective pixel 310-3.

[0154] Furthermore, the N-type transistor 321-3 belonging to the effective pixel 310-3 is positioned in the plan view at the location where the effective pixel 310-3 and the first connecting portion 270-3 overlap. Additionally, the N-type transistor 322-3 belonging to the effective pixel 310-3 is positioned in the plan view from the location where the effective pixel 310-3 and the first connecting portion 270-3 overlap to the location where only the effective pixel 310-3 is located.

[0155] Furthermore, the first connecting portion 270-4 belonging to the effective pixel 310-4 is placed on the effective pixel 310-4 in the plan view, without overlapping with the pixel separation portion 410 that contacts the effective pixel 310-4.

[0156] Furthermore, the N-type transistor 321-4 belonging to the effective pixel 310-4 is positioned in the plan view at the location where the effective pixel 310-4 and the first connecting portion 270-4 overlap. Additionally, the N-type transistor 322-4 belonging to the effective pixel 310-4 is positioned in the plan view from the location where the effective pixel 310-4 and the first connecting portion 270-4 overlap to the location where only the effective pixel 310-4 is located.

[0157] Note that the arrangement of the first connecting portion 270 in the effective pixels 310 is not limited to... Figure 10 Examples. Figure 11 This is a plan view showing another arrangement example of the first connecting portion 270 in the effective pixel 310 according to an embodiment of the present invention.

[0158] exist Figure 11 In the example, the first connecting portion 270-1 belonging to the effective pixel 310-1 is arranged in the plan view to overlap with one side of the effective pixel 310-1 (the side on the left in the figure) and also overlap with the pixel separation portion 410 that contacts the effective pixel 310-1 on that side.

[0159] Furthermore, the N-type transistor 321-1 belonging to the effective pixel 310-1 is positioned in the plan view at the location where the effective pixel 310-1 and the first connecting portion 270-1 overlap. Additionally, the N-type transistor 322-1 belonging to the effective pixel 310-1 is positioned in the plan view from the location where the effective pixel 310-1 and the first connecting portion 270-1 overlap to the location where only the effective pixel 310-1 is located.

[0160] Similarly, in Figure 11 In the example, the first connecting portion 270-2 belonging to the effective pixel 310-2 is arranged in the plan view to overlap with one side of the effective pixel 310-2 (the side on the left in the figure) and also overlap with the pixel separation portion 410 that contacts the effective pixel 310-2 on that side.

[0161] Furthermore, the N-type transistor 321-2 belonging to the effective pixel 310-2 is positioned in the plan view at the location where the effective pixel 310-2 and the first connecting portion 270-2 overlap. Additionally, the N-type transistor 322-2 belonging to the effective pixel 310-2 is positioned in the plan view from the location where the effective pixel 310-2 and the first connecting portion 270-2 overlap to the location where only the effective pixel 310-2 is located.

[0162] In addition, Figure 11 In the example, the first connecting portion 270-3 belonging to the effective pixel 310-3 is arranged in the plan view to overlap with one side of the effective pixel 310-3 (the side on the left in the figure) and also overlap with the pixel separation portion 410 that contacts the effective pixel 310-3.

[0163] Furthermore, the N-type transistor 321-3 belonging to the effective pixel 310-3 is positioned in the plan view at the location where the effective pixel 310-3 and the first connecting portion 270-3 overlap. Additionally, the N-type transistor 322-3 belonging to the effective pixel 310-3 is positioned in the plan view from the location where the effective pixel 310-3 and the first connecting portion 270-3 overlap to the location where only the effective pixel 310-3 is located.

[0164] In addition, Figure 11 In the example, the first connecting portion 270-4 belonging to the effective pixel 310-4 is arranged in the plan view to overlap with one side of the effective pixel 310-4 (the side on the left in the figure) and also overlap with the pixel separation portion 410 that contacts the effective pixel 310-4 on that side.

[0165] Furthermore, the N-type transistor 321-4 belonging to the effective pixel 310-4 is positioned in the plan view at the location where the effective pixel 310-4 and the first connecting portion 270-4 overlap. Additionally, the N-type transistor 322-4 belonging to the effective pixel 310-4 is positioned in the plan view from the location where the effective pixel 310-4 and the first connecting portion 270-4 overlap to the location where only the effective pixel 310-4 is located.

[0166] Figure 12 This is a plan view illustrating another arrangement example of the first connecting portion 270 in the effective pixels 310 according to an embodiment of the present invention. Figure 12 In the example, the first connecting portion 270-1 belonging to the effective pixel 310-1 is arranged in the plan view to overlap with the corner of the effective pixel 310-1 (the upper left corner in the figure), and also overlaps with the pixel separation portion 410 that contacts the corner of the effective pixel 310-1.

[0167] Furthermore, the N-type transistor 321-1 belonging to the effective pixel 310-1 is positioned in the plan view at the location where the effective pixel 310-1 and the first connecting portion 270-1 overlap. Additionally, the N-type transistor 322-1 belonging to the effective pixel 310-1 is positioned in the plan view from the location where the effective pixel 310-1 and the first connecting portion 270-1 overlap to the location where only the effective pixel 310-1 is located.

[0168] Similarly, in Figure 12 In the example, the first connecting portion 270-2 belonging to the effective pixel 310-2 is arranged in the plan view to overlap with the corner of the effective pixel 310-2 (the upper left corner in the figure), and also overlaps with the pixel separation portion 410 that contacts the corner of the effective pixel 310-2.

[0169] Furthermore, the N-type transistor 321-2 belonging to the effective pixel 310-2 is positioned in the plan view at the location where the effective pixel 310-2 and the first connecting portion 270-2 overlap. Additionally, the N-type transistor 322-2 belonging to the effective pixel 310-2 is positioned in the plan view from the location where the effective pixel 310-2 and the first connecting portion 270-2 overlap to the location where only the effective pixel 310-2 is located.

[0170] Furthermore, the first connecting portion 270-3 belonging to the effective pixel 310-3 is arranged in the plan view to overlap with the corner of the effective pixel 310-3 (the upper left corner in the figure), and also overlaps with the pixel separation portion 410 that contacts the corner of the effective pixel 310-3.

[0171] Furthermore, the N-type transistor 321-3 belonging to the effective pixel 310-3 is positioned in the plan view at the location where the effective pixel 310-3 and the first connecting portion 270-3 overlap. Additionally, the N-type transistor 322-3 belonging to the effective pixel 310-3 is positioned in the plan view from the location where the effective pixel 310-3 and the first connecting portion 270-3 overlap to the location where only the effective pixel 310-3 is located.

[0172] Furthermore, the first connecting portion 270-4 belonging to the effective pixel 310-4 is arranged in the plan view to overlap with the corner of the effective pixel 310-4 (the upper left corner in the figure), and also overlaps with the pixel separation portion 410 that contacts the corner of the effective pixel 310-4.

[0173] Furthermore, the N-type transistor 321-4 belonging to the effective pixel 310-4 is positioned in the plan view at the location where the effective pixel 310-4 and the first connecting portion 270-4 overlap. Additionally, the N-type transistor 322-4 belonging to the effective pixel 310-4 is positioned in the plan view from the location where the effective pixel 310-4 and the first connecting portion 270-4 overlap to the location where only the effective pixel 310-4 is located.

[0174] Figure 13 This is a plan view showing an example arrangement of through holes 402 and 405 relative to the first connecting portion 270 according to an embodiment of the present invention. Figure 13 As shown, the first connecting portion 270 according to this embodiment has a rectangular shape in the plan view. Then, in Figure 13 In the example, two through holes 402 and two through holes 405 are connected to the first connecting portion 270 of the rectangle.

[0175] By connecting the two vias 402 and the two vias 405 to a single first connection 270 in this manner, the resistance between the light receiving circuit 211 and the address event detection circuit 231 can be reduced.

[0176] Therefore, according to this embodiment, the signal detected by the photodiode 311 of the light receiving circuit 211 can be transmitted to the address event detection circuit 231 at high speed, enabling the asynchronous solid-state imaging device 200 to perform faster processing.

[0177] Note that in Figure 13The example has already illustrated an instance in which through holes 402 and 405 are arranged to overlap each other in the plan view, but through holes 402 and 405 may not be arranged to overlap each other in the plan view.

[0178] Furthermore, the planar shape of the first connecting portion 270 according to this embodiment is not limited to a rectangular shape. Figure 14 This is a plan view showing an example arrangement of through holes 402 and 405 relative to another first connection portion 270 according to an embodiment of the present invention.

[0179] exist Figure 14 In the example, the first connecting portion 270 has a circular shape in the plan view. Then, two through holes 402 and two through holes 405 are connected to the circular first connecting portion 270. Note that in... Figure 14 In the example, the planar shape of the first connecting part 270 can be elliptical.

[0180] Figure 15 This is a plan view showing an example arrangement of through holes 402 and 405 relative to another first connecting portion 270 according to an embodiment of the present invention. Figure 15 In the example, the first connecting portion 270 has a hexagonal shape in the plan view. Then, two through holes 402 and two through holes 405 are connected to the hexagonal first connecting portion 270.

[0181] exist Figure 15 In the example, by forming the first connecting portion 270 into a hexagonal shape, the first connecting portion 270 can be arranged in a dense state at the joint portion 203.

[0182] Figure 16 This is a plan view showing an example arrangement of through holes 402 and 405 relative to another first connecting portion 270 according to an embodiment of the present invention. Figure 16 In the example, the first connecting portion 270 has an octagonal shape in the plan view. Then, two through holes 402 and two through holes 405 are connected to the octagonal first connecting portion 270.

[0183] Furthermore, the number of through holes 402 and 405 connected to the first connection portion 270 according to this embodiment is not limited to two. Figure 17 This is a plan view showing another arrangement example of through holes 402 and 405 relative to the first connecting portion 270 according to an embodiment of the present invention.

[0184] exist Figure 17 In the example, the first connecting portion 270 has a rectangular shape in the plan view. Then, a through hole 402 and a through hole 405 are connected to the rectangular first connecting portion 270. Note that in... Figure 17In the example, the planar shape of the first connecting part 270 can be a circular shape, an elliptical shape, a hexagonal shape, or an octagonal shape, etc.

[0185] Figure 18 This is a plan view showing another arrangement example of through holes 402 and 405 relative to the first connecting portion 270 according to an embodiment of the present invention. Figure 18 In the example, the first connecting part 270 has a rectangular shape in the plan view.

[0186] Then, four through holes 402 and four through holes 405 are connected to the first connecting portion 270 of the rectangle. Note that in Figure 18 In the example, the planar shape of the first connecting part 270 can be a circular shape, an elliptical shape, a hexagonal shape, or an octagonal shape, etc.

[0187] Figure 19 This is a plan view showing another arrangement example of through holes 402 and 405 relative to the first connecting portion 270 according to an embodiment of the present invention. Figure 19 In the example, the first connecting part 270 has a rectangular shape in the plan view.

[0188] Then, five through holes 402 and five through holes 405 are connected to the first connecting portion 270 of the rectangle. Note that in Figure 19 In the example, the planar shape of the first connecting part 270 can be a circular shape, an elliptical shape, a hexagonal shape, or an octagonal shape, etc.

[0189] Note that in Figures 13 to 19 The example already illustrates an example of the same number of through holes 402 and through holes 405 being connected to a first connection part 270, but different numbers of through holes 402 and through holes 405 can also be connected to a first connection part 270.

[0190] In addition, Figures 13 to 19 The example has shown that the planar shape of through hole 402 and through hole 405 is rectangular, but the planar shape of through hole 402 and through hole 405 is not limited to rectangular shape.

[0191] Figure 20 This is a plan view showing another example of the arrangement of through holes 402 and 405 relative to the first connecting portion 270 according to an embodiment of the present invention. Figure 20 As shown, through holes 402 and 405, which have a circular planar shape, can be connected to a first connecting part 270.

[0192] [Various variations]

[0193] Next, we will refer to Figures 21 to 26 Explain various variations of the implementation plan. Figure 21 This is a diagram illustrating the circuit configuration of an effective pixel 310 according to a first variation of an embodiment of the present invention. Note that in the various variations below, components downstream of the buffer 330 in the address event detection circuit 231 are not shown.

[0194] like Figure 21 As shown, the first modified example differs from the implementation scheme in that a grayscale acquisition circuit 370 is provided in each effective pixel 310. The grayscale acquisition circuit 370 is connected to the drain of the N-type transistor 321 in the current-to-voltage conversion circuit 320 via the second connection portion 371.

[0195] Therefore, the solid-state imaging device 200 according to the first modification can obtain the absolute value of the brightness of the effective pixel 310 (i.e., the gray level of the effective pixel 310) by using the gray level acquisition circuit 370 to detect the amount of current flowing through the N-type transistor 321.

[0196] That is, the solid-state imaging device 200 according to the first modification can detect that the absolute value of the brightness change of each of the multiple pixels has exceeded a threshold as an address event, and can also obtain the grayscale of each of the multiple pixels.

[0197] Here, in the first variation, the light receiving circuit 211 and the grayscale acquisition circuit 370 belonging to the same effective pixel 310 are electrically connected by a second connection portion 371 provided at the joint 203 between the light receiving substrate 201 and the circuit board 202. The second connection portion 371 includes a first pad and a second pad (not shown).

[0198] The first pad is configured to be exposed on the surface of the light receiving substrate 201 opposite to the light incident side surface (i.e., the interface with the circuit board 202), and contains copper or a copper alloy. Furthermore, the second pad is configured to be exposed on the light incident side surface of the circuit board 202 (i.e., the interface with the light receiving substrate 201), and contains copper or a copper alloy.

[0199] In the first variation, the first pad and the second pad are directly joined together by Cu-Cu bonding to form the second connection portion 371. Then, in the first variation, each effective pixel 310 is provided with a second connection portion 371.

[0200] Therefore, in the first modified example, all the light receiving circuits 211 and grayscale acquisition circuits 370 are electrically connected by the second connection portion 371 formed by Cu-Cu bonding.

[0201] This can reduce the need for through-hole mounting sections 221, 222, 261 and 262 (see reference). Figure 3 and Figure 4The number of wiring connections required at the location can be reduced, thus reducing the area of ​​the through-hole mounting sections 221, 222, 261, and 262.

[0202] Therefore, the first modification enables additional effective pixels 310 to be arranged in the area created by reducing the size of the through-hole mounting portions 221, 222, 261 and 262, thereby improving the resolution of the solid-state imaging device 200.

[0203] Furthermore, in the first variant in which the light receiving circuit 211 and the grayscale acquisition circuit 370 are electrically connected by a second connection portion 371 formed by Cu-Cu bonding, the resistance between the light receiving circuit 211 and the grayscale acquisition circuit 370 can be reduced.

[0204] Therefore, the signal related to the brightness of the light incident on the photodiode 311 of the light receiving circuit 211 can be transmitted to the grayscale acquisition circuit 370 at high speed. Thus, the first modification enables the asynchronous solid-state imaging device 200 to perform faster processing.

[0205] Figure 22 This is a plan view illustrating an example arrangement of the first connecting portion 270 and the second connecting portion 371 in the effective pixels 310 according to a first modified embodiment of the present invention. Note that, for ease of understanding, in Figures 22 to 24 The first connecting portion 270 and the second connecting portion 371 are shown in a circular shape.

[0206] exist Figure 22 In the example, the first connecting portion 270-1 belonging to the effective pixel 310-1 is arranged in the plan view to overlap with one side of the effective pixel 310-1 (the side on the left in the figure), and also overlaps with the pixel separation portion 410 that contacts the effective pixel 310-1 on that side.

[0207] Furthermore, the second connecting portion 371-1 belonging to the effective pixel 310-1 is arranged in the plan view to overlap with the other side (the upper side in the figure) of the effective pixel 310-1, and also overlaps with the pixel separation portion 410 that contacts the other side of the effective pixel 310-1.

[0208] Similarly, in Figure 22 In the example, the first connecting portion 270-2 belonging to the effective pixel 310-2 is arranged in the plan view to overlap with one side of the effective pixel 310-2 (the side on the left in the figure), and also overlaps with the pixel separation portion 410 that contacts the effective pixel 310-2 on that side.

[0209] Furthermore, the second connecting portion 371-2 belonging to the effective pixel 310-2 is arranged in the plan view to overlap with the other side (the upper side in the figure) of the effective pixel 310-2, and also overlaps with the pixel separation portion 410 that contacts the other side of the effective pixel 310-2.

[0210] Furthermore, the first connecting portion 270-3 belonging to the effective pixel 310-3 is arranged in the plan view to overlap with one side of the effective pixel 310-3 (the side on the left in the figure), and also overlaps with the pixel separation portion 410 that contacts the effective pixel 310-3 on that side.

[0211] Furthermore, the second connecting portion 371-3 belonging to the effective pixel 310-3 is arranged in the plan view to overlap with the other side (the upper side in the figure) of the effective pixel 310-3, and also overlaps with the pixel separation portion 410 that contacts the other side of the effective pixel 310-3.

[0212] Furthermore, the first connecting portion 270-4 belonging to the effective pixel 310-4 is arranged in the plan view to overlap with one side of the effective pixel 310-4 (the side on the left in the figure), and also overlaps with the pixel separation portion 410 that contacts the effective pixel 310-4 on that side.

[0213] Furthermore, the second connecting portion 371-4 belonging to the effective pixel 310-4 is arranged in the plan view to overlap with the other side (the upper side in the figure) of the effective pixel 310-4, and also overlaps with the pixel separation portion 410 that contacts the other side of the effective pixel 310-4.

[0214] Note that the arrangement of the first connecting portion 270 and the second connecting portion 371 in the effective pixel 310 is not limited to... Figure 22 Examples. Figure 23 This is a plan view showing another arrangement example of the first connecting portion 270 and the second connecting portion 371 in the effective pixels 310 of a first modified embodiment of the present invention.

[0215] exist Figure 23 In the example, the first connecting portion 270-1 and the second connecting portion 371-1 belonging to the effective pixel 310-1 are placed on the effective pixel 310-1 in the plan view, without overlapping with the pixel separation portion 410 that contacts the effective pixel 310-1.

[0216] Similarly, in Figure 23 In the example, the first connecting portion 270-2 and the second connecting portion 371-2 belonging to the effective pixel 310-2 are placed on the effective pixel 310-2 in the plan view, without overlapping with the pixel separation portion 410 that contacts the effective pixel 310-2.

[0217] Furthermore, the first connecting portion 270-3 and the second connecting portion 371-3 belonging to the effective pixel 310-3 are arranged on the effective pixel 310-3 in the plan view, without overlapping with the pixel separation portion 410 that contacts the effective pixel 310-3.

[0218] Furthermore, the first connecting portion 270-4 and the second connecting portion 371-4 belonging to the effective pixel 310-4 are arranged on the effective pixel 310-4 in the plan view, without overlapping with the pixel separation portion 410 that contacts the effective pixel 310-4.

[0219] Figure 24 This is a plan view illustrating another arrangement example of the first connecting portion 270 and the second connecting portion 371 in the effective pixels 310 of a first modified embodiment of the present invention. Figure 24 In the example, the first connecting portion 270-1 belonging to the effective pixel 310-1 is arranged in the plan view to overlap with the corner of the effective pixel 310-1 (the upper left corner in the figure), and also overlaps with the pixel separation portion 410 that contacts the corner of the effective pixel 310-1.

[0220] Furthermore, the second connecting portion 371-1 belonging to the effective pixel 310-1 is placed on the effective pixel 310-1 in the plan view, without overlapping with the pixel separation portion 410 that contacts the effective pixel 310-1.

[0221] Similarly, in Figure 24 In the example, the first connecting portion 270-2 belonging to the effective pixel 310-2 is arranged in the plan view to overlap with the corner of the effective pixel 310-2 (the upper left corner in the figure), and also overlaps with the pixel separation portion 410 that contacts the corner of the effective pixel 310-2.

[0222] Furthermore, the second connecting portion 371-2 belonging to the effective pixel 310-2 is placed on the effective pixel 310-2 in the plan view, without overlapping with the pixel separation portion 410 that contacts the effective pixel 310-2.

[0223] Furthermore, the first connecting portion 270-3 belonging to the effective pixel 310-3 is arranged in the plan view to overlap with the corner of the effective pixel 310-3 (the upper left corner in the figure), and also overlaps with the pixel separation portion 410 that contacts the corner of the effective pixel 310-3.

[0224] Furthermore, the second connecting portion 371-3 belonging to the effective pixel 310-3 is placed on the effective pixel 310-3 in the plan view, without overlapping with the pixel separation portion 410 that contacts the effective pixel 310-3.

[0225] Furthermore, the first connecting portion 270-4 belonging to the effective pixel 310-4 is arranged in the plan view to overlap with the corner of the effective pixel 310-4 (the upper left corner in the figure), and also overlaps with the pixel separation portion 410 that contacts the corner of the effective pixel 310-4.

[0226] Furthermore, the second connecting portion 371-4 belonging to the effective pixel 310-4 is placed on the effective pixel 310-4 in the plan view, without overlapping with the pixel separation portion 410 that contacts the effective pixel 310-4.

[0227] Note that in Figures 22 to 24 In the example, the positions of the first connecting portion 270 and the second connecting portion 371 belonging to each valid pixel 310 can be changed.

[0228] Figure 25 This is a diagram illustrating the circuit configuration of an effective pixel 310 according to a second variation of an embodiment of the present invention. Figure 25 As shown, the second variant differs from the implementation in that the drain of the N-type transistor 321 belonging to the plurality of effective pixels 310 is connected to the power supply line 422 (i.e., power supply voltage VDD) through the same third connection 380.

[0229] The third connection portion 380 includes a first pad and a second pad (not shown).

[0230] The first pad is configured to be exposed on the surface of the light receiving substrate 201 opposite to the light incident side surface (i.e., the interface with the circuit board 202), and contains copper or a copper alloy. Furthermore, the second pad is configured to be exposed on the light incident side surface of the circuit board 202 (i.e., the interface with the light receiving substrate 201), and contains copper or a copper alloy.

[0231] In the second variation, the first pad and the second pad are directly joined together by Cu-Cu bonding to form the third connection portion 380. Furthermore, in the second variation, a third connection portion 380 is shared by multiple (two shown in the figure) effective pixels 310.

[0232] Therefore, in the second variation, the drain of the N-type transistor 321 and the power supply line 422 are electrically connected by the third connection portion 380 formed by Cu-Cu bonding.

[0233] This can reduce the need for through-hole mounting sections 221, 222, 261 and 262 (see reference). Figure 3 and Figure 4 The number of wiring connections required at the location can be reduced, thus reducing the area of ​​the through-hole mounting sections 221, 222, 261, and 262.

[0234] Therefore, the second modification enables additional effective pixels 310 to be arranged in the area created by reducing the size of the through-hole mounting portions 221, 222, 261 and 262, thereby improving the resolution of the solid-state imaging device 200.

[0235] Furthermore, in the second variation where multiple effective pixels 310 share a single third connection portion 380, the number of third connection portions 380 in the solid-state imaging device 200 can be reduced. Therefore, in the second variation, connection portions (first connection portion 270 and second connection portion 371) different from the third connection portion 380 can be easily placed at the joint portion 203.

[0236] Note that in Figure 25 The example already illustrates an instance where two valid pixels 310 share a third connecting part 380, but three or more valid pixels 310 can also share a third connecting part 380.

[0237] Figure 26 This is a diagram illustrating the circuit configuration of an effective pixel 310 according to a third variation of an embodiment of the present invention, and also showing a quantizer 350 for detecting the presence of either a selected on event or an off event.

[0238] The quantizer 350 according to the third variation includes a P-type transistor 351, an N-type transistor 352, and a switch 355. The P-type transistor 351 and the N-type transistor 352 are connected in series between the power supply voltage VDD terminal and the ground potential terminal.

[0239] Furthermore, the gate of the P-type transistor 351 is connected to the output terminal of the subtractor 340. The gate of the N-type transistor 352 is connected to the switch 355.

[0240] Then, by switching switch 355, control unit 130 can apply a bias voltage V representing the upper threshold to the gate of N-type transistor 352. bon Or, the bias voltage V representing the lower threshold. boff The connection point between P-type transistor 351 and N-type transistor 352 is connected to transmission circuit 360.

[0241] Therefore, when a bias voltage V is applied to the gate of the N-type transistor 352 in the quantizer 350 according to the third variation... bon At that time, the voltage at connection point 356 serves as the conduction event detection signal V. CH It is output to the transmission circuit 360.

[0242] On the other hand, when a bias voltage V is applied to the gate of the N-type transistor 352 in the quantizer 350 according to the third variant example boffAt that time, the voltage at connection point 356 serves as the cutoff event detection signal V. CL It is output to the transmission circuit 360.

[0243] Using this configuration, when the control unit 130 selects a conduction event, the quantizer 350 of the third variation outputs a high-level conduction event detection signal V when the differential signal exceeds the upper limit threshold. CH .

[0244] On the other hand, when the control unit 130 selects a cutoff event, the quantizer 350 of the third variation outputs a low-level cutoff event detection signal V when the differential signal is below the lower threshold. CL .

[0245] For example, when the light source (not shown) is turned on by a command from the control unit 130, the control unit 130 selects a conduction event, so that the solid-state imaging device 200 according to the third modification can efficiently output a conduction event detection signal V. CH .

[0246] Furthermore, when the light source (not shown) is turned off by a command from the control unit 130, the control unit 130 selects a cutoff event, enabling the solid-state imaging device 200 according to the third modification to efficiently output a cutoff event detection signal V. CL .

[0247] The third variation described above can reduce the number of transistors constituting the quantizer 350, thereby reducing the chip area of ​​the solid-state imaging device 200 and reducing the power consumption of the solid-state imaging device 200.

[0248] [Effect]

[0249] The solid-state imaging device 200 according to this embodiment includes a light-receiving substrate 201, a circuit board 202, and a plurality of first connection portions 270. The light-receiving substrate 201 includes a plurality of light-receiving circuits 211 on which photoelectric conversion elements (photodiodes 311) are disposed. The circuit board 202 is directly bonded to the light-receiving substrate 201 and includes a plurality of address event detection circuits 231, which respectively detect voltage changes output from the photoelectric conversion elements (photodiodes 311) of the plurality of light-receiving circuits 211. The plurality of first connection portions 270 are disposed at a junction 203 between the light-receiving substrate 201 and the circuit board 202 to electrically connect corresponding light-receiving circuits 211 and address event detection circuits 231.

[0250] This can improve the resolution of the solid-state camera device 200.

[0251] Furthermore, in the solid-state imaging device 200 according to this embodiment, a plurality of first connection portions 270 are located between a plurality of optical receiving circuits 211 and a plurality of address event detection circuits 231 corresponding to each other.

[0252] Therefore, the asynchronous solid-state camera device 200 is able to perform faster processing.

[0253] Furthermore, in the solid-state imaging device 200 according to this embodiment, at least one of the plurality of first connection portions 270 includes a first pad 403 formed on the bonding plane of the light receiving substrate 201 and a second pad 404 formed on the bonding plane of the circuit board 202. The first pad 403 and the second pad 404 then contain the same material.

[0254] This allows multiple first connections 270 in the solid-state imaging device 200 to be formed in a single process step.

[0255] Furthermore, in the solid-state imaging device 200 according to this embodiment, the first pad 403 and the second pad 404 are directly bonded together.

[0256] This allows multiple first connections 270 in the solid-state imaging device 200 to be formed in a single process step.

[0257] Furthermore, in the solid-state imaging device 200 according to this embodiment, the circuit board 202 includes a plurality of grayscale acquisition circuits 370, which acquire the grayscale of light incident on the photoelectric conversion elements (photodiodes 311) of the plurality of light receiving circuits 211. Then, the solid-state imaging device 200 according to this embodiment includes a plurality of second connection portions 371, which are disposed at the junction 203 between the light receiving substrate 201 and the circuit board 202 to electrically connect the corresponding light receiving circuits 211 and grayscale acquisition circuits 370.

[0258] This can improve the resolution of the solid-state camera device 200.

[0259] Furthermore, the solid-state imaging device 200 according to this embodiment includes a plurality of third connection portions 380, which are disposed at the junction 203 between the light receiving substrate 201 and the circuit board 202 to connect the photoelectric conversion element (photodiode 311) and the power supply voltage VDD. Then, the plurality of photoelectric conversion elements (photodiodes 311) share at least one of the plurality of third connection portions 380.

[0260] This allows for easy placement of connecting portions (first connecting portion 270 and second connecting portion 371) that are different from the third connecting portion 380 at the joint portion 203.

[0261] [Second Construction Example of Address Event Detection Unit]

[0262] Figure 27 This is a block diagram illustrating a second construction example of the address event detection unit 1000. For example... Figure 27 As shown, in addition to the current-to-voltage conversion unit 1331, buffer 1332, subtractor 1333, quantizer 1334 and transmission unit 1335, the address event detection unit 1000 according to this construction example also includes a storage unit 1336 and a control unit 1337.

[0263] Storage unit 1336 is disposed between quantizer 1334 and transmission unit 1335, and stores the output of quantizer 1334, i.e., the comparison result of comparator 1334a based on the sampled signal provided from control unit 1337. Storage unit 1336 may be a sampling circuit such as a switch or capacitor, or a digital storage circuit such as a latch or flip-flop.

[0264] Control unit 1337 supplies a predetermined threshold voltage V to the inverting (-) input terminal of comparator 1334a. th The threshold voltage V supplied from the control unit 1337 to the comparator 1334a th It can have a voltage value that varies in a time-division manner. For example, the control unit 1337 supplies a threshold voltage V corresponding to a conduction event where the change in the indicator photocurrent exceeds an upper limit threshold at different time intervals. th1 And the threshold voltage V corresponding to the cutoff event where the indicated change has fallen below the lower threshold. th2 This enables a single comparator 1334a to detect multiple types of address events.

[0265] For example, a threshold voltage V corresponding to a cutoff event is supplied from the control unit 1337 to the inverting (-) input terminal of the comparator 1334a. th2 During the specified time period, storage unit 1336 can store the threshold voltage V corresponding to the conduction event, as used by comparator 1334a. th1 The comparison results. Note that storage cell 1336 can be located in each pixel 2030 (see reference). Figure 28 The storage unit 1336 can be located inside or outside each pixel 2030. Furthermore, the storage unit 1336 is not a necessary component of the address event detection unit 1000. That is, the storage unit 1336 can be omitted.

[0266] [According to the second construction example, the camera device (scanning method)]

[0267] The camera device 100 according to the first construction example described above is an asynchronous camera device that reads events using an asynchronous reading method. However, the event reading method is not limited to asynchronous reading; it can also be synchronous reading. The camera device using the synchronous reading method is a scanning camera device, the same as a typical camera device that performs recording at a predetermined frame rate.

[0268] Figure 28 This is a block diagram illustrating a construction example of a camera device according to a second construction example (i.e., a scanning camera device used as camera device 2000 in a camera system employing the technology according to the present invention).

[0269] like Figure 28 As shown, the camera device 2000 according to the second configuration example of the camera device of the present invention includes a pixel array unit 2021, a driving unit 2022, a signal processing unit 2025, a reading area selection unit 2027, and a signal generation unit 2028.

[0270] The pixel array unit 2021 includes a plurality of pixels 2030. The plurality of pixels 2030 output an output signal in response to a selection signal from the readout region selection unit 2027. Each of the plurality of pixels 2030 may include a quantizer comparator. The plurality of pixels 2030 output an output signal corresponding to the amount of change in light intensity. For example... Figure 28 As shown, multiple pixels 2030 can be arranged into a matrix in two dimensions.

[0271] The driving unit 2022 drives each of the plurality of pixels 2030 so that the pixel signal generated in each pixel 2030 is output to the signal processing unit 2025. Note that the driving unit 2022 and the signal processing unit 2025 are circuit parts used to acquire grayscale information. Therefore, if only event information is acquired, the driving unit 2022 and the signal processing unit 2025 can be removed.

[0272] The reading region selection unit 2027 selects some pixels from the plurality of pixels 2030 included in the pixel array section 2021. Specifically, the reading region selection unit 2027 determines the selected region in response to requests from each pixel 2030 of the pixel array section 2021. For example, the reading region selection unit 2027 selects one or more rows included in the structure of a two-dimensional matrix corresponding to the pixel array section 2021. The reading region selection unit 2027 selects one or more rows sequentially according to a preset period. Furthermore, the reading region selection unit 2027 can determine the selected region in response to requests from each pixel 2030 of the pixel array section 2021.

[0273] Based on the output signal of the pixel selected by the readout region selection unit 2027, the signal generation unit 2028 generates an event signal for the active pixels among the selected pixels for which an event has been detected. An event is an event of a change in light intensity. An active pixel is a pixel whose change in light intensity corresponding to the output signal exceeds or falls below a preset threshold. For example, the signal generation unit 2028 compares the pixel's output signal with a reference signal; if the output signal is greater than or less than the reference signal, it detects the active pixels that output the signal and generates an event signal for each active pixel.

[0274] For example, the signal generation unit 2028 may include a column selection circuit for arbitrating signals entering the signal generation unit 2028. Furthermore, the signal generation unit 2028 can output not only information about active pixels where events have been detected, but also information about non-active pixels where events have not been detected.

[0275] The signal generation unit 2028 outputs address information and timestamp information (e.g., (X,Y,T)) about the active pixels that have detected the event via the output line 2015. However, the data output from the signal generation unit 2028 can be not only address information and timestamp information, but also frame format information (e.g., (0,0,1,0,...)).

[0276] [Distance measuring system]

[0277] The ranging system according to an embodiment of the present invention is a system for measuring the distance to a subject using structured light technology. Furthermore, the ranging system according to an embodiment of the present invention can also be used as a system for acquiring three-dimensional (3D) images, and in this case, it can be called a three-dimensional image acquisition system. Structured light measures distance by identifying the coordinates of a point image and the light source projecting that point image (a so-called point light source) through pattern matching.

[0278] Figure 29 This is a schematic diagram illustrating a construction example of a ranging system according to an embodiment of the present invention. Figure 30 This is a block diagram illustrating an example of circuit construction.

[0279] The ranging system 3000 according to this embodiment uses a surface-emitting semiconductor laser, such as a vertical-cavity surface-emitting laser (VCSEL) 3010, as a light source unit, and uses an event detection sensor 3020, called a DVS, as a light receiver. The VCSEL 3010 projects a predetermined pattern of light onto the subject. In addition to the VCSEL 3010 and the event detection sensor 3020, the ranging system 3000 according to this embodiment also includes a system control unit 3030, a light source driving unit 3040, a sensor control unit 3050, a light source-side optical system 3060, and a camera-side optical system 3070.

[0280] For example, the system control unit 3030 includes a processor (CPU) that drives the vertical-cavity surface-emitting laser 3010 via a light source driving unit 3040 and drives the event detection sensor 3020 via a sensor control unit 3050. More specifically, the system control unit 3030 synchronizes and controls the vertical-cavity surface-emitting laser 3010 and the event detection sensor 3020.

[0281] In the ranging system 3000 constructed according to this embodiment, light of a predetermined pattern emitted from a vertical-cavity surface-emitting laser 3010 is projected onto a subject (object to be measured) 3100 through a light source-side optical system 3060. The projected light is reflected from the subject 3100. Then, the light reflected from the subject 3100 enters an event detection sensor 3020 through a camera-side optical system 3070. The event detection sensor 3020 receives the light reflected from the subject 3100 and detects a change in pixel brightness exceeding a predetermined threshold as an event. The event information detected by the event detection sensor 3020 is provided to an application processor 3200 external to the ranging system 3000. The application processor 3200 performs predetermined processing on the event information detected by the event detection sensor 3020.

[0282] Although embodiments of the present invention have been described above, the technical scope of the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the present invention. Furthermore, the constituent elements of different embodiments and modifications can be appropriately combined.

[0283] Furthermore, the effects described in this specification are merely illustrative and not limiting, and other effects may also be included.

[0284] Note that this technology can also have the following configurations. (1)

[0286] A solid-state imaging device, comprising:

[0287] A light receiving substrate, comprising multiple light receiving circuits provided with photoelectric conversion elements;

[0288] A circuit board, directly bonded to the light-receiving substrate, includes multiple address event detection circuits, each detecting voltage changes output from the photoelectric conversion elements of the multiple light-receiving circuits; and

[0289] A plurality of first connection portions are disposed at the joint between the optical receiving substrate and the circuit board to electrically connect the optical receiving circuit and the address event detection circuit corresponding to each other. (2)

[0291] According to the solid-state imaging device described in (1) above, wherein,

[0292] The plurality of first connection portions are located between the plurality of optical receiving circuits and the plurality of address event detection circuits that correspond to each other. (3)

[0294] According to the solid-state imaging device described in (1) or (2) above, wherein,

[0295] At least one of the plurality of first connection portions includes a first pad formed at the bonding plane of the light receiving substrate and a second pad formed at the bonding plane of the circuit board, and

[0296] The first pad and the second pad contain the same material. (4)

[0298] According to the solid-state imaging device described in (3) above, wherein,

[0299] The first pad and the second pad are directly bonded together. (5)

[0301] According to any one of (1) to (4) above, the solid-state imaging device, wherein,

[0302] The circuit board also includes multiple grayscale acquisition circuits, which respectively acquire the grayscale of light incident on the photoelectric conversion elements of the multiple light receiving circuits, and

[0303] The solid-state imaging device further includes a plurality of second connection portions disposed at the junction between the light receiving substrate and the circuit board to electrically connect the corresponding light receiving circuit and the grayscale acquisition circuit. (6)

[0305] The solid-state imaging device according to any one of (1) to (5) above further includes:

[0306] A plurality of third connection portions are disposed at the junction between the light receiving substrate and the circuit board to connect the photoelectric conversion element and the power supply voltage, and at least one of the plurality of third connection portions is shared by a plurality of the photoelectric conversion elements. (7)

[0308] A camera device, comprising:

[0309] Lens;

[0310] Solid-state imaging devices; and

[0311] The control unit controls the solid-state camera device.

[0312] The solid-state imaging device includes:

[0313] A light-receiving substrate comprising multiple light-receiving circuits equipped with photoelectric conversion elements.

[0314] A circuit board, which is directly bonded to the light-receiving substrate, includes multiple address event detection circuits, each of which detects voltage changes output from the photoelectric conversion elements of the multiple light-receiving circuits.

[0315] A plurality of first connection portions are disposed at the joint between the optical receiving substrate and the circuit board to electrically connect corresponding optical receiving circuits and address event detection circuits.

[0316] A signal processing unit performs signal processing on the output of the solid-state imaging device. (8)

[0318] According to the camera device described in (7) above, wherein,

[0319] The plurality of first connection portions are located between the plurality of optical receiving circuits and the plurality of address event detection circuits that correspond to each other. (9)

[0321] According to the camera device described in (7) or (8) above, wherein,

[0322] At least one of the plurality of first connection portions includes a first pad formed at the bonding plane of the light receiving substrate and a second pad formed at the bonding plane of the circuit board, and

[0323] The first pad and the second pad contain the same material. (10)

[0325] According to the camera device described in (9) above, wherein,

[0326] The first pad and the second pad are directly bonded together. (11)

[0328] The camera device according to any one of (7) to (10) above, wherein,

[0329] The circuit board also includes multiple grayscale acquisition circuits, which respectively acquire the grayscale of light incident on the photoelectric conversion elements of the multiple light receiving circuits, and

[0330] The camera device further includes a plurality of second connecting parts, which are disposed at the joint between the light receiving substrate and the circuit board to electrically connect the light receiving circuit and the grayscale acquisition circuit that correspond to each other. (12)

[0332] The camera device according to any one of (7) to (11) above further includes:

[0333] A plurality of third connection portions are disposed at the junction between the light-receiving substrate and the circuit board to connect the photoelectric conversion element and the power supply voltage.

[0334] At least one of the plurality of third connecting portions is shared by the plurality of photoelectric conversion elements.

[0335] List of reference numerals

[0336] 100: Camera equipment

[0337] 110: Lens

[0338] 130: Control Unit

[0339] 200: Solid-state imaging device

[0340] 201: Optical receiving substrate

[0341] 202: Circuit Board

[0342] 203: Joint

[0343] 211: Optical receiving circuit

[0344] 231: Address Event Detection Circuit

[0345] 270, 270-1 to 270-4: First connecting part

[0346] 310: Effective pixels

[0347] 311: Photodiode (Example of a photoelectric conversion element)

[0348] 371, 371-1 to 371-4: Second connecting part

[0349] 380: Third connecting part

[0350] 403: First pad

[0351] 404: Second pad

Claims

1. A solid-state imaging device, comprising: A light receiving substrate, comprising multiple light receiving circuits provided with photoelectric conversion elements; A circuit board, which is directly bonded to the light receiving substrate, and includes multiple address event detection circuits, which respectively detect voltage changes output from the photoelectric conversion elements of the multiple light receiving circuits; A plurality of first connection portions are disposed at the joint between the optical receiving substrate and the circuit board to electrically connect the optical receiving circuit and the address event detection circuit corresponding to each other. and A plurality of third connection portions are disposed at the junction between the light-receiving substrate and the circuit board to connect the photoelectric conversion element and the power supply voltage. At least one of the plurality of third connecting portions is shared by the plurality of photoelectric conversion elements.

2. The solid-state imaging device according to claim 1, wherein, The plurality of first connection portions are located between the plurality of optical receiving circuits and the plurality of address event detection circuits that correspond to each other.

3. The solid-state imaging device according to claim 1, wherein, At least one of the plurality of first connection portions includes a first pad formed at the bonding plane of the light receiving substrate and a second pad formed at the bonding plane of the circuit board, and The first pad and the second pad contain the same material.

4. The solid-state imaging device according to claim 3, wherein, The first pad and the second pad are directly bonded together.

5. The solid-state imaging device according to claim 1, wherein, The circuit board also includes multiple grayscale acquisition circuits, which respectively acquire the grayscale of light incident on the photoelectric conversion elements of the multiple light receiving circuits, and The solid-state imaging device further includes a plurality of second connection portions disposed at the junction between the light receiving substrate and the circuit board to electrically connect the corresponding light receiving circuit and the grayscale acquisition circuit.

6. A camera device, comprising: Lens; Solid-state imaging devices; and The control unit controls the solid-state camera device. The solid-state imaging device includes: A light-receiving substrate comprising multiple light-receiving circuits equipped with photoelectric conversion elements. A circuit board, which is directly bonded to the light-receiving substrate, includes multiple address event detection circuits, each of which detects voltage changes output from the photoelectric conversion elements of the multiple light-receiving circuits. A plurality of first connection portions are disposed at the joint between the optical receiving substrate and the circuit board to electrically connect the optical receiving circuit and the address event detection circuit that correspond to each other. The signal processing unit performs signal processing on the output of the solid-state imaging device, and A plurality of third connection portions are disposed at the junction between the light-receiving substrate and the circuit board to connect the photoelectric conversion element and the power supply voltage. At least one of the plurality of third connecting portions is shared by the plurality of photoelectric conversion elements.

7. The camera device according to claim 6, wherein, The plurality of first connection portions are located between the plurality of optical receiving circuits and the plurality of address event detection circuits that correspond to each other.

8. The camera device according to claim 6, wherein, At least one of the plurality of first connection portions includes a first pad formed at the bonding plane of the light receiving substrate and a second pad formed at the bonding plane of the circuit board, and The first pad and the second pad contain the same material.

9. The camera device according to claim 8, wherein, The first pad and the second pad are directly bonded together.

10. The camera device according to claim 6, wherein, The circuit board also includes multiple grayscale acquisition circuits, which respectively acquire the grayscale of light incident on the photoelectric conversion elements of the multiple light receiving circuits, and The camera device further includes a plurality of second connecting parts, which are disposed at the joint between the light receiving substrate and the circuit board to electrically connect the light receiving circuit and the grayscale acquisition circuit that correspond to each other.

Images