A processing method of silicon carbide planar gate MOSFET and silicon carbide planar gate MOSFET device

Abstract

The present application relates to the technical field of semiconductor devices, in particular to a processing method of silicon carbide planar gate MOSFET and silicon carbide planar gate MOSFET device, comprising: S1: heat oxidation is carried out to polycrystalline silicon area to form mask layer; the mask layer extends to active area along the side surface of polycrystalline silicon area;S2: a pair of side walls are formed along the inner side of mask layer respectively;S3: deposition forms silicon dioxide dielectric layer, then the photoetching is carried out to silicon dioxide dielectric layer to form contact hole;The depth of contact hole reaches active area, and contact hole is located between side wall;S4: the metal layer is formed above the device, and the metal layer fills contact hole and is connected to active area.The beneficial effect is that: in the process of processing planar gate MOSFET, the side wall is formed between the polycrystalline silicon area of both sides, and then in the process of forming source contact hole by photoetching subsequently, the position of contact hole is defined by side wall, the problem that device consistency is poor and stability is reduced due to insufficient photoetching accuracy is avoided, and the consistency of contact hole is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and specifically to a method for fabricating a silicon carbide planar gate MOSFET and a silicon carbide planar gate MOSFET device. Background Technology

[0002] Planar gate MOSFETs, also known as vertical double-diffused MOSFETs (D-MOSFETs), are power MOSFET devices with a planar gate structure. This type of device typically places the source at the center of the device and leads out the gates at both ends to form a vertical channel within the device. The current and voltage of this type of device are related to the length and width of the channel, and it exhibits good saturation characteristics, making it widely used in amplifiers, LDOs, integrated power ICs, and high-voltage devices.

[0003] For power devices, specific on-resistance is a crucial performance indicator. Therefore, existing technologies have explored numerous improvements to the structure and fabrication methods of planar gate MOSFETs to achieve lower specific on-resistance. For example, a common approach is to reduce the dimensions of the unit cell, including the device channel size, the MESA size between P-wells, and the source contact via size, thereby achieving a lower specific on-resistance.

[0004] However, in actual implementation, the inventors discovered that the scheme for reducing the size of the pattern within the unit cell directly depends on the process capability (i.e., the minimum linewidth capability and registration accuracy of the lithography machine). Therefore, reducing the unit cell size through lithography would greatly increase the difficulty of the process, and due to the limitation of the machine's registration accuracy, it would result in poor consistency and symmetry of the contact hole size, affecting the stability of the device. Summary of the Invention

[0005] In view of the above-mentioned problems in the prior art, a method for fabricating a silicon carbide planar gate MOSFET and a silicon carbide planar gate MOSFET device are provided.

[0006] The specific technical solution is as follows:

[0007] A method for fabricating a silicon carbide planar gate MOSFET is applicable to fabricating a planar gate MOSFET device in the fabrication process. The device has an active region and polysilicon regions above the upper surface of the device are respectively disposed at both ends above the active region.

[0008] include:

[0009] Step S1: Perform thermal oxidation on the polycrystalline silicon region to form a mask layer;

[0010] The mask layer covers the upper surface of the polysilicon region and extends along the side of the polysilicon region to the active region;

[0011] Step S2: Form a pair of sidewalls along the inner side of the mask layer respectively;

[0012] Step S3: Deposit to form a silicon dioxide dielectric layer, and then perform photolithography on the silicon dioxide dielectric layer to form contact holes;

[0013] The depth of the contact hole reaches the active area, and the contact hole is located between the sidewalls;

[0014] Step S4: A metal layer is formed on top of the device, the metal layer filling the contact hole and connecting to the active region.

[0015] Preferably, step S2 includes:

[0016] Step S21: Deposit a first dielectric on the upper surface of the device;

[0017] The first medium covers the active region and the mask layer;

[0018] Step S22: Etch the device to a depth reaching the active region to form the sidewall.

[0019] Preferably, step S3 includes:

[0020] Step S31: Deposit the silicon dioxide dielectric layer over the device;

[0021] The thickness of the silicon dioxide dielectric layer is greater than the height of the polycrystalline silicon sidewall;

[0022] Step S32: Coat the silicon dioxide dielectric layer with photoresist, wherein the photoresist is located above the polysilicon region;

[0023] Step S33: Perform photolithography on the silicon dioxide dielectric layer to form the contact hole.

[0024] Preferably, in step S1, the active region is made of silicon carbide.

[0025] Preferably, in step S21, the thickness of the first medium is greater than 1000 Å, and the etching rate of the first medium is different from that of the silicon dioxide.

[0026] Preferably, the width of the sidewall is greater than 0.1 μm.

[0027] A silicon carbide planar gate MOSFET device, formed using the above-described fabrication method, includes:

[0028] Substrate, the substrate having a first doping type;

[0029] An epitaxial layer is formed above the substrate, and the epitaxial layer has the first doping type;

[0030] A well region, formed at the center of the epitaxial layer, wherein the well region has a second doping type;

[0031] A body region formed at the center of the well region, the body region having a second doping type;

[0032] Source regions are distributed on both sides of the source region, and the source regions have the first doping type;

[0033] An isolation layer is formed above the well region, covering the surface of the well region and the epitaxial layer;

[0034] A polycrystalline silicon region is formed above the isolation layer and located at both ends of the isolation layer;

[0035] A mask layer is formed above and on the side of the polysilicon region;

[0036] Sidewalls, each located inside the mask layer;

[0037] Silica dielectric layers are respectively disposed above the mask layers;

[0038] A top metal layer is formed above the body region and the source region and covers the surface of the silicon dioxide dielectric layer;

[0039] A back metal layer is formed beneath the substrate.

[0040] Preferably, the first doping type is N-type and the second doping type is P-type.

[0041] Preferably, the first doping type is P-type and the second doping type is N-type.

[0042] The above technical solution has the following advantages or beneficial effects: by forming a sidewall between the polysilicon regions on both sides during the processing of the planar gate MOSFET, the position of the contact hole is defined by the sidewall during the subsequent process of forming the source contact hole by photolithography, thus avoiding the problem of poor device consistency and reduced stability caused by insufficient photolithography precision, and improving the consistency of the contact hole. Attached Figure Description

[0043] Embodiments of the invention will be described more fully with reference to the accompanying drawings. However, the drawings are for illustration and explanation only and do not constitute a limitation on the scope of the invention.

[0044] Figure 1 This is an overall schematic diagram of an embodiment of the present invention;

[0045] Figure 2 This is a schematic diagram of the device at the start of processing in an embodiment of the present invention;

[0046] Figure 3 This is a schematic diagram of the device after step S1 is executed in an embodiment of the present invention;

[0047] Figure 4 This is a schematic diagram of the device after step S2 is executed in an embodiment of the present invention;

[0048] Figure 5 This is a schematic diagram of the device after step S3 is executed in an embodiment of the present invention;

[0049] Figure 6 This is a schematic diagram of the device after step S4 is executed in an embodiment of the present invention;

[0050] Figure 7 This is a schematic diagram of sub-step S2 in an embodiment of the present invention;

[0051] Figure 8 This is a schematic diagram of the device after step S21 is executed in an embodiment of the present invention;

[0052] Figure 9 This is a schematic diagram of sub-step S3 in an embodiment of the present invention;

[0053] Figure 10 This is a schematic diagram of the device after step S31 is executed in an embodiment of the present invention;

[0054] Figure 11 This is a schematic diagram of the device during step S32 of the present invention, when photoresist is coated.

[0055] Figure 12 This is a schematic diagram of the device during step S32 of the present invention when photoresist is coated;

[0056] Figure 13 This is a schematic diagram of the device during step S32 of the present invention when photoresist is coated;

[0057] Figure 14 This is a schematic diagram of the device during step S32 of the present invention when photoresist is coated;

[0058] Figure 15 This is a schematic diagram of a device formed using the above-described processing method in an embodiment of the present invention. Detailed Implementation

[0059] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0060] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0061] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but this is not intended to limit the scope of the invention.

[0062] This invention includes:

[0063] A method for fabricating a silicon carbide planar gate MOSFET is applicable to fabricating a planar gate MOSFET device in the fabrication process. The device has an active region and polysilicon regions above the upper surface of the device are respectively disposed at both ends above the active region.

[0064] like Figure 1 As shown, it includes:

[0065] Step S1: In such Figure 2 Based on the device shown, the polysilicon region A2 is thermally oxidized to form a mask layer;

[0066] like Figure 3 As shown, mask layer A3 covers the upper surface of polysilicon region A2 and extends along the side of polysilicon region A2 to active region A1.

[0067] Step S2: , as Figure 4 As shown, a pair of sidewalls A4 are formed along the inner side of the mask layer A3;

[0068] Step S3: Deposit and form a silicon dioxide dielectric layer A5, and then perform photolithography on the silicon dioxide dielectric layer A5 to form contact holes;

[0069] like Figure 5 As shown, the depth of the contact hole reaches the active region, and the contact hole is located between sidewalls A4;

[0070] Step S4: As Figure 6 As shown, a metal layer A6 is formed on top of the device, and the metal layer A6 fills the contact hole and connects to the active region A1.

[0071] Specifically, regarding planar gate MOSFETs in the prior art, during the process of reducing the unit cell size, the contact holes obtained by photolithography suffer from poor consistency due to the influence of the processing accuracy of the processing equipment, which affects the stability of the device. In this embodiment, in Figure 2 Based on the device shown, a mask layer and sidewalls are formed sequentially to define the area for subsequent contact hole formation, thereby avoiding problems such as photolithography position misalignment and poor contact hole consistency that may occur during contact hole photolithography, and improving the stability of the device.

[0072] In implementation, the aforementioned device refers to a planar gate MOSFET device. The device can be any semiconductor material with an oxidation rate much lower than that of polysilicon, depending on the material of its substrate. In one embodiment, the semiconductor material is silicon carbide. The active region A1 refers to the area pre-formed beneath the device, including substrate A11, epitaxial layer A12, well region A13, body region A14, source region A15, and isolation layer A16. The isolation layer A16 covers the surface of the active region A1 and directly contacts the polysilicon region A2. The polysilicon region A2 is located at both ends above the active region A1 and is used to form a planar gate structure in subsequent processing. The sidewalls A4 refer to the isolation structures located inside the mask layer, situated between the two polysilicon regions A2, surrounding the central region of the device. The positions between the sidewalls A4 are the locations where contact holes need to be etched laterally. The sidewalls A4 can be made of various materials, namely the first dielectric described below, whose etching rate differs from that of the silicon dioxide dielectric layer A5. In one embodiment, the first dielectric is polysilicon. During contact hole photolithography on the silicon dioxide dielectric layer A5, photoresist is typically applied over the silicon dioxide dielectric layer A5 to define the position of the contact holes. However, due to the inherent processing precision limitations of the photolithography machine, the photoresist application position may shift, resulting in poor consistency of the processed contact holes. This invention reduces the precision requirements of the processing equipment by pre-forming sidewalls in the device to define the contact hole position. During contact hole photolithography, the photoresist window only needs to fall within the width range of the sidewalls, allowing for misalignment and linewidth fluctuations within the sidewall width range. Therefore, contact hole photolithography is less affected by the machine's processing capabilities.

[0073] In the aforementioned planar gate MOSFET device fabricated using silicon carbide, in step S1, a mask layer A3 is formed on the polysilicon region A2 using thermal oxidation. This mask layer A3 is made of silicon dioxide formed through oxidation. Since the oxidation rate of silicon carbide is much lower than that of polysilicon, only a very thin layer of silicon dioxide remains on its surface, avoiding any impact on the fabricated device. This mask layer A3 is used in the subsequent step S2, during the fabrication of the sidewalls, to protect the polysilicon region A2 from etching.

[0074] In a preferred embodiment, such as Figure 7 As shown, step S2 includes:

[0075] Step S21: As Figure 8 As shown, a first dielectric A41 is deposited on the upper surface of the device;

[0076] The first dielectric A41 covers the active region A1 and the mask layer A3;

[0077] Step S22: Etch the device to a depth reaching the active region A1 to form a shape as shown in the image. Figure 4 The side wall A4 is shown.

[0078] Specifically, to achieve the effect of limiting the position of contact holes by generating sidewalls, in this embodiment, a first dielectric A41 is deposited on the upper surface of the device, and then the first dielectric A41 is etched to remove the first dielectric A41 deposited along the horizontal direction on the upper surface of the device, retaining only the first dielectric A41 set along the sidewall of the mask layer A3, thereby generating the sidewall A4. In this process, since the mask layer A3 is pre-formed on the polysilicon region A2, the requirements for the etching termination condition are lower, reducing the risk of damage to the polysilicon region A2. At the same time, by controlling the thickness of the deposited first dielectric A41, the width of the finally generated sidewall A4 can be adjusted.

[0079] In a preferred embodiment, such as Figure 9 As shown, step S3 includes:

[0080] Step S31: As Figure 10 As shown, a silicon dioxide dielectric layer A5 is deposited above the device;

[0081] The thickness of the silica dielectric layer A5 is greater than the height of the sidewall A4;

[0082] Step S32: As Figure 11 As shown, photoresist A51 is coated on the silicon dioxide dielectric layer A5, and photoresist A51 is located above the polysilicon region A2;

[0083] Step S33: Perform photolithography on the silicon dioxide dielectric layer A5 to form as shown in the figure. Figure 5 The contact hole shown.

[0084] Specifically, to achieve better contact hole consistency, in this embodiment, based on the original photolithography of the silicon dioxide dielectric layer A5, a sidewall A4 is introduced to block the photolithography area, thereby avoiding the problem of poor contact hole consistency caused by photoresist coating misalignment in step S32. For example, Figure 11The photoresist coating shown represents a relatively ideal processing condition. However, in actual processing, due to limitations such as equipment precision, it often exhibits variations such as... Figure 12 The case shown, where the left-side photoresist A51 is more than the right-side photoresist A52, will cause the contact hole obtained by photolithography to be offset to the right in the prior art; or, as shown in the figure... Figure 13 The case shown, where the left-side photoresist A51 is more than the right-side photoresist A52, will cause the contact hole obtained by photolithography to shift to the left in the prior art; or, as shown in the figure... Figure 14 The photoresist A51 shown is shorter than normal, resulting in an excessively long photolithography window. To address this, the position of the contact holes can be limited within a certain range by introducing a sidewall A4, thus avoiding poor contact hole consistency caused by photolithography precision issues.

[0085] In a preferred embodiment, in step S1, the oxidation rate of the active region A1 is lower than the oxidation rate of the polysilicon region A2.

[0086] Specifically, in order to avoid the above processing from adversely affecting the actual generated device, in this embodiment, the material of the active region A1 is adjusted so that the oxidation rate of the active region A1 is much lower than that of the polysilicon region A2. Thus, while the polysilicon region A2 is thermally oxidized to form the mask layer A3, only a very thin layer of oxide is formed on the surface of the active region A1, thus avoiding any impact on the generated device.

[0087] In a preferred embodiment, in step S21, the thickness of the first dielectric A41 is greater than 1000 Å, and the etching rate of the first dielectric A41 is different from that of silicon dioxide.

[0088] Specifically, in order to achieve better restriction of the contact hole during the subsequent contact hole photolithography process, in this embodiment, the thickness of the first dielectric A41 is controlled to be greater than 1000A during the deposition of the first dielectric A41, so that the first dielectric A41 is etched to form a sidewall A4 of sufficient width, thereby achieving a better restriction effect on the contact hole.

[0089] In a preferred embodiment, the width of the sidewall is greater than 0.1 μm.

[0090] A silicon carbide planar gate MOSFET device is formed using the above-described fabrication method, such as... Figure 15 The following are included:

[0091] Substrate B11, substrate B11 having a first doping type;

[0092] Epitaxial layer B12 is formed above substrate B11 and has a first doping type;

[0093] Well region B13 is formed in the center of the epitaxial layer and has a second doping type.

[0094] Body region B14 is formed at the center of well region B13 and has a second doping type.

[0095] The body region B14 has source regions B15 distributed on both sides, and the source regions B15 have the first doping type.

[0096] An isolation layer B16 is formed above the well region B13, covering the surfaces of the well region B13 and the epitaxial layer B12.

[0097] Polysilicon region B2 is formed above isolation layer B16 and located at both ends of isolation layer B16;

[0098] Mask layer B3 is formed above and on the side of polysilicon region B2;

[0099] Sidewall B4 is located inside mask layer B3.

[0100] Silicon dioxide dielectric layer B5 is disposed above mask layer B3;

[0101] A top metal layer B6 is formed above the source region B15 and the body region B14, and covers the surface of the silicon dioxide dielectric layer B5.

[0102] Back metal layer B7 is formed below substrate B1.

[0103] Specifically, for planar gate MOSFETs in the prior art, the contact holes obtained by photolithography have poor consistency due to the processing precision of the processing equipment during the process of reducing the unit cell size, which affects the stability of the device. In this embodiment, by introducing sidewall B4 during the processing, the photoresist window in the contact hole processing is limited, thereby achieving better contact hole consistency and better device stability than the prior art.

[0104] In a preferred embodiment, the first doping type is N-type and the second doping type is P-type.

[0105] In a preferred embodiment, the first doping type is P-type and the second doping type is N-type.

[0106] The beneficial effects of this invention are as follows: by forming a sidewall between the polysilicon regions on both sides during the processing of the planar gate MOSFET, the position of the contact hole is defined by the sidewall during the subsequent process of forming the source contact hole by photolithography, thus avoiding the problem of poor device consistency and reduced stability caused by insufficient photolithography precision, and improving the consistency of the contact hole.

[0107] The above are merely preferred embodiments of the present invention and are not intended to limit the implementation methods and protection scope of the present invention. Those skilled in the art should recognize that any equivalent substitutions and obvious changes made based on the description and illustrations of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for fabricating a silicon carbide planar gate MOSFET, applicable to fabricating a planar gate MOSFET device in the fabrication process, the device having an active region and polysilicon regions above the upper surface of the device being respectively disposed at both ends above the active region; Its features are, include: Step S1: Perform thermal oxidation on the polycrystalline silicon region to form a mask layer; The mask layer covers the upper surface of the polysilicon region and extends along the side of the polysilicon region to the active region; Step S2: Form a pair of sidewalls along the inner side of the mask layer respectively; Step S3: Deposit to form a silicon dioxide dielectric layer, and then perform photolithography on the silicon dioxide dielectric layer to form contact holes; The depth of the contact hole reaches the active area, and the contact hole is located between the sidewalls; Step S4: A metal layer is formed on top of the device, the metal layer filling the contact hole and connecting to the active region; Step S2 includes: Step S21: Deposit a first dielectric on the upper surface of the device; The first medium covers the active region and the mask layer; Step S22: Etch the device to a depth reaching the active region to remove the first dielectric deposited on the upper surface of the device in the horizontal direction, thereby forming the sidewall; In step S21, the width of the sidewall is adjusted by controlling the thickness of the deposited first medium; A mask layer is provided above the polysilicon region to reduce the requirement for etching termination in step S22. The mask layer is silicon dioxide formed by oxidation. Furthermore, the etching rate of the first medium is different from that of silicon dioxide.

2. The processing method according to claim 1, characterized in that, Step S3 includes: Step S31: Deposit the silicon dioxide dielectric layer over the device; The thickness of the silicon dioxide dielectric layer is greater than the height of the polycrystalline silicon sidewall; Step S32: Coat the silicon dioxide dielectric layer with photoresist, wherein the photoresist is located above the polysilicon region; Step S33: Perform photolithography on the silicon dioxide dielectric layer to form the contact hole.

3. The processing method according to claim 1, characterized in that, In step S1, the active region is made of silicon carbide.

4. The processing method according to claim 1, characterized in that, In step S21, the thickness of the first medium is greater than 1000 Å, and the etching rate of the first medium is different from that of the silicon dioxide.

5. The processing method according to claim 1, characterized in that, The width of the sidewall is greater than 0.1 μm.

6. A silicon carbide planar gate MOSFET device, characterized in that, Formed by the processing method described in any one of claims 1-5, comprising: Substrate, the substrate having a first doping type; An epitaxial layer is formed above the substrate, and the epitaxial layer has the first doping type; A well region, formed at the center of the epitaxial layer, wherein the well region has a second doping type; A body region formed at the center of the well region, the body region having a second doping type; Source regions are distributed on both sides of the source region, and the source regions have the first doping type; An isolation layer is formed above the well region, covering the surface of the well region and the epitaxial layer; A polycrystalline silicon region is formed above the isolation layer and located at both ends of the isolation layer; A mask layer is formed above and on the side of the polysilicon region; Sidewalls, each located inside the mask layer; Silica dielectric layers, wherein the silica dielectric layers are respectively disposed above the mask layers; A top metal layer is formed above the body region and the source region and covers the surface of the silicon dioxide dielectric layer; A back metal layer is formed beneath the substrate.

7. The planar gate MOSFET device according to claim 6, characterized in that, The first doping type is N-type, and the second doping type is P-type.

8. The planar gate MOSFET device according to claim 6, characterized in that, The first doping type is P-type, and the second doping type is N-type.

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