Nitride crystal, semiconductor laminate, method for manufacturing nitride crystal, and apparatus for manufacturing nitride crystal

Abstract

Nitride crystal, semiconductor laminate, method for manufacturing nitride crystal, and apparatus for manufacturing nitride crystal. The problem is to improve the quality of a nitride crystal. A crystal represented by a composition formula of In x Al y Ga 1－x－y N (where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1, 0 ≤ x + y ≤ 1), the concentration of carbon in the crystal is lower than 1 × 10 15 cm －3 -3, and the concentration of an electron trap E3 existing in the energy range of 0.5 eV or more and 0.65 eV or less from the bottom of the conduction band in the crystal is lower than 1 × 10 14 cm －3 -3.

Description

Technical Field

[0001] This invention relates to nitride crystals, semiconductor laminates, methods for manufacturing nitride crystals, and apparatus for manufacturing nitride crystals. Background Technology

[0002] When manufacturing semiconductor devices such as light-emitting elements or high-speed transistors, there are cases where crystals of group III nitrides such as gallium nitride (GaN) are used (see Patent Documents 1-4).

[0003] Prior art literature

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2016-104693

[0006] Patent Document 2: Japanese Patent Application Publication No. 2007-153664

[0007] Patent Document 3: Japanese Patent Application Publication No. 2005-39248

[0008] Patent Document 4: Japanese Patent Application Publication No. 2020-23427 Summary of the Invention

[0009] The purpose of this invention is to improve the quality of nitride crystals.

[0010] According to one aspect of the present invention, a nitride crystal is provided, which is made of In x Al y Ga 1-x-y The crystal represented by the formula N (where 0≤x≤1, 0≤y≤1, 0≤x+y≤1) is where,

[0011] The carbon concentration in the crystal is less than 1×10⁻⁶. 15 cm -3 ,

[0012] The concentration of electron trap E3 in the crystal, existing in the energy range of 0.5 eV above and 0.65 eV from the bottom of the conduction band, is less than 1 × 10⁻⁶. 14 cm -3 .

[0013] According to another aspect of the present invention, a nitride crystal is provided, which is made of In x Al y Ga 1-x-y The crystal represented by the formula N (where 0≤x≤1, 0≤y≤1, 0≤x+y≤1) is where,

[0014] Satisfying equations (1-1) and (1-2),

[0015] [E3] < 1 × 10 14 …(1-1)

[0016] [E3]·[C] 2 ≤1×10 43 …(1-2)

[0017] in,

[0018] [C] indicates that the unit is cm. -3 The concentration of carbon in the crystal,

[0019] [E3] is the concentration of electron trap E3 present in the crystal within the energy range of 0.5 eV above and 0.65 eV from the bottom of the conduction band, and the unit of E3 concentration is cm⁻¹. -3 .

[0020] According to another aspect of the present invention, a semiconductor laminate is provided, comprising:

[0021] Substrate;

[0022] A nitride crystal layer, wherein the nitride crystal layer is disposed on the substrate, and comprises an In crystal layer. x Al y Ga 1-x-y The crystal represented by the composition formula of N (where 0≤x≤1, 0≤y≤1, 0≤x+y≤1)

[0023] The carbon concentration in the nitride crystal layer is less than 1 × 10⁻⁶. 15 cm -3 ,

[0024] The concentration of electron trap E3 in the crystal, existing in the energy range of 0.5 eV above and 0.65 eV from the bottom of the conduction band, is less than 1 × 10⁻⁶. 14 cm -3 .

[0025] According to another aspect of the present invention, a semiconductor laminate is provided, comprising:

[0026] Substrate;

[0027] A nitride crystal layer, wherein the nitride crystal layer is disposed on the substrate, and comprises an In crystal layer. x Al y Ga 1-x-y The crystal represented by the composition formula of N (where 0≤x≤1, 0≤y≤1, 0≤x+y≤1)

[0028] The nitride crystal layer satisfies equations (1-1) and (1-2).

[0029] [E3] < 1 × 1014 …(1-1)

[0030] [E3]·[C] 2 ≤1×10 43 …(1-2)

[0031] in,

[0032] [C] indicates that the unit is cm. -3 The concentration of carbon in the nitride crystal layer,

[0033] [E3] is the concentration of electron trap E3 present in the crystal within the energy range of 0.5 eV above and 0.65 eV from the bottom of the conduction band, and the unit of E3 concentration is cm⁻¹. -3 .

[0034] According to another aspect of the present invention, a method for manufacturing nitride crystals is provided, comprising the following steps:

[0035] The process of preparing a reaction vessel to house the substrate;

[0036] For the substrate heated to a specified growth temperature within the reaction vessel, a Group III element feedstock gas and a nitrogen feedstock gas are supplied, causing the In... x Al y Ga 1-x-y The process of epitaxially growing a nitride crystal on the substrate, represented by the formula of N (where 0≤x≤1, 0≤y≤1, 0≤x+y≤1),

[0037] The process of preparing the reaction vessel includes the following steps:

[0038] The process of preparing a container as the reaction vessel includes a region heated to the growth temperature, i.e., a high-temperature reaction region in contact with the gas supplied to the substrate, and at least a portion of the surface of the components constituting the high-temperature reaction region having a protective layer formed of a ferricyanide complex.

[0039] In the high-temperature baking process, the temperature of the high-temperature reaction zone is heated to a temperature of over 1500°C while hydrogen and halogen gases are supplied to the reaction vessel, but the nitrogen raw material gas is not supplied to the reaction vessel, thereby cleaning and modifying the surface of the components constituting the high-temperature reaction zone.

[0040] According to another aspect of the present invention, a nitride crystal manufacturing apparatus is provided, comprising:

[0041] Reaction vessel containing substrate;

[0042] Heating at least the heating section of the substrate within the reaction vessel;

[0043] For the substrate within the reaction vessel, a gas supply system for supplying Group III element raw material gas and nitrogen raw material gas;

[0044] For the substrate heated to a specified growth temperature within the reaction vessel, the group III element feedstock gas and the nitrogen feedstock gas are supplied to allow the In... x Al y Ga 1-x-y The composition of N (where 0≤x≤1, 0≤y≤1, 0≤x+y≤1) represents the method of epitaxial growth of nitride crystals on the substrate, and the control unit controls the heating section and the gas supply system.

[0045] The reaction vessel has a region heated to the growth temperature, i.e., a high-temperature reaction region in contact with the gas supplied to the substrate.

[0046] At least a portion of the surface of the component constituting the high-temperature reaction zone has a protective layer formed of a ferricyanide complex.

[0047] Before the nitride crystal is epitaxially grown, the control unit performs a high-temperature baking process, heating the temperature of the high-temperature reaction zone to a temperature of 1500°C or higher, while supplying hydrogen and halogen gases into the reaction vessel, but not supplying the nitrogen raw material gas into the reaction vessel, thereby cleaning and modifying the surface of the components constituting the high-temperature reaction zone.

[0048] According to the present invention, the quality of nitride crystals can be improved. Attached Figure Description

[0049] Figure 1 (a) is a schematic top view of the nitride crystal substrate 10, and (b) is a schematic side view of the nitride crystal substrate 10.

[0050] Figure 2 This is a diagram illustrating a measurement example using isothermal capacitance transient spectroscopy.

[0051] Figure 3 This is a graph showing the results of measuring the electron trap concentration of the GaN crystal of the first embodiment of the present invention and the GaN crystal of Reference 4 by isothermal capacitance transient spectroscopy.

[0052] Figure 4 This is a schematic diagram of the HVPE apparatus 200, showing the crystal growth step in progress within the reaction vessel 203.

[0053] Figure 5This is a schematic diagram of the HVPE apparatus 200, showing the state in which the furnace opening 221 of the reaction vessel 203 is open.

[0054] Figure 6 (a) is a diagram showing the situation where a thicker crystal film 21 is grown on a seed substrate 20, and (b) is a diagram showing the situation where multiple substrates 10 are obtained by slicing the thicker grown crystal film 21.

[0055] Figure 7 This is a schematic cross-sectional view showing the semiconductor laminate according to the fourth embodiment of the present invention.

[0056] Figure 8 This is a graph showing the relationship between the concentration of electron trap E3 and the carbon concentration.

[0057] Symbol Explanation

[0058] 10. Substrate (nitride crystal substrate)

[0059] 20 seed substrates

[0060] 21 GaN crystal film

[0061] 30 substrate

[0062] 40 Crystal layers (nitride crystal layers) Detailed Implementation

[0063] <Insights gained by the inventor>

[0064] It is believed that in nitride crystals, the presence of impurities other than shallow donors such as silicon (Si), germanium (Ge), and oxygen (O) that provide electrons degrades device performance. Specifically, this can be manifested as reduced carrier mobility, increased diode resistance and decreased voltage withstand, and reduced luminous efficiency. Therefore, it is desirable to minimize the concentration of unintended impurities in nitride crystals.

[0065] Regarding the concentration of this impurity, as described in reference 4, the inventors have successfully achieved a concentration of boron (B), O, carbon (C), etc., in the nitride crystal below 1 × 10⁻⁶ using a novel manufacturing method. 15 cm -3 .

[0066] However, when the electron trap concentration in the nitride crystal described in Reference 4 was measured by isothermal capacitance transient spectroscopy (ICTS), it was determined that electron trap E3 remained at a position approximately 0.6 eV from the conduction band, and the concentration of this E3 was higher than 1 × 10⁻⁶. 14 cm -3 .

[0067] Here, based on recent papers (described later) Figure 8 Narita et al. (2020) reported that E3 originates from iron (Fe) in nitride crystals. According to their paper, if the E3 concentration in nitride crystals is measured using the ICTS method, the Fe concentration in the nitride crystals can be indirectly estimated.

[0068] As described in reference 4 above, the Fe concentration in the nitride crystals grown using the novel manufacturing method is below the lower limit of secondary ion mass spectrometry (SIMS).

[0069] However, as mentioned above, the E3 concentration of the nitride crystals in Document 4, measured according to the ICTS method, is higher than 1 × 10⁻⁶. 14 cm -3 Therefore, when indirectly estimating the Fe concentration in nitride crystals based on this, it can be seen that the nitride crystals in Reference 4 contain Fe slightly below the lower limit of the aforementioned SIMS (2 × 10⁻⁶). 14 cm -3 ~7×10 14 cm -3 (Approximately) Fe.

[0070] Reports on E3 concentration in nitride crystals obtained by existing metal-organic chemical vapor deposition (MOCVD) or hydride vapor phase epitaxy (HVPE) methods (described later) Figure 8 In Tanaka 2616, there is a trade-off between E3 concentration and C concentration. As mentioned above, since the origin of E3 is considered to be Fe, this is equivalent to a trade-off between Fe concentration and C concentration.

[0071] In other words, in existing MOCVD or HVPE methods, a specified amount of Fe and C are present in the crystal growth environment. If conditions that facilitate C uptake in the nitride crystal are chosen, Fe uptake is suppressed. Conversely, if conditions that discourage C uptake in the nitride crystal are chosen, Fe uptake is promoted.

[0072] Specifically, for example, if the concentration of C is 5 × 10⁻⁶ 16 cm -3 If the concentration is around 1, the Fe concentration can be reduced to 1×10⁻⁶. 11 cm -3 Nearby. On the other hand, if the C concentration is reduced to 1×10 15 cm -3 If the concentration is around 1, the Fe concentration may increase to 1 × 10⁻⁶. 15 cm -3 .

[0073] Therefore, nitride crystals with extremely low C and Fe concentrations have not yet been achieved. Specifically, for example, a C concentration below 1 × 10⁻⁶. 15 cm -3 And the Fe concentration is less than 1×10 14 cm -3 The novel manufacturing method described in Reference 4 above is also not feasible for producing nitride crystals.

[0074] Based on the above new understanding, the inventors have conducted intensive research in order to further reduce the concentration of impurities.

[0075] Here, stainless steel components are considered as the source of Fe generation in the MOCVD or HVPE processes, for example. However, the stainless steel reaction chamber in the MOCVD process is typically thoroughly water-cooled. Furthermore, in the HVPE process, for example, an opaque quartz gas supply pipe is used in the middle of a quartz gas supply pipe. This suppresses heating of the stainless steel flange due to thermal radiation. By implementing such countermeasures, overheating of the stainless steel component can be suppressed, and the Fe generation from that component can be inhibited.

[0076] On the other hand, carbon components are used in the high-temperature reaction zones of MOCVD or HVPE devices. Although these carbon components are made of high-purity C, they contain Fe of about 0.06 ppm or less as unavoidable impurities. Therefore, as described in Document 4, the inventors have, for example, provided a heat-resistant protective layer (coating) made of silicon carbide (SiC) on the outer periphery of these carbon components.

[0077] However, under the growth temperature and raw material gas atmosphere of nitride crystals, SiC is sometimes brittle. Therefore, there is a possibility that the protective layer may crack or become porous. Consequently, Fe impurities may leak from the carbon structure into the growth atmosphere through the protective layer.

[0078] Therefore, the inventors investigated coating the surface of carbon components, etc., in the high-temperature reaction zone with a protective layer formed of a ferricyanide complex (chemical formula: Fe4[Fe(CN)6]3) to replace SiC. The results showed that Fe leakage from the components in the high-temperature reaction zone into the growth atmosphere could be suppressed, and the incorporation of Fe into the nitride crystals could be drastically reduced. Furthermore, it was found that by combining the manufacturing method developed by the inventors, which includes a high-temperature baking step, nitride crystals with extremely low C and Fe concentrations could be obtained.

[0079] The following implementation is based on the insights discovered by the inventors.

[0080] <First Embodiment of the Invention>

[0081] Hereinafter, the first embodiment of the present invention will be described with reference to the accompanying drawings.

[0082] (1) Nitride crystal substrate

[0083] use Figure 1 The nitride crystal substrate 10 of this embodiment will be described. Figure 1 (a) is a schematic top view of the nitride crystal substrate 10, and (b) is a schematic side view of the nitride crystal substrate 10.

[0084] like Figure 1 As shown in (a) and (b), the nitride crystal substrate 10 of this embodiment (hereinafter also referred to as substrate 10) is configured as a disc-shaped substrate used in manufacturing the semiconductor stack 1 described later or a semiconductor device. The substrate 10 is made of a single crystal of a group III nitride semiconductor, and in this embodiment, for example, it is made of a single crystal of gallium nitride (GaN).

[0085] The crystal orientation of the principal surface (upper surface) of substrate 10 is, for example, the (0001) plane (+c plane, Ga polar plane). Furthermore, the GaN crystal constituting substrate 10 may also have a predetermined deflection angle relative to the principal surface of substrate 10. The deflection angle refers to the angle between the normal direction of the principal surface of substrate 10 and the principal axis (c-axis) of the GaN crystal constituting substrate 10. Specifically, the deflection angle of substrate 10 is, for example, 0° or more and 1.2° or less.

[0086] Furthermore, the principal surface of substrate 10 is an Epi-ready surface, and the root mean square roughness (RMS) of the principal surface of substrate 10 is, for example, less than 10 nm, preferably less than 1 nm. Also, the "RMS" mentioned here means the RMS measured in a 20 μm angular region using an atomic force microscope (AFM).

[0087] Furthermore, the diameter D of the substrate 10 is not particularly limited, but can be, for example, 25 mm or more. If the diameter D of the substrate 10 is less than 25 mm, the productivity of the semiconductor device is likely to decrease. Therefore, the diameter D of the substrate 10 is preferably 25 mm or more. Additionally, the thickness T of the substrate 10 is, for example, 150 μm or more and 2 mm or less. If the thickness T of the substrate 10 is less than 150 μm, the mechanical strength of the substrate 10 decreases, and it may be difficult to maintain its upright position. Therefore, the thickness T of the substrate 10 is preferably 150 μm or more. Here, for example, the diameter D of the substrate 10 is 2 inches (50.8 mm), and the thickness T of the substrate 10 is 400 μm.

[0088] [Impurity Concentration]

[0089] In this embodiment, as described later, a container with a protective layer formed by a ferricyanide complex in the high-temperature reaction region is used as the reaction vessel, and a high-temperature baking step is performed to manufacture the substrate 10, thereby ensuring that the concentration of each impurity in the GaN crystal constituting the substrate 10 is lower than the measurement limit (detection limit) of SIMS.

[0090] Specifically, the C concentration in the crystal was measured using SIMS with a high-sensitivity, known grating variation method, for example, below 1 × 10⁻⁶. 15 cm -3 .

[0091] Furthermore, the so-called "grating variation method" involves changing the area of ​​the grating scan during the depth profile analysis of SIMS to differentiate the elements contained in the sample from the background energy level of the SIMS device, thereby accurately determining the net concentration of the elements contained in the sample.

[0092] Furthermore, the O concentration in the crystal measured using SIMS with grating variation method is, for example, below 1 × 10⁻⁶. 15 cm -3 .

[0093] Furthermore, the boron concentration in the crystal, measured by depth profile analysis using SIMS, is, for example, below 1 × 10⁻⁶. 15 cm -3 .

[0094] Furthermore, in this embodiment, since Si is not doped as an n-type impurity in the crystal, the Si concentration in the crystal measured by SIMS depth profile analysis is, for example, less than 1 × 10⁻⁶. 15 cm -3 .

[0095] Furthermore, in this embodiment, the Fe concentration in the crystal, like in Reference 4, is below the lower limit of the depth profile analysis using SIMS. However, in the crystal of this embodiment, the Fe concentration estimated based on the electron trap E3 concentration is lower than that in Reference 4. Details regarding this will be described later.

[0096] Furthermore, the crystals of this embodiment are grown using the HVPE method, as described later, rather than using a flux method that uses alkali metals such as sodium (Na) and lithium (Li) as fluxes. Therefore, the crystals of this embodiment do not substantially contain alkali metal elements such as Na and Li.

[0097] Furthermore, in the crystal of this embodiment, none of the elements among arsenic (As), chlorine (Cl), phosphorus (P), fluorine (F), Na, Li, potassium (K), tin (Sn), titanium (Ti), manganese (Mn), chromium (Cr), molybdenum (Mo), tungsten (W), and nickel (Ni) were detected.

[0098] That is, the concentration of these impurities in the crystal is below the lower limit of SIMS. Furthermore, the current lower limits of detection for each element in SIMS are as follows.

[0099] As: 5×10 12 cm -3 ,

[0100] Cl: 1×10 14 cm -3 ,

[0101] P: 2×10 15 cm -3 ,

[0102] F: 4×10 13 cm -3 ,

[0103] Na: 5×10 11 cm -3 ,

[0104] Li: 5×10 11 cm -3 ,

[0105] K: 2×10 12 cm -3 ,

[0106] Sn: 1×10 13 cm -3 ,

[0107] Ti: 1×10 12 cm -3 ,

[0108] Mn: 5×10 12 cm -3 ,

[0109] Cr: 7×10 13 cm -3 ,

[0110] Mo: 1×10 15 cm -3 ,

[0111] W: 3×10 16 cm -3 ,

[0112] Ni: 1×10 14 cm -3

[0113] [Electron trap concentration]

[0114] In this embodiment, as described later, a container with a protective layer formed of ferricyanide complex in the high-temperature reaction region is used as the reaction vessel, and a high-temperature baking step is performed to manufacture the substrate 10, thereby reducing the concentration of electron traps in the crystal.

[0115] Here, using Figure 2 The ICTS method, which is used to measure electron traps, will be explained. Figure 2 This is a diagram illustrating a measurement example using isothermal capacitance transient spectroscopy.

[0116] In the measurement based on the ICTS method, firstly, an ohmic electrode is provided on the back side of the sample, and a Schottky electrode is provided on the surface side of the sample. Specifically, the ohmic electrode on the back side of the substrate 10, which is made of GaN crystal, is, for example, titanium (Ti) / aluminum (Al), and the Schottky electrode on the surface side is, for example, nickel (Ni) / gold (Au).

[0117] After the sample preparation is completed, such as Figure 2 As shown in Figure a, a reverse bias voltage (bias voltage V) is applied in the Schottky junction between the substrate 10 and the Schottky electrode. b ).

[0118] Next, as Figure 2 As shown in b, positive pulses (fill pulses) are overlapped in this Schottky junction. At this time, electrons are captured by electron traps in the GaN crystal constituting the substrate 10.

[0119] Next, as Figure 2 As shown in c, we return to the state where a reverse bias is applied to the Schottky junction. Taking the moment t, when the reverse bias is applied, as 0, we measure the change in junction capacitance C(t) from t=0 using a high-speed transit capacitance meter.

[0120] When the reverse bias is applied (t=0), electrons trapped in trap levels above the Fermi level are emitted to the conduction band. As electrons are emitted after t=0, the depletion layer width gradually decreases, and the junction capacitance C(t) increases.

[0121] The junction capacitance C(t) described above is defined relative to the time-varying ICTS spectrum S(t) by the following equation (i).

[0122]

Equation 1

[0123]

[0124] The ICTS spectrum S(t) shows the thermal emission time constant (τ) at the electron trap energy level. e The corresponding time t=τ e Below, there is a peak.

[0125] Here, the crystal includes multiple electron trap energy levels, and if the thermal emission time constant of the i-th energy level is set as τ... e i Then S(t) is represented by the following equation (ii).

[0126]

Equation 2

[0127]

[0128] Where q is the fundamental charge of the electron, and ε r ε0 is the relative permittivity of the crystal, ε0 is the vacuum permittivity, and V0 is the relative permittivity of the crystal. d It is the diffusion potential, V b It is the bias voltage, A is the junction cross-sectional area, N is the bias voltage, A is the junction cross-sectional area, and N is the junction cross-sectional area. T i It is the concentration (density) of the i-th trap level.

[0129] Each τ e i In the case of full discretization, S(t) at each t=τ e i The spectrum S(t) has peaks. Therefore, based on the peak positions of each electron trap energy level S(t), the thermal emission time constant τ of each electron trap energy level can be calculated. e i By obtaining t = τ in this way e i Substituting into equation (ii), the concentration N of the electron trap can be calculated based on the peak intensities of each peak in the ICTS spectrum S(t). T i .

[0130] In addition, according to the thermal emission time constant τ of each electron trap energy level e i Based on equation (iii), the activation energy ΔE of this energy level can be calculated. i .

[0131]

Equation 3

[0132]

[0133] Where, N c It is the effective density of states in the conduction band, σ n i ν is the capture cross-sectional area of ​​the i-th electron trap. th is the thermal velocity of the electron, g is the degeneracy of the trap, k is the Boltzmann constant, and T is the absolute temperature.

[0134] Here, use Figure 3 The electron traps of the GaN crystal in this embodiment will be explained. Figure 3This is a graph showing the results of measuring the respective electron trap concentrations of the GaN crystal of this embodiment (Si trace-doped sample A4' described later) and the GaN crystal of Reference 4 (Si trace-doped sample B7' described later) by isothermal capacitance transient spectroscopy.

[0135] like Figure 3 As shown, the ICTS spectrum S(t) of the GaN crystal measured by ICTS has multiple peaks corresponding to different energy levels. Among them, the electron traps existing in the energy range of 0.5 eV above and 0.65 eV from the bottom of the conduction band are called "E3", the electron traps existing in the energy range of 0.15 eV above and 0.3 eV from the bottom of the conduction band are called "E1", and the electron traps existing in the energy range of 0.68 eV above and 0.75 eV from the bottom of the conduction band are called "Ex".

[0136] Furthermore, the measurement temperature for the ICTS method is set based on the energy position of each electron trap, for example, within a range of above 80K and below 350K. Figure 3 In this study, the measurement temperature for electron traps E3 and Ex is set to room temperature (300K). On the other hand, the temperature for measuring electron trap E1, which is located at an energy position close to the conduction band, is set to, for example, above 100K and below 150K.

[0137] In the GaN crystal described in Reference 4, the concentration of electron trap E3 is 1 × 10⁻⁶. 14 cm -3 The above (for example, approximately 3 × 10) 14 cm -3 (Approximately). As mentioned above, since E3 originates from Fe, the Fe concentration in the GaN crystal described in Reference 4 is equivalent to 1 × 10⁻⁶. 14 cm -3 above.

[0138] Furthermore, in the GaN crystal described in Reference 4, the concentration of electron trap E1 is higher than 3 × 10⁻⁶. 12 cm -3 .

[0139] Furthermore, in the GaN crystal described in Reference 4, the concentration of electron-trapped Ex is higher than 3 × 10⁻⁶. 13 cm -3 .

[0140] In contrast, in the GaN crystal of this embodiment, the concentration of electron trap E3 is, for example, less than 1 × 10⁻⁶. 14 cm -3 If the Fe concentration in the GaN crystal is estimated indirectly as described above, then the Fe concentration in the GaN crystal of this embodiment is equivalent to being less than 1 × 10⁻⁶. 14 cm-3 .

[0141] Furthermore, in the GaN crystal of this embodiment, the concentration of electron trap E1 is, for example, 3 × 10⁻⁶. 12 cm -3 the following.

[0142] Furthermore, in the GaN crystal of this embodiment, the concentration of the electron trap Ex is, for example, 3 × 10⁻⁶. 13 cm -3 the following.

[0143] Furthermore, in the GaN crystal of this embodiment, since there are no electron traps other than E1, E3, and Ex in the temperature range where ICTS measurements are performed, i.e., between 80 K and 350 K, it can be said that the total concentration of electron traps existing in the energy range of 0.1 eV and 1.0 eV from the conduction band bottom is less than 1 × 10⁻⁶. 14 cm -3 .

[0144] [Relationship between C concentration and E3 concentration]

[0145] In this embodiment, as described later, by using a container with a protective layer formed of a ferricyanide complex in the high-temperature reaction region as the reaction vessel, and by performing a high-temperature baking step to manufacture the substrate 10, both the C concentration and E3 concentration in the crystal, which are in a trade-off relationship as described above, can be reduced. Accordingly, the GaN crystal of this embodiment also satisfies the following requirements.

[0146] That is, the GaN crystal of this embodiment satisfies, for example, the following formulas (1-1) and (1-2).

[0147] [E3] < 1 × 10 14 …(1-1)

[0148] [E3]·[C] 2 ≤1×10 43 …(1-2)

[0149] in,

[0150] [C] indicates that the unit is cm. -3 The concentration of carbon in the crystal.

[0151] [E3] is the concentration of electron trap E3 in the crystal, and the unit of E3 concentration is cm⁻¹. -3 .

[0152] Furthermore, the GaN crystal of this embodiment preferably satisfies, for example, the following formula (2).

[0153] [E3]·[C]2 ≤1×10 42 …(2)

[0154] [Insulation]

[0155] In this embodiment, the concentration of conductive (n-type impurities) in the crystal is extremely low. Therefore, even if the concentrations of C and Fe, which form deep energy levels in the crystal, are low, the substrate 10 can still be configured as a semi-insulating substrate.

[0156] Specifically, the resistivity of the GaN crystal constituting the substrate 10 of this embodiment is, for example, 1 × 10⁻⁶ at a temperature of 20°C or higher and 300°C or lower. 6 For values ​​above Ωcm, under temperature conditions above 300℃ and below 400℃, the value is 1×10⁻⁶. 5 Ωcm or more.

[0157] Furthermore, there is no specific upper limit to the resistivity of GaN crystals; for example, it could be 1 × 10⁻⁶. 10 Approximately Ωcm.

[0158] (2) Manufacturing method of GaN substrate

[0159] Hereinafter, the method for manufacturing the substrate 10 of this embodiment will be specifically described.

[0160] First, refer to Figure 4 The structure of the HVPE apparatus 200 for GaN crystal growth will be described in detail below. The HVPE apparatus 200 includes, for example, a reaction vessel 203 configured as a cylinder. The reaction vessel 203 is a sealed structure to prevent the entry of external atmosphere and gas from the glove-type operating box 220 (described later). Inside the reaction vessel 203, a reaction chamber 201 for crystal growth is formed. Inside the reaction chamber 201, a base 208 is provided to hold a seed substrate 20 composed of a GaN single crystal. The base 208 is connected to a rotation shaft 215 of a rotation mechanism 216 and is configured to rotatably. Furthermore, the base 208 includes an internal heater 210 as a heating element. The temperature of the internal heater 210 is configured to be controllable separately from the area heater 207 (described later). Additionally, the base 208 is covered by a heat-insulating wall 211 on its upstream side and surrounding area. By providing a heat insulation wall 211, gases other than those supplied by nozzles 249a to 249c (described later) will not be supplied to the seed substrate 20.

[0161] The reaction vessel 203 is connected to the glove box 220 via a cylindrical metal flange 219 made of SUS or similar materials. The glove box 220 is also an airtight structure to prevent atmospheric contamination. An exchange chamber 202 located inside the glove box 220 is continuously purged with high-purity nitrogen (hereinafter referred to as N2 gas) to maintain low oxygen and moisture concentrations. The glove box 220 includes: a transparent acrylic wall; multiple rubber gloves connected to holes penetrating the wall; and a transfer box for moving items between the inside and outside of the glove box 220. The transfer box is configured with a vacuum mechanism and an N2 purging mechanism, allowing items to be moved between the inside and outside of the glove box 220 without introducing oxygen-containing atmosphere by replacing the internal atmosphere with N2 gas. When moving items from the reaction vessel 203 to the crystal substrate, as... Figure 5 As shown, the opening of the metal flange 219, i.e., the furnace opening 221, is opened. Thus, by performing the high-temperature baking step described later, it is possible to prevent the surfaces of the components within the reaction vessel 203, which have undergone purification and modification treatment, from being recontaminated, and to prevent atmospheric gases and gases containing the aforementioned impurities from adhering to the surfaces of these components. The impurities referred to here include at least any one of the following: O2 and moisture (H2O) from the atmosphere; organic matter containing C, O, and hydrogen (H), Na, K, etc., from the human body, etc.; As, Cl, P, F, etc., from gases used in crystal growth processes or equipment manufacturing processes, etc.; Fe, Sn, Ti, Mn, Cr, Mo, W, Ni, etc., from metal components within the furnace, etc.

[0162] At one end of the reaction vessel 203, there are gas supply pipes 232a for supplying HCl gas to the gas generator 233a (described later), 232b for supplying ammonia (NH3) gas to the reaction chamber 201, 232c for supplying HCl gas for high-temperature baking and ordinary baking to the reaction chamber 201, and 232d for supplying nitrogen (N2) gas to the reaction chamber 201. Furthermore, gas supply pipes 232a to 232c are configured to supply hydrogen (H2) gas and N2 gas as carrier gases, in addition to HCl and NH3 gas. Gas supply pipes 232a to 232c are configured to each have a flow controller and valve (not shown) for each type of gas, and to control the flow rate and start / stop the supply of each gas. Gas supply pipe 232d is also equipped with a flow controller and valve (not shown). N2 gas supplied from gas supply pipe 232d is used to purge the upstream side and surrounding area of ​​the insulation wall 211 in the reaction chamber 201, thereby maintaining the cleanliness of the atmosphere in these parts.

[0163] The HCl gas supplied from gas supply pipe 232c and the H2 gas supplied from gas supply pipes 232a to 232c serve as cleaning gases to clean the surfaces of the components inside the reaction chamber 201 (especially the inner side of the heat insulation wall 211) during the high-temperature baking and normal baking steps described later. They also function as modifying gases to reduce the probability of releasing impurities from these surfaces. The N2 gas supplied from gas supply pipes 232a to 232c serves to properly clean desired areas inside the reaction chamber 201 (especially the inner side of the heat insulation wall 211) during each baking step by appropriately adjusting the jet flow rates of the HCl gas and H2 gas ejected from the tips of nozzles 249a to 249c.

[0164] The HCl gas introduced from gas supply pipe 232a acts as a reactant gas in the crystal growth step described later. It reacts with the Ga raw material to generate GaCl gas, a Ga halide, also known as the Ga raw material gas. This Ga raw material gas is also referred to as "Group III element raw material gas." The NH3 gas supplied from gas supply pipe 232b acts as a nitriding agent, or N raw material gas, in the crystal growth step described later. It reacts with GaCl gas to grow GaN, a Ga nitride, on the seed substrate 20. Hereinafter, GaCl gas and NH3 gas may be collectively referred to as raw material gases. Furthermore, the H2 and N2 gases supplied from gas supply pipes 232a to 232c function in the crystal growth step described later by appropriately adjusting the jet flow rate of the raw material gases ejected from the tips of nozzles 249a to 249c, directing the raw material gases toward the seed substrate 20.

[0165] Downstream of gas supply pipe 232a, as described above, a gas generator 233a is provided to contain molten Ga, which is a Ga raw material. A nozzle 249a is provided on the gas generator 233a, which supplies GaCl gas, generated by the reaction of HCl gas and molten Ga, to the main surface of the seed substrate 20 held on the base 208. Downstream of gas supply pipes 232b and 232c, nozzles 249b and 249c are provided, which supply various gases supplied by these gas supply pipes to the main surface of the seed substrate 20 held on the base 208. Nozzles 249a to 249c are respectively configured to extend through the upstream side of the heat insulation wall 211.

[0166] Furthermore, the gas supply pipe 232c is configured to supply, in addition to HCl, H2, and N2 gases, as doping gases, also include, for example: ferrocene (Fe(C5H5)2, abbreviated as Cp2Fe) gas or ferric chloride (FeCl3) gas containing Fe; silane (SiH4) gas or dichlorosilane (SiH2Cl2) gas containing Si; magnesium diazocene (Mg(C5H5)2, abbreviated as Cp2Mg) gas containing Mg.

[0167] The gas supply system consists of the gas supply pipes 232a to 232d, the flow controller, the valve, and the nozzles 249a to 249c.

[0168] An exhaust pipe 230 for venting the reaction chamber 201 is provided on a metal flange 219 located at the other end of the reaction vessel 203. An APC valve 244 and a pump 231, serving as pressure regulators, are sequentially provided on the exhaust pipe 230, starting from the upstream side. Alternatively, a blower with a pressure regulating mechanism can be used instead of the APC valve 244 and pump 231.

[0169] Around the outer periphery of the reaction vessel 203, a zone heater 207 is provided as a heating unit to heat the reaction chamber 201 to the desired temperature. The zone heater 207 consists of at least two heaters, one on the upstream side including a gas generator 233a and the other on the downstream side including a base 208. Each heater has a temperature sensor and a temperature regulator (not shown) that can be individually adjusted in the range of room temperature to 1200°C.

[0170] The base 208 holding the seed substrate 20, as described above, differs from the zone heater 207 in that it is equipped with an internal heater 210, a temperature sensor 209, and a temperature regulator (not shown) to enable temperature regulation within a range of at least room temperature to 1600°C. Furthermore, the upstream side and surrounding area of ​​the base 208, as described above, are surrounded by a heat insulation wall 211. The inner peripheral surface of the heat insulation wall 211, at least the surface facing the base 208, must be made of a specific material that does not produce impurities, as described later. However, for the other surfaces (outer peripheral surfaces), there are no limitations on the material used, as long as it can withstand temperatures above 1600°C. The heat insulation wall 211, excluding the inner peripheral surface, can be made of, for example, a non-metallic material with high heat resistance such as carbon, silicon carbide (SiC), or tantalum carbide (TaC), or a metallic material with high heat resistance such as Mo and W. It can also be a structure formed by a laminated plate-like reflector. By adopting such a structure, even when the temperature of the base 208 is 1600°C, the external temperature of the heat insulation wall 211 can be suppressed to below 1200°C. Since this temperature is below the softening point of quartz, quartz can be used in this structure for the components that constitute the reaction vessel 203, the gas generator 233a, and the upstream portion of the gas supply pipes 232a to 232d.

[0171] Within the reaction chamber 201, there is a region that is heated to above 900°C during the crystal growth step described later, which is a region (high-temperature reaction region) 201a that can come into contact with the gas supplied to the seed substrate 20.

[0172] Here, in this embodiment, at least a portion of the surface of the component constituting the high-temperature reaction region 201a has, for example, a protective layer (not shown) formed of a ferricyanide complex (chemical formula: Fe4[Fe(CN)6]3).

[0173] Ferric cyanide complexes, also known as Prussian blue or iron blue, are raw materials for blue pigments. However, in ferric cyanide complexes, the Fe atoms and cyanide ions are extremely firmly bonded, making the complexes very difficult to decompose. Furthermore, while cyanides are generally considered to be toxic, the bond between Fe and cyanide ions in the ferric cyanide complex is extremely stable, so the ferric cyanide complex itself is non-toxic. This strong bond between Fe atoms and cyanide ions inhibits the separation of Fe from the ferric cyanide complex and suppresses the incorporation of Fe into the GaN crystal caused by the ferric cyanide complex itself.

[0174] Based on the stable properties of the ferricyanide complex described above, by coating the surface of the component constituting the high-temperature reaction region 201a with a protective layer formed of the ferricyanide complex, the protective layer formed by the ferricyanide complex can be stably maintained even under conditions of GaN crystal growth temperature and high-temperature baking step, and under the atmosphere of raw material gas. That is, it can suppress the formation of cracks in the protective layer and prevent the protective layer from becoming porous.

[0175] However, if the protective layer formed by the ferricyanide complex is directly coated onto the components composed of carbon or the like that constituting the high-temperature reaction zone 201a, the protective layer may crack due to physical impact.

[0176] Therefore, in this embodiment, it is preferable to provide a base layer (buffer layer, adhesive reinforcement layer) between the main body of the component constituting the high-temperature reaction region 201a and the protective layer. For example, SiC can be used as a material for the base layer. By placing such a base layer between the main body and the protective layer, the protective layer can be firmly bonded to the main body of the component constituting the high-temperature reaction region 201a via the base layer. As a result, the strength of the protective layer can be ensured.

[0177] Among the components constituting the high-temperature reaction zone 201a, the parts for which the aforementioned protective layer is provided include, for example, the inner wall of the heat insulation wall 211 upstream of the base 208, the portion of the nozzles 249a to 249c that penetrates into the inner side of the heat insulation wall 211, the portion of the outer side of the heat insulation wall 211 that is heated to 900°C or higher during the crystal growth step, and the surface of the base 208.

[0178] The thickness of the protective layer is not limited, for example, it can be 30 μm or more and 300 μm or less. By making the protective layer thickness 30 μm or more, the durability of the protective layer can be ensured. By making the protective layer thickness 300 μm or less, cracks in the protective layer caused by the difference in thermal expansion coefficients between the substrate material and the protective layer during temperature rise and fall can be suppressed. Similarly, the thickness of the base layer is not limited, for example, it can be 30 μm or more and 200 μm or less. By making the base layer thickness 30 μm or more, the adhesion of the base layer can be ensured. By making the base layer thickness 200 μm or less, cracks in the base layer caused by the difference in thermal expansion coefficients between the substrate material and the base layer during temperature rise and fall can be suppressed.

[0179] The various components of the HVPE device 200 described above, such as the various valves and flow controllers of the gas supply pipes 232a to 232d, the pump 231, the APC valve 244, the zone heater 207, the internal heater 210, the temperature sensor 209, etc., are respectively connected to the controller 280, which is a computer.

[0180] Next, while referring to Figure 4The following is a detailed description of an example of epitaxial growth of GaN single crystals on a seed substrate 20 using the HVPE apparatus 200 described above. In the following description, the operation of each part constituting the HVPE apparatus 200 is controlled by the controller 280.

[0181] (High-temperature baking step)

[0182] This step is performed when the reaction chamber 201 and exchange chamber 202 are exposed to the atmosphere due to maintenance of the HVPE apparatus 200 or the addition of Ga raw material to the gas generator 233a. Before performing this step, it is confirmed that the reaction chamber 201 and exchange chamber 202 are airtight. After confirming the airtightness, the reaction chamber 201 and exchange chamber 202 are purged with N2 gas respectively. Under the condition that the reaction vessel 203 is in a specified atmosphere, the surfaces of various components constituting the reaction chamber 201 are heated. This treatment is performed without the seed substrate 20 being added to the reaction vessel 203, and with Ga raw material being added to the gas generator 233a.

[0183] In this step, the temperature of the zone heater 207 is adjusted to the same level as that of the crystal growth step. Specifically, the temperature of the heater upstream of the gas generator 233a is set to 700–900°C, and the temperature of the heater downstream of the substrate 208 is set to 1000–1200°C. Furthermore, the temperature of the internal heater 210 is set to a predetermined temperature of 1500°C or higher. As described later, during crystal growth, the internal heater 210 is turned off or set to a temperature below 1200°C, thus the temperature of the high-temperature reaction zone 201a is 900°C or higher and below 1200°C. On the other hand, in the high-temperature baking step, the temperature of the internal heater 210 is set to 1500°C or higher, the temperature of the high-temperature reaction zone 201a is 1000–1500°C or higher, the area near the substrate 208 on which the seed substrate 20 is placed reaches a high temperature of 1500°C or higher, and even at other locations, the temperature is at least 100°C higher than that in the crystal growth step. Within the high-temperature reaction zone 201a, the area with the lowest temperature of 900°C during the crystal growth step—specifically, the area upstream of nozzles 249a-249c inside the heat insulation wall 211—is where adhering impurity gases are most difficult to remove. To ensure this area's temperature is at least 1000°C, the internal heater 210 is set at 1500°C or higher. This effectively achieves the purification and modification treatment described later, i.e., reducing impurities in the grown GaN crystal. If the internal heater 210's temperature is below 1500°C, the temperature at any point within the high-temperature reaction zone 201a cannot be sufficiently increased, making it difficult to achieve the purification and modification treatment described later, i.e., reducing impurities in the GaN crystal.

[0184] The upper limit of the temperature of the internal heater 210 in this step depends on the capacity of the heat insulation wall 211. As long as the temperature of the quartz parts, etc., on the outside of the heat insulation wall 211 can be kept below their heat resistance temperature, the higher the temperature of the internal heater 210, the easier it is to achieve the purification and modification treatment effect within the reaction chamber 201. When the temperature of the quartz parts, etc., on the outside of the heat insulation wall 211 exceeds their heat resistance temperature, the maintenance frequency and cost of the HVPE device 200 increase.

[0185] In this step, after the zone heater 207 and the internal heater 210 reach their respective predetermined temperatures, H2 gas is supplied from gas supply pipes 232a and 232b at a flow rate of approximately 3 slm, for example. Additionally, HCl gas is supplied from gas supply pipe 232c at a flow rate of approximately 2 slm, and H2 gas is supplied at a flow rate of approximately 1 slm. Furthermore, N2 gas is supplied from gas supply pipe 232d at a flow rate of approximately 10 slm. Then, by maintaining this state for a predetermined time, baking is performed within the reaction chamber 201. By ensuring that the supply of H2 and HCl gas begins at the aforementioned time, starting from the temperature rise within the reaction chamber 201, the amount of gas flowing ineffectively and not contributing to the subsequent purification and modification processes can be reduced, thereby lowering the processing cost of crystal growth.

[0186] Furthermore, in the high-temperature baking step of this embodiment, it is preferable not to supply O2 gas. That is, it is preferable not to perform the "oxidation sequence" of supplying O2 gas as described in Document 4. If O2 gas is supplied, the ferricyanide complex will be oxidized, which may make the protective layer fragile. In contrast, not supplying O2 gas, that is, performing the high-temperature baking step in a gas atmosphere that intentionally does not contain O2 gas, can suppress the oxidation of the ferricyanide complex and suppress the fragility of the protective film.

[0187] Furthermore, this step is performed with pump 231 operating. At this time, by adjusting the opening of APC valve 244, the pressure inside reaction vessel 203 is maintained at, for example, between 0.5 atmospheres and 2 atmospheres. By performing this step through venting from reaction vessel 203, impurities can be removed from reaction vessel 203, i.e., the reaction vessel 203 is effectively cleaned. Also, if the pressure inside reaction vessel 203 is below 0.5 atmospheres, the cleaning and modification treatments described later will be difficult to achieve. Furthermore, if the pressure inside reaction vessel 203 is above 2 atmospheres, the components inside reaction chamber 201 will suffer excessive etching damage.

[0188] Furthermore, in this step, the partial pressure ratio of HCl gas to H2 gas (partial pressure of HCl / partial pressure of H2) within the reaction vessel 203 is set, for example, to a value between 1 / 50 and 1 / 2. If the aforementioned partial pressure ratio is less than 1 / 50, the purification and modification effects within the reaction vessel 203 will be difficult to achieve. Conversely, if the aforementioned partial pressure ratio is greater than 1 / 2, the components within the reaction chamber 201 will suffer excessive etching damage.

[0189] Furthermore, this pressure control can be achieved through flow regulation by the flow controller located in the gas supply pipes 232a to 232c.

[0190] This step, for example, is performed for a period of 30 minutes to 300 minutes, thereby cleaning the surfaces of various components constituting at least the high-temperature reaction zone 201a within the reaction chamber 201 and removing foreign matter adhering to these surfaces. Then, by maintaining the surfaces of these components at a temperature at least 100°C higher than the temperature in the crystal growth step described later, the release of impurity gases from these surfaces is promoted, modifying them into surfaces where the release of impurities such as Si, B, Fe, O, and C is difficult to occur under the temperature and pressure conditions of the crystal growth step (surfaces where outgassing is difficult to occur). Furthermore, if this step is performed for less than 30 minutes, the cleaning and modification effects described here may be insufficient. Additionally, if this step is performed for more than 300 minutes, excessive damage to the components constituting the high-temperature reaction zone 201a may occur.

[0191] Furthermore, when supplying H2 gas and HCl gas into reaction vessel 203, NH3 gas is not supplied into reaction vessel 203. If NH3 gas is supplied into reaction vessel 203 in this step, it will be difficult to achieve the above-mentioned purification and modification effects, especially the modification effect.

[0192] Alternatively, when supplying H2 or HCl gas into reaction vessel 203, a halogen gas such as chlorine (Cl2) can be supplied instead of HCl gas. In this case, the purification and modification effects described above can also be obtained.

[0193] In addition, when supplying H2 or HCl gas into the reaction vessel 203, N2 gas can also be added as a carrier gas from the gas supply pipes 232a to 232c. By adding N2 gas, the flow rate of the gas from the nozzles 249a to 249c can be adjusted, thereby preventing incomplete purification and modification treatments as described above. Furthermore, rare gases such as Ar or He can be supplied instead of N2 gas.

[0194] After the above-described purification and modification treatments are completed, the output power of the zone heater 207 is reduced to cool the reaction vessel 203 to a temperature, for example, below 200°C, at which point the seed substrate 20, etc., can be introduced into the reaction vessel 203. Furthermore, the supply of H2 and HCl gases to the reaction vessel 203 is stopped, and it is purged with N2 gas. After purging of the reaction vessel 203, while maintaining the supply of N2 gas to the reaction vessel 203, the opening of the APC valve 244 is adjusted to maintain the pressure inside the reaction vessel 203 at atmospheric pressure or a pressure slightly higher than atmospheric pressure.

[0195] (Standard baking steps)

[0196] The aforementioned high-temperature baking step is performed with the reaction chamber 201 and exchange chamber 202 exposed to the atmosphere. However, during the crystal growth step, typically, including before and after it, the reaction chamber 201 and exchange chamber 202 are not exposed to the atmosphere, so a high-temperature baking step is unnecessary. However, during the crystal growth step, GaN polycrystals adhere to the surfaces of nozzles 249a-249c, the surface of the substrate 208, the inner wall of the heat insulation wall 211, etc. If the subsequent crystal growth step is performed with GaN polycrystal residue remaining, GaN polycrystal powder and Ga droplets scattered from the polycrystals through separation, etc., adhere to the seed substrate 20, becoming a cause of hindering good crystal growth. Therefore, after the crystal growth step, a normal baking step is performed to remove the aforementioned GaN polycrystals. The processing sequence and conditions of the normal baking step are as follows: the internal heater 210 is turned off, and the temperature near the substrate 208 is set to 1000-1200°C; otherwise, it is the same as the high-temperature baking step. GaN polycrystalline material can be removed from reaction chamber 201 by performing a standard baking process.

[0197] (Crystal growth steps)

[0198] After the high-temperature baking step or the normal baking step has been performed, and after the cooling and purging of the reaction vessel 203 has been completed, as follows: Figure 5 As shown, the furnace opening 221 of the reaction vessel 203 is opened, and the seed substrate 20 is placed on the base 208. The furnace opening 221 is isolated from the atmosphere and connected to a glove box 220 that has been continuously purged with N2 gas. The glove box 220, as described above, has transparent acrylic walls, multiple rubber gloves connected to holes in the through walls, and a transfer box for moving items between the inside and outside of the glove box 220. By replacing the atmosphere inside the transfer box with N2 gas, items can be moved between the inside and outside of the glove box 220 without introducing atmospheric gas into it. By using such a mechanism to place the seed substrate 20, recontamination of the components within the reaction vessel 203, which has undergone purification and modification treatment through a high-temperature baking step, and re-attachment of impurity gases to these components can be prevented. Furthermore, the surface of the seed substrate 20 placed on the base 208, namely the main surface (crystal growth surface, substrate surface) opposite to the nozzles 249a to 249c, is, for example, the (0001) surface of the GaN crystal, namely the +c surface (Ga polarity surface).

[0199] After the seed substrate 20 is placed into the reaction chamber 201, the furnace opening 221 is closed. While heating and venting the reaction chamber 201, H2 gas, or a combination of H2 and N2 gas, is supplied into the reaction chamber 201. Then, with the reaction chamber 201 at the desired processing temperature and pressure, and with the desired atmosphere, HCl and NH3 gases are supplied from the gas supply pipes 232a and 232b, respectively, to the surface of the seed substrate 20. Thus, as... Figure 6 As shown in the cross-sectional view of (a), GaN crystals are epitaxially grown on the surface of the seed substrate 20 to form a GaN crystal film 21.

[0200] Furthermore, in this step, to prevent thermal decomposition of the GaN crystal constituting the seed substrate 20, it is preferable to start supplying NH3 gas into the reaction chamber 201 when the temperature of the seed substrate 20 reaches 500°C or before. Additionally, to improve the in-plane thickness uniformity of the GaN crystal film 21, it is preferable to perform this step while the substrate 208 is rotated.

[0201] In this step, the temperature of the zone heater 207 is preferably set to, for example, 700–900°C for the heater upstream of the gas generator 233a, and to, for example, 1000–1200°C for the heater downstream of the base 208. Thus, the temperature of the base 208 is adjusted to a predetermined crystal growth temperature of 1000–1200°C. In this step, the internal heater 210 can also be used in a turned-off state, but temperature control can be implemented using the internal heater 210 only when the temperature of the base 208 is within the aforementioned range of 1000–1200°C.

[0202] Other processing conditions for this step are illustrated below.

[0203] Processing pressure: 0.5–2 atm

[0204] Partial pressure of GaCl gas: 0.1~20kPa

[0205] Partial pressure of NH3 gas / partial pressure of GaCl gas: 1~100

[0206] Partial pressure of H2 gas / partial pressure of GaCl gas: 0~100

[0207] Furthermore, when supplying GaCl gas and NH3 gas to the surface of the seed substrate 20, N2 gas can also be added as a carrier gas from the gas supply pipes 232a to 232c. By adding N2 gas, the jet flow rate of the gas supplied from the nozzles 249a to 249c can be adjusted, thereby appropriately controlling the distribution of the raw material gas supply on the surface of the seed substrate 20 and achieving a uniform growth rate distribution over the entire in-plane area. Alternatively, rare gases such as Ar or He gas can be supplied instead of N2 gas.

[0208] (Steps to move it out)

[0209] After growing a GaN crystal film 21 of desired thickness on the seed substrate 20, NH3 and N2 gases are supplied to the reaction chamber 201. Meanwhile, after the reaction chamber 201 has been vented, the supply of HCl and H2 gases, as well as heating by the zone heater 207, is stopped. Then, the temperature inside the reaction chamber 201 is cooled to below 500°C, and the supply of NH3 gas is stopped. The atmosphere inside the reaction chamber 201 is then replaced with N2 gas to restore it to atmospheric pressure. Next, the temperature inside the reaction chamber 201 is cooled to, for example, below 200°C, the temperature at which the GaN ingot (the seed substrate 20 on which the GaN crystal film 21 is formed) can be removed from the reaction vessel 203. Subsequently, the ingot is removed from the reaction chamber 201 via a glove-operated box 220 and a transfer box.

[0210] (Slicing steps)

[0211] Subsequently, by slicing the removed ingot, for example, parallel to the growth plane, it is possible to achieve... Figure 6 As shown in (b), one or more substrates 10 are obtained. This slicing process can be performed, for example, using a wire saw or an electrical discharge machining (EDM) machine. Then, a prescribed grinding process is performed on the surface (+c surface) of the substrate 10 to make it an Epi-ready mirror surface. Furthermore, the back surface (-c surface) of the substrate 10 is a polished or mirror surface.

[0212] Furthermore, the execution order of the aforementioned high-temperature baking step, ordinary baking step, crystal growth step, and removal step is preferably as follows: that is, when n is an integer of 1 or more, for example, it is preferably performed in the following order: exposure of reaction chamber 201 and exchange chamber 202 to the atmosphere → high-temperature baking step → crystal growth step → removal step → (ordinary baking step → crystal growth step → removal step) × n.

[0213] (3) Effects obtained from this embodiment

[0214] According to this embodiment, one or more of the following effects can be obtained.

[0215] (a) In this embodiment, by coating at least a portion of the surface of the component constituting the high-temperature reaction region 201a with a protective layer formed of a ferricyanide complex (chemical formula: Fe4[Fe(CN)6]3), leakage of Fe from the component constituting the high-temperature reaction region 201a into the growth atmosphere can be suppressed, and the incorporation of Fe into the GaN crystal can be drastically reduced. Furthermore, by combining the manufacturing method with a high-temperature baking step developed by the inventors, GaN crystals with extremely low C concentration and electron trap E3 concentration equivalent to Fe concentration can be obtained.

[0216] Specifically, it enables the C concentration in crystals measured using SIMS with grating variation method to be below 1 × 10⁻⁶. 15 cm -3 Furthermore, the concentration of electron trap E3 in the GaN crystal is reduced to below 1×10⁻⁶. 14 cm -3 Preferably, it is less than 2×10 13 cm -3 .

[0217] Furthermore, the GaN crystal in this embodiment satisfies the above formula (1-1) "[E3]<1×10 14 And it also satisfies equation (1-2) "[E3]·[C]". 2 ≤1×10 43 Preferably, it satisfies the above formula (2) "[E3]·[C]". 2 ≤1×10 42 ".

[0218] Thus, by manufacturing GaN crystals using the above method, both the reported trade-off between C concentration and electron trap E3 concentration can be drastically reduced.

[0219] As a result, the GaN crystal of this embodiment has excellent crystal quality, such as significantly reduced impurity concentration and trap concentration, compared to existing GaN crystals with high C concentration and E3 concentration.

[0220] Furthermore, when a semiconductor device is fabricated using a substrate 10 obtained by slicing the GaN crystal of this embodiment, compared to the case where a substrate composed of a conventional GaN crystal with a high C concentration and E3 concentration is used, device degradation caused by impurity diffusion or instability in device operation caused by charging and discharging from impurity traps can be suppressed.

[0221] (b) In this embodiment, the reaction vessel 203 is a container in which at least a portion of the surface of the component constituting the high-temperature reaction zone 201a has a protective layer formed by a ferricyanide complex. Based on the stable properties of the ferricyanide complex, the protective layer formed by the ferricyanide complex can be stably maintained even under conditions of GaN crystal growth temperature, high-temperature baking step temperature, and raw material gas atmosphere. That is, the occurrence of cracks in the protective layer can be suppressed, and the protective layer can be prevented from becoming porous. Therefore, impurities such as Fe can be prevented from leaking from the component constituting the high-temperature reaction zone 201a, made of carbon or the like, into the growth atmosphere.

[0222] Furthermore, during the high-temperature baking step, while heating the temperature of the high-temperature reaction zone 201a to a temperature of 1506°C or higher, H2 gas and halogen gas are supplied to the reaction vessel 203, but NH3 gas is not supplied. This allows for the surface purification and modification of the components constituting the high-temperature reaction zone 201a. Specifically, it promotes the release of impurity gases from the surface of the components constituting the high-temperature reaction zone 201a, modifying it into a surface where the release of impurities such as C is difficult to occur under the temperature and pressure conditions of the crystal growth step (a surface where gas release is difficult).

[0223] As a result, in the GaN crystal of this embodiment, both the C concentration and the electron trap E3 concentration, which is equivalent to the Fe concentration, can be drastically reduced.

[0224] (c) In this embodiment, the GaN crystal manufactured by the above-described manufacturing method can drastically reduce the impurity concentration, thereby improving the crystal quality of the GaN crystal. This not only reduces the concentration of electron trap E3 in the GaN crystal, but also reduces the concentration of other electron traps.

[0225] Specifically, the concentration of electron trap E1 can be made 3 × 10⁻⁶. 12 cm -3 The concentration of the electron trap Ex is then set to 3 × 10⁻⁶. 13 cm -3 Furthermore, the origins of these E1 and Ex traps are currently unclear. However, by using the protective layer of this embodiment, the concentrations of E1 and Ex can be reduced respectively. Therefore, it can be considered that E1 and Ex, like the E3 trap, are impurity-related traps caused by the matrix material of the component constituting the high-temperature reaction region 201a.

[0226] Thus, by reducing the concentration of various electron traps occurring in GaN crystals, it is possible to prevent equipment instability caused by the charging and discharging of electron traps.

[0227] (d) In this embodiment, by manufacturing GaN crystals according to the above-described manufacturing method, the concentration of impurities other than C in the GaN crystal can be drastically reduced. Specifically, the O concentration in the crystal, as measured by SIMS using the grating variation method, can be reduced to below 1 × 10⁻⁶. 15 cm -3 Furthermore, it enables the B concentration in crystals measured by SIMS depth profiling to be below 1 × 10⁻⁶. 15 cm -3 .

[0228] (e) The GaN crystal obtained in this embodiment has high purity as described above, and therefore has a resistivity of 1×10⁻⁶ at temperatures above 20°C and below 300°C. 6 High insulation properties exceeding Ωcm are achieved. Furthermore, when GaN crystals contain a large amount of donor impurities such as Si and O, methods are known to improve the insulation of the crystal, such as those disclosed in Japanese Patent Application Publication No. 2007-534580, which involves adding donor compensation impurities (hereinafter referred to as compensation impurities) such as Mn, Fe, Cobalt (Co), Ni, and Copper (Cu) to the crystal. However, a problem with this method is that the addition of compensation impurities easily degrades the quality of the GaN crystal. For example, if compensation impurities are added to the GaN crystal, the substrate obtained by slicing the crystal is prone to cracking. Additionally, because the compensation impurities diffuse into the stacked structure formed on the substrate, the characteristics of semiconductor devices fabricated using this substrate are easily degraded. In contrast, in the GaN crystal of this embodiment, high insulation properties can be obtained without adding compensation impurities, thus avoiding the problem of crystallinity degradation that easily causes problems in existing methods.

[0229] (d) The insulation of the GaN crystal obtained by this embodiment is stable with low temperature dependence compared to the insulation obtained by adding compensating impurities to the crystal. This is believed to be because, for example, at a temperature of 1 × 10⁻⁶, the insulation is stable. 17 cm -3 The GaN crystals containing Si and O at the above concentrations appear to possess insulation properties similar to those of the GaN crystal in this embodiment if Fe is added at a higher concentration. However, the energy level of Fe, used as a compensating impurity, is relatively shallow, around 0.6 eV. Therefore, the insulation properties obtained by adding Fe tend to decrease with increasing temperature, compared to the insulation properties of the GaN crystal in this embodiment.

[0230] In contrast, according to this embodiment, insulation can be achieved without adding compensating impurities, thus avoiding the problem of increased temperature dependence that is prone to cause problems in existing methods.

[0231] (e) The GaN crystal obtained by this embodiment, as described above, is of high purity. Therefore, when the crystal is made into an n-type semiconductor by Si ion implantation or formed into a p-type semiconductor by Mg ion implantation, the amount of ion implantation can be kept low. That is, the GaN crystal of this embodiment can provide the desired semiconductor characteristics while suppressing the reduction in crystal quality caused by ion implantation as much as possible, which is more advantageous than existing GaN crystals containing more impurities such as Fe. In addition, since the concentration of impurities, which is a factor in charge carrier scattering, is extremely low in the GaN crystal of this embodiment, the reduction in charge carrier mobility can be avoided, which is also more advantageous than existing GaN crystals containing more impurities.

[0232] <Second Embodiment of the Invention>

[0233] Next, the second embodiment of the present invention will be described focusing on the points that differ from the first embodiment.

[0234] The GaN crystal in this embodiment has extremely low C concentration and electron trapping E3 concentration, similar to the first embodiment, but the Si concentration is 1×10⁻⁶. 15 cm -3 This differs from the first embodiment in that respect. The GaN crystal of this embodiment, by containing Si at such a concentration, has a resistivity of 1×10⁻⁶ at a temperature of 20°C or higher and 300°C or lower. 2 With conductivity below Ωcm, it functions as a so-called n-type semiconductor crystal. Furthermore, the Si concentration can be, for example, 1 × 10⁻⁶. 15 cm -3 Above and 5×10 19 cm -3 The following values ​​apply. In this case, the free electron concentration (n-type carrier concentration) at temperatures above 20°C and below 300°C is, for example, 1 × 10⁻⁶. 15 cm -3 Above and 5×10 19 cm -3 The resistivity under the same temperature conditions is, for example, 1 × 10⁻⁶. -4 Above Ωcm and below 100Ωcm.

[0235] In the GaN crystal of this embodiment, the Si concentration is approximately equal to the free electron concentration. This indicates that the actual concentration of impurities other than Si that serve as carrier sources (Fe and C to compensate for free electrons, or O as donors, etc.) is extremely small, and the minimum Si concentration in this embodiment is 1 × 10⁻⁶. 15 cm -3 In comparison, it is contained in GaN crystals to a negligible degree.

[0236] The addition of Si to the GaN crystal can be achieved by simultaneously supplying a Si-containing gas, such as SiH4 gas or SiH2Cl2 gas, to the seed substrate 20 along with the raw material gas (GaCl gas + NH3 gas) during the crystal growth step described above. The partial pressure ratio of the Si-containing gas to the Group III raw material gas within the reaction vessel 203 (partial pressure of the Si-containing gas / total partial pressure of the GaCl gas) can, for example, be 1 / 10. 8 ~1 / 10 3 The size. In addition, the addition of Si to the GaN crystal can also be performed by implanting Si ions into the substrate 10 after obtaining the substrate 10 by the same method as in the first embodiment.

[0237] The GaN crystal obtained by this embodiment has extremely low concentrations of B, Fe, O, and C, similar to those of the GaN crystal in the first embodiment. Therefore, it exhibits superior quality compared to conventional GaN crystals that contain more of these impurities. Furthermore, according to this embodiment, since the impurity concentrations, such as Fe, estimated based on the concentration of electron trap E3 in the GaN crystal, are as low as described above, the desired conductivity (n-type semiconductor characteristics) can be imparted to the GaN crystal even with minimal Si addition. In other words, the GaN crystal of this embodiment effectively suppresses the reduction in crystal quality caused by Si addition while providing the desired semiconductor characteristics, which is advantageous compared to conventional GaN crystals that contain more impurities such as Fe and C. Additionally, since the concentration of impurities, which are a factor in carrier scattering, is extremely low in the GaN crystal of this embodiment, a decrease in carrier mobility can be avoided, which is advantageous compared to conventional GaN crystals that contain more impurities.

[0238] Furthermore, the GaN crystal obtained by this embodiment has extremely low concentrations of impurities such as Fe and C that compensate for n-type conductivity, similar to those in the GaN crystal of the first embodiment. Therefore, compared with more existing GaN crystals containing these impurities, it can improve the uniformity of carrier concentration.

[0239] For example, when growing GaN crystals on a GaN substrate with a +c plane as the surface and an angular distribution, the amount of Fe and C incorporated into the GaN crystal depends on the angular distribution. Therefore, when a large amount of Fe or C is incorporated into the GaN crystal, the resulting GaN crystal will have a deviation of tens of percent or more in the free electron concentration within the wafer plane. For example, at Shiojima 2019 (described later), when the angular distribution of a 2-inch substrate was approximately 0.3°, the in-plane effective carrier concentration was 5 × 10⁻⁶. 15 cm -3 ~8×10 15 cm-3 The range of variation. As a dispersion of carrier concentration measured over the entire in-plane range, it is equivalent to a deviation of more than 15% of the average value.

[0240] In contrast, the GaN crystal of this embodiment has a very low concentration of impurities such as Fe and C, which compensate for n-type conductivity, just like the GaN crystal of the first embodiment. Therefore, even if the surface of the GaN crystal constituting the seed substrate 20 has a large skew angle distribution, a uniform carrier concentration distribution can still be easily obtained.

[0241] Specifically, for example, if substrate 10 is a GaN substrate of 25 mm or larger (2 inches, 4 inches, or 6 inches), and the radially measured angular distribution of substrate 10 (the maximum difference between the angular differences measured at any two points within a distance of 80% of the radial radius from the center) is less than 0.4°, then if the average carrier concentration (average free electron concentration) in the plane of substrate 10 is 1 × 10⁻⁶, 15 cm -3 The above can make the carrier concentration dispersion less than 3% of the average value.

[0242] Furthermore, the GaN crystal of this embodiment has an extremely low concentration of impurities, which is a factor in carrier scattering, thus suppressing the decrease in carrier mobility. This is advantageous compared to existing GaN crystals that contain more impurities. For example, the electron concentration in the GaN crystal of this embodiment is 2 × 10⁻⁶. 15 cm -3 At the following time, 1500cm can be obtained at room temperature. 2 A migration rate of / Vs or higher.

[0243] Furthermore, it can be confirmed that as an n-type dopant, the same effect can be obtained even when Ge replaces Si or when both Si and Ge are used. In these cases, the combined concentration of Si and Ge in the crystal is, for example, 1 × 10⁻⁶. 15 cm -3 The preferred value is 5×10. 19 cm -3 the following.

[0244] <Modifications of the Second Embodiment of the Invention>

[0245] In the second embodiment described above, by further reducing the amount of Si-containing gas supplied during the crystal growth step, the free electron concentration can also be made to be 1×10⁻⁶. 14 cm -3 Above and below 1×10 15 cm -3However, in this case, because the Si concentration in the crystal cannot be measured, the current estimate of the Si concentration can only be stated as being below 1 × 10⁻⁶. 15 cm -3 Alternatively, as an n-type dopant, Ge can be used instead of Si, or both Si and Ge can be used.

[0246] <Third Embodiment of the Invention>

[0247] Next, the third embodiment of the present invention will be described focusing on the points that differ from the first embodiment.

[0248] The GaN crystal in this embodiment has extremely low C concentration and electron-trapping E3 concentration, similar to the first embodiment, but it also contains Mg with a concentration of 3 × 10⁻⁶. 18 cm -3 The above differs from the first embodiment in that respect. The GaN crystal of this embodiment, by containing Mg at such a concentration, exhibits a resistivity of less than 1×10⁻⁶ at temperatures between 20°C and 300°C. 2 With a conductivity of Ωcm, it functions as a so-called p-type semiconductor crystal. Furthermore, the Mg concentration can be, for example, 1 × 10⁻⁶. 17 cm -3 Above and 5×10 20 cm -3 The following size. In this case, the hole (p-type carrier) concentration at temperatures above 20°C and below 300°C is, for example, 5 × 10⁻⁶. 15 cm -3 Above and 5×10 18 cm -3 The resistivity under the same temperature conditions is, for example, 0.5 Ωcm or more and 100 Ωcm or less.

[0249] The addition of Mg to the GaN crystal can be carried out by simultaneously supplying a Mg-containing gas, such as Cp2Mg gas, to the seed substrate 20 along with the raw material gas (GaCl gas + NH3 gas) during the crystal growth step described above. The partial pressure ratio of the Mg-containing gas to the Group III raw material gas in the reaction vessel 203 (partial pressure of Mg-containing gas / total partial pressure of GaCl gas) can, for example, be 1 / 10. 5 ~1 / 10 2The size of the doping gas. Furthermore, the addition of Mg to the GaN crystal can be achieved by using a gas containing magnesium nitride (Mg3N2) or metallic Mg instead of Cp2Mg gas. These gases, for example, can be positioned in a high-temperature region of approximately 800°C along the gas supply pipe 232c to generate vapors of these substances. Additionally, the addition of Mg to the GaN crystal can also be performed by implanting Mg ions into the substrate 10 after obtaining the substrate 10 using the same method as in the first embodiment. Similar to the second embodiment, when using a doping gas, Mg can be added uniformly throughout the thickness direction of the GaN crystal, and it is advantageous in that damage to the crystal surface caused by ion implantation is easily avoided. Furthermore, when using ion implantation, it is advantageous in that the C component contained in the Cp2Mg gas is easily avoided from mixing into the crystal, i.e., the C concentration in the GaN crystal is increased.

[0250] The GaN crystal obtained in this embodiment has extremely low concentrations of Si, B, Fe, O, and C, similar to those in the GaN crystal of the first embodiment. Therefore, it exhibits superior quality compared to existing GaN crystals containing more of these impurities. Furthermore, according to this embodiment, since the concentrations of impurities such as Si and O in the GaN crystal are as low as described above, the desired conductivity (p-type semiconductor characteristics) can be imparted to the GaN crystal even with minimal Mg addition. In other words, the GaN crystal of this embodiment effectively suppresses the reduction in crystal quality caused by Mg addition while providing the desired semiconductor characteristics, which is advantageous compared to existing GaN crystals containing more impurities such as Si and O. Additionally, since the concentration of impurities, which are factors contributing to carrier scattering, is extremely low in the GaN crystal of this embodiment, a decrease in carrier mobility can be avoided, which is advantageous compared to existing GaN crystals containing more impurities. For example, the hole concentration in the GaN crystal of this embodiment is 1 × 10⁻⁶. 18 cm -3 At that time, it was possible to obtain 20cm at room temperature. 2 A migration rate of / Vs or higher.

[0251] <Fourth Embodiment of the Invention>

[0252] Next, the fourth embodiment of the present invention will be described focusing on points that differ from the first embodiment.

[0253] In this embodiment, the GaN crystal is not formed as a substrate 10, but rather forms at least a crystal layer 40 of the semiconductor stack 1, which is different from the first embodiment.

[0254] Figure 7 This is a schematic cross-sectional view showing the semiconductor stack of this embodiment.

[0255] like Figure 7 As shown, the semiconductor stack 1 of this embodiment has, for example, a substrate 30 and a crystal layer 40.

[0256] The substrate 30 serves as the base substrate for the epitaxial growth of the crystal layer 40.

[0257] Examples of substrates 30 include sapphire substrates, SiC substrates, and nitride crystal substrates. When substrate 30 is a nitride crystal substrate, substrate 30 may be composed of any one of the GaN crystals in embodiments 1 to 3.

[0258] A crystal layer 40 is disposed on the substrate 30 and is composed of any one of the GaN crystals described in the first to third embodiments above. That is, the C concentration in the crystal constituting the crystal layer 40 is less than 1 × 10⁻⁶. 15 cm -3 Furthermore, the concentration of electron trap E3 in the crystal is less than 1 × 10⁻⁶. 14 cm -3 Furthermore, the crystals constituting crystal layer 40 satisfy the above equation (1-1) "[E3]<1×10 14 And it also satisfies equation (1-2) "[E3]·[C]". 2 ≤1×10 43 ".

[0259] For example, by arbitrarily combining and stacking (bonding) any of the following crystals: the semi-insulating crystal shown in the first and second embodiments, the n-type crystal shown in the third embodiment, and the p-type crystal shown in the fourth embodiment, various semiconductor devices can be manufactured.

[0260] For example, in a semiconductor stack 1 used to manufacture a pn junction diode, for example, the substrate 30 is made of an n-type GaN crystal of the second embodiment, and the crystal layer 40 is made of a p-type GaN crystal of the third embodiment.

[0261] For example, in a semiconductor stack 1 used to manufacture a Schottky barrier diode, for example, a substrate 30 is formed of an n-type GaN crystal with high carrier concentration according to the second embodiment, and a crystal layer 40 is formed of an n-type GaN crystal with low carrier concentration according to the second embodiment.

[0262] For example, in a semiconductor stack 1 used to manufacture a high electron mobility transistor (HEMT), the substrate 30 may be a semi-insulating SiC substrate or a substrate made of a semi-insulating GaN crystal as in the first embodiment. For example, the crystal layer 40 may be composed of an electron transport layer made of an GaN crystal as in the first embodiment and an electron supply layer made of an aluminum gallium nitride (AlGaN) crystal manufactured in the same manner as in the first embodiment.

[0263] Furthermore, when forming p-type GaN crystals and n-type GaN crystals, as mentioned above, Si and Mg can be added to the crystal using doping gases, or Si and Mg ion implantation can be performed on semi-insulating GaN crystals.

[0264] Alternatively, a nucleation layer (not shown) may be disposed between the substrate 10 and the crystal layer 40, for example. The nucleation layer may also be composed of aluminum nitride (AlN).

[0265] According to this embodiment, the crystal layer 40 is formed by the high-quality GaN crystal of the above embodiment, which can improve the device performance of the semiconductor device obtained from the semiconductor laminate 1.

[0266] <Other embodiments of the present invention>

[0267] The embodiments of the present invention have been described above in detail. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from its spirit.

[0268] (a) This invention is not limited to GaN, but also includes, for example, group III nitride crystals such as aluminum nitride (AlN), aluminum gallium nitride (AlGaN), indium nitride (InN), indium gallium nitride (InGaN), and aluminum indium gallium nitride (AlInGaN), i.e., In... x Al y Ga 1-x-y The formula for N (where 0≤x≤1, 0≤y≤1, 0≤x+y≤1) is also suitable for crystal growth.

[0269] (b) In the above embodiments, the ICTS method is described as a method for measuring the concentration of electron trap E3, etc., but the method for measuring electron traps is not limited to the ICTS method. Any other measurement method may be used as long as it can be measured.

[0270] (c) In the above embodiments, a method for separating the substrate 10 by slicing a thick ingot grown on a seed substrate 20 composed of GaN single crystals has been described, but this method is not limited to this. For example, the substrate 10 can also be manufactured by the so-called VAS (Void-Assisted Separation) method. That is, a GaN layer on a heterogeneous substrate as described in Document 2 can be formed as a base layer, and a thick GaN layer can be grown using a nanomask or the like composed of titanium nitride (TiN), and then peeled off from the heterogeneous substrate to remove the crystals grown on the small facets of the heterogeneous substrate side, thereby obtaining the substrate 10.

[0271] (d) The crystal growth steps of the present invention are not limited to the methods shown in the above embodiments, and the following methods may also be used in combination.

[0272] For example, by optimizing the size and shape of the gas generator to ensure a long residence (contact) time (e.g., more than 1 minute) of HCl gas on the Ga molten metal, the impurity concentration contained in the GaCl gas can be further reduced. Alternatively, for example, a nanomask made of TiN or the like, with numerous micropores having an impurity-trapping effect, can be formed on a seed substrate, and GaN crystals can be grown on it. Furthermore, for example, during crystal growth on the seed substrate, the growth period for facets other than the c-plane, where impurities are easily introduced, can be shortened. When performing facet growth on the seed substrate as described above, it is preferable to grow a relatively thick GaN layer, peel it off from the seed substrate, and remove the facet-grown crystal from the off-substrate side to obtain substrate 10.

[0273] According to the methods described in embodiments 1 to 3, the monomers described above can significantly reduce the impurity concentration in GaN crystals. However, by further combining these auxiliary methods described herein, the impurity concentration in the crystals can be reduced more reliably. However, without performing a high-temperature baking step, and only combining these auxiliary methods, the various effects shown in the embodiments described above cannot be achieved.

[0274] (e) In the above embodiments, the case of growing GaN crystals using the HVPE apparatus 200 has been described, but it is not limited to this case; an MOCVD apparatus can also be used. That is, as an MOCVD apparatus, an apparatus that has a protective layer formed by a ferricyanide complex on at least a portion of the surface of the component constituting the high-temperature reaction region can be used, and GaN crystals can also be grown by performing the above-described high-temperature baking step.

[0275]

Example

[0276] The following describes the experimental results that confirm the effectiveness of the above-described embodiments.

[0277] (1) Samples of GaN crystal substrate

[0278] Using an HVPE apparatus, GaN crystal films were grown on GaN seed substrates with a diameter of 3 inches and a surface composed of +c planes under the following growth conditions, thereby fabricating GaN crystal substrates of samples A1–A5 and B1–B10. Impurity doping will be discussed later.

[0279] (Samples A1 to A5)

[0280] Among samples A1 to A5, samples A3 and A4 are equivalent to substrates made of GaN crystals as described in the above embodiments.

[0281] In samples A1 to A5, an HVPE apparatus was used, which had a protective layer formed by a ferrocyanine complex on the surface of the carbon component constituting the high-temperature reaction zone. In samples A1 to A4, a high-temperature baking step was performed without an oxidation sequence supplied with O2 gas before the crystal growth step. The high-temperature baking temperatures for samples A1 to A4 were 1100°C, 1400°C, 1500°C, and 1600°C, respectively. The pressure condition was 1 atmosphere. For sample A5, the high-temperature baking step was not performed. Next, a 5 mm thick GaN crystal was grown on a seed substrate in the reaction chamber without atmospheric release. Afterward, the outer diameter of the GaN crystal was ground to adjust its outer diameter, and a 400 μm thick substrate was sliced. The substrate had a diameter of 2 inches or more.

[0282] (Samples B1~B10)

[0283] Samples B1 to B10 are respectively equivalent to samples 8 to 17 in reference 4.

[0284] In samples B1 to B10, an HVPE apparatus was used, which had a protective layer formed of SiC on the surface of the components constituting the high-temperature reaction region. In samples B1 to B4, the same high-temperature baking step as in samples A1 to A4 was performed before the crystal growth step. In samples B5 to B9, a high-temperature baking step involving alternating oxidation and etching sequences supplied with O2 gas was performed before the crystal growth step. The high-temperature baking temperatures for samples B5 to B9 were 1100°C, 1400°C, 1500°C, 1550°C, and 1600°C, respectively. The pressure condition was 1 atmosphere for all samples. For sample B10, no high-temperature baking step was performed. Next, a 5 mm thick GaN crystal was grown on a seed substrate in the reaction chamber without atmospheric release. Subsequently, a 400 μm thick substrate was sliced ​​from the GaN crystal.

[0285] (Regarding impurity doping)

[0286] Initially, all the above-described samples were prepared without impurity doping, and then subjected to SIMS-based impurity analysis and conductivity confirmation as described later. The impurity concentrations listed in Tables 1-3 are the measurement results for samples without impurity doping.

[0287] On the other hand, in the absence of impurity doping, if the GaN crystal film is of high purity, it exhibits high resistance. Therefore, electrical property measurements such as those using the ICTS method cannot be performed on samples with high resistance. Therefore, regarding measurements based on the ICTS method, the sample is prepared and evaluated according to its conductivity as follows.

[0288] Among the undoped samples, for samples that do not have high resistance, the measurements based on the ICTS method, which will be described later, are performed on the undoped samples themselves.

[0289] In contrast, among the undoped samples, measurements based on the ICTS method cannot be performed on samples A3, A4, A5, B3, B4, and B7–B10, which have high resistance. Therefore, excluding samples with a resistance of 1×10⁻⁶… 16 cm -3 Apart from the point where Si is intentionally gas-doped to impart n-type conductivity, a separate sample is prepared under the same growth conditions as the undoped sample. Hereinafter, this sample will be numbered with an apostrophe and referred to as "Si trace-doped sample A3'", etc. After sample preparation, measurements based on the ICTS method, described later, are performed on Si trace-doped samples A3', A4', A5', B3', B4', B7' to B10'.

[0290] Here, in the Si micro-doped samples A3', A4', A5', B3', B4', B7' to B10', even if a trace amount of Si is doped by Si-containing gas (SiH2Cl2 gas), it is considered that there is almost no situation where Fe originates from the Si-containing gas and mixes into the GaN crystal. As mentioned above, since the origin of E3 is Fe, if the Si doping is removed and the same growth conditions are applied, it is considered that there is no difference in electron trap concentration between the undoped sample and the Si micro-doped sample.

[0291] Therefore, the measurement results of Si micro-doped samples A3', A4', A5', B3', B4', B7' to B10' are recorded in the columns of samples A3, A4, A5, B3, B4, B7 to B10 in Tables 1 to 3, respectively.

[0292] (2) Evaluation

[0293] The following evaluation was performed on the GaN crystal substrate of the above-mentioned sample.

[0294] (SIMS)

[0295] The Si, B, and Fe concentrations in each crystal were measured using in-depth profiling analysis with SIMS.

[0296] In addition, the O and C concentrations in each crystal were measured using SIMS with grating variation method.

[0297] (ICTS Law)

[0298] As described above, measurements based on the ICTS method are performed on the conductivity of the undoped samples. Specifically, for low-resistance samples A1, A2, B1, B2, B5, and B6, measurements based on the ICTS method are performed directly. On the other hand, for high-resistance samples A3, A4, A5, B3, B4, and B7 to B10, measurements based on the ICTS method are performed on Si-trace doped samples A3', A4', A5', B3', B4', and B7' to B10', and these measurement results are used as the evaluation results for samples A3, A4, A5, B3, B4, and B7 to B10.

[0299] As a result, in each crystal, the concentrations of electron trap E3, which exists in the energy range from the bottom of the conduction band to above 0.5 eV and below 0.65 eV, electron trap E1, which exists in the energy range from the bottom of the conduction band to above 0.15 eV and below 0.3 eV, and electron trap Ex, which exists in the energy range from the bottom of the conduction band to above 0.68 eV and below 0.75 eV, were measured.

[0300] In ICTS measurements, the measurement temperature is adjusted within a range above 80K and below 350K by incorporating the time constant of the thermionic emission of the target trap into the measurable time range (0.01 seconds to 1000 seconds). For example, in Figure 3 In the measurement, the measurement temperature for electron traps E3 and Ex is set to room temperature (300K). On the other hand, the temperature for measuring electron trap E1, which is located near the energy position of the conduction band, is set, for example, to be above 100K and below 150K. In addition, the reverse bias voltage for ICTS measurement is set to -2V, and the fill pulse is set to 100ms at 0V.

[0301] Furthermore, in measurements based on the ICTS method, the ohmic electrode on the back side of the sample is Ti / Al, and the Schottky electrode on the surface side is Ni / Au.

[0302] (3) Results

[0303] The evaluation results for GaN crystal substrates of samples A1–A5 and B1–B10 are shown in Tables 1–3 below. Furthermore, the term "(lower limit)" in the tables indicates the detection limit for each evaluation; results below this detection limit are described as "DL".

[0304] Table 1

[0305]

[0306] Table 2

[0307]

[0308] Table 3

[0309]

[0310] (Samples B1~B10)

[0311] In samples B1 to B10, as described above, a protective layer is formed on the surface of the high-temperature reaction region by SiC. Among them, the O and C concentrations are high in sample B10, which did not undergo a high-temperature baking step; samples B1 to B4, which did not undergo a high-temperature baking step; and samples B5 and B6k, which underwent an oxidation step but had a high-temperature baking temperature below 1506°C.

[0312] In addition, the concentration of B was high in sample B10, which did not undergo the high-temperature baking step.

[0313] In addition, samples B1, B2, B5, and B6, which were baked at temperatures below 1500°C, had high Si concentrations.

[0314] In contrast, samples B7 to B9, which underwent high-temperature baking steps including oxidation at temperatures above 1500°C, showed that the concentrations of Si, B, O, and C were below the detection limit, i.e., below 1 × 10⁻⁶. 15 cm -3 .

[0315] Furthermore, in samples B1 to B10, the Fe concentrations measured by depth profile analysis using SIMS were all below the detection limit.

[0316] However, when measured using the ICTS method in samples B1 to B10, the concentration of electron trap E3 in each sample B1 to B10 was 2.0 × 10⁻⁶. 14 cm -3 The above. Since the origin of electron trap E3 is Fe, the Fe concentration in samples B1–B10, based on the E3 concentration, is 2.0 × 10⁻⁶. 14 cm -3 above.

[0317] In addition, the concentrations of electron trap E1 and electron trap Ex in samples B1–B10 are 2 × 10⁻⁶. 13 cm -3 Above, 1×10 14 cm -3 above.

[0318] In samples B1 to B10, because the protective layer of SiC constitutes the high-temperature reaction region, the protective layer becomes fragile under the growth temperature of the GaN crystal and the atmosphere of the raw material gas. Therefore, it can be assumed that trace amounts of Fe, as impurities, leak from the carbon components constituting the high-temperature reaction region. Therefore, it is believed that the concentration of electron trap E3 cannot be reduced. Furthermore, since these impurities cause a slight decrease in the crystal quality of the GaN crystal, it is believed that electron traps E1 or Ex occur in the crystal. Additionally, since impurities other than Fe also occur from the carbon components, it is believed that electron traps E1 and Ex are introduced into the crystal.

[0319] The above results indicate that, in samples B1 to B10 based on the technology described in Reference 4, it is impossible to reduce both the C concentration and the electron trap E3 concentration, which are in a trade-off relationship.

[0320] (Samples A1 to A5)

[0321] In samples A1 to A5, as described above, a protective layer on the surface of the high-temperature reaction zone is formed by a ferricyanide complex. Among them, in sample A5, which did not undergo a high-temperature baking step, and in samples A1 and A2, where the high-temperature baking temperature was lower than 1500°C, the concentrations of O and C were high.

[0322] Furthermore, in sample A5, which did not undergo a high-temperature baking step, the B concentration was high. Additionally, in samples A1 and A2, where the high-temperature baking temperature was below 1500°C, the Si concentration was high.

[0323] In contrast, samples A3 and A4, which have a protective layer on the surface of the high-temperature reaction region composed of ferricyanide complexes and have undergone a high-temperature baking step at temperatures above 1500°C without oxidation, can achieve Si and B concentrations below the detection limit, i.e., below 1×10⁻⁶. 15 cm -3 It can also reduce O and C concentrations to below 1×10⁻⁶. 15 cm -3 In particular, in sample A4, which underwent a high-temperature baking step at 1600℃, the O concentration was able to be lower than the lower limit of the grating variation method, i.e., lower than 5 × 10⁻⁶. 14 cm -3 This also allows the C concentration to be close to the lower limit of the grating variation method, which is 1.1 × 10⁻⁶. 14 cm -3 .

[0324] Furthermore, in the Si micro-doped samples A3' and A4', the electron trap E3 concentration of the crystal, as measured by the ICTS method, can be lower than 1 × 10⁻⁶. 14 cm -3 In particular, in the Si micro-doped sample A4', the concentration of electron trap E3 can be reduced to below 2 × 10⁻⁶. 13 cm-3 .

[0325] Here, in this experiment, the source of Fe generation, which is the cause of electron trap E3, is considered to be the carbon components in the high-temperature reaction region. However, in samples A3 and A4, the generation of Fe from the carbon components in the high-temperature reaction region is suppressed by the ferricyanide complex coating. At this point, it can be considered that Fe generation is suppressed regardless of whether Si doping is present.

[0326] That is, the concentration of electron trap E3 is reduced in the Si trace doped samples A3' and A4'. Therefore, the concentration of electron trap E3 in samples A3 and A4, which are prepared under the same conditions except that they are not doped with Si, should also be reduced. Furthermore, it can be considered that it is even lower than that in the Si trace doped samples A3' and A4'.

[0327] Based on the above results regarding the electron trapping E3 concentrations of Si trace-doped samples A3' and A4', the electron trapping E3 concentrations of samples A3 and A4 are less than 1 × 10⁻⁶. 14 cm -3 Furthermore, the concentration of electron trap E3 in samples A3 and A4 was confirmed to be below 2 × 10⁻⁶. 13 cm -3 .

[0328] Furthermore, since E3 originates from Fe, it can be confirmed, based on the E3 concentration, in samples A3 and A4, that the Fe concentration can be reduced to below 1 × 10⁻⁶. 14 cm -3 .

[0329] Furthermore, based on the concentrations of electron traps E1 and Ex in the Si micro-doped samples A3' and A4', it can be confirmed that the concentration of electron trap E1 can be 3 × 10⁻⁶ in samples A3 and A4. 12 cm -3 The concentration of the electron trap Ex is then set to 3 × 10⁻⁶. 13 cm -3 the following.

[0330] Thus, in samples A3 and A4, it was confirmed that both the reported C concentration and the electron trap E3 concentration, which were in a trade-off relationship, could be reduced sharply at the same time.

[0331] Here, refer to Figure 8 The relationship between the C concentration and the electron trap E3 concentration of samples A3 and A4 is explained. Figure 8 This is a graph showing the relationship between the concentration of electron trap E3 and the carbon concentration. Also, Figure 8 The so-called "pE+q" for each axis means p×10 q .

[0332] exist Figure 8 In this context, "sample A3 and A4 series" refers to the results of samples A3 and A4 obtained based on Si micro-doped samples A3' and A4', and also to the results of samples whose growth conditions have been evolved from those of samples A3 and A4 within the scope of satisfying the requirements of the above-described embodiments.

[0333] In addition, Figure 8 The data presented in the paper or patent document is considered as prior art.

[0334] [Honda 2012]

[0335] Honda, Shiojima JJAP 51(2012)04DF04

[0336] [Shio Jima 2019]

[0337] Shiojima et al.,Phys.Status Solidi B 2019, 1900561

[0338] [Tanaka 2016]

[0339] T.Tanaka,K.Shio jima,T.Mishima,Y.Tokuda,Jpn.J.Appl.Phys.55,061101(2016)

[0340] [Horikiri 2018]

[0341] Japanese Patent Application Publication No. 2020-35980

[0342] [Zhang 2020]

[0343] Zhang et al., J.Appl.Phys.127, 215707(2020)

[0344] [Tokuda 2016]

[0345] Yutaka Tokuda,ECS Transactions,75(4)39-49(2016)

[0346] [Kanegae 2019]

[0347] Kanegae et al.,Appl.Phys.Lett.115,012103(2019)

[0348] [Narita 2020]

[0349] Narita et al.,Jpn.J.Appl.Phys.59,105505(2020)

[0350] in addition, Figure 8 In the text, “Equation(1-1)”, “Equation(1-2)”, and “Equation 2” respectively represent [E3] = 1 × 10 14 [E3]·[C] 2 =1×10 43 [E3]·[C] 2 =1×10 42 .

[0351] like Figure 8 As shown, in the prior art, it is confirmed once again that the C concentration and the electron trap E3 concentration in GaN crystals are in a trade-off relationship.

[0352] Furthermore, data from existing papers and patent documents do not show a reduction in both the C concentration and the electron trapping E3 concentration in GaN crystals. Specifically, data from existing papers and patent documents indicate that [E3] ≥ 1 × 10⁻⁶. 14 , or [E3]·[C] 2 >1×10 43 .

[0353] In contrast, in samples A3 and A4, and equivalent samples, it was confirmed that both the above equation (1-1) "[E3]<1×10" could be satisfied. 14 ", and can also satisfy equation (1-2) "[E3]·[C" 2 ≤1×10 43 Preferably, it satisfies the above formula (2) "[E3]·[C]". 2 ≤1×10 42 ".

[0354] Furthermore, in samples A3 and A4, since there were no electron traps other than E1, E3, and Ex within the temperature range where ICTS measurements were performed (i.e., above 80 K and below 350 K), it can be confirmed that the total concentration of electron traps existing in the energy range of 0.1 eV above and 1.0 eV below the conduction band bottom is less than 1 × 10⁻⁶. 14 cm -3 .

[0355] As described above, it can be confirmed that samples A3 and A4, and equivalent samples, which meet the requirements of the above-described embodiments, can achieve very high-quality GaN crystals that are not achievable by the prior art.

[0356] (4) Supplement

[0357] In the above experiments, the electron trap concentrations of samples A3 and A4 were estimated based on the measurement results of the electron trap concentrations in the Si micro-doped samples A3' and A4', but this is not limited to this case.

[0358] For example, for samples A3 and A4, which originally had high resistance, respectively, with 1×10 16 cm -3 When Si is intentionally implanted with ions, the concentration can be directly measured by the ICTS method in samples A3 and A4, respectively.

[0359] In this case, it can also be confirmed that in samples A3 and A4, where Si underwent micro-ion implantation, the concentration of electron trap E3 can be reduced to below 2 × 10⁻⁶. 13 cm -3 This keeps the concentration of electron trap E1 at 3 × 10⁻⁶. 12 cm -3 The concentration of electron trap Ex is then set at 3 × 10⁻⁶. 13 cm -3 the following.

[0360] <Preferred embodiments of the present invention>

[0361] The preferred embodiments of the present invention are described below.

[0362] (Note 1)

[0363] A nitride crystal, made from In x Al y Ga 1-x-y The crystal represented by the formula N (where 0≤x≤1, 0≤y≤1, 0≤x+y≤1) is where,

[0364] The carbon concentration in the crystal is less than 1×10⁻⁶. 15 cm -3 ,

[0365] The concentration of electron trap E3 in the crystal, existing in the energy range of 0.5 eV above and 0.65 eV from the bottom of the conduction band, is less than 1 × 10⁻⁶. 14 cm -3 .

[0366] (Note 2)

[0367] According to the nitride crystal described in Note 1, wherein equation (1-2) is satisfied,

[0368] [E3]·[C] 2 ≤1×10 43 …(1-2)

[0369] in,

[0370] [C] indicates that the unit is cm. -3 The concentration of carbon in the crystal,

[0371] [E3] sets the unit to cm. -3 The E3 concentration in the crystal.

[0372] (Note 3)

[0373] A nitride crystal, made from In x Al y Ga 1-x-y The crystal represented by the composition formula of N (where 0≤x≤1, 0≤y≤1, 0≤x+y≤1), wherein,

[0374] Satisfying equations (1-1) and (1-2),

[0375] [E3] < 1 × 10 14 …(1-1)

[0376] [E3]·[C] 2 ≤1×10 43 …(1-2)

[0377] in,

[0378] [C] indicates that the unit is cm. -3 The concentration of carbon in the crystal,

[0379] [E3] is the concentration of electron trap E3 present in the crystal within the energy range of 0.5 eV above and 0.65 eV from the bottom of the conduction band, and the unit of E3 concentration is cm⁻¹. -3 .

[0380] (Note 4)

[0381] According to the nitride crystal described in Note 2 or 3, the following equation (2) is satisfied.

[0382] [E3]·[C] 2 ≤1×10 42 …(2)

[0383] (Note 5)

[0384] According to any one of Notes 1 to 4, the concentration of electron trap E1 present in the crystal in the energy range of 0.15 eV to 0.3 eV from the bottom of the conduction band is 3 × 10⁻⁶. 12 cm -3 the following.

[0385] (Note 6)

[0386] According to any one of Notes 1 to 5, the concentration of electron traps Ex in the crystal, existing in the energy range of 0.68 eV and 0.75 eV from the bottom of the conduction band, is 3 × 10⁻⁶. 13 cm -3 the following.

[0387] (Note 7)

[0388] The nitride crystal according to any one of Notes 1 to 6, wherein the E3 concentration in the crystal is less than 2 × 10⁻⁶. 13 cm -3 .

[0389] (Note 8)

[0390] According to any one of Notes 1 to 7, the nitride crystal wherein the boron concentration in the crystal is less than 1 × 10⁻⁶. 15 cm -3 .

[0391] (Note 9)

[0392] According to any one of Notes 1 to 8, the nitride crystal has an oxygen concentration of less than 1 × 10⁻⁶. 15 cm -3 .

[0393] (Note 10)

[0394] According to any one of Notes 1 to 9, the nitride crystal wherein the total concentration of electron traps present in the crystal in the energy range of 0.1 eV to 1.0 eV from the bottom of the conduction band is less than 1 × 10⁻⁶. 14 cm -3 .

[0395] (Note 11)

[0396] The nitride crystal according to any one of Notes 1 to 10, wherein the silicon concentration in the crystal is less than 1 × 10⁻⁶. 15 cm -3 .

[0397] (Note 12)

[0398] According to any one of Notes 1 to 11, the resistivity of the nitride crystal at a temperature of 20°C or higher and 300°C or lower is 1 × 10⁻⁶. 6 Ωcm or more.

[0399] (Note 13)

[0400] According to the nitride crystal described in Note 12, the resistivity at temperatures above 20°C and below 300°C is 1×10⁻⁶.7 Ωcm or more.

[0401] (Note 14)

[0402] According to any one of the nitride crystals in Notes 1 to 10, wherein the combined concentration of Si and Ge in the crystal is 1 × 10⁻⁶. 15 cm -3 The preferred value is 5×10. 19 cm -3 the following.

[0403] (Note 15)

[0404] According to the nitride crystal described in Note 14, the resistivity at temperatures above 20°C and below 300°C is 1×10⁻⁶. 2 Below Ωcm, preferably 1×10 -4 Ωcm or more,

[0405] Furthermore, a free electron concentration of 1×10⁻⁶ is preferably achieved under temperature conditions above 20°C and below 300°C. 15 cm -3 Above and 5×10 19 cm -3 the following.

[0406] (Note 16)

[0407] The nitride crystal according to any one of Notes 1 to 10, wherein the Mg concentration in the crystal is 1 × 10⁻⁶. 17 cm -3 The above. Preferably, it is 5×10. 20 cm -3 the following.

[0408] (Note 17)

[0409] According to the nitride crystal described in Note 16, the resistivity at temperatures above 20°C and below 300°C is 1×10⁻⁶. 2 Below Ωcm. Preferably, it is between 0.5Ωcm and 100Ωcm.

[0410] The preferred hole concentration is 2×10⁻⁶ under temperature conditions above 20°C and below 300°C. 17 cm -3 Above and 5×10 18 cm -3 the following.

[0411] (Note 18)

[0412] A semiconductor laminate having:

[0413] Substrate,

[0414] and disposed on the substrate, comprising In x Al y Ga 1-x-y The nitride crystal layer of the crystal represented by the formula of N (where 0≤x≤1, 0≤y≤1, 0≤x+y≤1),

[0415] The carbon concentration in the nitride crystal layer is less than 1 × 10⁻⁶. 15 cm -3 ,

[0416] The concentration of electron trap E3 in the crystal, existing in the energy range of 0.5 eV above and 0.65 eV from the bottom of the conduction band, is less than 1 × 10⁻⁶. 14 cm -3 .

[0417] (Note 19)

[0418] A semiconductor laminate having:

[0419] Substrate,

[0420] and disposed on the substrate, comprising In x Al y Ga 1-x-y The nitride crystal layer of the crystal represented by the formula of N (where 0≤x≤1, 0≤y≤1, 0≤x+y≤1),

[0421] The nitride crystal layer satisfies equations (1-1) and (1-2).

[0422] [E3] < 1 × 10 14 …(1-1)

[0423] [E3]·[C] 2 ≤1×10 43 …(1-2)

[0424] in,

[0425] [C] indicates that the unit is cm. -3 The concentration of carbon in the nitride crystal layer,

[0426] [E3] is the concentration of electron trap E3 present in the crystal within the energy range of 0.5 eV above and 0.65 eV from the bottom of the conduction band, and the unit of E3 concentration is cm⁻¹. -3 .

[0427] (Note 20)

[0428] A method for manufacturing a nitride crystal, comprising the following steps:

[0429] The process of preparing a reaction vessel to house the substrate;

[0430] For the substrate heated to a specified growth temperature within the reaction vessel, a Group III element feedstock gas and a nitrogen feedstock gas are supplied to allow In to grow. x Al y Ga 1-x-y The process of epitaxially growing a nitride crystal on the substrate, represented by the formula of N (where 0≤x≤1, 0≤y≤1, 0≤x+y≤1).

[0431] The process of preparing the reaction vessel includes the following steps:

[0432] The process of preparing a container as the reaction vessel includes a region heated to the growth temperature, i.e., a high-temperature reaction region in contact with a gas supplied to the substrate, and at least a portion of the surface of the components constituting the high-temperature reaction region having a protective layer formed of a ferricyanide complex.

[0433] In the high-temperature baking process, the temperature of the high-temperature reaction zone is heated to a temperature of over 1500°C while hydrogen and halogen gases are supplied to the reaction vessel, but the nitrogen raw material gas is not supplied to the reaction vessel, thereby cleaning and modifying the surface of the components constituting the high-temperature reaction zone.

[0434] (Note 21)

[0435] According to the method for manufacturing nitride crystals described in Note 20, during the high-temperature baking process, the pressure inside the reaction vessel is maintained at a pressure of 0.5 atmospheres or more and 2 atmospheres or less.

[0436] Furthermore, it is preferable that during the high-temperature baking process, the temperature of at least the high-temperature reaction zone within the reaction vessel is maintained at a temperature above 1500°C.

[0437] Alternatively, the high-temperature baking process is preferably carried out while the air inside the reaction vessel is being vented.

[0438] In addition, it is preferable that the high-temperature baking process be carried out for more than 30 minutes.

[0439] (Note 22)

[0440] A nitride crystal manufacturing apparatus, comprising:

[0441] Reaction vessel containing substrate;

[0442] Heating at least the heating section of the substrate within the reaction vessel;

[0443] For the substrate within the reaction vessel, a gas supply system for supplying Group III element raw material gas and nitrogen raw material gas;

[0444] For the substrate heated to a specified growth temperature within the reaction vessel, the group III element feedstock gas and the nitrogen feedstock gas are supplied to allow In... x Al y Ga 1-x-y The method of epitaxial growth of nitride crystals on the substrate, represented by the formula of N (where 0≤x≤1, 0≤y≤1, 0≤x+y≤1), and the control unit of the heating section and the gas supply system.

[0445] The reaction vessel has a region heated to the growth temperature, i.e., a high-temperature reaction region in contact with the gas supplied to the substrate.

[0446] At least a portion of the surface of the component constituting the high-temperature reaction zone has a protective layer formed of a ferricyanide complex.

[0447] Before the nitride crystal is epitaxially grown, the control unit performs a high-temperature baking process, heating the temperature of the high-temperature reaction zone to a temperature of 1500°C or higher, while supplying hydrogen and halogen gases into the reaction vessel, but not supplying the nitrogen raw material gas into the reaction vessel, thereby cleaning and modifying the surface of the components constituting the high-temperature reaction zone.

Claims

1. A nitride crystal, made from In x Al y Ga 1－x－y The crystal represented by the compositional formula of N, wherein, 0≤x≤1, 0≤y≤1, 0≤x+y≤1, The carbon concentration in the crystal is less than 1×10⁻⁶. 15 cm －3 , The concentration of electron trap E3 in the crystal, existing in the energy range of 0.5 eV above and 0.65 eV from the bottom of the conduction band, is less than 1 × 10⁻⁶. 14 cm －3 , Furthermore, equation (1-2) is satisfied. [E3]·[C] 2 ≤1×10 43 …(1-2) in, [C] is the unit to be cm －3 The concentration of carbon in the crystal, [E3] is to make the unit cm －3 The E3 concentration in the crystal.

2. The nitride crystal according to claim 1, wherein, It satisfies the following equation (2). [E3]·[C] 2 ≤1×10 42 …(2)。 3. The nitride crystal according to claim 1, wherein, The concentration of electron trap E1 in the crystal, existing in the energy range of 0.15 eV above and 0.3 eV below the conduction band bottom, is 3 × 10⁻⁶. 12 cm －3 the following.

4. The nitride crystal according to claim 1, wherein, The concentration of electron traps Ex in the crystal, existing in the energy range of 0.68 eV above and 0.75 eV from the bottom of the conduction band, is 3 × 10⁻⁶. 13 cm －3 the following.

5. The nitride crystal according to claim 1, wherein, The E3 concentration in the crystal is less than 2 × 10⁻⁶. 13 cm －3 .

6. The nitride crystal according to claim 1, wherein, The boron concentration in the crystal is less than 1×10⁻⁶. 15 cm －3 .

7. The nitride crystal according to claim 1, wherein, The oxygen concentration in the crystal is less than 1 × 10⁻⁶. 15 cm －3 .

8. The nitride crystal according to claim 1, wherein, The total concentration of electron traps in the crystal within the energy range of 0.1 eV above and 1.0 eV from the bottom of the conduction band is less than 1 × 10⁻⁶. 14 cm －3 .

9. A semiconductor laminate having: Substrate, and Distributed on the substrate, comprising In x Al y Ga 1－x－y The compositional formula of N represents the nitride crystal layers of the crystal, wherein, 0≤x≤1, 0≤y≤1, 0≤x+y≤1, The carbon concentration in the nitride crystal layer is less than 1 × 10⁻⁶. 15 cm －3 , The concentration of electron trap E3 in the crystal, existing in the energy range of 0.5 eV above and 0.65 eV from the bottom of the conduction band, is less than 1 × 10⁻⁶. 14 cm －3 , The nitride crystal layer satisfies equation (1-2). [E3]·[C] 2 ≤1×10 43 …(1-2) in, [C] is the unit to be cm －3 The concentration of carbon in the crystal, [E3] is used to set the unit to cm. －3 The E3 concentration in the crystal.

10. A method for manufacturing a nitride crystal, comprising the method for manufacturing the nitride crystal according to claim 1, wherein, It has the following processes: The process of preparing a reaction vessel to house the substrate; For the substrate heated to a specified growth temperature within the reaction vessel, a Group III element feedstock gas and a nitrogen feedstock gas are supplied, causing the In... x Al y Ga 1－x－y The process of epitaxially growing a nitride crystal represented by the composition formula of N on the substrate, wherein 0≤x≤1, 0≤y≤1, and 0≤x+y≤1. The process of preparing the reaction vessel includes the following steps: The process of preparing a container as the reaction vessel includes a region heated to the growth temperature, i.e., a high-temperature reaction region in contact with a gas supplied to the substrate, and at least a portion of the surface of the component constituting the high-temperature reaction region having a protective layer formed of a ferricyanide complex represented by Fe4[Fe(CN)6]3. In the high-temperature baking process, the temperature of the high-temperature reaction zone is heated to a temperature of over 1500°C while hydrogen and halogen gases are supplied to the reaction vessel, but the nitrogen raw material gas is not supplied to the reaction vessel, thereby cleaning and modifying the surface of the components constituting the high-temperature reaction zone.

11. A nitride crystal manufacturing apparatus, comprising the apparatus for manufacturing the nitride crystal according to claim 1, wherein: Reaction vessel containing substrate; A heating element that heats at least the substrate within the reaction vessel; A gas supply system that supplies group III element raw material gas and nitrogen raw material gas to the substrate within the reaction vessel; The control unit supplies the group III element feedstock gas and the nitrogen feedstock gas to the substrate, which is heated to a predetermined growth temperature within the reaction vessel, so that the In... x Al y Ga 1－x－y The method of epitaxial growth of a nitride crystal represented by the composition of N on the substrate, controlling the heating element and the gas supply system, wherein... 0≤x≤1, 0≤y≤1, 0≤x+y≤1, The reaction vessel has a region heated to the growth temperature, i.e., a high-temperature reaction region in contact with the gas supplied to the substrate. At least a portion of the surface of the component constituting the high-temperature reaction zone has a protective layer formed of a ferricyanide complex represented by Fe4[Fe(CN)6]3. Before the nitride crystal is epitaxially grown, the control unit performs a high-temperature baking process, heating the temperature of the high-temperature reaction zone to a temperature of 1500°C or higher, while supplying hydrogen and halogen gases into the reaction vessel, but not supplying the nitrogen raw material gas into the reaction vessel, thereby cleaning and modifying the surface of the components constituting the high-temperature reaction zone.

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