Resistance variation type memory device

Abstract

An embodiment provides a resistance-varying memory device capable of interference suppression and high integration. One embodiment of the resistance-varying memory device includes a memory cell, a first conductor, a second conductor, and a third conductor. The memory cell includes a first sub-memory cell and a second sub-memory cell. The first sub-memory cell includes a first variable resistor element and a first bidirectional switching element. The second sub-memory cell includes a second variable resistor element and a second bidirectional switching element. The first sub-memory cell is located above the first conductor. The second conductor is located above the first sub-memory cell. The second sub-memory cell is located above the second conductor. The third conductor is located above the second sub-memory cell. The resistance-varying memory device is configured to receive first data, and when second data read from the memory cell is inconsistent with the first data, write the first data back to the memory cell.

Description

[0001] [Related Applications]

[0002] This application enjoys priority to Japanese Patent Application No. 2021-023416 (filed on February 17, 2021). This application incorporates the entire contents of the basic application by reference to that basic application. Technical Field

[0003] The implementation generally relates to a resistance-varying storage device. Background Technology

[0004] As a type of storage device, resistance-variable storage devices are known. Resistance-variable storage devices use components with dynamically variable resistance to store data. They are required to suppress interference and / or have high integration density. Summary of the Invention

[0005] The problem to be solved by the present invention is to provide a resistance variation type memory device that can achieve interference suppression and high integration.

[0006] One embodiment of a resistance-varying memory device includes a memory cell, a first conductor, a second conductor, and a third conductor. The memory cell includes a first sub-memory cell and a second sub-memory cell. The first sub-memory cell includes a first variable resistor element and a first bidirectional switching element. The second sub-memory cell includes a second variable resistor element and a second bidirectional switching element. The first sub-memory cell is located above the first conductor. The second conductor is located above the first sub-memory cell. The second sub-memory cell is located above the second conductor. The third conductor is located above the second sub-memory cell. The resistance-varying memory device is configured to receive first data, and when second data read from the memory cell is inconsistent with the first data, write the first data into the memory cell. Attached Figure Description

[0007] Figure 1 This represents a function block representing the resistance-varying storage device of the first embodiment.

[0008] Figure 2 This is a circuit diagram of the memory cell array according to the first embodiment.

[0009] Figure 3 This is a circuit diagram of the storage unit in the first embodiment.

[0010] Figure 4 This shows a partial cross-sectional structure of the memory cell array in the first embodiment.

[0011] Figure 5This shows a partial cross-sectional structure of the memory cell array in the first embodiment.

[0012] Figure 6 A cross section showing a construction example of the sub-storage unit in the first embodiment.

[0013] Figure 7 This represents a function block of the write circuit in the first embodiment.

[0014] Figure 8 This represents a function block of the readout circuit in the first embodiment.

[0015] Figure 9 This shows the constituent elements and connections of a portion of the readout circuit and a portion of the column selection circuit of the first embodiment.

[0016] Figure 10 This shows the constituent elements and connections of the row selection circuit in the first embodiment.

[0017] Figure 11 This shows the constituent elements and connections of the column selection circuit in the first embodiment.

[0018] Figure 12 This indicates the state during the period when data "1" is written to a portion of the resistance-changing type memory device in the first embodiment.

[0019] Figure 13 This indicates the state during the period when data "0" is written to a portion of the resistance-varying memory device in the first embodiment.

[0020] Figure 14 This indicates the state during the period when a portion of the resistance-varying storage device in the first embodiment is reading data.

[0021] Figure 15 This represents a function block representing the resistance-varying storage device of the second embodiment.

[0022] Figure 16 This indicates the data writing operation in the resistance-varying storage device of the second embodiment.

[0023] Figure 17 It represents the potential of a certain wiring during the data writing period of the second embodiment in chronological order.

[0024] Figure 18 It represents the potential of a certain wiring during the data writing period of the second embodiment in chronological order.

[0025] Figure 19 This shows a partial planar structure of the memory cell array in the third embodiment.

[0026] Figure 20 This shows a partial planar structure of the memory cell array in the third embodiment.

[0027] Figure 21 This shows a partial cross-sectional structure of the memory cell array in the third embodiment.

[0028] Figure 22 This shows a partial cross-sectional structure of the memory cell array in the third embodiment.

[0029] Figure 23 This shows a partial cross-sectional structure of the memory cell array in the third embodiment.

[0030] Figure 24 This shows a partial cross-sectional structure of the memory cell array in the third embodiment.

[0031] Figure 25 This shows a partial planar structure of the memory cell array in the fourth embodiment.

[0032] Figure 26 This shows a partial planar structure of the memory cell array in the fifth embodiment.

[0033] Figure 27 This shows a partial planar structure of the memory cell array in the fifth embodiment.

[0034] Figure 28 This shows a partial cross-sectional structure of the memory cell array in the fifth embodiment.

[0035] Figure 29 This shows a partial planar structure of the memory cell array in the sixth embodiment.

[0036] Figure 30 This shows a partial planar structure of the memory cell array in the sixth embodiment.

[0037] Figure 31 This shows a partial cross-sectional structure of the memory cell array in the sixth embodiment. Detailed Implementation

[0038] Hereinafter, embodiments will be described with reference to the accompanying drawings. In the following description, constituent elements having substantially the same function and structure are labeled with the same reference numerals. To distinguish between multiple constituent elements having substantially the same function and structure, sometimes another number or word may be added at the end of the reference numeral.

[0039] The accompanying drawings are schematic diagrams, and the relationship between thickness and planar dimensions, as well as the ratio of thicknesses of each layer, may differ from actual measurements. The drawings may contain portions with different dimensional relationships or ratios. Furthermore, all descriptions of a particular embodiment, unless explicitly or clearly excluded, also apply to descriptions of other embodiments.

[0040] There is no need to distinguish between functional blocks as in the following example. For instance, some functions may be executed by a different functional block than the instanced functional block. Furthermore, the instanced functional block can be divided into more subdivided functional sub-blocks.

[0041] In this specification and claims, the term "connected" to another second element includes the first element being directly or always connected to the second element, or being connected to the second element via a selectively conductive element.

[0042] The following describes the implementation method using an xyz orthogonal coordinate system.

[0043] 1. First Implementation Method

[0044] 1.1. Structure (Composition)

[0045] 1.1.1. Overall Structure

[0046] Figure 1 This represents a function block representing the resistance-varying storage device of the first embodiment. Figure 1 The memory controller is also shown.

[0047] like Figure 1 As shown, the resistance-varying memory device 1 is controlled by the memory controller 2. The resistance-varying memory device 1 receives a power supply potential Vdd and a ground potential (or common potential) Vss from an external source. For example, the resistance-varying memory device 1 receives the power supply potential Vdd and the ground potential Vss from the memory controller 2. The ground potential Vss is, for example, 0V. The resistance-varying memory device 1 operates using the power supply potential Vdd and the ground potential Vss, based on the control of the memory controller 2.

[0048] The resistance-variable type storage device 1 includes a storage cell array 11, an input / output circuit 12, a control circuit 13, a column selection circuit 15, a write circuit 16, and a read circuit 17.

[0049] The storage cell array 11 includes multiple storage cells MC, multiple word lines WL, multiple bit lines BL, and multiple bit lines ˉBL. The storage cells MC can non-volatilely store data. Each storage cell MC is connected to one word line WL and one bit line pair BLP. Each bit line pair BLP consists of bit lines BL and ˉBL. The word line WL is associated with a row. The bit line pair BLP is associated with a column. One or more storage cells MC can be specified by selecting one row and selecting one column.

[0050] The input / output circuit 12 receives control signals CNT, instructions CMD, address signals ADD, and data DAT from the memory controller 2. The input / output circuit 12 also sends data DAT to the memory controller 2. When writing data to the resistance-varying memory device 1, data DAT represents the written data. When reading data from the resistance-varying memory device 1, data DAT represents the read data.

[0051] Control circuit 13 receives control signal CNT and instruction CMD from input / output circuit 12. Based on the control signal CNT and instruction CMD, control circuit 13 controls writing circuit 16. Specifically, control circuit 13 sends control signal CN1 to writing circuit 16, using control signal CN1 to control writing circuit 16. Control signal CN1 may contain multiple different control signals.

[0052] The control circuit 13 controls the readout circuit 17 based on the control signal CNT and the control instruction CMD. Specifically, the control circuit 13 sends a control signal CN2 to the readout circuit 17 to control the readout circuit 17. The control signal CN1 may contain multiple different control signals.

[0053] The write circuit 16 performs processing and control for writing data to the memory cell MC. The write circuit 16 receives a power supply potential Vdd and a ground potential Vss. The write circuit 16 receives write data Dw from the input / output circuit 12. The write data Dw is the data to be written to the memory cell MC, which is the target of the data write. The write circuit 16 uses the power supply potential Vdd and the ground potential Vss to generate multiple potentials used during data writing. These multiple potentials used during data writing have various magnitudes. These multiple potentials used during data writing are referred to as the write potentials Vw. The write circuit 16 receives a control signal CN1 and the write data Dw. Based on the control signal CN1 and the write data Dw, the write circuit 16 supplies one or more write potentials Vw to the row selection circuit 14 and the column selection circuit 15.

[0054] The readout circuit 17 performs processing and control for reading data from the memory cell MC. The readout circuit 17 receives a power supply potential Vdd and a ground potential Vss. Using the power supply potential Vdd and the ground potential Vss, the readout circuit 17 generates multiple potentials used for data readout. These multiple potentials have various magnitudes. These multiple potentials used for data readout are referred to as readout potentials Vr. The readout circuit 17 receives a control signal CN2. Based on the control signal CN2, the readout circuit 17 supplies one or more readout potentials Vr to the row selection circuit 14 and the column selection circuit 15.

[0055] The readout circuit 17 includes one or more sense amplifiers. The readout circuit 17 is connected to a bit line pair BLP via a control signal CN2 and a column select circuit 15. The bit line pair BLP is connected to the memory cell MC to be read. The readout circuit 17 receives potentials Vb1 and Vb2 on the bit lines BL and ˉBL of the connected bit line pair BLP. Using the sense amplifiers, the readout circuit 17 identifies the data stored in the memory cell MC to be read based on the potentials Vb1 and Vb2. The identified data is supplied to the input / output circuit 12 as readout data Dr.

[0056] Row selection circuit 14 receives a write potential Vw from write circuit 16. Row selection circuit 14 receives a read potential Vr from read circuit 17. Row selection circuit 14 receives an address signal ADD from input / output circuit 12. Row selection circuit 14 applies a write potential Vw to one word line WL associated with the row specified by the received address signal ADD. Row selection circuit 14 applies another write potential Vw to word lines WL other than the one word line WL associated with the row specified by the received address signal ADD. Row selection circuit 14 applies a read potential Vr to one word line WL associated with the row specified by the received address signal ADD. Row selection circuit 14 applies another read potential Vr to word lines WL other than the one word line WL associated with the row specified by the received address signal ADD.

[0057] Column select circuit 15 receives a write potential Vw from write circuit 16. Column select circuit 15 receives a read potential Vr from read circuit 17. Column select circuit 15 receives an address signal ADD from input / output circuit 12. Column select circuit 15 applies a write potential Vw based on the write data Dw to one bit line pair BLP associated with the column specified by the received address signal ADD. Column select circuit 15 applies another write potential Vw to bit line pairs BLP other than the one associated with the column specified by the received address signal ADD. Column select circuit 15 applies a read potential Vr to one bit line pair BLP associated with the column specified by the received address signal ADD. Column select circuit 15 applies another read potential Vr to bit line pairs BLP other than the one associated with the column specified by the received address signal ADD.

[0058] 1.1.2. Circuit Structure of a Memory Cell Array

[0059] Figure 2 This is a circuit diagram of the memory cell array 11 according to the first embodiment. Figure 2As shown, the memory cell array 11 includes M+1 (M is a natural number) word lines WL (WL<0>, WL<1>, ..., WL<M>). The memory cell array 11 also includes N+1 (N is a natural number) bit lines BL (BL<0>, BL<1>, ..., BL<N>) and N+1 bit lines ˉBL (ˉBL<0>, ˉBL<1>, ..., ˉBL<N>).

[0060] Each memory cell MC is connected to one bit line pair BLP and one word line WL. Each memory cell MC has a first node N1, a second node N2, and a third node N3. Each memory cell MC is located in the first node N1 and connected to the word line WL. Each memory cell MC is located in the second node N2 and connected to the bit line BL in the bit line pair BLP. Each memory cell MC is located in the third node N3 and connected to the bit line ˉBL in the bit line pair BLP. More specifically, for all instances of integers α being 0 to M and β being 0 to N, the memory cell MC contains the memory cell MC<α, β>. For all instances of integers α being 0 to M and β being 0 to N, the memory cell MC<α, β> is connected to the word line WL<α> in the first node N1. For all instances of α being integers greater than or equal to M and for all combinations of instances of β being integers greater than or equal to N, the storage unit MC<α, β> is connected to the bit line BL<β> at node 2 N2. For all instances of α being integers greater than or equal to M and for all combinations of instances of β being integers greater than or equal to N, the storage unit MC<α, β> is connected to the bit line BL<β> at node 3 N3.

[0061] 1.1.3. Circuit Structure of Storage Cell

[0062] Figure 3 This is a circuit diagram of the memory cell MC according to the first embodiment. (Example) Figure 3 As shown, each memory cell MC contains two sub-memory cells SMC. Sometimes, one of the sub-memory cells SMC is referred to as the first sub-memory cell SMCa, and the other sub-memory cell SMC is referred to as the second sub-memory cell SMCb. The first sub-memory cell SMCa and the second sub-memory cell SMCb each contain one variable resistor element VR (VRa or VRb) and one selector SE (SEa or SEb). Specifically, the first sub-memory cell SMCa contains one variable resistor element VRa and one selector SEa, and the second sub-memory cell SMCb contains one variable resistor element VRb and one selector SEb.

[0063] In each memory cell MC, selector SEa, variable resistor VRa, selector SEb, and variable resistor VRb are connected in series sequentially. In each memory cell MC, the node connecting variable resistor VRa and selector SEb functions as node 1 N1. In each memory cell MC, the end of selector SEa opposite to variable resistor VRa functions as node 2 N2. In each memory cell MC, the end of variable resistor VRb opposite to selector SEb functions as node 3 N3.

[0064] The variable resistance element VR can switch between a low resistance state and a high resistance state. The variable resistance element VR can store 1 bit of data by utilizing the difference between these two resistance states.

[0065] The selector SE can be a switching element, such as those described below. The switching element has two terminals. When a voltage less than a first threshold is applied between the two terminals in a first direction, the switching element is in a high-resistance state, for example, a non-conducting state (off state). On the other hand, when a voltage greater than or equal to the first threshold is applied between the two terminals in the first direction, the switching element is in a low-resistance state, for example, a conducting state (on state). Furthermore, the switching element also has the same function in a second direction opposite to the first direction, switching between a high-resistance state and a low-resistance state based on the magnitude of the voltage applied in the first direction. In other words, the switching element is a bidirectional switching element such as a bidirectional diode. By turning the switching element on or off, it is possible to control whether current is supplied to the variable resistor element VR connected to the switching element, that is, whether the variable resistor element VR is selected or not.

[0066] Each memory cell (MC) uses two variable resistors, VRa and VRb, to store one bit of data. Within each memory cell (MC), the variable resistors VRa and VRb store complementary one-bit data. Each memory cell (MC) stores one bit of data based on whether either of the variable resistors VRa or VRb stores the data "0".

[0067] The state where either variable resistor element VRa or VRb stores data "0" can be considered as the state where the memory cell MC stores data "0". The following description is based on the example where the state where variable resistor element VRa stores data "0" is the same as the state where the memory cell MC containing that variable resistor element VRa stores data "1". Conversely, the state where variable resistor element VRb stores data "0" is considered as the state where the memory cell MC containing that variable resistor element VRa stores data "0".

[0068] 1.1.4. Construction of a Storage Cell Array

[0069] Figure 4 and Figure 5 This shows a partial cross-sectional structure of the memory cell array 11 in the first embodiment. Figure 4 This represents a cross section along the xz plane. Figure 5 This represents a cross section along the yz plane.

[0070] like Figure 4 and Figure 5 As shown, a plurality of conductors 21 are disposed above a semiconductor substrate (not shown). The conductors 21 extend along the y-axis and are arranged along the x-axis. Each conductor 21 functions as a bit line BL. The plurality of conductors 21 originate from the same conductor. That is, the plurality of conductors 21 are formed by partially removing the conductors that extend along the xy plane for the conductors 21. Hereinafter, even if not explicitly stated, independent constituent elements located in a certain layer (a region of a continuous range at a certain height) are also formed by partially removing a certain material or by laminating multiple materials. As a result, such constituent elements have the characteristic that they have less non-uniformity compared to those formed from separately formed independent materials.

[0071] Each conductor 21 is connected on its upper surface to the bottom surface of each of the first sub-memory cells SMCa of the plurality of memory cells MC. Each first sub-memory cell SMCa has, for example, a circular shape on the xy plane. The first sub-memory cells SMCa are arranged along the y-axis on each conductor 21, and according to this configuration, the first sub-memory cells SMCa are arranged in a matrix on the xy plane. Each first sub-memory cell SMCa includes a structure that functions as a selector SE and a structure that functions as a variable resistor element VRa. The structure that functions as a selector SEa and the structure that functions as a variable resistor element VRa are described below, and each includes one or more stacked components.

[0072] In the layer above the layer containing the first sub-memory cell SMCa, multiple conductors 22 are disposed. The conductors 22 extend along the x-axis and are arranged along the y-axis. Each conductor 22 is on its bottom surface and is connected to the top surface of each of the multiple first sub-memory cells SMCa arranged along the x-axis. Each conductor 22 functions as a word line WL.

[0073] Each conductor 22 is on its upper surface and connected to the bottom surface of each of the plurality of second sub-memory cells SMCb. Each second sub-memory cell SMCb is in the xy plane and has, for example, a circular shape. The second sub-memory cells SMCb are arranged along the x-axis on each conductor 22, and according to this configuration, the second sub-memory cells SMCb are arranged in a matrix on the xy plane. Each second sub-memory cell SMCb includes a structure that functions as a selector SEb and a structure that functions as a variable resistor element VRb. The structures that function as the selector SEb and the structures that function as the variable resistor element VRb are described below, and each includes one or more stacked components. Each second sub-memory cell SMCb and a first sub-memory cell SMCa directly below it at least partially constitute a memory cell MC.

[0074] Conductors 23 are disposed on the upper surface of each of the multiple second sub-memory cells SMCb arranged along the y-axis. Each conductor 23 functions as a bit line BL.

[0075] 1.1.4.1. Construction of Secondary Storage Units

[0076] Figure 6 A cross-section showing a construction example of the sub-memory cell (SMC) in the first embodiment. For example... Figure 6 As shown and as described below, the secondary storage cell SMC includes a selector SE and a variable resistor element VR.

[0077] The selector SE includes a variable resistive material. The selector SE may also include a lower electrode and an upper electrode. In this case, the variable resistive material is located on the upper surface of the lower electrode, and the upper electrode is located on the upper surface of the variable resistive material. The selector SE is, for example, a two-terminal switching element, where the first terminal of the two terminals corresponds to one of the upper and bottom surfaces of the selector SE, and the second terminal of the two terminals corresponds to the other of the upper and bottom surfaces of the selector SE.

[0078] The variable resistor element VR is located on the upper surface of the selector SE. The variable resistor element VR is, for example, a magnetic tunnel junction (MTJ) element. The following description and figures are based on the example where the variable resistor element VR is an MTJ element. MTJ elements are elements used in MRAM (Magnetoresistive Random Access Memory).

[0079] The resistance-varying memory device 1 contains two sub-memory cells SMC within one memory cell MC, and each of the two sub-memory cells SMC contains an MTJ element. Hereinafter, this cell configuration is sometimes referred to as the 2MTJ per cell configuration.

[0080] Specifically, the MTJ element VR includes a ferromagnetic layer 41, an insulating layer 42, and a ferromagnetic layer 43. As an example, the insulating layer 42 is located on the upper surface of the ferromagnetic layer 41, and the ferromagnetic layer 43 is located on the upper surface of the insulating layer 42.

[0081] The ferromagnetic layer 41 has an easy magnetization axis along the interface that runs through the ferromagnetic layer 41, the insulating layer 42, and the ferromagnetic layer 43. The easy magnetization axis of the ferromagnetic layer 41 has an angle of 45° to 90° relative to the interface, and is, for example, orthogonal to the interface of the ferromagnetic layer 41, the insulating layer 42, and the ferromagnetic layer 43. It is intended that the magnetization direction of the ferromagnetic layer 41 is not changed by reading data from and writing data to the sub-memory cell SMC in the resistance-changing type memory device 1. The ferromagnetic layer 41 can function as a so-called reference layer. The ferromagnetic layer 41 contains, for example, one or more of iron (Fe), cobalt (Co), and nickel (Ni). The ferromagnetic layer 41 may also contain boron (B). As a more specific example, the ferromagnetic layer 41 contains cobalt-iron-boron (CoFeB) or iron boride (FeB).

[0082] The ferromagnetic layer 41 may comprise multiple sublayers. The ferromagnetic layer 41 may have a SAF (Synthetic Antiferromagnetic) structure. In this case, the ferromagnetic layer 41 comprises two ferromagnetic bodies (ferromagnetic layers) and a conductor (conductive layer) between the two ferromagnetic bodies. The conductor enables the two ferromagnetic bodies to be antiferromagnetically exchange-coupled.

[0083] The insulating layer 42, for example, contains magnesium oxide (MgO) or is composed of magnesium oxide, and functions as a so-called tunnel barrier.

[0084] The ferromagnetic layer 43 contains a material exhibiting ferromagnetism, at least containing iron. Therefore, the ferromagnetic layer 43 exhibits magnetization. The ferromagnetic layer 43 may contain, for example, cobalt iron boron or iron boride, or be substantially composed of cobalt iron boron or iron boride. In this specification and claims, the term "substantially constituted" and similar descriptions imply that the constituent elements of the "substantially constituted" are permitted to contain undesirable impurities. Examples of undesirable impurities include atoms of elements contained in the gas used in the manufacturing process of the resistive change type memory device 1, and atoms of elements diffused from the surroundings of other constituent elements of the "substantially constituted" element into the constituent elements of the "substantially constituted" element.

[0085] The ferromagnetic layer 43 has an easy magnetization axis along the interface that runs through the ferromagnetic layer 41, the insulating layer 42, and the ferromagnetic layer 43. The easy magnetization axis of the ferromagnetic layer 43 has an angle of 45° to 90° relative to the interface, for example, orthogonal to the interface of the ferromagnetic layer 41, the insulating layer 42, and the ferromagnetic layer 43. The magnetization direction of the ferromagnetic layer 43 is variable, depending on the data written to the sub-memory cell SMC, and the ferromagnetic layer 43 can function as a so-called storage layer.

[0086] When the magnetization direction of the ferromagnetic layer 43 is parallel to the magnetization direction of the ferromagnetic layer 41, the MTJ element VR has a relatively low resistance. Hereinafter, the state where the magnetization direction of the ferromagnetic layer 43 is parallel to the magnetization direction of the ferromagnetic layer 41 is referred to as the P state or low-resistance state of the sub-memory cell SMC. On the other hand, when the magnetization direction of the ferromagnetic layer 43 is antiparallel to the magnetization direction of the ferromagnetic layer 41, the resistance of the MTJ element VR is higher than the resistance when the magnetization direction of the ferromagnetic layer 41 is parallel to the magnetization direction of the ferromagnetic layer 43. Hereinafter, the state where the magnetization direction of the ferromagnetic layer 43 is antiparallel to the magnetization direction of the ferromagnetic layer 41 is referred to as the AP state or high-resistance state of the sub-memory cell SMC.

[0087] When a write current Iwp of a certain magnitude flows from ferromagnetic layer 43 to ferromagnetic layer 41, the magnetization direction of ferromagnetic layer 43 is parallel to the magnetization direction of ferromagnetic layer 41. On the other hand, when a write current Iwap of a certain magnitude flows from ferromagnetic layer 41 to ferromagnetic layer 43, the magnetization direction of ferromagnetic layer 43 is antiparallel to the magnetization direction of ferromagnetic layer 41.

[0088] The write currents Iwp and Iwap are the currents flowing in the secondary storage cell (SMC) that is being written to during data writing. They are named from the perspective of this purpose and can have dynamically variable magnitudes during the operation of the resistance-varying storage device 1.

[0089] The write current Iwp turns on the selector SE, allowing current to flow from the surface facing the ferromagnetic layer 41 to the surface opposite to the ferromagnetic layer 41. The write current Iwap turns on the selector SE, allowing current to flow from the surface opposite to the ferromagnetic layer 41 to the surface facing the ferromagnetic layer 41.

[0090] The write current Iwp flows into each sub-memory cell SMC, where the magnetization direction of the ferromagnetic layer 43 of the sub-memory cell SMC is parallel to the magnetization direction of the ferromagnetic layer 41; this is sometimes referred to as P-write. Hereinafter, the write current Iwp will sometimes be referred to as the P-write current.

[0091] On the other hand, the process of allowing the write current Iwap to flow into each sub-memory cell SMC, causing the magnetization direction of the ferromagnetic layer 43 of that sub-memory cell SMC to be antiparallel to the magnetization direction of the ferromagnetic layer 41, is sometimes referred to as AP write. Hereinafter, the write current Iwap will sometimes be referred to as the AP write current.

[0092] 1.1.5. Writing Circuit

[0093] Figure 7 This represents a functional block of the write circuit 16 in the first embodiment. For example... Figure 7 As shown, the write circuit 16 includes potential generation circuits WD1, WD2 and WD3, a write circuit control circuit WCD, and switching circuits SW1 and SW2.

[0094] The write circuit control circuit WCD receives control signal CN1 and write data Dw from control circuit 13 (not shown). In order to write the data specified by control signal CN1 and write data Dw, the write circuit control circuit WCD outputs signals CS1, CS2, CS3, CS4 and CS5 to activate the potential generation circuits WD1, WD2 and WD3, and the switching circuits SW1 and SW2.

[0095] The potential generation circuit WD1 uses the ground potential Vss and the power supply potential Vdd to generate a write potential Vp. The write potential Vp is the potential applied to a word line WL during data writing; it is named for this purpose and can have a dynamically variable magnitude during the operation of the resistance-varying memory device 1. The write potential Vp, for example, has the same magnitude as the power supply potential Vdd. The potential generation circuit WD1, for example, includes a charge pump CP1, which uses the ground potential Vss, the power supply potential Vdd, and the charge pump CP1 to generate the write potential Vp. The potential generation circuit WD1 receives a signal CS1 from the write circuit control circuit WCD. Based on the signal CS1, the potential generation circuit WD1 generates a write potential Vp of a certain magnitude and outputs the generated write potential Vp. The potential generation circuit WD1 may, for example, include a current-driven circuit, or may function as a current-driven circuit.

[0096] The potential generation circuit WD2 receives the ground potential Vss and the signal CS2 from the write circuit control circuit WCD. Based on the signal CS2, the potential generation circuit WD2 outputs the ground potential Vss. The potential generation circuit WD2 can be, for example, a current absorption circuit.

[0097] The potential generation circuit WD3 uses the ground potential Vss and the power supply potential Vdd to generate an intermediate potential Vm. The intermediate potential Vm has a value between the power supply potential Vdd and the ground potential Vss. For example, the intermediate potential Vm may be half the size of the power supply potential Vdd. The potential generation circuit WD3 may include a charge pump CP, which uses the ground potential Vss, the power supply potential Vdd, and the charge pump CP3 to generate the intermediate potential Vm. The potential generation circuit WD3 receives a signal CS3 from the write circuit control circuit WCD. Based on the signal CS3, the potential generation circuit WD3 generates the intermediate potential Vm and outputs the generated intermediate potential Vm. The intermediate potential Vm is supplied to the row selection circuit 14 and the column selection circuit 15. The potential generation circuit WD3 may include, for example, a current drive circuit, or may function as a current drive circuit.

[0098] Switching circuit SW1 has a first terminal, a second terminal, and a third terminal. Switching circuit SW1 is connected to the output of the potential generation circuit WD1 at its first terminal. Its second terminal is connected to the row selection circuit 14. Its third terminal is connected to the column selection circuit 15. Switching circuit SW1 receives signal CS4 from the write circuit control circuit WCD. Switching circuit SW1 connects its first terminal to one of its second and third terminals based on signal CS4. Switching circuit SW1 may contain, for example, multiple transistors.

[0099] Switching circuit SW2 has a first terminal, a second terminal, and a third terminal. Terminal SW2 is connected to the output of the potential generation circuit WD2. Terminal 2 is connected to the row selection circuit 14. Terminal 3 is connected to the column selection circuit 15. Switching circuit SW2 receives signal CS5 from the write circuit control circuit WCD. Switching circuit SW1 connects its first terminal to one of its second and third terminals based on signal CS5. Switching circuit SW2 may contain, for example, multiple transistors.

[0100] The write circuit control circuit WCD, based on the write data Dw, outputs signals CS4 and CS5 to supply a write potential Vp to the row selection circuit 14 and a ground potential Vss to the column selection circuit 15. Additionally, the write circuit control circuit WCD, based on the write data Dw, outputs signals CS4 and CS5 to supply a ground potential Vss to the row selection circuit 14 and a write potential Vp to the column selection circuit 15. Whether the write potential Vp is supplied to either the row selection circuit 14 or the column selection circuit 15 depends on the value of the write data Dw, i.e., the value of the data written to the memory cell MC.

[0101] 1.1.6. Readout Circuit

[0102] Figure 8 This represents a functional block of the readout circuit 17 in the first embodiment. For example... Figure 8As shown, the readout circuit 17 includes a potential generation circuit RD, a sensing amplifier SA, and a readout circuit control circuit RCD.

[0103] The readout circuit control circuit RCD receives control signal CN2 from control circuit 13 (not shown). The readout circuit control circuit RCD outputs signals CS6 and CS7 to activate the potential generation circuit RD and the sensing amplifier SA, in order to read out the data.

[0104] The potential generation circuit RD uses the ground potential Vss and the power supply potential Vdd to generate the read potential Vread. The potential generation circuit RD may include, for example, a charge pump CP3, which uses the ground potential Vss, the power supply potential Vdd, and the charge pump CP3 to generate the read potential Vread. The potential generation circuit RD receives a signal CS6 from the read circuit control circuit RCD. Based on the signal CS6, the potential generation circuit RD outputs the read potential Vread. The potential generation circuit RD may include, for example, a current drive circuit, or may function as a current drive circuit. The read potential Vread is supplied to the row selection circuit 14.

[0105] The sense amplifier SA receives signal CS7 from the readout circuit control circuit RCD. The sense amplifier SA operates based on signal CS7. During data readout, the sense amplifier SA connects to one bit line pair BLP, which is associated with the column specified by the address signal ADD, through column selection circuit 15. The sense amplifier SA is a so-called differential amplifier circuit, and the following description will be based on this example. The differential amplifier amplifies the potential on one of the two wirings to the magnitude of one of two different levels, and amplifies the potential on the other of the two wirings to the magnitude of the other of two different levels. The sense amplifier SA receives potential Vb1 on bit line BL in the connected bit line pair BLP and potential Vb2 on bit line BL' in the connected bit line pair BLP. Based on potentials Vb1 and Vb2, the sense amplifier SA identifies the data stored in the memory cell MC connected to the connected bit line pair BLP.

[0106] 1.1.6.1. Sensing Amplifier

[0107] Figure 9 This shows the components and connections of a portion of the readout circuit 17 and a portion of the column selection circuit 15 in the first embodiment.

[0108] The column selection circuit 15 connects the multiple bit line pairs BLP that are associated with the column specified by the address signal ADD to the sense amplifier SA. Figure 9 Only one bit line pair BLP is shown, namely bit line BL and bit line ˉBL.

[0109] The column selection circuit 15 includes p-type MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors) TP1 and TP2, and n-type MOSFETs TN1 and TN2. Transistors TP1 and TN1 are connected in parallel between bit line BL and the global bit line GBL. Transistor TN1 receives signal CL at its gate. Signal CL is based on the address signal ADD and specifically outputs... Figure 9 The bit line pair BLP is shown. The signal CL is supplied, for example, from control circuit 13. Transistor TP1 receives the signal ˉCL at its gate. The symbol “ˉ” at the beginning of the signal name indicates that it has the opposite logic to the signal whose name does not have the symbol “ˉ”.

[0110] Transistors TP2 and TN2 are connected in parallel between bit line BL and global bit line GBL. Transistor TN2 receives signal CL at its gate. Transistor TP2 receives signal CL at its gate.

[0111] The sensing amplifier SA includes n-type MOSFETs TN3, TN4, TN5, TN6, TN7, TN8 and TN9, and p-type MOSFETs TP3, TP4, TP5 and TP6.

[0112] Transistors TN3 and TN4 are connected in series between the global bit line GBL and the node at ground potential Vss (hereinafter sometimes referred to as the ground node). Transistor TN3 receives the sense amplifier enable signal SAE at its gate. The sense amplifier enable signal SAE controls the activation and deactivation of the sense amplifier SA, for example, as contained in the signal CS7 from the sense circuit control circuit RCD. Transistor TN4 receives the signal PDE at its gate. The signal PDE is, for example, contained in the signal CS7 from the sense circuit control circuit RCD. The node connecting transistors TN3 and TN4 is called node NBL1.

[0113] Transistors TN5 and TN6 are connected in series between the global bit line (GBL) and the ground node. Transistor TN5 receives the sense amplifier enable signal (SAE) at its gate. Transistor TN6 receives the signal PDE at its gate. The node connecting transistors TN5 and TN6 is called node NBL2.

[0114] Transistor NT7 is connected between nodes NBL1 and NBL2. Transistor NT7 receives signal PDE at its gate.

[0115] Transistors TP3, TP4, and TN8 are connected in series between the power supply node (hereinafter sometimes referred to as the power node) and the ground node. Transistor TP3 receives the sense amplifier enable signal ˉSAE at its gate. The sense amplifier enable signal ˉSAE is, for example, included in the signal CS7 from the readout circuit control circuit RCD. Transistor TP4 and transistor TN8 constitute the first inverter. The node connecting transistors TP4 and TN8 functions as the output of the first inverter and is connected to node NBL1. The gate of transistor TP4 is connected to the gate of transistor TN8 and functions as the input of the first inverter.

[0116] Transistors TP5, TP6, and TN9 are connected in series between the power supply node and the ground node. Transistor TP5 receives the sense amplifier enable signal ˉSAE at its gate. Transistors TP6 and TN9 form the second inverter. The node connecting transistors TP6 and TN9 functions as the output of the second inverter and is connected to node NBL2. The gates of transistors TP6 and TN9 are connected, functioning as the input of the second inverter.

[0117] The first inverter, consisting of transistors TP4 and TN8, and the second inverter, consisting of transistors TP6 and TN9, are cross-connected. That is, the inputs of the first inverter, i.e., the gates of transistors TP4 and TN8, are connected to node NBL2, and the gates of transistors TP6 and TN9 are connected to node NBL1. Node NBL2 functions as the output of the sense amplifier SA.

[0118] 1.1.7. Row Selection Circuit

[0119] Figure 10 The diagram illustrates the components and connections of the row selection circuit 14 in the first embodiment. The row selection circuit 14 is configured to transmit one dynamically selected potential from a plurality of potentials received by the row selection circuit 14 to one or more dynamically selected word lines WL.

[0120] like Figure 10As shown, the row selection circuit 14 includes switches Tp (Tp0, Tp1, ... TpM), Tm (Tm0, Tm1, ... TmM), Ts (Ts0, Ts1, ... TsM), and Tr (Tr0, Tr1, ... TrM) for each word line WL. Switches Tp, Tm, Ts, and Tr are, for example, n-type MOSFETs. The following description will be based on this example. Each transistor Tp is connected between a word line WL and a wiring line Wvp. A write potential Vp is applied to wiring line Wvp. Each transistor Tm is connected between a word line WL and a wiring line Wvm. A midpoint potential Vm is applied to wiring line Wvm. Each transistor Ts is connected between a word line WL and a wiring line Wvs. A ground potential Vss (ground) is applied to wiring line Wvs. Each transistor Tr is connected between a word line WL and a wiring line Wvr. A read potential Vread is applied to wiring line Wvr.

[0121] The row selection circuit 14 includes a row decoder RDE. The row decoder RDE receives the address signal ADD. Based on the address signal ADD, the row decoder RDE controls the turn-on and turn-off of transistors Tp, Tm, Ts, and Tr.

[0122] A more specific example of the row selection circuit 14 is as follows. For example, for all instances where α is an integer greater than or equal to M, the row selection circuit 14 includes transistors Tpα, Tmα, Tsα, and Trα. For all instances where α is an integer greater than or equal to M, transistor Tpα is connected between the wiring Wvp and the word line WLα. For all instances where α is an integer greater than or equal to M, transistor Tmα is connected between the wiring Wvm and the word line WLα. For all instances where α is an integer greater than or equal to M, transistor Tsα is connected between the wiring Wvs and the word line WLα. For all instances where α is an integer greater than or equal to M, transistor Trα is connected between the wiring WVr and the word line WLα. Transistors Tp, Tm, Ts, and Tr are each connected to the row decoder RDE at their gates.

[0123] 1.1.8. Column Selection Circuit

[0124] Figure 11 This describes the components and connections of the column selection circuit 15 in the first embodiment. The column selection circuit 15 is configured to transmit one dynamically selected potential from a plurality of potentials received by the column selection circuit 15 to one or more dynamically selected bit line pairs BLP. The bit line pairs BLP are interconnected.

[0125] like Figure 11As shown, the column select circuit 15 includes switches Qp (Qp0, Qp1, ... QpN), Qm (Qm0, Qm1, ... QmN), and Qs (Qs0, Qs1, ... QsN) for setting each bit line pair BLP. Switches Qp, Qm, and Qs are, for example, n-type MOSFETs. The following description will be based on this example. Each transistor Qp is connected between a bit line pair BLP and a line Bvp. A write potential Vp is applied to line Bvp. Each transistor Qm is connected between a bit line pair BLP and a line Bvm. A mid-level potential Vm is applied to line Bvm. Each transistor Qs is connected between a bit line pair BLP and a line Bvs. A ground potential Vss (ground) is applied to line Bvs.

[0126] The column selection circuit 15 also includes a column decoder CDE. The column decoder CDE receives the address signal ADD. Based on the address signal ADD, the column decoder CDE controls the turn-on and turn-off of transistors Qp, Qm, and Qs respectively.

[0127] A more specific example of column selection circuit 15 is as follows. For example, for all instances of β being an integer greater than or equal to N, column selection circuit 15 includes transistors Qpβ, Qmβ, and Qsβ. For all instances of β being an integer greater than or equal to N, transistor Qpβ is connected between wiring Bvp and the nodes connected to bit lines BLβ and ˉBLβ. For all instances of β being an integer greater than or equal to N, transistor Qmβ is connected between wiring Bvm and the nodes connected to bit lines BLβ and ˉBLβ. For all instances of β being an integer greater than or equal to N, transistor Qsβ is connected between wiring Bvs and the nodes connected to bit lines BLβ and ˉBLβ. Transistors Qp, Qm, and Qs are each connected to the column decoder CDE at their gates.

[0128] 1.2. Actions

[0129] 1.2.1. Data Writing

[0130] Figure 12 and Figure 13 This indicates the state during the period when data is written to a portion of the resistance-varying memory device 1 in the first embodiment. Specifically, Figure 12 and Figure 13 This indicates the state of the constituent elements related to data writing during the data writing process of the storage cell MC, which is the object of writing. Hereinafter, the storage cell MC, which is the object of writing or reading, is sometimes referred to as the selected storage cell MCs. The secondary storage cells SMCs within the selected storage cells MCs are sometimes referred to as selected secondary storage cells SMCs. The first secondary storage cell SMCa within the selected storage cells MCs is sometimes referred to as the first selected secondary storage cell SMCas. The second secondary storage cell SMCb within the selected storage cells MCs is sometimes referred to as the second selected secondary storage cell SMCbs.

[0131] Storage cells MC other than the selected storage cells MCs are sometimes referred to as non-selected storage cells MCns. The first secondary storage cell SMCa in the non-selected storage cells MCns is sometimes referred to as the non-selected first secondary storage cell SMCans. The second secondary storage cell SMCb in the non-selected storage cells MCns is sometimes referred to as the non-selected second secondary storage cell SMCbns.

[0132] The word lines WL specified by the address signal ADD are sometimes referred to as select word lines WLs. The word lines WL other than select word lines WLs are sometimes referred to as non-select word lines WLns.

[0133] The bit line pair BLP specified by the address signal ADD is sometimes referred to as the select bit line pair BLPs. The bit line BL in the select bit line pair BLPs is sometimes referred to as the select bit line BLs. The bit line ˉBL in the select bit line pair BLPs is sometimes referred to as the select bit line ˉBLs.

[0134] Bit line pairs BLPs other than selected bit line pairs BLPs are sometimes referred to as non-selected bit line pairs BLPns. Bit lines BL in non-selected bit line pairs BLPns are sometimes referred to as non-selected bit lines BLns. Bit lines ˉBL in non-selected bit line pairs BLPns are sometimes referred to as non-selected bit lines ˉBLns.

[0135] Figure 12 and Figure 13 It represents a circuit, but also demonstrates Figure 12 and Figure 13 The structure of several constituent elements is shown below. Specifically, the first secondary storage unit SMCa and... Figure 4 and Figure 5 The structure shown is consistent and is depicted below the word line WL. The second sub-memory cell SMCb is... Figure 4 and Figure 5 The structure shown is consistent and is depicted above the letter line WL.

[0136] Figure 12 This indicates the state during the writing of data "1" to the selected storage unit MCs. Figure 13 This indicates the state during the writing of data "0" to the selected memory cell MCs. Writing data to the selected memory cell MCs is performed in parallel by writing data to the MTJ element VRa of the first selected memory cell SMCas and to the MTJ element VRb of the second selected memory cell SMCbs.

[0137] 1.2.1.1. Writing the data "1"

[0138] In order to write the data "1" to the selected memory cell MCs, the write circuit 16, the row selection circuit 14, and the column selection circuit 15 form a control signal CN1, the write data Dw, and the address signal ADD. Figure 12 The status shown is as follows. Details are as follows.

[0139] The write circuit 16 outputs the write potential Vp, the ground potential Vss, and the intermediate potential Vm.

[0140] The column selection circuit 15 connects the wiring Bvs, to which a ground potential Vss is applied, to the select bit lines BLs and ˉBLs. The column selection circuit 15 connects the wiring Bvm, to which an intermediate potential Vm is applied, to the non-select bit lines BLns and ˉBLns.

[0141] The row selection circuit 14 connects the line Wvp, to which the write potential Vp is applied, to the select word line WLs. The row selection circuit 14 connects the line Wvm, to which the intermediate potential Vm is applied, to the non-select word line WLns.

[0142] By reference Figure 12 The connection of word lines WL, bit lines BL, and ˉBL as described so far applies to word lines WL, bit lines BL, and ˉBL. Figure 12The voltage is shown. That is, a voltage equal to the potential difference between the write potential Vp and the ground potential Vss is applied from the select word line WLs to the select bit line BLs. Hereinafter, this voltage having a potential difference equal to the write potential Vp and the ground potential Vss is sometimes referred to as the write voltage Vwd. The magnitude of the write voltage Vwd depends on the magnitude of the write potential Vp. The write potential Vp has a magnitude such that it causes the P write current Iwp or the AP write current Iwap to flow into the sub-memory cell SMC to which the write voltage Vwd is applied, and turns on the selector SE of that sub-memory cell SMC. Therefore, by applying the write voltage Vwd, the P write current Iwp or the AP write current Iwap flows into the selected sub-memory cell SMCs. By applying a write voltage Vwd from the select word line WLs towards the select bit line BLs, a P write current Iwp flows through the first select sub-cell SMCas, performing a P write to the first select sub-cell SMCas. After the P write, the first select sub-cell SMCas becomes the P state. Similarly, by applying a write voltage Vwd from the select word line WLs towards the select bit line BLs, an AP write current Iwap flows through the second select sub-cell SMCbs, performing an AP write to the second select sub-cell SMCbs. After the AP write, the second select sub-cell SMCbs becomes the AP state. After performing a P write to the first select sub-cell SMCas and an AP write to the second select sub-cell SMCbs, the select sub-cell MCs becomes a state storing data "1". Hereinafter, the action used to make a certain sub-cell MC become a state storing data "1" is sometimes referred to as writing data "1" to that sub-cell MC.

[0143] On the other hand, an intermediate potential Vm is applied to the non-select bit lines BLns and ˉBLns. Therefore, voltages are applied to the first non-selected secondary memory cell SMSans between the select word line WLs and the non-selected bit line BLns, and the second non-selected secondary memory cell SMCbns between the select word line WLs and the non-selected bit line ˉBLns. Hereinafter, the first non-selected secondary memory cell SMSans between the select word line WLs and the non-selected bit line BLns, and the second non-selected secondary memory cell SMCbns between the select word line WLs and the non-selected bit line ˉBLns are sometimes referred to as being in a half-selected state, and sometimes also as half-selected secondary memory cell SMCh. Hereinafter, the voltage applied to the half-selected secondary memory cell SMCh is sometimes referred to as the half-select voltage.

[0144] No potential difference was generated in the first non-selected memory cell SMCans between the non-selected word line WLns and the non-selected bit line BLns, and in the second non-selected memory cell SMCbns between the non-selected word line WLns and the non-selected bit line BLns.

[0145] A half-select voltage is also applied to the first non-selected sub-memory cell SMCans between the non-select word line WLns and the select bit line BLs, and to the second non-selected sub-memory cell SMCbns between the non-select word line WLns and the select bit line BLs.

[0146] The half-select voltage is equal to the difference between the write potential Vp and the intermediate potential Vm, or the difference between the ground potential Vss and the intermediate potential Vm. The intermediate potential Vm is higher than the ground potential Vss, and as mentioned above, it is, for example, half the size of the power supply potential Vdd. Therefore, the half-select voltage is lower than the write voltage Vwd, allowing only a current smaller than the P write current Iwp and the AP write current Iwap to flow. Thus, neither P writes nor AP writes are performed on the half-select sub-cell SMCh; instead, data is selectively written to the select cell MCs.

[0147] 1.2.1.2. Writing data "0"

[0148] In order to write the data "0" to the selected memory cell MCs, the write circuit 16, the row selection circuit 14, and the column selection circuit 15 form a control signal CN1, the write data Dw, and the address signal ADD. Figure 13 The status shown is as follows. Details are as follows.

[0149] The write circuit 16 outputs the write potential Vp, the ground potential Vss, and the intermediate potential Vm.

[0150] The column select circuit 15 connects the wiring Bvp, to which the write potential Vp is applied, to the select bit lines BLs and ˉBLs. The column select circuit 15 connects the wiring Bvm, to which the intermediate potential Vm is applied, to the non-select bit lines BLns and ˉBLs.

[0151] BLns.

[0152] The row selection circuit 14 connects the line Wvs, to which a ground potential Vss is applied, to the select word line WLs. The row selection circuit 14 connects the line Wvm, to which an intermediate potential Vm is applied, to the non-select word line WLns.

[0153] By reference Figure 13 The connection of word lines WL, bit lines BL, and ˉBL as described so far applies to word lines WL, bit lines BL, and ˉBL. Figure 13The potentials are shown. That is, a write voltage Vwd is applied from the select bit line BLs towards the select word line WLs, and a write voltage Vwd is also applied from the select bit line BLs towards the select word line WLs. By applying the write voltage Vwd, the AP write current Iwap or the P write current Iwp flows into the selected secondary memory cell SMCs. By applying the write voltage Vwd from the select bit line BLs towards the select word line WLs, the AP write current Iwap flows into the selected first secondary memory cell SMCas, performing an AP write to the selected first secondary memory cell SMCas. After the AP write, the selected first secondary memory cell SMCas becomes the AP state. Additionally, by applying the write voltage Vwd from the select bit line BLs towards the select word line WLs, the P write current Iwp flows into the selected second secondary memory cell SMCbs, performing a P write to the selected second secondary memory cell SMCbs. After the P write, the selected second secondary memory cell SMCbs becomes the P state. After performing an AP write to the first selected storage cell SMCas and a P write to the second selected storage cell SMCbs, the selected storage cell MCs becomes a state where it stores data "0". Hereinafter, the action used to make a storage cell MC become a state where it stores data "0" is sometimes referred to as writing data "0" to that storage cell MC.

[0154] For the same reasons as those stated regarding the writing of data "1", the writing of data "0" is also selective, with data being written to selected memory cells (MCs).

[0155] 1.2.2. Data Reading

[0156] Figure 14 This indicates the state during the period when a portion of the resistance-varying storage device 1 in the first embodiment is reading data. Specifically, Figure 14 This indicates the state of the constituent elements related to data reading during the process of reading data from selected storage units (MCs). Figure 14 and Figure 12 and Figure 13 The same not only indicates the circuit, but also the location of the first sub-memory cell SMCa and the second sub-memory cell SMCb.

[0157] In order to read data from the selected memory cells MCs, the readout circuit 17, the row selection circuit 14, and the column selection circuit 15 are formed based on the control signal CN2 and the address signal ADD. Figure 14 The status shown is as follows. Details are as follows.

[0158] The readout circuit 17 outputs the readout potential Vread, the ground potential Vss, and the intermediate potential Vm.

[0159] The column selection circuit 15 keeps the signal CL at a high level. As a result, the selection bit line BLs and the sense amplifier SA (refer to...) are... Figure 9 The global bit line GBL in the sensor amplifier SA is connected, and the selected bit line BLs is connected to the global bit line BLs in the sense amplifier SA. The readout circuit 17 temporarily activates the signal PDE. During activation, the global bit line GBL and the global bit line BLs discharge. Subsequently, the column select circuit 15 connects the wiring Bvs, which is applied with a ground potential Vss, to the selected bit line BLs and the selected bit line BLs. The column select circuit 15 connects the wiring Bvm, which is applied with an intermediate potential Vm, to the non-selected bit line BLns and the non-selected bit line BLns.

[0160] Subsequently, the row selection circuit 14 connects the line Wvr to which the read potential Vread is applied to the select word line WLs. The row selection circuit 14 connects the line Wvs to which the ground potential Vss is applied to the non-select word line WLns.

[0161] Figure 14In the indicated state, the readout circuit 17 activates the sense amplifier enable signal SAE. As a result, the sense amplifier SA begins sensing operation. That is, a readout current Iread flows through the first sub-memory cell SMCas and the second sub-memory cell SMCbs. Using the readout current Iread, the potential based on the resistance state (P state or AP state) of the first sub-memory cell SMCas is transferred to the global bit line GBL. Additionally, using the readout current Iread, the potential based on the resistance state of the second sub-memory cell SMCbs is transferred to the global bit line ˉGBL. One of the selected sub-memory cells SMCas and SMCbs is in the P state, and the other is in the AP state. Therefore, there is a difference between the potential on the global bit line GBL and the potential on the global bit line ˉGBL. This difference is amplified by the sense amplifier SA. Through amplification, a power supply potential Vdd is displayed on one of nodes NBL1 and NBL2, and a ground potential Vss is displayed on the other. The data stored in the selected memory cell MCs is determined based on whether the potential on node NBL2 is higher than that on node NBL1 (e.g., whether it is the power supply potential Vdd) or lower than that on node NBL1 (e.g., whether it is the ground potential Vss). If the potential on node NBL2 is lower than that on node NBL1, it means that the first secondary memory cell SMCas is in the P state and the second secondary memory cell SMCbs is in the AP state. Therefore, the selected memory cell MCs is determined to store the data "1". Conversely, if the potential on node NBL2 is higher than that on node NBL1, it means that the first secondary memory cell SMCas is in the AP state and the second secondary memory cell SMCbs is in the P state. Therefore, the selected memory cell MCs is determined to store the data "0".

[0162] The first non-selected memory cell SMCans between the non-selected word line WLns and the non-selected bit line BLns, and the second non-selected memory cell SMCbns between the non-selected word line WLns and the non-selected bit line BLns, are in a half-selected state.

[0163] No potential difference is generated between the first non-selected sub-memory cell SMCans between the non-selected word line WLns and the select bit line BLs, and between the second non-selected sub-memory cell SMCbns between the non-selected word line WLns and the select bit line BLs. The first non-selected sub-memory cell SMCans between the select word line WLs and the non-selected bit line BLns, and between the second non-selected sub-memory cell SMCbns between the select word line WLs and the non-selected bit line BLs, are in a half-selected state. A half-select voltage is applied to the half-selected sub-memory cell SMCh. The half-select voltage is equal to the difference between the read potential Vread and the intermediate potential Vm. The intermediate potential Vm is higher than the ground potential Vss, and as described above, has, for example, half the size of the power supply potential Vdd. Therefore, the half-select voltage allows only a current smaller than the read current Iread to flow. Consequently, data cannot be read from the half-selected sub-memory cell SMCh, but data is selectively read from the selected memory cell MCs.

[0164] 1.3. Effects

[0165] According to the first embodiment, as described below, a resistance-variable type memory device that can operate at high speed and achieve high integration can be provided.

[0166] MTJ elements store data using low-resistance and high-resistance states. Data is read from an MTJ element based on whether it is in either a low-resistance or high-resistance state. The resistance state of an MTJ element is determined, for example, using a reference resistor that has the average resistance of the MTJ element in its low-resistance and high-resistance states. The resistance state of the MTJ element can be determined by whether the current flowing through the MTJ element being read is greater than or less than the current flowing through the reference resistor (hereinafter, sometimes called the reference current). When the MTJ element is in a low-resistance state, it will flow with a read current greater than the reference current (hereinafter, called the high read current); when it is in a high-resistance state, it will flow with a read current less than the reference current (hereinafter, called the low read current).

[0167] The greater the difference between the reference current and the high readout current, and / or the difference between the reference current and the low readout current, the larger the readout margin, enabling more accurate readout. The difference between the reference current and the high readout current, and the difference between the reference current and the low readout current, depends on the ratio of the resistance of the MTJ element in its low-resistance state to its resistance in its high-resistance state (MR (magnetoresistance) ratio). Therefore, a high MR ratio is expected for the MTJ element. However, the MR ratio is not as high as expected. As a countermeasure to low MR ratios, so-called self-reference readout is known. Self-reference readout includes a first data readout from the MTJ element being read, a data write to the MTJ element being read, and a second data readout from the MTJ element being read. However, self-reference readout requires time to identify the data.

[0168] As a countermeasure to low MR ratios, a 2MTJ per cell approach was considered. The 2MTJ per cell approach requires no reference current during data readout, thus avoiding the readout margin limitations caused by low MR ratios. However, while the number of MTJ elements in a resistance-varying memory device using the 2MTJ per cell approach is the same as in the case of one MTJ element per memory cell (sometimes referred to as the 1MTJ per cell approach), it only has half the storage capacity. To increase the storage capacity of a resistance-varying memory device using the 2MTJ per cell approach, the number of MTJ elements must be increased. However, this requires increasing the area of ​​the memory cell array in the resistance-varying memory device.

[0169] The resistance-varying memory device 1 of the first embodiment uses a 2MTJ per cell configuration. Therefore, data readout can be achieved regardless of the MR ratio of the MTJ elements VR. Furthermore, in the resistance-varying memory device 1 of the first embodiment, bit lines BL, word lines WL, and bit lines ˉBL are arranged along the z-axis, each first sub-memory cell SMCa is located between one bit line BL and one word line WL, and each second sub-memory cell SMCb is located between one word line WL and one bit line ˉBL. Therefore, the two sub-memory cells SMC constituting one memory cell MC are arranged along the z-axis. Thus, a two-dimensional memory cell array 11 with a certain number of sub-memory cells SMC can be provided with twice that number of sub-memory cells SMC. Even with the 2MTJ per cell configuration, sub-memory cells SMC for implementing the 2MTJ per cell configuration can be provided with the same area as the arrangement area of ​​memory cells in the 1MTJ per cell configuration. Therefore, a resistance-variable storage device 1 with the same area and storage capacity as the arrangement of storage cells MC in the 1MTJ per cell configuration can be realized.

[0170] 1.4. Variation Example

[0171] Data can also be read simultaneously from two or more memory cells (MCs) connected to the select word line (WLs).

[0172] The resistance-variable type memory device 1 of the variation example includes two or more sense amplifiers SA in the readout circuit 17. The number of sense amplifiers SA is the same as or more than the number of memory cells MC that are simultaneously read out. The group formed by the MCs that are simultaneously read out forms, for example, a column, and is specified according to the column address in the address signal ADD.

[0173] During data readout, column selection circuit 15 connects multiple select bit line pairs (BLPS) to a sense amplifier SA, and each of the multiple select bit line pairs (BLPS) is connected to a plurality of memory cells (MC) specified by the address signal ADD. In this state, each select bit line pair (BLPS) is simultaneously referenced. Figure 14 The data recorded on the BLPS with respect to one select bit line is read out.

[0174] 2. Second Implementation Method

[0175] The second embodiment is based on the first embodiment and involves data writing. Hereinafter, the features that differ from the first embodiment will be described.

[0176] 2.1. Composition

[0177] Figure 15 This represents a function block indicating the resistance-varying storage device of the second embodiment. (Regarding...) Figure 15 In the description, the undescribed constituent elements (functional blocks) are the same as the constituent elements of the first embodiment.

[0178] like Figure 15 As shown, the resistance-changing type memory device 1 of the second embodiment includes, in addition to the components included in the resistance-changing type memory device 1 of the first embodiment, a comparison circuit 18. The resistance-changing type memory device 1 of the second embodiment is sometimes referred to as the resistance-changing type memory device 1b to distinguish it from the resistance-changing type memory device 1 of the first embodiment. Furthermore, the control circuit 13, write circuit 16, and read circuit 17 of the second embodiment are partially different from those of the control circuit 13, write circuit 16, and read circuit 17 of the first embodiment. Hereinafter, the control circuit 13, write circuit 16, and read circuit 17 of the second embodiment are sometimes referred to as control circuit 13b, write circuit 16b, and read circuit 17b, respectively, to distinguish them from the control circuit 13, write circuit 16, and read circuit 17 of the first embodiment.

[0179] The write circuit 16b includes a data latch 16A. After the write circuit 16b receives the write data Dw, the data latch 16A stores the received write data Dw. Based on the control signal CN1, the write circuit 16b supplies the write data Dw stored in the data latch 16A to the comparator circuit 18.

[0180] The readout circuit 17b includes a data latch 17A. When the readout data Dr is acquired, the data latch 17A stores the readout data Dr. The readout circuit 17b supplies the readout data Dr to the comparator circuit 18 based on the control signal CN2.

[0181] Comparison circuit 18 receives control signal CN3 from control circuit 13b. Based on control signal CN3, comparison circuit 18 compares the received write data Dw with the received read data Dr. Based on the comparison result, comparison circuit 18 supplies signal SI to control circuit 13b. Signal SI transmits information about whether the write data Dw and the read data Dr are consistent or inconsistent.

[0182] The control circuit 13b, the write circuit 16b, the read circuit 17b, and the comparator circuit 18 are controlled in a manner that performs the actions described below.

[0183] 2.2. Actions

[0184] Figure 16 This describes the operation during data writing in the resistance-varying memory device of the second embodiment. Specifically, Figure 16 This indicates the action of writing data to the selected memory cell MCs. For example... Figure 16 As shown, data writing involves one or more loops. Figure 16 This represents an example of multiple loops. Each loop includes a write phase and a verification phase.

[0185] The write phase includes the same data write as described in the data write section of the first embodiment. However, as explained below, the write potential Vp and, consequently, the write voltage Vwd may differ in each cycle.

[0186] The verification phase includes the same data reading as described in the data reading section of the first embodiment. The verification phase also includes comparing the read data with the written data. In the verification phase of a certain loop included in a data writing process, if the read data and the written data match, the data writing ends. Conversely, in the verification phase of a certain loop, if the read data and the written data do not match, the data writing proceeds to the next loop.

[0187] Figure 17 and Figure 18This represents the potentials of several wirings during the data writing period of the second embodiment, arranged in chronological order. Specifically, Figure 17 It represents the potentials of the word line WL, bit line BL, and bit line ˉBL during the writing of data "1" to the selected memory cell MCs in chronological order. Figure 18 This represents the potentials of the word line WL and bit line BL, and ˉBL, during the writing of data "0" to the selected memory cell MCs, in chronological order. As part of the data writing process, refer to the following... Figure 17 and Figure 18 Before the recorded action, the written data Dw is saved to the data latch 16A.

[0188] 2.2.1. Writing the data "1"

[0189] like Figure 17 As shown, during data writing, a ground potential Vss is applied to the select bit lines BLs and ˉBLs. During data writing, an intermediate potential Vm is applied to the non-select word line WLns, the non-select bit line BLns, and the non-select bit line ˉBLns.

[0190] Control circuit 13b executes the first loop of writing data "1" from time t1 to time t5. The writing phase of the first loop is from time t1 to time t2. The verification phase of the first loop is from time t3 to time t5.

[0191] From time t1 to time t2, control circuit 13b writes the data "1" to the selected memory cell MCs. That is, at time t1, control circuit 13b controls write circuit 16b to apply a write potential Vp to the select word line WLs. The write potential Vp has a magnitude Vp1. Hereinafter, the write potential Vp of the nth cycle (n is a natural number) is sometimes referred to as the write potential Vpn. The application of write potential Vp1 continues until time t2. Through the potential application from time t1 to time t2, the data "1" is written to the selected memory cell MCs. More specifically, a write voltage Vwd is applied from the select word line WLs to the select bit line BLs, and a write voltage Vwd is applied from the select word line WLs to the select bit line BLs. Hereinafter, the write voltage Vwd of the nth cycle is sometimes referred to as the write voltage Vwdn. By applying write voltage Vwd1, the P write current Iwp flows in the first sub-memory cell SMCas, and the AP write current Iwap flows in the second sub-memory cell SMCbs. In the following, the AP write current Iwap flowing due to the write voltage Vwd in the nth cycle is sometimes referred to as the AP write current Iwapn. The P write current Iwp flowing due to the write voltage Vwd in the nth cycle is sometimes referred to as the P write current Iwpn.

[0192] From time t3 to time t4, control circuit 13b performs the verification of the first cycle of writing data "1". As part of this verification, control circuit 13b controls read circuit 17b to read data from the selected memory cell MCs. To do this, control circuit 13b controls read circuit 17b to apply read potential Vread to the selected word line WLs from time t3 to time t4. Through the action from time t3 to time t4, the read data Dr is obtained.

[0193] From time t4 to time t5, control circuit 13b compares the read data Dr with the write data Dw. More specifically, from time t4 to time t5, control circuit 13b performs the following operations: Control circuit 13b uses control signal CN1 to instruct write circuit 16b to supply write data Dw to comparison circuit 18. Additionally, control circuit 13b uses control signal CN2 to instruct read circuit 17b to supply read data Dr to comparison circuit 18. Control circuit 13b uses control signal CN3 to instruct comparison circuit 18 to output signal SI. Control signal CN3, for example, contains information to start comparison circuit 18. When signal SI indicates that read data Dr and write data Dw match, control circuit 13b completes the writing of the data "1". The case where read data Dr and write data Dw match is called verification success. On the other hand, when signal SI indicates that read data Dr and write data Dw do not match, control circuit 13b enters the second cycle. A discrepancy between the read data Dr and the written data Dw is called a verification failure.

[0194] The same actions performed in the first loop are repeated until verification is successful. However, after the second loop, the write potential Vpn used in the nth loop is ΔVn higher than the write potential Vpm used in the mth loop (m is n-1). ΔVn in a certain loop can be the same as or different from ΔVn in other loops.

[0195] The following is a summary of the actions following the second cycle, focusing on the potential applied to the select word line WLs. The second cycle occurs from time t6 to time t10. Specifically, from time t6 to time t7, control circuit 13b controls write circuit 16b to apply a write potential Vp2 to the select word line WLs. The write potential Vp2 has a magnitude equal to the sum of the write potential Vp1 and ΔV2. The write potential Vp2 is higher than the write potential Vp1. Therefore, the AP write current Iwap2 in the second cycle is higher than the AP write current Iwap1 in the first cycle, and the P write current Iwp2 in the second cycle is higher than the P write current Iwp1 in the first cycle.

[0196] For all instances where n is an integer greater than 3, the actions at times t(5n-4), t(5n-3), t(5n-2), t(5n-1), and t(5n) in the nth cycle are the same as those at times t1, t2, t3, t4, and t5, except that the write potential Vpn is used.

[0197] 2.2.2. Writing data "0"

[0198] Writing data "0" is similar to writing data "1". The following describes the differences between writing data "0" and writing data "1". The difference lies in the voltage application during the write phase. Specifically, in each write phase, a ground potential Vss is applied to the select word line WLs, and a write potential Vp is applied to the select bit lines BLs and ˉBLs. More details are as follows.

[0199] like Figure 18 As shown, control circuit 13b executes the first loop of writing data "0" from time t31 to time t35. The writing phase of the first loop is from time t31 to time t32. The verification phase of the first loop is from time t33 to time t35.

[0200] From time t31 to time t32, control circuit 13b writes the data "0" to the selected memory cell MCs. That is, at time t31, control circuit 13b controls write circuit 16b to apply a write potential Vp1 to the select bit lines BLs and ˉBLs. Through the potential application from time t31 to time t32, a write voltage Vwd1 is applied from the select bit line BLs to the select word line WLs, and from the select bit line ˉBLs to the select word line WLs. By applying the write voltage Vwd1, the AP write current Iwap1 flows through the first sub-memory cell SMCas, and the P write current Iwp flows through the second sub-memory cell SMCbs.

[0201] The actions from time t33 to time t34 are the same as the actions from time t3 to time t4 during the writing of data "1".

[0202] The second loop is the same as the first loop in writing data "0". That is, for all instances of integers n greater than 2, the actions at times t(20n-4), t(20n-3), t(20n-2), t(20n-1), and t(20n) in the nth loop are the same as those at times t31, t32, t33, t34, and t35, respectively, except that the write potential Vpn is used.

[0203] 2.3. Effects

[0204] The resistance-varying memory device 1b of the second embodiment is the same as that of the first embodiment, using a 2MTJ per cell configuration. Furthermore, in the resistance-varying memory device 1b, as in the first embodiment, the bit line BL, word line WL, and bit line ˉBL are arranged along the z-axis, each first sub-memory cell SMCa is located between one bit line BL and one word line WL, and each second sub-memory cell SMCb is located between one word line WL and one bit line ˉBL. Therefore, the same effects as in the first embodiment can be obtained.

[0205] Furthermore, according to the second embodiment, as described below, a resistance-varying memory device in which write defects are suppressed can be realized.

[0206] As a countermeasure to address the low MR ratio of MTJ components, self-reference readout is known. Self-reference readout can be applied to a 1-MTJ per cell configuration. In self-reference readout, data reading from a single memory cell (hereinafter, sometimes referred to as a memory cell MCR) includes reading data from the memory cell MCR (hereinafter, sometimes referred to as a selected memory cell MCRs), writing data to the selected memory cell MCRs, and reading data from the selected memory cell MCRs. The data stored in the selected memory cell MCRs is identified by comparing the result of the first data readout with the result of the second data readout.

[0207] Self-reference readout can be applied to Figure 4 and Figure 5 The structure is as follows. However, in this case, the structure used as a secondary memory cell SMC in the first embodiment is used as a single memory cell MCR. There is no need to distinguish between bit lines BL and bit lines ˉBL as in the first embodiment. Therefore, the conductor 23 used as bit line ˉBL in the first embodiment also functions as bit line BL. Each memory cell MCR is selected using a word line (select word line WLs) connected to that memory cell and a bit line (select bit line BLs) connected to that memory cell MCR. Data readout is the same as in the first embodiment, applying a readout potential Vread to the select word line WLs, and then comparing the first and second data readout results from the sense amplifier connected to the select bit line BLs. During data readout, as in the first embodiment, an intermediate potential Vm is applied to the non-select word line WLns and the non-select bit line BLns. The non-select memory cell MCR between the select word line WLs and the non-select bit line BLns is sometimes referred to as a half-select memory cell MCRh. Figure 4 and Figure 5 The structure employs a resistance-varying memory device with self-reference readout, sometimes referred to as a reference resistance-varying memory device 100.

[0208] have Figure 4 and Figure 5 Regardless of the read method, resistive variable memory devices can cause write interference. This means that applying a half-select voltage to the half-select memory cell MCRh can cause unwanted data writes, i.e., accidental writes, to the half-select memory cell MCRh with a certain probability.

[0209] Incorrect writes can be suppressed by decreasing the half-select voltage. The half-select voltage depends on the difference between the write potential Vp and the intermediate potential Vm, and the difference between the intermediate potential Vm and the ground potential Vss. Therefore, by using a smaller write potential Vp and a smaller intermediate potential Vm, the half-select voltage can be suppressed, thereby suppressing incorrect writes. However, decreasing the write potential Vp leads to a decrease in the write voltage Vwd. A decrease in the write voltage Vwd leads to a decrease in the AP write current Iwap and the P write current Iwp, which in turn increases write errors (write failures). Therefore, adjusting the write potential Vp and the intermediate potential Vm cannot achieve both write interference suppression and write error suppression.

[0210] Write interference suppression and erroneous write suppression can be achieved by repeatedly executing a loop that includes verification. That is, by suppressing the write potential Vp and the intermediate potential Vm in the first loop, write interference can be suppressed. On the other hand, write errors may occur due to the limitation of the write voltage Vwd. However, by repeatedly executing verification and loops where each loop is accompanied by a rise in the write potential Vp, writes at the lowest write voltage Vwd that can suppress write interference can be achieved. However, as mentioned above, self-reference reads involve two data reads from the selected memory cells (MCRs) during the identification of data requiring verification. Therefore, each verification in the loop requires two data reads. Consequently, the combined use of self-reference reads and verification makes data writing excessively long.

[0211] The resistance-varying memory device 1b of the second embodiment employs a 2MTJ per cell configuration. As described in the first embodiment, in the 2MTJ per cell configuration, although data reading from the selected memory cell MCs includes data reading from two selected secondary memory cells SMCs, these readings are performed simultaneously. Therefore, the resistance-varying memory device 1b does not require, for example, the two data reads required for self-reference reading from the selected memory cells MCRs, nor does it require, for example, data writing required for self-reference reading. Thus, the resistance-varying memory device 1b can read data in a short time. Therefore, verification can be performed in a short time, and the repetition of the verification cycle only requires a shorter time than that required by the reference resistance-varying memory device 100. Thus, the resistance-varying memory device 1b can achieve write interference suppression, write error suppression, and data writing in a short time.

[0212] 3. Third Implementation Method

[0213] The third embodiment differs from the first embodiment in the construction of the memory cell array. Hereinafter, the features that differ from the first embodiment will be mainly described.

[0214] 3.1. Composition

[0215] Hereinafter, the resistance-changing type memory device 1 of the third embodiment will sometimes be referred to as the resistance-changing type memory device 1c, in order to distinguish it from the resistance-changing type memory devices 1 of the first and second embodiments. The resistance-changing type memory device 1c includes a memory cell array 11 that is different from the memory cell array 11 of the resistance-changing type memory device 1 of the first embodiment. Hereinafter, the memory cell array 11 of the third embodiment will sometimes be referred to as the memory cell array 11c, in order to distinguish it from the memory cell array 11 of the first embodiment.

[0216] Figure 19 and Figure 20 This shows a partial planar structure of the storage cell array 11c in the third embodiment. Figure 19 and Figure 20 This represents the construction along the xy plane, and also represents the same region on the xy plane. Figure 19 This represents a set of multiple layers arranged along the z-axis. Figure 20 express Figure 19 A portion of the layer shown, and compared to Figure 19 The layer shown is the uppermost layer. Figure 19 and Figure 20 The elements are marked with shading to make them easily distinguishable by visual inspection. However, the shading is only used to distinguish the elements; the material of the elements is not specific to or limited by the material indicated by the shading pattern.

[0217] like Figure 19 As shown, multiple conductors 51 are disposed on a certain layer. The conductors 51 include conductors 51A and conductors 51B. Conductors 51A extend along the x-axis and are arranged at intervals along the y-axis. Each conductor 51A functions as at least part of a word line WL.

[0218] Conductors 51B extend along the y-axis. Each conductor 51B is located between a group of conductors 51A arranged along the y-axis and another group of conductors 51A arranged along the y-axis. Each conductor 51B is spaced apart from the conductors 51A on either side of it. Each conductor 51B functions as at least part of a bit line BL.

[0219] On the layer above the conductor 51, a plurality of contact plugs 53 and a plurality of sub-memory cells (SMCs) are disposed. The contact plugs 53 are circular, for example, along the xy-plane. The contact plugs 53 include contact plugs 53A and 53B. One contact plug 53A and one contact plug 53B form a pair. Each pair of contact plugs 53A and 53B at least partially overlaps with one conductor 51A, for example, located directly above one conductor 51A along the z-axis. Contact plug 53A overlaps with the left end of conductor 51A. Contact plug 53B overlaps with the right end of conductor 51A. The plurality of contact plugs 53A, which overlap with the plurality of conductors 51A arranged along the y-axis, are arranged along the y-axis. The plurality of contact plugs 53B, which overlap with the plurality of conductors 51A arranged along the y-axis, are arranged along the y-axis.

[0220] Each sub-memory cell SMCb overlaps at least partially with one conductor 51A, for example, located directly above one conductor 51A along the z-axis. Each sub-memory cell SMCb is located between one contact plug 53A and one contact plug 53B. In other words, one contact plug 53A, one sub-memory cell SMCb, and one contact plug 53B are arranged along the x-axis above each conductor 51A along the z-axis. Multiple sub-memory cells SMCb, which overlap with the multiple conductors 51A arranged along the y-axis, are arranged along the y-axis.

[0221] Each sub-memory cell SMCa at least partially overlaps with a conductor 51B, for example, located directly above the conductor 51B along the z-axis. Several sub-memory cells SMCa are arranged at intervals along the y-axis. Each sub-memory cell SMCa is located between two conductors 51A arranged along the x-axis. Thus, a contact plug 53B, a sub-memory cell SMCa, and a contact plug 53A are arranged along the x-axis.

[0222] A memory cell MC is formed by a contact plug 53 arranged along the x-axis and the area extending along the x-axis to the two secondary memory cells SMC on both sides. Figure 19 The following figures and descriptions are based on an example where each memory cell MC contains one sub-memory cell SMCa, contact plug 53A, and one sub-memory cell SMCb arranged along the x-axis within a single memory cell MC. However, each memory cell MC may also contain one sub-memory cell SMCb, contact plug 53B, and one sub-memory cell SMCa arranged along the x-axis within a single memory cell MC.

[0223] like Figure 20As shown, a plurality of conductors 55 are disposed on the layer above the layer containing the contact plug 53 and the plurality of sub-memory cells SMC. The conductors 55 include conductors 55A and 55B. Conductors 55A extend along the x-axis and are arranged at intervals along the y-axis. Each conductor 55A partially overlaps with one contact plug 53B, one sub-memory cell SMCa, and one contact plug 53A arranged along the x-axis. For example, each conductor 55A is located directly above one contact plug 53B, one sub-memory cell SMCa, and one contact plug 53A arranged along the z-axis. Each conductor 55A functions as at least a part of a word line WL.

[0224] Each conductor 55B extends along the y-axis. Each conductor 55B is located between a group of conductors 55A arranged along the y-axis and another group of conductors 55A arranged along the y-axis. Each conductor 55B is spaced apart from the two conductors 55A on either side of it. Each conductor 55B partially overlaps with a group of sub-memory cells SMCb arranged along the y-axis, for example, located directly above the group of sub-memory cells SMCb arranged along the z-axis. Each conductor 55B functions as at least a part of a bit line BL.

[0225] Figure 21 , Figure 22 , Figure 23 and Figure 24 This shows a partial cross-sectional structure of the memory cell array 11c of the third embodiment. Figure 21 Indicates along Figure 19 and Figure 20 The cross section of the XXI-XXI line. Figure 22 Indicates along Figure 19 and Figure 20 The cross section of line XXII-XXII. Figure 23 Indicates along Figure 19 and Figure 20 The cross section of line XXIII-XXIII. Figure 24 Indicates along Figure 19 and Figure 20 The cross section of line XXIV-XXIV.

[0226] like Figure 21 As shown and referenced Figure 19 and Figure 20 As recorded, in Figure 21 In the bottom layer shown, conductors 51A and 51B are arranged alternately along the x-axis. Conductors 51A and 51B originate from the same conductor. That is, conductors 51A and 51B are formed by partially removing the conductors that extend along the xy plane for conductors 51A and 51B.

[0227] Contact plugs 53A and 53B, and sub-memory cells SMCa and SMCb, are located on the layer above the layers containing conductors 51A and 51B. Groups consisting of one contact plug 53A, one sub-memory cell SMCb, and one contact plug 53B are located on the upper surface of one conductor 51A. Each group of one contact plug 53A, one sub-memory cell SMCb, and one contact plug 53B is arranged at intervals along the x-axis. Each sub-memory cell SMCa is located on the upper surface of one conductor 51B.

[0228] The secondary memory cells SMCa and SMCb originate from the same material. That is, the constituent elements in a certain layer of the secondary memory cell SMCa and the constituent elements in the same layer of the secondary memory cell SMCb originate from the same material (conductor, insulator, or ferromagnetic material, etc.). More details are as follows. (See reference...) Figure 6 As described, the sub-memory cell SMC comprises multiple components, including a selector SE, a ferromagnetic layer 41, an insulating layer 42, and a ferromagnetic layer 43, which are stacked together. In the third embodiment, the sub-memory cells SMCa and SMCb are formed simultaneously through a series of steps in the manufacturing process of the resistance-varying memory device 1c. As an example, if based on... Figure 6 The construction involves forming a material extending along the xy plane for the selector SE. By partially removing this material, selectors SEa and SEb for the sub-memory cells SMCa and SMCb are formed, respectively. The same applies to the ferromagnetic layer 41, insulating layer 42, and ferromagnetic layer 43. Multiple materials extending along the xy plane for the ferromagnetic layer 41, insulating layer 42, and ferromagnetic layer 43 are stacked, and these materials are partially removed, thereby forming the MTJ element VRa for the sub-memory cell SMCa and the MTJ element VRb for the sub-memory cell SMCb. Regardless of whether the sub-memory cells SMCa and SMCb have... Figure 6 The same applies whether it is an example of another component not shown, or an example of one or more components including the selector SE, ferromagnetic layer 41, and ferromagnetic layer 43. Therefore, it is possible to suppress the characteristic deviations of SMCa and SMCb caused by process deviations.

[0229] Conductors 55A and 55B are located on the layer above contact plugs 53A and 53B, and sub-memory cells SMCa and SMCb. Each conductor 55A is in contact with the upper surface of one contact plug 53B, one sub-memory cell SMCa, and one contact plug 53A. Each conductor 55B is located on the upper surface of one sub-memory cell SMCb. Conductors 55A and 55B originate from the same conductor. That is, conductors 55A and 55B are formed by partially removing the conductors that extend along the xy plane for conductors 55A and 55B.

[0230] like Figure 22 As shown and referenced Figure 19 and Figure 20 As described, the sub-memory cell SMCa is located on the upper surface of each conductor 51B. Each conductor 55A is in contact with the upper surface of the respective sub-memory cell SMCa arranged along the y-axis on its bottom surface.

[0231] like Figure 23 As shown and referenced Figure 19 and Figure 20 As described, one contact plug 53A is located on the upper surface of each conductor 51A. Each conductor 55B is located on the upper surface of one contact plug 53A.

[0232] like Figure 24 As shown and referenced Figure 19 and Figure 20 As described, one sub-memory cell SMCb is located on the upper surface of each conductor 51A. Each conductor 55B is connected at its bottom surface to the upper surface of each sub-memory cell SMCb arranged along the y-axis.

[0233] 3.2. Effects

[0234] The memory cell array 11c of the third embodiment can also be constructed according to the reference configuration of the first embodiment. Figure 3 The circuit described herein. Therefore, according to the third embodiment, a 2MTJ configuration per unit can also be implemented, and for the same reasons as described in the first embodiment, data readout with an MR ratio independent of the MTJ element VR can be performed.

[0235] Furthermore, according to the third embodiment, as described below, a resistance-variable type memory device 1c can be provided that makes it easier to control the data writing and / or data reading of the memory cell MC.

[0236] The secondary memory cell (SMC) is heat-sensitive. Therefore, by applying heat to the SMC during the manufacturing process, its characteristics may change. The secondary memory cells SMCa and SMCb originate from a group of the same multiple laminated components and are formed through the same series of manufacturing processes. Consequently, SMCa and SMCb undergo the same heat treatment, during which their characteristics change in the same way. This suppresses characteristic deviations in SMCa and SMCb, ensuring they have substantially identical characteristics. Therefore, the P-write current Iwp and AP-write current Iwap required for SMCa are very close to, for example, substantially the same as, the P-write current Iwp and AP-write current Iwap required for SMCb. This suppresses the difference between the conditions required to write data "0" to the selected memory cell MCs (e.g., write voltage Vwd) and the conditions required to write data "1" to the selected memory cell MCs. This facilitates data writing control.

[0237] Furthermore, by suppressing the characteristic deviations of the sub-cells SMCa and SMCb, the resistances of the sub-cell SMCa in its low-resistance state and high-resistance state are very close to, for example, substantially the same as, the resistances of the sub-cell SMCb in its low-resistance state and high-resistance state. This suppresses the difference between the conditions required to read data "0" from the selected cell MCs (e.g., the read potential Vread) and the conditions required to read data "1" from the selected cell MCs. Therefore, data readout is easily controlled.

[0238] 3.3. Variation Example

[0239] The resistance-varying memory device 1c of the third embodiment employs a 2MTJ per cell. Therefore, the third embodiment can be combined with the second embodiment to further achieve the same effects as those obtained through the second embodiment.

[0240] 4. Fourth Implementation Method

[0241] The fourth embodiment differs from the first and third embodiments in the construction of the storage cell array. Hereinafter, the features that differ from the third embodiment will be mainly described.

[0242] 4.1. Composition

[0243] Hereinafter, the resistance-varying memory device 1 of the fourth embodiment will sometimes be referred to as the resistance-varying memory device 1d, in order to distinguish it from the resistance-varying memory devices 1 of the first and third embodiments. The resistance-varying memory device 1 includes a memory cell array 11 that is different from the memory cell array 11 of the first and third embodiments. Hereinafter, the memory cell array 11 of the fourth embodiment will sometimes be referred to as the memory cell array 11d, in order to distinguish it from the memory cell array 11 of the first and third embodiments.

[0244] Figure 25 This shows a partial planar structure of the storage cell array 11d in the fourth embodiment. Figure 25 This indicates the construction along the xy plane. Figure 25 The elements are marked with shading to make them easily distinguishable by visual inspection. However, the shading is only used to distinguish the elements; the material of the elements is not specific to or limited by the material indicated by the shading pattern.

[0245] like Figure 25 As shown, the secondary storage cells SMC (SMCa and SMCb) and contact plugs 53 (53A and 53B) are arranged along the x-axis but not along the y-axis. Specifically: Several contact plugs 53 are arranged along the x-axis, and multiple groups of contact plugs 53 arranged along the x-axis are arranged along the y-axis. Additionally, several contact plugs 53 are arranged along the y-axis, and multiple groups of contact plugs 53 arranged along the y-axis are arranged along the x-axis. In other words, the contact plugs 53 are arranged in a matrix. Each row of the matrix of contact plugs 53 (a group of contact plugs 53 arranged along the x-axis) contains alternately arranged contact plugs 53A and 53B. The matrix of contact plugs 53 contains multiple columns of contact plugs 53A (a group of contact plugs 53A arranged along the y-axis) and multiple columns of contact plugs 53B. The columns of contact plugs 53A and 53B are arranged alternately along the x-axis.

[0246] Each column of the secondary storage cell SMC is located between one column of contact plug 53A and one column of contact plug 53B. For example, each column of the secondary storage cell SMC is located between two columns of contact plug 53. The columns of contact plug 53A and contact plug 53B are arranged alternately along the x-axis. The column of contact plug 53B is located to the left of the column of secondary storage cell SMCa, and the column of contact plug 53A is located to the right of the column of secondary storage cell SMCa. The column of contact plug 53A is located to the left of the column of secondary storage cell SMCb, and the column of contact plug 53B is located to the right of the column of secondary storage cell SMCa.

[0247] Several secondary storage cells (SMCs) are arranged along the x-axis. Each row of secondary storage cells (a group of SMCs arranged along the x-axis) contains alternately arranged secondary storage cells SMCa and SMCb. Each row of secondary storage cells (SMCs) is located on the y-axis, between two rows of contact plugs 53. For example, each row of secondary storage cells (SMCs) is located in the middle of two rows of contact plugs 53.

[0248] With the configuration described above, the secondary storage cells (SMCs) are arranged in a matrix.

[0249] The sub-storage units SMCa and SMCb, as well as contact plugs 53A and 53B, configured as described above are the same as those in the third embodiment, and are electrically connected to conductors 51A and 51B. Details are as follows.

[0250] Each conductor 51A is the same as in the third embodiment, connected to the bottom surface of each of the contact plugs 53A, SMCb, and 53B. Therefore, each conductor 51A extends along the contact plug 53A, SMCb, and 53B. Each conductor 51A extends across the position of the contact plug 53A connected to it along the z-axis and the position of the contact plug 53B connected to it along the z-axis. Each conductor 51A extends, for example, along an axis rotated 45° clockwise from the x-axis.

[0251] Each conductor 55A is the same as in the third embodiment, connected to the upper surface of one contact plug 53B, one sub-memory cell SMCa, and one contact plug 53A respectively. Therefore, it extends along one contact plug 53B, one sub-memory cell SMCa, and one contact plug 53A. Each conductor 55A extends across the position of the contact plug 53B connected to it above the z-axis and the position of the contact plug 53A connected to it above the z-axis. Each conductor 55A extends along an axis rotated 45° counterclockwise from the x-axis.

[0252] 4.2. Effects

[0253] The memory cell array 11d of the fourth embodiment can also be constructed according to the reference configuration of the first embodiment. Figure 3 The circuit described herein. Therefore, according to the fourth embodiment, a 2MTJ configuration per unit can also be implemented, and for the same reasons as described in the first embodiment, data readout with an MR ratio independent of the MTJ element VR can be performed.

[0254] Furthermore, according to the fourth embodiment, similar to the third embodiment, the sub-memory cells SMCa and SMCb originate from a group composed of the same multiple stacked components and are formed through the same series of processes. Therefore, the same effects as in the third embodiment can be obtained.

[0255] Furthermore, according to the fourth embodiment, the contact plugs 53 and the sub-memory cells SMC do not form rows along the x-axis, nor columns along the y-axis. The rows of contact plugs 53 and the rows of sub-memory cells SMC are arranged alternately, and the columns of contact plugs 53 and the columns of sub-memory cells SMC are arranged alternately. Therefore, each sub-memory cell SMC is located at the center of an arrangement of four contact plugs 53, each located at a vertex of a square, and each contact plug 53 is located at the center of an arrangement of four sub-memory cells SMC, each located at a vertex of a square. This enables a high-density configuration of the sub-memory cells SMC and contact plugs 53. If the conductors 51 and 55 of the third and fourth embodiments are formed with the smallest achievable line and gap pattern size, then according to the fourth embodiment, the contact plugs 53 and sub-memory cells SMC can be configured at a higher density than in the third embodiment.

[0256] 5. Fifth Implementation Method

[0257] The fifth embodiment differs from the first, third, and fourth embodiments in the construction of the storage cell array. Hereinafter, the features that differ from the third embodiment will be mainly described.

[0258] 5.1. Composition

[0259] Hereinafter, the resistance-varying memory device 1 of the fifth embodiment will sometimes be referred to as the resistance-varying memory device 1e, in order to distinguish it from the resistance-varying memory devices 1 of the first, third, and fourth embodiments. The resistance-varying memory device 1 includes a memory cell array 11 that is different from the memory cell array 11 of the first, third, and fourth embodiments. Hereinafter, the memory cell array 11 of the fifth embodiment will sometimes be referred to as the memory cell array 11e, in order to distinguish it from the memory cell array 11 of the first, third, and fourth embodiments.

[0260] Figure 26 and Figure 27 This shows a partial planar structure of the storage cell array 11e in the fifth embodiment. Figure 26 and Figure 27 This represents the construction along the xy plane, and also represents the same region within the xy plane. Figure 26 and Figure 27 This represents a set of multiple layers arranged along the z-axis. Figure 27 express Figure 26 A portion of the layer shown, and compared to Figure 26 The layer shown is the uppermost layer. Figure 26 and Figure 27 The elements are marked with shading to make them easily distinguishable by visual inspection. However, the shading is only used to distinguish the elements; the material of the elements is not specific to or limited by the material indicated by the shading pattern.

[0261] The storage cell array 11e is similar to the storage cell array 11d in the third embodiment. In the fourth embodiment, one sub-storage cell SMC is disposed between the contact plugs 53A and 53B arranged along the x-axis. In contrast, in the fifth embodiment, two sub-storage cells SMC are disposed between the contact plugs 53A and 53B arranged along the x-axis.

[0262] like Figure 26 As shown, conductor 51 includes conductor 51B and conductor 51C. Conductors 51C extend along the x-axis and are arranged at intervals along the y-axis. Each conductor 51C functions as at least a part of a word line WL.

[0263] Each conductor 51B is located between a group of conductors 51C arranged along the y-axis and another group of conductors 51C arranged along the y-axis. Two conductors 51B are disposed between each pair of conductors 51C arranged along the x-axis.

[0264] Each contact plug 53A at least partially overlaps with a conductor 51C, for example, located directly above the conductor 51C along the z-axis. Each contact plug 53A is at the left end of a conductor 51C, overlapping with it. Each contact plug 53B at least partially overlaps with a conductor 51C, for example, located directly above the conductor 51C along the z-axis. Each contact plug 53B is at the right end of a conductor 51C, overlapping it.

[0265] Each of the two secondary storage cells SMCa is located between one contact plug 53B and one contact plug 53A, for example, one contact plug 53B and one contact plug 53A are arranged along the x-axis.

[0266] Each sub-memory cell SMCb at least partially overlaps with one conductor 51C, for example, located directly above one conductor 51C along the z-axis. Each conductor 51C at least partially overlaps with two (a pair) sub-memory cells SMCb. Each pair of sub-memory cells SMCb is located between one contact plug 53A and one contact plug 53B. For example, one contact plug 53A, two sub-memory cells SMCb, and one contact plug 53B are arranged along the x-axis. Several sub-memory cells SMCb are arranged at intervals along the y-axis.

[0267] Each group of four sub-storage cells SMC, consisting of two (one pair) sub-storage cells SMCa arranged along the x-axis and two (one pair) sub-storage cells SMCb arranged side-by-side with the sub-storage cell SMCa pair, constitutes two storage cells MC. Specifically, one sub-storage cell SMCa on the first side (e.g., the left side) of the sub-storage cell SMCa pair, and one sub-storage cell SMCb on the first side of the sub-storage cell SMCb pair arranged side-by-side with the sub-storage cell SMCa pair, constitutes one storage cell MC1. One sub-storage cell SMCa on the second side (e.g., the right side) of the sub-storage cell SMCa pair, and one sub-storage cell SMCb on the second side of the sub-storage cell SMCb pair arranged side-by-side with the sub-storage cell SMCa pair, constitutes one storage cell MC2.

[0268] like Figure 27 As shown, conductor 55 includes conductor 55B and conductor 55C. Conductors 55C extend along the x-axis and are arranged at intervals along the y-axis. Each conductor 55C partially overlaps with one contact plug 53B, two sub-memory cells SMCa, and one contact plug 53A arranged along the x-axis. For example, each conductor 55C is located directly above the one contact plug 53B, two sub-memory cells SMCa, and one contact plug 53A arranged along the x-axis along the z-axis. Each conductor 55C functions as at least a part of a word line WL.

[0269] Conductor 55B is located between a group of conductors 55C arranged along the y-axis and another group of conductors 55C arranged along the y-axis. Two conductors 55B are disposed between each pair of conductors 55C arranged along the x-axis.

[0270] Figure 28 This shows a partial cross-sectional structure of the memory cell array 11e in the fifth embodiment. Figure 28 Indicates along Figure 26 and Figure 27 The cross section of the XXVIII-XXVIII line.

[0271] like Figure 28 As shown and referenced Figure 26 and Figure 27 As recorded, in Figure 28 The bottommost layer shown consists of groups of one conductor 51C and two conductors 51B arranged alternately along the x-axis. Conductors 51B and 51C originate from the same conductor. That is, conductors 51B and 51C are formed by partially removing the conductors that extend along the xy plane for conductors 51B and 51C.

[0272] Contact plugs 53A and 53B, and sub-memory cells SMCa and SMCb are located on the layer above the layers containing conductors 51B and 51C. Each group consisting of one contact plug 53A, two sub-memory cells SMCb, and one contact plug 53B is located on the upper surface of one conductor 51C.

[0273] Each sub-memory cell SMCa is located on the upper surface of a conductor 51B.

[0274] Conductors 55B and 55C are located on the layer above the layers containing contact plugs 53A and 53B, as well as sub-memory cells SMCa and SMCb. Each conductor 55C is in contact with the upper surface of one contact plug 53B, two sub-memory cells SMCa, and one contact plug 53A on its bottom surface.

[0275] 5.2. Effects

[0276] The memory cell array 11e of the fifth embodiment can also be constructed according to the reference configuration of the first embodiment. Figure 3 The circuit described herein. Therefore, according to the fifth embodiment, a 2MTJ configuration per unit can also be implemented, and for the same reasons as described in the first embodiment, data readout with an MR ratio independent of the MTJ element VR can be performed.

[0277] Furthermore, according to the fourth embodiment, similar to the third embodiment, the sub-memory cells SMCa and SMCb originate from a group composed of the same multiple stacked components and are formed through the same series of manufacturing processes. Therefore, the same effects as in the third embodiment can be obtained.

[0278] Furthermore, according to the fifth embodiment, two sub-memory cells (SMCs) are arranged along the x-axis between one contact plug 53A and one contact plug 53B. This enables a high-density configuration of the sub-memory cells (SMCs). If the conductors 51 and 55 of the third and fifth embodiments are formed with the smallest achievable line and gap pattern size, then according to the fifth embodiment, the contact plug 53 and the sub-memory cells (SMCs) can be configured at a higher density than in the third embodiment, where one sub-memory cell (SMC) is disposed between the contact plugs 53A and 53B arranged along the x-axis.

[0279] 6. Sixth Implementation Method

[0280] The sixth embodiment differs from the first, third, fourth, and fifth embodiments in the construction of the memory cell array. Hereinafter, the features that differ from the fifth embodiment will be mainly described.

[0281] 6.1. Composition

[0282] Hereinafter, the resistance-varying memory device 1 of the sixth embodiment will sometimes be referred to as the resistance-varying memory device 1f, in order to distinguish it from the resistance-varying memory devices 1 of the first, third, fourth, and fifth embodiments. The resistance-varying memory device 1 includes a memory cell array 11 different from the memory cell array 11 of the first, third, fourth, and fifth embodiments. Hereinafter, the memory cell array 11 of the sixth embodiment will sometimes be referred to as the memory cell array 11f, in order to distinguish it from the memory cell array 11 of the first, third, fourth, and fifth embodiments.

[0283] The sixth embodiment is an extension of the fifth embodiment. That is, in the sixth embodiment, four sub-storage cells (SMCs) are arranged between the contact plugs 53A and 53B arranged along the x-axis.

[0284] Figure 29 and Figure 30 This shows a partial structure of the memory cell array 11f in the sixth embodiment. Figure 29 and Figure 30 This represents the construction along the xy plane, and also represents the same region on the xy plane. Figure 29 and Figure 30 This represents a set of multiple layers arranged along the z-axis. Figure 30 express Figure 29 A portion of the layer shown, and compared to Figure 29 The layer shown is the uppermost layer. Figure 29 and Figure 30 The elements are marked with shading to make them easily distinguishable by visual inspection. However, the shading is only used to distinguish the elements; the material of the elements is not specific to or limited by the material indicated by the shading pattern.

[0285] like Figure 29 As shown, four conductors 51B are disposed between each pair of conductors 51C arranged along the x-axis among a plurality of conductors 51C.

[0286] Each of the four sub-storage cells SMCa is located between one contact plug 53B and one contact plug 53A, for example, one contact plug 53B and one contact plug 53A are arranged along the x-axis.

[0287] Each conductor 51C overlaps with one group of four sub-memory cells SMCb. Each group of sub-memory cells SMCb is located between one contact plug 53A and one contact plug 53B. For example, one contact plug 53A, four sub-memory cells SMCb, and one contact plug 53B are arranged along the x-axis. Several sub-memory cells SMCb are arranged at intervals along the y-axis.

[0288] Each of the eight sub-storage cells SMC, consisting of four (groups) of sub-storage cells SMCa and four (groups) of sub-storage cells SMCb, constitutes a storage cell MC1. The four (groups) of sub-storage cells SMCa are arranged along the x-axis, and the four (groups) of sub-storage cells SMCb, with the spacer contact plug 53, are arranged side-by-side with the sub-storage cell SMCa group. That is, the first sub-storage cell SMCa from the first side (e.g., the leftmost side) of the sub-storage cell SMCa group, and the first sub-storage cell SMCb from the first side of the sub-storage cell SMCb group with the spacer contact plug 53, constitutes a storage cell MC2. The third sub-storage cell SMCa from the first side of the sub-storage cell group SMCa, along with the dielectric contact plug 53, and the third sub-storage cell SMCb from the first side of the sub-storage cell group SMCb arranged side-by-side with the sub-storage cell group SMCa, constitute one storage cell MC3. The fourth sub-storage cell SMCa from the first side of the sub-storage cell group SMCa, along with the dielectric contact plug 53, and the fourth sub-storage cell SMCb from the first side of the sub-storage cell group SMCb arranged side-by-side with the sub-storage cell group SMCa, constitute one storage cell MC4.

[0289] like Figure 30 As shown, each conductor 55C partially overlaps with one contact plug 53B, four sub-memory cells SMCa, and one contact plug 53A arranged along the x-axis. For example, each conductor 55C is located directly above the one contact plug 53B, four sub-memory cells SMCa, and one contact plug 53A arranged along the z-axis.

[0290] Four conductors 55B are disposed between each pair of conductors 55C arranged along the x-axis.

[0291] Figure 31 This shows a partial cross-sectional structure of the memory cell array 11f in the fifth embodiment. Figure 31 Indicates along Figure 29 and Figure 30 The cross section of the XXXI-XXXI line.

[0292] like Figure 31 As shown and referenced Figure 29 and Figure 30 As recorded, in Figure 31The bottommost layer shown consists of alternating groups of one conductor 51C and four conductors 51B along the x-axis. Groups consisting of one contact plug 53A, four sub-memory cells SMCb, and one contact plug 53B are located on the upper surface of one conductor 51C. Each conductor 55C is in contact with the upper surfaces of one contact plug 53B, four sub-memory cells SMCb, and one contact plug 53A on its bottom surface.

[0293] 6.2. Effects

[0294] Based on the construction of the memory cell array 11f in the sixth embodiment, the reference array in the first embodiment can also be constructed. Figure 3 The circuit described herein. Therefore, according to the sixth embodiment, a 2MTJ configuration per unit can also be implemented, and for the same reasons as described in the first embodiment, data readout with an MR ratio independent of the MTJ element VR can be performed.

[0295] Furthermore, according to the sixth embodiment, similar to the third embodiment, the sub-memory cells SMCa and SMCb originate from a group composed of the same multiple stacked components and are formed through the same series of manufacturing processes. Therefore, the same effects as in the third embodiment can be obtained.

[0296] Furthermore, according to the sixth embodiment, four secondary storage cells (SMCs) are arranged along the x-axis between one contact plug 53A and one contact plug 53B. This enables a high-density configuration of the secondary storage cells (SMCs). According to the sixth embodiment, the contact plugs 53 and the secondary storage cells (SMCs) can be configured at a higher density than in the fifth embodiment, where two secondary storage cells (SMCs) are arranged between the contact plugs 53A and 53B arranged along the x-axis.

[0297] 6.3. Variation Example

[0298] More than four sub-memory cells (SMCs) can also be arranged between one contact plug 53A and one contact plug 53B. This enables a higher density configuration of the contact plugs 53 and the sub-memory cells (SMCs).

[0299] 7. Variation Examples

[0300] In each sub-memory cell (SMC), the selector (SE) can be located on the upper surface of the variable resistor element (VR).

[0301] When the variable resistor element VR is an MTJ element, the ferromagnetic layer 41 can be located above the ferromagnetic layer 43 through the insulating layer 42.

[0302] A variable resistor element (VR) can be any element other than an MTJ element. Such elements include phase-change elements and ferroelectric elements. Phase-change elements, used in PCRAM (Phase Change RAM), contain sulfides and other materials that become crystalline or amorphous due to the heat generated by the write current, thus exhibiting different resistance values. Alternatively, a variable resistor element (VR) can also contain an element containing metal oxides or perovskite oxides, used in ReRAM (Resistive RAM). In this case, the resistance value of the variable resistor element (VR) varies depending on the width (duration of the pulse), amplitude (current or voltage value), or polarity (direction) of the write pulse.

[0303] While several embodiments of the invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in many other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are also included within the scope of the invention as set forth in the claims and their equivalents.

[0304] [Explanation of Symbols]

[0305] 1. Resistance variation type memory device

[0306] 2. Memory controller

[0307] 11-cell array

[0308] 12 Input / Output Circuits

[0309] 13 Control Circuit

[0310] 14-line selection circuit

[0311] 15-column selection circuit

[0312] 16. Write circuit

[0313] 17 Readout Circuit

[0314] 18 Comparator Circuit

[0315] MC storage unit

[0316] WL lettering

[0317] BL bitline

[0318] ˉBL bit line

[0319] BLP bit line pair

[0320] CN1 control signal

[0321] CN2 control signal

[0322] Dw writes data

[0323] Dr reads data

[0324] Vw write potential

[0325] Vr readout potential

[0326] SMC secondary storage unit

[0327] SMCa First Sub-memory Unit

[0328] SMCb Second Sub-Memory Unit

[0329] VR variable resistor element

[0330] VR MTJ components

[0331] SE Selector

[0332] 21 Conductors

[0333] 22 Conductors

[0334] 23 Conductors

[0335] 41 Ferromagnetic layer

[0336] 42 Insulation layer

[0337] 43 Ferromagnetic layer.

Claims

1. A resistance-varying storage device, have: A storage unit includes a first secondary storage unit and a second secondary storage unit, wherein the first secondary storage unit includes a first variable resistor element and a first bidirectional switching element, and the second secondary storage unit includes a second variable resistor element and a second bidirectional switching element; First conductor; The second conductor; and Third conductor; The first secondary storage unit is located above the first conductor. The second conductor is located above the first sub-memory cell. The second secondary storage unit is located above the second conductor. The third conductor is located above the second sub-memory cell. The resistance-varying storage device is configured to receive first data, and when second data read from the storage unit is inconsistent with the first data, write the first data into the storage unit; wherein... The first variable resistor element exhibits the ability to switch between a first resistor and a second resistor. The second resistor is higher than the first resistor. The second variable resistor element exhibits the ability to switch between a third or fourth resistor. The fourth resistor is higher than the third resistor. The storage unit stores 1 bit of data based on the first variable resistor element exhibiting the first resistance and the second variable resistor element exhibiting the fourth resistance, or the first variable resistor element exhibiting the second resistance and the second variable resistor element exhibiting the third resistance.

2. The resistance-varying memory device according to claim 1, wherein... The process of writing the first data into the storage unit includes: Simultaneously, processes are performed to make the first variable resistor element exhibit the state of the first resistor, and to make the second variable resistor element exhibit the state of the fourth resistor; or Simultaneously, processes are performed to make the first variable resistor element exhibit the state of the second resistor, and to make the second variable resistor element exhibit the state of the third resistor.

3. The resistance-varying memory device according to claim 1, wherein the device is configured as follows: When the first data is received Write the first data into the storage unit. After writing the first data, the second data is read from the storage unit. After reading the second data, if the first data and the second data are inconsistent, the first data is written to the storage unit.

4. The resistance-varying memory device according to claim 1, wherein... It includes a first node connected to the first conductor and a second node connected to the third conductor, and It also includes an amplifier circuit, which comprises: The first inverter is connected to the first node at its first input and to the second node at its first output; and The second inverter is connected to the second node at the second input and to the first node at the second output.

5. A resistance-varying storage device, have: First conductor; The first secondary storage unit above the first conductor includes a first variable resistor element and a first bidirectional switching element; The second conductor above the first secondary storage unit; The third conductor is connected to the second conductor below it; A fourth conductor is connected to the third conductor below it; and The second secondary storage unit above the fourth conductor includes a second variable resistor element and a second bidirectional switching element; wherein The first variable resistor element exhibits the ability to switch between a first resistor and a second resistor. The second resistor is higher than the first resistor. The second variable resistor element exhibits the ability to switch between a third or fourth resistor. The fourth resistor is higher than the third resistor. The first and second sub-storage units are grouped together to store 1 bit of data based on the first variable resistor element exhibiting the first resistance and the second variable resistor element exhibiting the fourth resistance, or the first variable resistor element exhibiting the second resistance and the second variable resistor element exhibiting the third resistance.

6. The resistance-varying memory device according to claim 5, wherein the first conductor and the fourth conductor are located in the first layer, and the first sub-memory cell, the third conductor and the second sub-memory cell are located in the second layer.

7. The resistance-varying memory device according to claim 6, wherein... The first variable resistor element and the second variable resistor element are located in the third layer. The first bidirectional switching element and the second bidirectional switching element are located in the fourth layer.

8. The resistance-varying memory device according to claim 5, wherein... It also includes a fifth conductor above the second sub-memory cell. The second conductor and the fifth conductor are located in the fifth layer.

9. The resistance-varying memory device according to claim 5, wherein The first conductor extends along the first axis. The second conductor and the fourth conductor extend along the second axis, which intersects the first axis.

10. The resistance-varying memory device according to claim 9, wherein... It also includes a fifth conductor above the second sub-memory cell. The fifth conductor extends along the first axis.

11. The resistance-varying memory device according to claim 9, wherein The first sub-memory cell, the third conductor, and the second sub-memory cell are arranged along the second axis.

12. The resistance-varying memory device according to claim 5, wherein... The first conductor extends along the first axis. The second conductor extends along a second axis that intersects with the first axis. The fourth conductor extends along a third axis that intersects the first axis and the second axis.

13. The resistance-varying memory device according to claim 12, wherein... It also includes a fifth conductor above the second sub-memory cell. The fifth conductor extends along the first axis.

14. The resistance-varying memory device according to claim 12, wherein... The first and second sub-memory cells are not separated by the third conductor, but are arranged along the fourth axis that intersects the first axis.

15. The resistance-varying memory device according to claim 11, wherein... It also has: Fifth conductor; The third secondary storage unit above the fifth conductor includes a third variable resistor element and a third bidirectional switching element; and The fourth sub-memory cell above the fourth conductor includes a fourth variable resistor element and a fourth bidirectional switching element.

16. The resistance-varying memory device according to claim 15, wherein The first conductor, the fourth conductor, and the fifth conductor are located in the sixth layer. The first sub-memory cell, the third conductor, the second sub-memory cell, the third sub-memory cell, and the fourth sub-memory cell are located in the 7th layer.

17. The resistance-varying memory device according to claim 16, wherein... The first, second, third, and fourth variable resistor elements are located in the eighth layer. The first bidirectional switching element, the second bidirectional switching element, the third bidirectional switching element, and the fourth bidirectional switching element are located in the 9th layer.

18. The resistance-varying memory device according to claim 15, wherein... Also includes: The sixth conductor above the second sub-memory unit, and The seventh conductor above the fourth sub-memory cell. The second conductor, the sixth conductor, and the seventh conductor are located in the tenth layer.

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