Processing device based on a magnetic tunnel junction element and electronic system comprising the processing device

Abstract

A processing device and an electronic system including the same are provided, which has improved reliability and power efficiency of analog computation and high cost efficiency due to a reduction in bit cell size. The processing device includes at least one bit cell line on which a plurality of bit cells are connected in series to each other, wherein each of the bit cells includes a first magnetic tunnel junction (MTJ) element, a second MTJ element connected in parallel to the first MTJ element, a first switching element connected in series to the first MTJ element, and a second switching element connected in series to the second MTJ element, and wherein on the bit cell line, two adjacent bit cells are connected in series to each other in a mirror structure.

Description

Technical Field

[0001] The present invention relates to a processing device, and more specifically, to a processing device for performing analog calculations, and an electronic system including the processing device. Background Technology

[0002] To overcome the structural limitations of chips based on the von Neumann architecture, neural network hardware and / or neuromorphic computing hardware have been developed. These neural networks consist of neurons as basic units (e.g., modeled based on neurons included in the human brain) and synapses that provide interconnections between neurons. Neural networks can surpass the limitations of existing machine learning algorithms and exhibit image, video, and pattern learning and recognition capabilities at near-human levels, with applications across various fields. Furthermore, the development of application-specific integrated circuits (ASICs) for performing computational operations faster with low power consumption is underway. Summary of the Invention

[0003] The present invention provides a processing device and an electronic system including the processing device, which has improved reliability and power efficiency of analog computing and high cost efficiency due to the reduction in bit-cell size.

[0004] According to one aspect of the present invention, a processing device based on a magnetic tunnel junction (MTJ) element is provided, comprising: at least one bit cell line, wherein a plurality of bit cells are connected in series on the at least one bit cell line, wherein each of the bit cells comprises: a first MTJ element configured to switch between different resistance states and programmed with a resistance value; a second MTJ element configured to switch between different resistance states and programmed with a resistance value; a first switching element connected in series to the first MTJ element and configured to switch on at least one of a current or a voltage applied to the first MTJ element; and a second switching element connected in series to the second MTJ element and configured to switch on at least one of a current or a voltage applied to the second MTJ element, wherein the second switching element is configured to perform a switching complementary to the first switching element, and wherein on the bit cell line, two adjacent bit cells are connected in series with each other in a mirror structure.

[0005] Furthermore, according to another aspect of the present invention, a processing device based on a magnetic tunnel junction (MTJ) element is provided, comprising: a substrate; an active layer on the substrate, the active layer including a plurality of switching elements; at least two metal distribution layers on the active layer, the at least two metal distribution layers including a first upper metal layer and a second upper metal layer; an MTJ element layer disposed between the first upper metal layer and the second upper metal layer; and at least one bit cell line, wherein a plurality of bit cells on the at least one bit cell line are connected in series with each other, wherein each bit cell includes: a first MTJ element on the MTJ element layer; a second MTJ element on the MTJ element layer and connected in parallel with the first MTJ element; and a first switching element in the active layer and connected in series with the first MTJ element. The first MTJ element; and a second switching element, which is connected in series with the second MTJ element in the active layer, the first MTJ element and the second MTJ element are programmed with complementary resistance values, the first switching element and the second switching element are configured to switch complementaryly and apply at least one of current or voltage to the first MTJ element and the second MTJ element respectively, and on at least one bit cell line, two adjacent bit cells are connected in series with each other in a mirroring structure, and the mirroring structure includes a first mirror of the first switching element and the second switching element and a second mirror of the first MTJ element and the second MTJ element, and the first mirror and the second mirror alternately repeat between two adjacent bit cells in one direction of the at least one bit cell line.

[0006] Furthermore, according to aspects of the present invention, an electronic system is provided, comprising: a processing device based on a magnetic tunnel junction (MTJ) element; a processing unit configured to control the operation of the processing device; and a memory unit configured to store at least one of a program, data, and commands to be used in the operation of the processing device; wherein the processing device includes at least one bit cell line, wherein a plurality of bit cells on the at least one bit cell line are connected in series with each other, wherein each of the bit cells includes: a first MTJ element configured to switch between different resistance states and programmed with a resistance value; a second MTJ element configured to switch between different resistance states and programmed with a resistance value; a first switching element connected in series with the first MTJ element and configured to switch the application of at least one of a current or a voltage to the first MTJ element; and a second switching element connected in series with the second MTJ element and configured to switch the application of at least one of a current or a voltage to the second MTJ element, wherein the second switching element is configured to perform a switching complementary to the first switching element, and wherein on the bit cell line, two adjacent bit cells are connected in series with each other in a mirror structure.

[0007] According to another aspect of the present invention, an electronic system is provided, comprising: a processing device based on a magnetic tunnel junction (MTJ) element; a processing unit configured to control the operation of the processing device; a memory unit configured to store at least one of a program, data, and commands to be used in the operation of the processing device; a sensor module configured to collect information; and a communication module configured to communicate with an external device, wherein the processing device comprises: a substrate; an active layer on the substrate, the active layer comprising a plurality of switching elements; at least two metal distribution layers on the active layer, the at least two metal distribution layers comprising a first upper metal layer and a second upper metal layer; an MTJ element layer between the first upper metal layer and the second upper metal layer; and at least one bit cell line, a plurality of bit cells on the at least one bit cell line being connected in series with each other, wherein each of the bit cells comprises: a first MTJ element on the MTJ element layer. A second MTJ element is connected in parallel with the first MTJ element on the MTJ element layer; a first switching element is connected in series with the first MTJ element in the active layer; and a second switching element is connected in series with the second MTJ element in the active layer. The first MTJ element and the second MTJ element are programmed with complementary resistance values. The first switching element and the second switching element are configured to switch complementaryly and apply at least one of current or voltage to the first MTJ element and the second MTJ element, respectively. On at least one bit cell line, two adjacent bit cells are connected in series with each other in a mirror structure. The mirror structure includes a first mirror image of the first switching element and the second switching element and a second mirror image of the first MTJ element and the second MTJ element. On one direction of the at least one bit cell line, the first mirror image and the second mirror image are alternately repeated between two adjacent bit cells. Attached Figure Description

[0008] From the following detailed description taken in conjunction with the accompanying drawings, exemplary embodiments of the inventive concept will become clearer, wherein:

[0009] Figure 1 This is a conceptual diagram of biological neurons and their operations;

[0010] Figure 2 This is a concept diagram of an example of a neural network;

[0011] Figure 3 This is a circuit diagram of a bit cell included in a processing device based on a magnetic tunnel junction (MTJ) element, according to some example embodiments;

[0012] Figure 4A and Figure 4B yes Figure 3 A conceptual diagram illustrating the structure and operation of the MTJ element, which utilizes bit units;

[0013] Figure 5 It is a circuit diagram of bit cell pairs included in a processing device according to some example embodiments;

[0014] Figures 6A to 6C It is used to describe Figure 5 Circuit diagrams and conceptual diagrams for programming operations on bit pairs in the code;

[0015] Figure 7 It is used to describe Figure 5 Circuit diagram of the read operation of bit pairs in the data;

[0016] Figure 8 This is a conceptual diagram of a detailed example of a neural network;

[0017] Figure 9A and 9B It is used to describe the use of Figure 5 Processing equipment Figure 8 The circuit diagram of the computational operations required by the neural network;

[0018] Figure 10 It is used to describe Figure 9A The connection relationship between MTJ components and switching components in the circuit diagram. Figure 5 A cross-sectional view of a portion of the processing equipment;

[0019] Figure 11 It is shown in detail Figure 10 A horizontal cross-sectional view of the MTJ component layer in a part of the processing equipment;

[0020] Figure 12A and 12B It is a circuit diagram of bit cell pairs included in a processing device according to some example embodiments;

[0021] Figure 13A and 13B This is a circuit diagram illustrating the individual and shared structures of bit cell lines included in a processing device according to some example embodiments;

[0022] Figure 14 It is used to describe Figure 13B Circuit diagram of read operation in the shared structure of bit cell lines;

[0023] Figure 15 This is a structural block diagram of a processing device according to some example embodiments; and

[0024] Figure 16 This is a structural block diagram of an electronic system including a processing device according to some example embodiments. Detailed Implementation

[0025] In the following, some exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used for the same constituent elements, and repeated descriptions thereof are omitted.

[0026] When the terms “approximately” and / or “substantially” are used in conjunction with numerical values ​​in this specification, it is intended that the relevant numerical values ​​include manufacturing tolerances (e.g., ±10%) around the values. Furthermore, when the words “generally” and / or “substantially” are used in conjunction with structures and / or constructions, it is intended that precision of the structures and / or constructions is not required, but the degrees of freedom of the structures and / or constructions are within the scope of this disclosure. Moreover, it should be understood that these values, structures, and / or constructions should be interpreted to include manufacturing or operational tolerances (e.g., ±10%) around the numerical values, structures, or constructions.

[0027] Figure 1 It is a conceptual diagram of biological neurons and their operations, and Figure 2 This is a conceptual diagram of an example of a neural network.

[0028] refer to Figure 1 Biological neurons 10 can represent cells in the human nervous system and can be one of the basic biological computing objects. The human brain can include approximately 100 billion biological neurons 10 and approximately 100 trillion interconnections located between them.

[0029] The biological neuron 10 may include a single cell and may include a neuronal cell body (including various organelles), multiple dendrites radiating from the cell body, axons extending from the cell body to another neuron, etc. Various organelles may include, for example, the cell nucleus, mitochondria, endoplasmic reticulum, etc.

[0030] Generally, axons can transmit signals from one neuron to another, and dendrites can receive signals from another neuron. For example, when different neurons are interconnected, signals transmitted via the axons of one neuron can be received by the dendrites of another neuron. These signals can be transmitted via special interconnections called synapses, and several neurons can connect to each other to form a neural network. Referring to a synapse, neurons that secrete neurotransmitters (e.g., neurons that transmit signals) can be called presynaptic neurons, and neurons that receive information transmitted via neurotransmitters (e.g., neurons that receive signals) can be called postsynaptic neurons.

[0031] The brain (such as the human brain) can learn and memorize vast amounts of information by transmitting and processing various signals via neural networks formed by a large number of interconnected neurons. Various attempts have been maintained and developed to develop processing and / or computing devices for efficiently processing large amounts of information by mimicking biological neural networks.

[0032] refer to Figure 2The neural network 20 may include an artificial neural network (ANN) that mimics the aforementioned biological neural network, and may include, for example, a deep neural network (DNN). Figure 2 For ease of description, neural network 20 is shown as including two hidden layers. However, neural network 20 is not limited to this and may include various numbers of hidden layers (e.g., one or more). Furthermore, in Figure 2 In this embodiment, the neural network 20 is shown to include an input layer 21, which is separate from the hidden layer for receiving input data; however, according to some embodiments, the input data can be directly input into the hidden layer.

[0033] Besides the output layer in neural network 20, nodes within a layer can be connected to nodes in the next layer (e.g., a downstream layer) via links for transmitting output signals. Values ​​obtained by multiplying the node values ​​of nodes in the previous layer by the weights assigned to each link can be input to a node via the link. The node values ​​of the previous layer can correspond to axon values, and the weights can correspond to synaptic weights. These weights can be referred to as parameters of neural network 20. Activation functions can include the sigmoid function, hyperbolic tangent (tanh), rectified linear unit (ReLU) function, etc., and the nonlinearity of neural network 20 can be achieved through activation functions.

[0034] The output of any node 22 included in the neural network 20 can be represented by the following formula 1.

[0035]

[0036] Formula 1 can represent the output value y of the i-th node 22 in a layer with m input values. i x j It can represent the output value of the j-th node in the previous layer, and w j,i This can represent the weights applied to the interconnection between the j-th node in the previous layer and the i-th node in the current layer. f can represent the activation function. As shown in Equation 1, the activation function can use the input value x. j Multiplied by weight w j,i The accumulated result. For example, you can perform the operation of adding the input value x. j Multiplied by weight w j,iThis involves adding the results together (e.g., multiply accumulate operation (MAC)). Besides this application, there may be various other applications requiring MAC operations; for this purpose, processing devices capable of handling MAC operations in the analog circuit region can be used.

[0037] Figure 3 This is a circuit diagram of bit cells included in a processing device 100 based on MTJ elements according to some example embodiments.

[0038] refer to Figure 3 The processing device 100 based on MTJ elements (hereinafter referred to as the "processing device") may include a device for implementing a neuromorphic processor, a neural processor, etc., and may include a plurality of bit-cells (BCs) arranged in a two-dimensional array structure. According to some embodiments, the processing device 100 may include an in-memory processing device, which, for example, stores data in a memory, i.e., the first and second MTJ elements MTJ and In, and use the data stored therein when needed for operation.

[0039] exist Figure 3 In the diagram, the circuit portion corresponding to the unit bit cell BC is represented by a dashed line. The unit bit cell BC may include a pair of MTJ elements MTJ and and respectively connected to the first MTJ element MTJ and the second MTJ element A pair of unit switching elements Sb and In some embodiments, the alignment unit switching element Sb and It can be connected to data lines DLa or DLb via the first or second access switch element Sa1 or Sa2. However, Figure 3 The circuitry for bit cell BC shown is merely an example, and bit cell BC can be implemented in different ways. Figure 3 This can be achieved through circuitry, for example, by using other circuit elements. In this case, and The dash (―) can indicate complementary operations on MTJ and Sb, respectively.

[0040] By using complementary operations, this pair of MTJ elements MTJ and They can be programmed to have different resistance values ​​from each other. Furthermore, a pair of MTJ elements, MTJ and... The resistance value can be determined by applying weights to the bit cell BC. For example, the first and second MTJ elements MTJ and Each of them can have two resistance values ​​(i.e., R). AP Or R PThe resistance value of any one of the resistance values ​​in ). For example, R AP The resistance value can be, for example, approximately 20Ω, and R P The resistance value can be, for example, approximately 5Ω. However, R AP and / or R P The resistance value is not limited to this. Please refer to... Figure 4A and 4B Given R AP and R P A further detailed description of the resistance value.

[0041] In some embodiments, when the weights applicable to bit cell BC are assumed to be "-1" and / or "1", and a weight of "1" is applied to bit cell BC, the first MTJ element MTJ can be programmed as R. AP (e.g., approximately 20Ω), and the second MTJ element It can be programmed as R P (For example, approximately 5Ω). Alternatively, when the bit cell BC is weighted with "-1", the first MTJ element MTJ can be programmed to R. AP (e.g., approximately 5Ω), and the second MTJ element It can be programmed as R P (For example, approximately 20Ω). In this example, the first and second MTJ elements MTJ and The resistance values ​​can be complementaryly programmed so that the first and second MTJ elements MTJ and They have different resistance values.

[0042] For reference, an MTJ element may include a component that switches between different resistance states depending on the voltage or current applied to its terminals, and may have multiple resistance states. Furthermore, an operation in which the MTJ element changes from a high resistance state to a low resistance state may be referred to as a set operation, and an operation in which the MTJ element changes from a low resistance state to a high resistance state may be referred to as a reset operation. Therefore, an MTJ element can be programmed to a high resistance state or a low resistance state by using set and reset operations. (Refer to...) Figure 4A and Figure 4B Provide a detailed description of the structure and operation of the MTJ component.

[0043] First and second MTJ elements MTJ and Each of them can be programmed using the following method. First, the first and second MTJ components to be programmed are MTJ and... The two ends can be connected to the first data line DLa and the second data line DLb, respectively. Taking the first MTJ element MTJ as an example, one end of the first MTJ element MTJ can be connected to the first data line DLa via the first access switch element Sa1 and the first unit switch element Sb, and the other end of the first MTJ element MTJ can be connected to the second data line DLb via the second access switch element Sa2.

[0044] like Figure 3 As shown, because the bit cell switching element and MTJ element of another unit are arranged between the first MTJ element MTJ and the second access switching element Sa2, it is not possible to program only the first MTJ element MTJ. Therefore, in the processing device 100 according to some example embodiments, the MTJ element of each bit cell BC may not be programmed individually, but the MTJ elements of two adjacent bit cells BC may be programmed simultaneously. However, to describe the case where only the first MTJ element MTJ is programmed, it is assumed that there are currently no bit cell switching elements and MTJ elements of other bit cells.

[0045] When the first MTJ element MTJ is connected to the first and second data lines DLa and DLb via the first unit switch element Sb, the first access switch element Sa1, and the second access switch element Sa2, respectively, by controlling the voltage across the first MTJ element MTJ or by controlling the current flowing through the first MTJ element MTJ, a programming operation, i.e., a write operation, can be performed on the first MTJ element MTJ. In this case, the programming operation can correspond to a setting or reset operation based on the previous state of the first MTJ element MTJ. This differs from the case when the second MTJ element... Each via the second unit switching element When the first access switch element Sa1 and the second access switch element Sa2 are connected to the first and second data lines DLa and DLb, the second MTJ element can be activated. Programming operations.

[0046] On the other hand, the application of programming for the first and second MTJ elements MTJ and The voltage and / or current can be relatively greater than the voltage applied to read the first and second MTJ elements. The voltage and / or current of the resistance value. For example, the first and second MTJ elements MTJ and It is possible to read the first and second MTJ elements without being applied. The voltage and / or current of the resistance value are programmed.

[0047] MTJ and connected in series to the first and second MTJ elements A pair of unit switching elements Sb and On / off operations can be performed based on the input applied to the positioning unit BC. Furthermore, the positioning unit switching element Sb and... They can operate complementaryly, such that when one is off, the other is on. For example, a unit bit cell BC can be designed such that when the input applicable to bit cell BC is assumed to be "-1" or "1", and when input "1" is applied, the first unit switching element Sb can be off, and the second unit switching element... It can be connected, and when the input "-1" is applied, the first unit switch element Sb can be connected, and the second unit switch element... It can be disconnected.

[0048] Based on the above operating methods of the MTJ element and the bit unit switching element, the resistance value of the bit unit BC can be determined according to the application... Figure 3 The weight of bit cell BC varies with the input. The relationship between the weight of bit cell BC, the input, and the resistance value can be summarized in Table 1 below.

[0049] [Table 1]

[0050] 1 1 1 <![CDATA[20(R AP )]]> 1 -1 -1 <![CDATA[5(R P )]]> -1 1 -1 <![CDATA[5(R P )]]> -1 -1 1 <![CDATA[20(R AP )]]>

[0051] Referring to Table 1, when the input multiplied by the weight is 1, the resistance of the bit cell BC can be approximately 20Ω, and when the input multiplied by the weight is -1, the resistance of the bit cell BC can be approximately 5Ω.

[0052] For example, by measuring the resistance of bit cell BC and / or measuring a constant voltage drop at bit cell BC (e.g., due to current), the product of the input and the weights applied to bit cell BC can be known. By utilizing this characteristic of bit cell BC, processing devices (e.g., neuromorphic processing, etc.) can be implemented to obtain the multiplication of the input and weights, as well as the sum of the multiplications. For reference, input * weights can correspond to the XOR operation value.

[0053] Figure 4A and 4B It is applied to Figure 3 A conceptual diagram illustrating the structure and operation of the MTJ element in bit cell BC. (See diagram for example.) Figure 3 The MTJ element used in the bit cell BC can have a resistance value that varies according to the magnitude and / or direction of the current (and / or voltage) and can have non-volatile characteristics such that its resistance value remains unchanged even when the input current (and / or voltage) is cut off.

[0054] refer to Figure 4A and Figure 4BAn MTJ element may include a pinned layer L3, a free layer L1, and a tunnel layer L2. The magnetization direction of the pinned layer L3 may be fixed, while the magnetization direction of the free layer L1 may be the same as or different from that of the pinned layer L3. For example, the magnetization direction of the free layer L1 may be adjustable (e.g., programmable).

[0055] exist Figure 4A In the diagram, the MTJ element is shown with the magnetization directions of the free layer L1 and the fixed layer L3 parallel to each other. When the magnetization directions are parallel to each other in this manner, the resistance value R of the MTJ element is... P It can be reduced to, for example, approximately 5Ω. Furthermore, in Figure 4B In the diagram, the MTJ element can be shown to have its free layer L1 and fixed layer L3 magnetization directions anti-parallel. When the magnetization directions are anti-parallel in this manner, the resistance value R of the MTJ element is... AP It can be increased to, for example, approximately 20Ω. Therefore, changing the magnetization direction of the free layer L1 can change the resistance value of the MTJ element, thereby allowing the MTJ element to be programmed.

[0056] The magnetization direction of the free layer L1 can be changed by electro / magnetic causes provided from the outside and / or inside of the resistive memory cell. The free layer L1 can include materials with variable magnetization directions, such as ferromagnetic materials. The free layer L1 can include, for example, CoFeB, FeB, Fe, Co, Ni, Gd, Dy, CoFe, NiFe, MnAs, MnBi, MnSb, CrO2, MnOFe2O3, FeOFe2O3, NiOFe2O3, CuOFe2O3, MgOFe2O3, EuO, Y3Fe5O 12 And / or at least one of their combinations.

[0057] The tunnel layer L2 may have a thickness less than the spin diffusion distance, and / or may include at least one of the following non-magnetic materials: magnesium (Mg), titanium (Ti), aluminum (Al), magnesium zinc (MgZn), magnesium boron oxide (MgB oxide), and vanadium (V), and / or combinations thereof.

[0058] Due to the antiferromagnetic layer, the fixed layer L3 can have a fixed magnetization direction. The fixed layer L3 can include ferromagnetic materials such as CoFeB, FeB, Fe, Co, Ni, Gd, Dy, CoFe, NiFe, MnAs, MnBi, MnSb, CrO2, MnOFe2O3, FeOFe2O3, NiOFe2O3, CuOFe2O3, MgOFe2O3, EuO, and Y3Fe5O. 12and / or combinations thereof, and may further include an antiferromagnetic layer and / or a synthetic antiferromagnetic layer for fixing the magnetization direction. The antiferromagnetic layer may include PtMn, IrMn, MnO, MnS, MnTe, MnF2, FeC l2 ,FeO,CoC l2 CoO, NiC l2 NiO, Cr, and / or combinations thereof. In some embodiments, the synthesized antiferromagnetic layer may include Cu, Ru, Ir, and / or combinations thereof.

[0059] Figure 5 This is a circuit diagram of bit pairs included in a processing device 100 according to some example embodiments.

[0060] refer to Figure 5 In the processing device 100, bit cells BC can be connected in series with each other in one direction and form a bit cell line BCL. Figure 5 In the diagram, the bit cell line BCL is shown as comprising four bit cells connected in series with each other. However, in the processing device 100, the number of bit cells BC included in the bit cell line BCL is not limited to four, and may include fewer and / or more bit cells BC.

[0061] In the processing device 100, two adjacent bit units BC connected in series on the bit unit line BCL can form a bit unit pair BCP. For example, the i-th bit unit pair BCP[i] (where i is a natural number) may include the (2i-1)-th bit unit BC[2i-1] and the (2i)-th bit unit BC[2i] connected in series with the (2i-1)-th bit unit BC[2i-1].

[0062] In a bit cell pair BCP, two adjacent bit cells BC can be connected in series with each other using a second mirror structure Mir2. For example, as Figure 5 As shown, the MTJ element MTJ[u] of the (2i-1)th unit BC[2i-1] and (For example, the MTJ element MTJ[u] shown above and) It can be connected in series with the MTJ element MTJ[d] of the (2i)th bit unit BC[2i] symmetrical to the second mirror structure Mir2 and (For example, the MTJ element MTJ[d] shown below and) Furthermore, in two adjacent bit pairs (BCP), two adjacent bit units (BC) can be connected in series with each other using a first mirror structure (Mir1). For example... Figure 5 As shown, the bit unit switching element Sb[u] of the (2i-1)th bit unit BC[2i-1] and The bit unit switching element Sb[d] that can be connected in series to the [2i-2]th bit unit BC[2i-2] and The first mirror structure Mir1 is symmetrical. In this case, the (2i-2)th bit cell BC[2i-2] can correspond to the (i-1)th bit cell pair BCP. However, the example embodiment is not limited to this, and the first mirror structure Mir1 and the second mirror structure Mir2 can be arranged alternately along the bit cell line BCL.

[0063] In some example embodiments, regarding the second mirror structure Mir2 of the bit cell pair BCP, the upper MTJ element MTJ[u] and And the lower MTJ element MTJ[d] and They can be programmed complementaryly. (Refer to...) Figures 6A to 6C The complementary programming of the bit cell to the BCP is described in more detail.

[0064] In the processing device 100, each bit cell pair BCP can be arranged with one of the access switching elements Sa. However, since when a bit cell pair BCP is programmed, it may require two access switching elements Sa, the number of access switching elements Sa can be greater than the number of bit cell pairs BCP (e.g., one more). For example, when the bit cell line BCL includes 2n (where n is a natural number), corresponding to an even number of bit cells BC, the number of bit cell pairs BCP can be n, and the number of access switching elements Sa can be (n+1). On the other hand, when the bit cell line BCL includes (2n-1) (where n is a natural number), corresponding to an odd number of bit cells BC, the number of bit cell pairs BCP can be (n-1), and the number of access switching elements Sa can be n+1. In some embodiments, when the bit cell line BCL includes an odd number of bit cells BC, the first and / or last bit cells BC may not constitute a bit cell pair BCP, and the first or last bit cells BC may be arranged between two adjacent access switching elements Sa.

[0065] The processing device 100 can reduce the size of the bit cell BC and / or the size of the bit cell array including the bit cell BC by using a second mirror structure Mir2 that includes MTJ elements in the bit cell pair BCP and a first mirror structure Mir1 that includes bit cell switching elements between adjacent bit cell pairs BCP. For example, since the access switching element Sa is only used when programming begins for the MTJ elements MTJ used to store neural network weights, and only read operations on the input vector are performed when performing simulated MAC calculations, the size of the bit cell BC and the size of the bit cell array can be reduced by optimizing the bias line and the size of the access switching element Sa.

[0066] Furthermore, in processing device 100, because no via contacts are formed in the bit cell BC, the size of the bit cell and the size of the bit cell array can be further reduced. Additionally, in processing device 100, because the series-connected MTJ elements MTJ are used as memory and there are no via contacts, the reliability and power efficiency of analog operation can be improved. (See reference...) Figure 10 and 11 A more detailed description related to via contacts is provided.

[0067] Figures 6A to 6C It is used to describe Figure 5 The circuit diagram and conceptual diagram of the programming operation of the bit unit in BCP.

[0068] refer to Figure 6A By activating the first and second access switching elements Sa[1] and Sa[2], the upper unit switching element is activated. and lower unit switching elements Disconnect the upper unit switching element Sb[u] and the lower unit switching element Sb[d], and allow current to flow through the upper MTJ element. and lower MTJ components It can simultaneously process the upper MTJ components. and lower MTJ components To perform programming, such as Figure 6A As shown by the large arrow in the image. Upper MTJ component. and lower MTJ components They can be programmed in opposite directions (e.g., according to the direction of the spin polarization current). For example, the upper MTJ element. and lower MTJ components It can be programmed using different resistance values.

[0069] Subsequently, the upper unit switching element is disconnected. and lower unit switching elements By switching on the upper unit switching element Sb[u] and the lower unit switching element Sb[d], and allowing current to flow through the upper MTJ element MTJ[u] and the lower MTJ element MTJ[d], both the upper and lower MTJ elements MTJ[u] and MTJ[d] can be programmed simultaneously. The upper and lower MTJ elements MTJ[u] and MTJ[d] can also be programmed in opposite directions (e.g., according to the direction of the spin-polarized current).

[0070] refer to Figure 6B By activating the first and second access switching elements Sa[1] and Sa[2], the upper unit switching element is activated. And the lower unit switching element Sb[d], disconnect the upper unit switching element Sb[u] and the lower unit switching element. And allow current to flow through the upper MTJ component. and the lower MTJ element MTJ[d] (e.g.) Figure 6B (As shown by the large arrow), it can simultaneously target the upper MTJ component. The lower MTJ element MTJ[d] is programmed. In this case, the upper MTJ element is programmed according to the direction of the spin polarization current. and lower MTJ components It can be programmed in the opposite direction.

[0071] Subsequently, the upper unit switching element is disconnected. And the lower unit switching element Sb[d], connects the upper unit switching element Sb[u] and the lower unit switching element. And allows current to flow through the upper MTJ element MTJ[u] and the lower MTJ element. It can simultaneously target both the upper MTJ element MTJ[u] and the lower MTJ element. Programming. Upper MTJ element MTJ[u] and lower MTJ element. They can also be programmed in opposite directions based on the direction of their respective spin polarization currents.

[0072] like Figure 6A The programming method shown, which allows current to flow through two MTJ elements that are directly adjacent to each other in the downward direction, can be called vertical writing, and as... Figure 6B The programming method shown, which allows current to flow through two MTJ elements that are diagonally adjacent to each other, can be called diagonal writing.

[0073] refer to Figure 6C By using Figure 6A Vertical writing and / or Figure 6B In diagonal writing, the number of modes for a bit cell to BCP can be four. In this case, no other mode can be programmed and may not be necessary for XNOR operation. For example, when the upper first MTJ element MTJ[u] and the upper second MTJ element of the first bit cell BC[1] are... When the resistance values ​​are referred to as R11 and R12 respectively, the lower first MTJ element MTJ[d] and the lower second MTJ element of the second unit BC[2] The resistance values ​​are referred to as R21 and R22, respectively, and each of R11, R12, R21, and R22 has a resistance value corresponding to either 1 or 0, such as... Figure 6CAs shown, a matrix R containing R11, R12, R21, and R22 as elements can have Any of the modes. Furthermore, as can be understood from the arrows below, the two modes on the left can be programmed using vertical writing, and the two modes on the right can be programmed using diagonal writing. For reference, in this case and description, "1" can correspond to R. AP For example, approximately 25Ω, and "0" can correspond to R. P For example, approximately 5Ω. However, conversely, "1" can correspond to R. P And "0" can correspond to R AP .

[0074] In the processing device 100, based on the mirror structure and the method of simultaneously writing two MTJ elements, the access switch element arranged one per bit cell (where the number of access switch elements is one more than the number of bit cells) can be replaced by an access switch element arranged one per bit cell pair (where the number of access switch elements is one more than the number of bit cell pairs). For example, the number of access switch elements can be reduced to one for every two bit cells. Therefore, the size of the bit cells can be reduced. Furthermore, since the mirror structure eliminates the need for via contacts, the size of the bit cells can be further reduced, and thus, the size of the bit cell array can be further reduced. Regarding the reduction of access switch elements, refer to... Figure 12A and 12B Provide a detailed description.

[0075] Figure 7 It is used to describe Figure 5 The circuit diagram for reading operations from bit pairs in the data.

[0076] refer to Figure 7 Generally, when two access switching elements are arranged in (e.g., one) bit cell BC, a single MTJ element can be directly accessed via the two access switching elements and the bit cell switching element, and correspondingly, the resistance value of the corresponding MTJ element can be directly read. Furthermore, in the processing device 100, the two bit cells BC can be connected in series with each other in a bit cell pair BCP, and write and read operations can be performed simultaneously via the two access switching elements of a bit cell pair BCP. For example, in the case of a write operation, refer to... Figure 6A and Figure 6B The given description of it is applicable.

[0077] In the case of a read operation, in addition to the bit cell BC of the MTJ element to be read, the MTJ element of another cell BC on the current path can be read. For example, in Figure 7 In the middle, we can consider the following situation, where the bold MTJ element... When the target MTJ element to be read is specified, all MTJ elements in the (2i-1)th bit cell BC[2i-1] of the path are connected to the MTJ element. For example, the upper unit switching element Sb[u] and All connections are active. On the other hand, as mentioned above... Figure 6A and Figure 6B As part of the write operation, the two MTJ elements MTJ[u] and MTJ[u] of the (2i-1)th bit cell BC[2i-1] They can have different resistance values. Therefore, the two MTJ elements MTJ[u] and MTJ[u] of the (2i-1)th unit BC[2i-1] on the path. They can be connected in parallel, and regardless of the value of each individual resistor, the resistance is always R. P and R AP The parallel form. In this case, R can always be read. P / / R AP The resistance value. For example, the resistance value in parallel form of "0" and "1" can be read. Furthermore, the two MTJ elements MTJ[u] and MTJ[u] in the (2i-1)th bit cell... The MTJ element can be connected in series to the (2i)th unit BC[2i]. Or the target MTJ element, and the MTJ element It can have R P and R AP Any of the resistance values, therefore, according to MTJ components The total resistance along the path of the resistance value can be represented by the following:

[0078] Rtotal = R P +R P / / R AP , or Rtotal = R AP +R P / / R AP .

[0079] In this case, R P and R AP The resistance value may already be known, therefore, R P / / R AP The resistance value may also be known. Therefore, by excluding R from the total resistance value Rtotal... P / / R AP The resistance value can be used to identify MTJ components. (For example, the resistance value of the target MTJ component Target).

[0080] In some example embodiments, as an exclusion of RP / / R AP One method for determining the resistance value is to consider 1) flowing a quiescent current (e.g., 1 μA) and adjusting the comparator's reference voltage (1 μA * R). P / / R AP To eliminate R P / R AP Methods of influence, 2) Arrangement with R P / / R AP A fixed resistor of value and subtract R differentially. P / / R AP The method of value, 3) connect the two dummy MTJ elements in parallel to R respectively. P and R AP And subtract R P / / R AP Methods such as finding the value of Rtotal. Alternatively, as a direct comparison method, one could consider i) comparing the total resistance value Rtotal with a value equal to 2*R. P / / R AP The method of directly comparing the fixed resistance values, and / or ii) arranging the four virtual MTJ elements with R P / / R AP +R P / / R AP The method involves directly comparing the resistance values.

[0081] exist Figure 7 In the middle, although the MTJ element of the (2i)th bit unit BC[2i] The i-th cell is selected as the target MTJ element, but the resistance value of the i-th cell to other MTJ elements in BCP[i] can also be identified in the same way.

[0082] Figure 8 It is a conceptual diagram of a detailed example of a neural network, and Figure 9A and 9B It is used to describe the use of Figure 5 The processing equipment 100 performs Figure 8 The circuit diagram of the computational operations required by the neural network.

[0083] refer to Figure 8 and Figure 9AAs shown in Formula 2 below, at the first node a1 of the second layer L2, a MAC operation can be performed, which involves multiplying the inputs x1, x2, and x3 (provided from the nodes of the first layer L1) by weights w11, w21, and w31 respectively, and then performing an addition operation on the multiplication results. Furthermore, as shown in Formula 3 below, at the second node a2 of the second layer L2, a MAC operation can be performed, which involves multiplying the inputs x1, x2, and x3 (provided from the nodes of the first layer L1) by weights w12, w22, and w32 respectively, and then performing an addition operation on the multiplication results.

[0084] a1=x1·w11+x2·w21+x3·w31.....................Formula 2

[0085] a2=x1·w12+x2·w22+x3·w32.....................Formula 3

[0086] Figure 9A The processing device 100 may be equipped with a bit unit pair BCP and a bit unit BC to perform... Figure 8 The second layer (L2) requires operations. In some embodiments, although the number of inputs and weights is shown as three, the number of bit pairs (BCP) and bit cells (BC) can vary. Furthermore, when the number of inputs and weights is even, only bit pairs (BCP) can be configured, but bit cells (BC) can be excluded. Additionally, when using... Figure 9A In the case of MAC operation of the processing device 100, since access switching elements Sa11, Sa12, Sa13, Sa21, Sa22, and Sa23 remain in the ON state, the concept of bit unit BC may not be necessary. Therefore, for ease of description, MAC operation will be described below using only bit unit BC.

[0087] Figure 9A The processing device 100 may include a first bit line BCL1, which includes three bit units BC11, BC12 and BC13 connected in series with each other, and a second bit line BCL2, which includes three bit units BC21, BC22 and BC23 connected in series with each other. Figure 8 The operation of Formula 2 required for the first node a1 can be performed on the first unit line BCL1, and the operation of Formula 3 required for the second node a2 can be performed on the second unit line BCL2.

[0088] When a constant current I is applied to each of the first and second bit cell lines BCL1 and BCL2, the sum of the products of the weights applied to each of bit cells BC11, BC12, and BC13, and BC21, BC22, and BC23, and the input, can be obtained from the sum of the voltage drops occurring at each of the bit cells BC11, BC12, BC13, BC21, BC22, and BC23. The input and weight cases shown in Table 2 are described below as examples.

[0089] [Table 2]

[0090] x1＝1 w11＝1 w12＝-1 x2＝1 w21＝-1 w22＝-1 x3＝-1 w31＝-1 w32＝1

[0091] By using the weights in Table 2, Figure 9A The processing device 100 includes the MTJ element R11, R12, ..., R23, The settings can be configured as shown in Table 3 below. For example, by using inputs (such as those included in Table 2), they can be connected in series to MTJ components R11, ..., respectively. The bit unit switching element Sb11, Sb12, ..., Sb23, The on / off state can be set as shown in Table 4 below.

[0092] [Table 3]

[0093]

[0094] [Table 4]

[0095]

[0096] For example, when approximately 1A of current is supplied to the first and second bit cell lines BCL1 and BCL2 (e.g., as set in [Tables 3] and [Tables 4]), the current can flow to the closed bit cell switching element of the MTJ element included in each bit cell, and then a voltage drop may occur. In this case, when the voltage is measured at the upper end of the first and second bit cell lines BCL1 and BCL2, the measured voltage can correspond to the value that has been added to the voltage drop that occurs in each bit cell. The voltage drops that occur in the bit cells BC11, BC12, and BC13 included in the first bit cell line BCL1 can be shown as in [Table 5], and the voltage drops that occur in the bit cells BC21, BC22, and BC23 included in the second bit cell line BCL2 can be shown as in [Table 6].

[0097] [Table 5]

[0098]

[0099] [Table 6]

[0100]

[0101] The voltage drop of approximately 45V on the first bit cell line BCL1 and the voltage drop of approximately 15V on the second bit cell line BCL2 can correspond to the weights applied to the bit cells included in each bit cell line and the results of the input MAC operation. For example, the relationship between the voltage drop and the MAC operation results can be expressed as shown in Table 7 below.

[0102] [Table 7]

[0103]

[0104] Referring to Table 7, it is understandable that, given the measured voltage drop of the first unit line BCL1 is approximately 45V, the sum of the products of the inputs and weights applied to the first unit line BCL1 is "1". Furthermore, it is understandable that, given the measured voltage drop of the second unit line BCL2 is approximately 15V, the sum of the products of the inputs and weights applied to the second unit line BCL2 is "-3".

[0105] exist Figure 9A In this example, each of the first and second bit cell lines BCL1 and BCL2 includes three bit cells; however, the example embodiment is not limited to this, and a bit cell line may include a variety of numbers of bit cells, equal to or greater than one. For example, a bit cell line may include 64 to 256 bit cells. Furthermore, in... Figure 9A In this example, processing device 100 includes only two bit cell lines, BCL1 and BCL2, but processing device 100 may include various numbers of bit cell lines, and may include one or more bit cell lines. The number of bit cell lines in processing device 100 may include 64 to 128 bit cell lines. In some embodiments, multiple bit cells in a bit cell line may be arranged to form a bit cell array.

[0106] As above, Figure 9A The processing device 100 may include an in-memory processing device that stores values ​​corresponding to weights in memory (including MTJ elements) and uses the values ​​stored in memory to perform operations. Unlike the von Neumann architecture where memory and operation units are separated, the in-memory processing device can improve data transfer speed and power consumption. Figure 9A In one embodiment, a processing device is described in which a constant current I is applied to bit cells connected in series with each other, and an operational result is obtained corresponding to the sum of products of voltage drops appearing on the bit cell lines. However, including Figure 5The bit unit in the BCP structure can be applied to other types of processing devices.

[0107] refer to Figure 8 and Figure 9B The processing device 100a according to some example embodiments may be different Figure 9A The processing device 100a further includes capacitors BCLc1 and BCLc2 connected in series to the lower ends of each of the first and second bit cell lines BCL1 and BCL2. The processing device 100a according to an example embodiment may include a structure comprising capacitors BCLc1 and BCLc2 connected in series to the lower ends of each of the first and second bit cell lines BCL1 and BCL2, and may operate in a time-to-digital converter (TDC) manner. For example, the TDC method may be a method in which, after a voltage V is applied to each of the first and second bit cell lines BCL1 and BCL2, the time until the voltage of each of the first and second capacitors BCLc1 and BCLc2 rises to a specific value is measured.

[0108] Figure 10 yes Figure 5 A cross-sectional view of a portion of the processing device 100, used to describe Figure 9A The connection relationship between the MTJ component and the switching component in the circuit diagram, and Figure 11 It is shown in detail Figure 10 A horizontal cross-sectional view of the MTJ element layer L200 in a part of the processing equipment.

[0109] refer to Figure 10 In some example embodiments of the processing device 100, bit unit switching elements Sb11, Sb12 and are formed. The active layer L100. The first to sixth metal distribution layers M100 to M600, the MTJ element layer L200, and the seventh metal distribution layer M700 can be sequentially stacked on the substrate. The active layer L100 can be formed first, and the positional relationship between the active layer L100 and the MTJ element layer L200 can be defined by using a process that forms the first to sixth metal distribution layers M100 to M600 and the MTJ element layer L200 above the active layer L100.

[0110] The active layer L100 can be formed therein. Figure 9A The bit unit switching elements Sb11, Sb12, Layers such as Sb11 and Sb12 can be formed on a silicon wafer using transistor fabrication processes such as transistor fabrication. Layers such as the active layer L100. For example, the active layer L100 may be and / or may be included in a region of the silicon wafer.

[0111] In the processing device 100 of the example embodiment, the switching element may include a transistor. For ease of description, the switching element Sb11, Sb12, Sb13 Sa11, Sa12 and Sa13 (e.g., ... Figure 9A The diagram shown includes the bit cell switching elements Sb11, Sb12, and Sb12 along the path of the current I flowing through the first cell line BCL1 due to the inputs and weights in [Table 2]. Other switching elements Sb13, Sa11, Sa12 and Sa13 (e.g., ... Figure 9A (As shown) can be in an open circuit state, and Figure 10 Not shown, because the current I applied to the first unit line BCL1 does not flow. However, Figure 10 Not shown Figure 9A Other switching elements in Sb13, Sa11, Sa12, and Sa13 can also be formed in the active layer L100 and can be arranged horizontally with the switching elements Sb11, Sb12, and... Different locations.

[0112] MTJ element layer L200 may include MTJ elements R11, R12 as shown in FIG9. The seventh metal distribution layer M700 can be disposed on the MTJ element layer L200, and the sixth metal distribution layer M600 can be disposed below the MTJ element layer L200. However, the example embodiment is not limited to this, and for example, the number of metal distributions is not limited to seven, and the position of the MTJ element layer L200 is not limited to the above-described position. In some embodiments, MTJ elements R11, R12, ... The elements can be formed in the vertical direction in the MTJ element layer L200, such that one end of each MTJ element contacts the seventh metal distribution layer M700, and the other end contacts the sixth metal distribution layer M600.

[0113] In the following text, MTJ elements R11, R12, and R13 are formed vertically on one side of the seventh metal distribution layer M700. The end of the MTJ element can be referred to as the upper part, and the end on one side of the sixth metal distribution layer M600 can be referred to as the lower part. For reference, in the processing device 100 (e.g., Figure 7 and Figure 9AIn the ), the upper part of the MTJ element is represented as "Top", and its lower part is represented as "bot".

[0114] like Figure 10 As shown, the current flows through MTJ components R11, R12, The current I can flow in the direction from the top of the MTJ element to its bottom and / or from its bottom to its top. Only a portion of the MTJ element layer L200 is shown. Figure 9A The first unit line BCL1 includes the MTJ element R11. R12, R13 and The input and weighted current I in [Table 2] flows through the MTJ elements R11, R12 and... However, despite Figure 10 Not shown, but other MTJ components R11 and R13 can be formed in the MTJ element layer L200, and can be horizontally arranged with MTJ elements R11, R12 and R13. Different locations.

[0115] The first to seventh metal distribution layers M100 to M700 may include layers in which conductive wiring is formed, such as for MTJ components. R13 is connected to switching elements Sb11, Sb12 and The wiring, and the wiring for supplying power to the switching elements Sb11, Sb12 and Wiring for transmitting on / off signals.

[0116] Described Figure 10 The switching elements Sb11 and Sb12 shown are... and MTJ components The connection relationship between R11 and R13. The switching elements Sb11, Sb12 and... (The rest of the text appears to be unrelated and possibly machine-generated.) They can be connected to the corresponding MTJ components respectively. And R13, and the bit unit switching element Sb12 included in the second bit unit BCL2 can be connected to the bit unit switching element included in the third bit unit BCL3. They simultaneously share source regions and are adjacent to each other. Furthermore, the MTJ element R11 included in the first bit cell BC11 can be directly adjacent to the MTJ element R12 included in the second bit cell BCL2 and connected to the MTJ element R12 included in the second bit cell BCL2 via the seventh metal distribution layer M700. In this way, the bit cell switching element Sb12 and The reason why MTJ components R11 and R12 are arranged adjacent to each other may be as follows: Figure 5 As shown, in the processing device 100 of the embodiment, adjacent bit cells in one direction of the bit cell line BCL are alternately connected in series with each other in a first mirror structure Mir1 and a second mirror structure Mir2.

[0117] For reference, when bit cells are not connected to each other in a mirror structure in one direction of the bit cell line BCL, at least one of the bit cell switching elements can be connected to the upper part of the MTJ element. In this case, it may be necessary to form a via contact between the sixth metal distribution layer M600 and the seventh metal distribution layer M700 for connecting one end of the corresponding bit cell switching element to the upper part of the MTJ element. However, when the via contact is arranged adjacent to the MTJ element, this arrangement may adversely affect the characteristics of the MTJ element. Therefore, the via contact can be arranged away from the MTJ element, which may increase the size of the bit cell. However, in the processing device 100 of the embodiment, since the bit cells adjacent to each other in one direction of the bit cell line BCL are connected in series with each other in a first mirror structure Mir1 and a second mirror structure Mir2, it is not necessary and / or not necessary to form a via contact. Therefore, the size of the bit cell and the size of the bit cell array can be reduced, and the reliability of the MTJ element can be improved.

[0118] refer to Figure 11 In some example embodiments of the processing device 100, the MTJ element layer L200 may include multiple bit cell lines (e.g., four bit cell lines BCL1 to BCL4), each bit cell line including three bit cells. For example, in Figure 11 In order to describe the arrangement structure of MTJ components, and Figure 9A In contrast, four bit cell lines are shown, including third and fourth bit cell lines BCL3 and BCL4. However, in the processing device 100 of the example embodiment, the number of bit cell lines and / or the number of bit cells included in each bit cell line are not limited thereto.

[0119] like Figure 11 As shown, the structure of the first element line BCL1 is basically the same as the structure of the third element line BCL3. Furthermore, the structure of the second element line BCL2 is basically the same as the structure of the fourth element line BCL4. Therefore, separate reference numerals are not given to the third and fourth element lines BCL3 and BCL4.

[0120] In addition to MTJ elements, each bit cell may also include an inactive MTJ element Rd. Taking the first bit cell BC11 of the first bit cell line BCL1 as an example, besides... Figure 9A MTJ component R11 and In addition, the first unit BC11 may also include nine inactive MTJ elements Rd. However, the number of inactive MTJ elements Rd is not limited to this and may be greater than or less than nine. Inactive MTJ elements Rd may be MTJ elements not used for processing (different from the MTJ elements R11 and Rd described above). And it can be connected without electrical connection. Figure 9A The switching element Sb11 in etc. MTJ component R11 used for processing, These can be referred to as active MTJ elements to distinguish them from inactive MTJ elements Rd. Inactive MTJ elements Rd can be configured to achieve active MTJ elements R11 with uniform electrical characteristics. Due to issues in the manufacturing process, MTJ elements formed where they are surrounded by other MTJ elements can have relatively uniform electrical characteristics compared to MTJ elements formed at the boundary. Therefore, only MTJ elements located in the central portion (e.g., where their reliability is high) can be processed, while other MTJ elements may be unused, inactive MTJ elements.

[0121] will describe Figure 11 The MTJ elements included in the four bit units BC11, BC12, BC21, and BC22 are used as examples. Eleven MTJ elements can be formed in a single bit unit, and a total of forty-four (44) MTJ elements can be formed in the four bit units BC11, BC12, BC21, and BC22. In this case, the active MTJ elements can be arranged in the central part of the bit unit and surrounded by other MTJ elements. In other words, in the four bit units BC11, BC12, BC21, and BC22, eight MTJ elements R11, R21, R22, R21, R22, R21, R22, R21, R21, R22, R21, R22, R21, R21, R22, R21, R22, R21, R21, R22, R21, R22, R21, R22, R21, R22, R21, R22, R21, R22, R21, R22, R23, R24, R21, R22, R23, R24, R22, R23, R24, R22, R23, R24, R22, R23, R24, R22, R23, R24, R22, R23, R24, R25, R26 ...4, R25, R26, R26, R27, R26, R26, R27, R2 R12, R21, R22 and This can correspond to an active MTJ component. MTJ component R11, The distance between Rd and others can be, for example, from about 0.10 micrometers (μm) to about 0.40 μm. However, for MTJ elements R11, The distance between Rd and other values ​​is not limited to the range of values ​​mentioned above.

[0122] MTJ elements in adjacent bit cells can be arranged in a top-bottom symmetrical and / or left-right symmetrical structure with reference to the boundary line between adjacent bit cells. For example, MTJ element R11, Rd can be referenced to the boundary line between adjacent bit units BC11 and BC12 relative to the MTJ element R12 included in the second bit unit BC12. Rd is arranged in a symmetrical structure. Similarly, the first unit BC11 of the first unit line BCL1 includes the MTJ element R11, Rd can be referenced to the boundary line between adjacent bit units BC11 and BC21, relative to the MTJ element R21 included in the first bit unit BC21 of the second bit unit line BCL2. Rd is arranged in a left-right symmetrical structure.

[0123] Figure 12A and 12B These are circuit diagrams of bit unit pairs included in processing devices 100b and 100c according to some example embodiments.

[0124] refer to Figure 12A and 12B The processing device 100b of the example embodiment can expand the bit cell pair into a structure comprising a bit cell group BCG of 2m (where m is a natural number equal to or greater than 2) bit cells based on the above-described mirror structure and simultaneous write operations on two MTJ elements. Even within this bit cell group BCG, adjacent bit cells can have a mirror structure; furthermore, adjacent bit cells between adjacent bit cell groups BCG can also have a mirror structure. For example, when m is 2, as... Figure 12A As shown, the processing device 100b may have a structure in which the bit unit group BCG includes four bit units. For ease of explanation, in Figure 12A and 12B The markings for MTJ components and bit unit switching components have been omitted. Furthermore, in... Figure 12A and 12B In addition, as mentioned above, "Top" and "bot" can respectively represent the upper and lower parts of the MTJ element.

[0125] like Figure 12A As shown, the number of access switching elements can be further reduced compared to the structure of a bit cell pair BCP, which includes two bit cells. For example, since each bit cell group BCG has one access switching element, the number of access switching elements can be reduced by half again compared to the structure of a bit cell pair BCP. When the bit cell line is extended to include 2n (n is a natural number) (even number) bit cells, and when it is assumed that the bit cell group BCG includes 2l (where l is a natural number less than n) bit cells, the number of access switching elements can be reduced to ceil(2n / l+1). In this case, ceil can represent the upper bound function, and ceil(x) can represent the smallest integer equal to or greater than x.

[0126] In some embodiments, considering aspects of the write operation of MTJ elements, even for the case of four MTJ elements, the write operation of MTJ elements can be performed for all cases by appropriately combining bit cell switching elements. Successive expansion is possible; for example, for m = 3, 4, 5, ..., etc., eventually, it may be possible for 2m to become the maximum value 2n (where 2n equals the total number of rows of bit cell lines). In this case, similar to... Figure 12B The processing device 100c shown may not require separate data lines and access switch elements for write / read operations, and may result in a structure in which only bit cells are connected in series with each other.

[0127] Considering the read operation aspect, a method can be considered where all MTJ elements in the remaining bit units, except for the bit unit containing the target MTJ element on the path, are connected in parallel to each other. In this case, the series-connected R... P / / R AP The resistance value can be read (n-1) times, and correspondingly, it can be determined using a reference similar to the one described above. Figure 7 The described method is a way to read the resistance value of the target MTJ component.

[0128] Figure 13A and 13B This is a circuit diagram illustrating the individual and shared structures of bit cell lines included in processing devices 100 and 100d according to some example embodiments.

[0129] refer to Figure 13A and 13B In the processing device 100 of the example embodiment, a bit cell line (BCL) can be connected to two separate data lines for read / write operations. For example, an MTJ element can be programmed by applying a "+" or "-" voltage via both data lines during a write operation, and / or the state (e.g., resistance value) of the MTJ element can be read via the same data line. For example, as... Figure 13A As shown, read / write operations can be performed on the first bit cell line BCL1 via two first data lines BDLa1 and BDLb1, and read / write operations can be performed on the second bit cell line BCL2 via two second data lines BDLa2 and BDLb2. For reference, in Figure 13A and 13B For ease of description, the reference numerals for MTJ elements and bit unit switching elements are omitted, and "Top" and "bot" can respectively represent the upper and lower parts of the MTJ element.

[0130] As described above, in the processing device 100 of the example embodiment, based on the mirror structure of adjacent bit cells, via contacts may not be necessary, and the size of the bit cells can be reduced. However, when the size of the bit cells is reduced, limitations may arise in the distribution path space. Therefore, as a method for reducing the number of distribution lines, such as Figure 13B As shown, the processing device 100d of the embodiment may have a structure in which two adjacent bit cell lines BCL1 and BCL2 share two distribution lines DLa and DLb. In this shared distribution line structure, the value "0" or "1" can be programmed to the corresponding MTJ element by sequentially selecting row and / or bit cell pairs and selecting the direction of voltage supplied via the distribution lines using access switching elements.

[0131] For example, the same operation (e.g., writing "1") can be performed on two adjacent bit cell lines BCL1 and BCL2 that share two distribution lines DLa and DLb. As a result, the structure where two distribution lines are routed for each bit cell line can be changed to a structure where two distribution lines for each pair of bit cell lines are routed based on the shared structure of distribution lines DLa and DLb. Therefore, in some example embodiments, only one distribution line may be needed for each bit cell line. Thus, in the processing device 100d of the example embodiment, the number of distribution lines can be reduced, and the size of the bit cell array including the distribution lines can be reduced.

[0132] Figure 14 It is used to describe Figure 13B The circuit diagram for the read operation in the shared structure of bit cell lines.

[0133] refer to Figure 14 We will consider such Figure 13B The diagram illustrates a read operation in a structure where two adjacent bit cells share two data lines. For reference, in... Figure 14 For ease of explanation, the reference numerals for the MTJ element and the bit unit switch element have been omitted. As shown above, "Top" and "bot" can respectively represent the upper and lower parts of the MTJ element.

[0134] In a shared data line structure, limitations may exist because the MTJ elements on both sides of the bit cell line are read simultaneously, as shown below. First, both the first target MTJ element Target1 and the second target MTJ element Target2 are in a "1" state (e.g., R). AP ) or both are in a "0" state (e.g., R) P The case of ( ) is relatively easy to read. In each case, the total resistance value Rtotal can be read as follows.

[0135] i) When both have R P Time: Rtotal = 1 / 2 * (RP / / R AP +R P )

[0136] ii) When both have R AP Time: Rtotal = 1 / 2 * (R P / / R AP +R P )

[0137] However, if the first target MTJ element Target1 is in a different state than the second target MTJ element Target2, the following value can be read, but it may be difficult and / or impossible to know which of the two bit cell lines the MTJ element is R. P Or R AP In this case, the total resistance value Rtotal can be read as follows.

[0138] iii) When the two have different values: Rtotal = (R P / / R AP +R P ) / / (R P / / R AP +R AP )

[0139] For example, in a shared data line structure, information can be obtained for the following situations: i) when both have R AP When, ii) when both have R P When, and iii) when the two have different values.

[0140] Figure 15 This is a structural block diagram of a processing device 700 according to some example embodiments.

[0141] refer to Figure 15 The processing device 700 in the example embodiment may include a bit cell array 710, a controller 720, a row decoder 730, a column decoder 740, a weight driver 750, a current source controller 760, a data buffer 770, and a voltage measurement device 780. Furthermore, the processing device 700 according to the example embodiment, in addition to... Figure 15 In addition to those shown, other general-purpose components may also be included.

[0142] The bit cell array 710 may include a bit cell array that includes the aforementioned MTJ element and switching element.

[0143] The controller 720 can decode commands required to drive and operate the processing device 700. For example, the controller 720 can decode commands for setting weights, weight setting checks, input applications, measuring voltages, etc., and in some embodiments, can send signals to components required to execute these commands (e.g., as described below).

[0144] The line decoder 730 can receive a line address and an input signal, and apply the input value to the bit cell array 710. The line decoder 730 may include, for example, a digital-to-analog converter (DAC) or an analog-to-digital converter (ADC), and can apply a drive voltage to a switching element connected in series with the MTJ based on the input value. Furthermore, the line decoder 730 can change the resistance value of the MTJ elements included in the bit cell array 710, and in this case, a drive voltage can be applied to the associated switching element to select a target MTJ element.

[0145] The column decoder 740 can receive column address and weight setting signals and apply current / voltage to the MTJ element. The column decoder 740 can select the bit cell lines required for voltage measurement and the weight lines connected to the bit cells that need weight setting.

[0146] When weights are set, weight driver 750 can send weight data to the bit cells selected by row decoder 730 and column decoder 740. Weight driver 750 can drive the weight lines connected to column decoder 740 based on data received from data buffer 770, and perform weight setting and checking of the set weights. Weight driver 750 may include a current source that applies a check current to the weight lines to check whether the required resistance value has been set to the MTJ element.

[0147] The current source controller 760 can receive signals from the controller 720 to drive the current source and apply current to the bit cell line.

[0148] The voltage measuring device 780 can measure the voltage of a capacitor connected to a bit cell line or one end of a bit cell line and store the measured value in an external memory (not shown). The voltage measuring device 780 may include an ADC that outputs the measured value as a digital value.

[0149] In some embodiments, functional elements configured to perform and / or decode tasks and / or commands (e.g., controller 720, column decoder 740, weight driver 750, and / or current source controller 760) may include: processing circuitry, such as hardware including logic circuitry; hardware / software combinations, such as a processor running software; or combinations thereof. For example, the processing circuitry may more specifically include and / or be included in, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), and programmable logic units, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0150] Figure 16 This is a structural block diagram of an electronic system 800 including a processing device 810 according to some example embodiments.

[0151] refer to Figure 16 The electronic system 800 can extract information by analyzing input data based on a neural network device 830, which includes a processing device (e.g., as described above), and determine a state based on the extracted information, and / or control components of electronic devices on which the electronic system 800 is mounted. For example, the electronic system 800 can be applied to automated devices such as unmanned aerial vehicles and / or advanced driver assistance systems (ADAS), smart TVs, smartphones, medical devices, mobile devices, image display devices, measuring devices, Internet of Things (IoT) devices, etc. Furthermore, the electronic system 800 can be mounted on and / or included in various electronic devices.

[0152] In addition to the neural network device 830, the electronic system 800 may also include a processing unit 810, random access memory (RAM) 820, a memory 840, a sensor module 850, and / or a communication module (Tx / Rx module) 860. Furthermore, the electronic system 800 may also include an input / output module, a security module, a power controller, etc. A portion of the hardware components of the electronic system 800 may be mounted as a semiconductor chip. The neural network device 830 may include the processing device of the above embodiments implemented on-chip, or may include a device incorporating the processing device of the above embodiments as part of the neural network device 830.

[0153] The processing unit 810 can control all operations of the electronic system 800. The processing unit 810 may include, for example, a central processing unit (CPU), and may include single-core or multi-core processors. The processing unit 810 can process and / or execute programs and / or data stored in the memory 840, and by running programs stored in the memory 840, it can control the functions of the neural network device 830. In some embodiments, in addition to a CPU, the processing unit 810 may also be implemented in a graphics processing unit (GPU), an application processor (AP), etc.

[0154] RAM 820 can temporarily store programs, data, and / or instructions. For example, programs and / or data stored in memory 840 can be temporarily stored in RAM 820 according to the control and / or booting code of processing unit 810. RAM 820 can be implemented in and / or as storage devices such as dynamic RAM (DRAM) and static RAM (SRAM).

[0155] The neural network device 830 can perform neural network operations based on received input data and can generate information signals based on the results of the operations. The neural network device 830 may include the processing device described in the above embodiments. In addition to DNNs, the neural network device 830 may also include convolutional neural networks (CNNs), recurrent neural networks (RNNs), deep belief networks, restricted Boltzmann machines, etc., but is not limited thereto. The neural network device 830 may correspond to a hardware accelerator dedicated to neural networks.

[0156] Information signals can include various recognition signals, such as audio recognition signals, object recognition signals, image recognition signals, and biometric recognition signals. For example, the neural network device 830 can receive frame data included in a video stream and / or audio data included in an audio stream as input data, and generate recognition signals for objects included in the image represented by the frame data and / or the sound represented by the audio data. The neural network device 830 can receive various types of input data depending on the type or function of the electronic device installed thereon, and can generate recognition signals based on the input data.

[0157] The memory 840 can serve as a storage area for storing data, including the operating system (OS), various programs, and various data. The memory 840 may include volatile memory and / or non-volatile memory.

[0158] Sensor module 850 can collect information about the periphery of the electronic device on which electronic system 800 is installed. Sensor module 850 may include various types of sensing devices and can sense or receive signals from outside the electronic device (e.g., image signals, audio signals, magnetic signals, biosignals, touch signals, etc.), and convert the sensed or received signals into data. Furthermore, sensor module 850 can provide the converted data to neural network device 830 as input data. In some embodiments, as described below, sensor module 850 may also include a user interface device.

[0159] The communication module 860 may include various wired or wireless interfaces capable of communicating with external devices. For example, the communication module 860 may facilitate communication between the electronic system 800 and a network.

[0160] The electronic system 800 may also include user interface devices (such as touch panels, buttons, and paddles), a processor, memory devices for storing and running program data, permanent storage (such as disk drives), and communication ports for communicating with external devices. Methods implemented as software modules or algorithms may be stored on a computer-readable recording medium as computer-readable code or program commands executable in a processor.

[0161] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it should be understood that various changes in form and detail may be made without departing from the spirit and scope of the appended claims.

Claims

1. A processing device based on a magnetic tunnel junction (MTJ) element, comprising: At least one bit cell line, wherein multiple bit cells on the at least one bit cell line are connected in series with each other. Each of the plurality of bit units includes The first MTJ component is configured to switch between different resistance states and is programmed with a resistance value. The second MTJ component is configured to switch between different resistance states and is programmed with resistance values. A first switching element, connected in series with the first MTJ element, is configured to switch on or off the first MTJ element by applying at least one of current or voltage. A second switching element, connected in series with the second MTJ element, is configured to switch on or off the application of at least one of current or voltage to the second MTJ element. The second switching element is configured to perform a switching action complementary to that of the first switching element, and In the bit cell line, two adjacent bit cells are connected in series with each other in a mirror structure.

2. The processing apparatus according to claim 1, wherein The first MTJ element and the second MTJ element of the (2i-1)th bit cell of the at least one bit cell line are adjacent to and connected in series with the first MTJ element and the second MTJ element of the (2i)th bit cell of the at least one bit cell line, where i represents a natural number, and The first and second switching elements of the (2i)th bit unit of the at least one bit unit line are adjacent to and connected in series with the first and second switching elements of the (2i+1)th bit unit of the at least one bit unit line.

3. The processing apparatus according to claim 2, wherein The first switching element and the second switching element each include a transistor, and The first and second switching elements of the (2i)th bit cell of the at least one bit cell line share the source region with the first and second switching elements of the (2i+1)th bit cell of the at least one bit cell line.

4. The processing apparatus according to claim 2, further comprising: At least two third switching elements between the bit cell line and the data line for programming Wherein, when the bit cell line includes an even number of bit cells, The (2i-1)th bit unit and the (2i)th bit unit constitute a bit unit pair. The number of the third switching elements is one more than the number of the bit unit pairs, and One of the bit units is located between two adjacent third switching elements, or Wherein, when the bit cell line includes an odd number of bit cells, At least one of the (2i-1)th bit unit and the (2i)th bit unit, or the (2i)th bit unit and the (2i+1)th bit unit, constitutes a bit unit pair. The first or last bit unit does not form a bit unit pair, and The number of the third switching elements is two more than the number of bit pairs, and At least one of the bit unit pair, the first bit unit, or the last bit unit is located between two adjacent third switching elements.

5. The processing apparatus according to claim 4, wherein, At least one of the first MTJ element and the second MTJ element of the first unit of the bit cell pair, and at least one of the first MTJ element and the second MTJ element of the second bit cell pair, are simultaneously and complementaryly programmed in either a vertical write or a diagonal write type.

6. The processing apparatus according to claim 1, wherein Each of the plurality of bit cells is configured to perform an XNOR operation using the resistance values ​​of the first MTJ element and the second MTJ element, and the switching operations of the first switching element and the second switching element. The bit cell line is configured to perform a multiply-accumulate (MAC) operation, which includes a multiplication operation and an addition operation on the result of the multiplication operation.

7. The processing apparatus according to claim 1, wherein The at least one bit cell line includes multiple bit cell lines, and Two adjacent bit cell lines among the plurality of bit cell lines share a data line used for programming the first MTJ element and the second MTJ element.

8. The processing apparatus according to claim 1, further comprising: The substrate includes an active region and at least two metal distribution layers on the active region. Wherein, the first switching element and the second switching element are included in the active region, and The first MTJ element and the second MTJ element of each of the plurality of bit cells are arranged between the first upper metal layer and the second upper metal layer of the at least two metal distribution layers.

9. The processing apparatus of claim 8, wherein there are no through-hole contacts between the first upper metal layer and the second upper metal layer.

10. A processing device based on a magnetic tunnel junction (MTJ) element, comprising: Base; An active layer, on the substrate, includes a plurality of switching elements; At least two metal distribution layers are provided on the active layer, the at least two metal distribution layers including a first upper metal layer and a second upper metal layer; The MTJ component layer is located between the first upper metal layer and the second upper metal layer; and At least one bit cell line, wherein multiple bit cells on the at least one bit cell line are connected in series with each other. Each of the plurality of bit units includes The first MTJ element is located on the MTJ element layer. The second MTJ element is connected in parallel to the first MTJ element on the MTJ element layer. A first switching element is connected in series with the first MTJ element in the active layer, and A second switching element is connected in series with the second MTJ element in the active layer. The first MTJ element and the second MTJ element are programmed with complementary resistance values. The first switching element and the second switching element are configured to switch complementaryly to each other, and at least one of current or voltage is applied to the first MTJ element and the second MTJ element, respectively. On at least one bit cell line, two adjacent bit cells are connected in series with each other in a mirror structure, the mirror structure including The first mirror image of the first switching element and the second switching element, and The second mirror image of the first MTJ element and the second MTJ element, and In one direction of the at least one bit cell line, the first mirror image and the second mirror image are alternately repeated between two adjacent bit cells.

11. The processing apparatus according to claim 10, wherein The (2i-1)th bit unit of the at least one bit unit line is connected in series with the (2i)th bit unit of the at least one bit unit line via the second mirror image, where i represents a natural number. The (2i)th bit cell of the at least one bit cell line is connected in series with the (2i+1)th bit cell of the at least one bit cell line via the first mirror image. When the bit cell line includes an even number of bit cells, the (2i-1)th bit cell and the (2i)th bit cell form a bit cell pair; or when the bit cell line includes an odd number of bit cells, at least one of the (2i-1)th bit cell and the (2i)th bit cell, or the (2i)th bit cell and the (2i+1)th bit cell form a bit cell pair. At least one of the first MTJ element and the second MTJ element of the first unit of the bit unit pair, and one of the first MTJ element and the second MTJ element of the second unit of the bit unit pair, are programmed with complementary resistance values.

12. The processing apparatus according to claim 11, further comprising: At least two third switching elements between the bit cell line and the data line for programming the first MTJ element and the second MTJ element. Wherein, the at least two third switching elements include one or two more third switching elements than the number of bit unit pairs. One of the bit units is located between two adjacent third switching elements, and At least one of the first MTJ element or the second MTJ element of the first bit unit, and one of the first MTJ element or the second MTJ element of the second bit unit, are configured to be programmed simultaneously and complementaryly according to the current.

13. The processing apparatus according to claim 10, wherein The at least one bit cell line includes multiple bit cell lines. in, Each of the plurality of bit units is configured to perform an XNOR operation. Each of the multiple bit cell lines is configured to perform a multiply-accumulate (MAC) operation, and The multiple bit cell lines constitute a two-dimensional bit cell array type neural network.

14. The processing apparatus according to claim 10, wherein, There are no through-hole contacts between the first upper metal layer and the second upper metal layer.

15. The processing apparatus according to claim 10, further comprising: The MTJ element layer contains multiple inactive MTJ elements that are not connected to either the first or the second switching element, and In each of the plurality of bit cells, the first MTJ element and the second MTJ element are located at the central portion of the bit cell in the plan view, and the inactive MTJ element is located at the boundary portion of the bit cell, the boundary portion surrounding the central portion in the plan view.

16. An electronic system comprising: Processing equipment based on magnetic tunnel junction (MTJ) elements; The processing unit is configured to control the operation of the processing device; and A memory unit is configured to store at least one of a program, data, or commands to be used in the operation of the processing device. The processing device includes at least one bit cell line, and multiple bit cells on the at least one bit cell line are connected in series with each other. Each of the plurality of bit units includes The first MTJ element is configured to switch between different resistance states and is programmed with a resistance value; A second MTJ element is connected in parallel to the first MTJ element. The second MTJ element is configured to switch between different resistance states and is programmed with a resistance value that is complementary to the resistance value of the first MTJ element. A first switching element, connected in series with the first MTJ element, is configured to switch on or off the first MTJ element by applying at least one of a current or a voltage; and A second switching element, connected in series with the second MTJ element, is configured to switch on or off the application of at least one of current or voltage to the second MTJ element. The second switching element is configured to perform a switching operation complementary to that of the first switching element, and In the bit cell line, two adjacent bit cells are connected in series with each other in a mirror structure.

17. The electronic system according to claim 16, wherein The first MTJ element and the second MTJ element of the (2i-1)th bit cell of the at least one bit cell line are adjacent to and connected in series with the first MTJ element and the second MTJ element of the (2i)th bit cell of the at least one bit cell line, where i represents a natural number. The first and second switching elements of the (2i)th bit cell of the at least one bit cell line are adjacent to and connected in series with the first and second switching elements of the (2i+1)th bit cell of the at least one bit cell line. in, When the at least one bit cell line includes an even number of bit cells, the (2i-1)th bit cell and the (2i)th bit cell constitute a bit cell pair; or when the at least one bit cell line includes an odd number of bit cells, at least one of the (2i-1)th bit cell and the (2i)th bit cell, or the (2i)th bit cell and the (2i+1)th bit cell constitutes a bit cell pair. In this configuration, at least one of the first MTJ element or the second MTJ element of the first unit of the bit cell pair, and one of the first MTJ element or the second MTJ element of the second bit cell of the bit cell pair, are configured to have complementary resistance values.

18. An electronic system comprising: Processing equipment based on magnetic tunnel junction (MTJ) elements; The processing unit is configured to control the operation of the processing device; The memory unit is configured to store at least one of programs, data, and commands to be used in the operation of the processing device; The sensor module is configured to collect information; and The communication module is configured to communicate with external devices. The processing equipment includes Base, An active layer, on the substrate, includes a plurality of switching elements. At least two metal distribution layers, on the active layer, the at least two metal distribution layers including a first upper metal layer and a second upper metal layer, The MTJ component layer is located between the first upper metal layer and the second upper metal layer. At least one bit cell line, wherein multiple bit cells on the at least one bit cell line are connected in series with each other. Each of the plurality of bit units includes The first MTJ element is located on the MTJ element layer. The second MTJ element is connected in parallel to the first MTJ element on the MTJ element layer. A first switching element is connected in series with the first MTJ element in the active layer, and A second switching element is connected in series with the second MTJ element in the active layer. The first MTJ element and the second MTJ element are programmed with complementary resistance values. The first switching element and the second switching element are configured to switch complementaryly, and at least one of current or voltage is applied to the first MTJ element and the second MTJ element, respectively. On at least one bit cell line, two adjacent bit cells are connected in series with each other in a mirror structure, the mirror structure including The first mirror image of the first switching element and the second switching element, and The second mirror image of the first MTJ element and the second MTJ element, and In one direction of the at least one bit cell line, the first image and the second image alternately repeat between two adjacent bit cells.

19. The electronic system according to claim 18, wherein The (2i-1)th bit unit of the at least one bit unit line is connected in series with the (2i)th bit unit of the at least one bit unit line via the second mirror image, where i represents a natural number, and The (2i)th bit cell of the at least one bit cell line is connected in series with the (2i+1)th bit cell of the at least one bit cell line via the first mirror image. When the at least one bit cell line includes an even number of bit cells, the (2i-1)th bit cell and the (2i)th bit cell form a bit cell pair; or when the at least one bit cell line includes an odd number of bit cells, the (2i-1)th bit cell and the (2i)th bit cell, or the (2i)th bit cell and the (2i+1)th bit cell form a bit cell pair. At least one of the first MTJ element or the second MTJ element of the first unit of the at least one bit unit pair, and one of the first MTJ element or the second MTJ element of the second bit unit of the at least one bit unit pair, are programmed with complementary resistance values.

20. The electronic system according to claim 18, wherein The at least one bit cell line includes multiple bit cell lines. Each of the plurality of bit units is configured to perform an XNOR operation. Each of the multiple bit cell lines is configured to perform a multiply-accumulate (MAC) operation. The multiple bit cell lines constitute a two-dimensional bit cell array type neural network, and There are no through-hole contacts between the first upper metal layer and the second upper metal layer.

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