Semiconductor device and method of manufacturing the same

Abstract

Disclosed is a semiconductor device and a method for manufacturing the same. The semiconductor device includes a substrate, a first interlayer insulating layer provided on the substrate, a first trench formed inside the first interlayer insulating layer, a contact plug provided inside the first trench, a first wiring pattern provided on the contact plug, a second wiring pattern provided on the first interlayer insulating layer and spaced apart from the first wiring pattern in a horizontal direction, a second interlayer insulating layer provided on the first interlayer insulating layer and surrounding each sidewall of the first wiring pattern and each sidewall of the second wiring pattern, and a first air gap formed on the contact plug inside the first trench.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2021-0020867, filed on February 17, 2021, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to a semiconductor device and a method for manufacturing the same. Background Technology

[0003] Semiconductor components are considered a crucial element in the electronics industry due to their characteristics such as miniaturization, versatility, and / or low manufacturing costs. Semiconductor components can be classified into semiconductor memory components that store logic data, semiconductor logic components that perform computational processes involving logic data, and hybrid semiconductor components that combine memory and logic elements, etc.

[0004] With the increasing speed and low power consumption of electronic devices in recent years, the semiconductor components embedded in these devices also need to have high operating speeds and / or low operating voltages. To meet these required characteristics, semiconductor components are being integrated more deeply. The deeper the integration of a semiconductor component, the lower its reliability. However, with the rapid development of the electronics industry, the demand for high reliability of semiconductor components is increasing. Therefore, much research is underway to improve the reliability of semiconductor components. Summary of the Invention

[0005] This disclosure provides a semiconductor device that ensures isolation margin from adjacent wiring patterns by forming wiring patterns on a contact plug whose upper portion is etched, and a method for manufacturing the semiconductor device.

[0006] According to an exemplary embodiment of the present disclosure, a semiconductor device is provided, the semiconductor device comprising: a substrate; a first interlayer insulating layer disposed on the substrate; a first trench formed inside the first interlayer insulating layer; a contact plug disposed inside the first trench; a first wiring pattern disposed on the contact plug; a second wiring pattern disposed on the first interlayer insulating layer and spaced horizontally from the first wiring pattern; a second interlayer insulating layer disposed on the first interlayer insulating layer and surrounding each sidewall of the first wiring pattern and each sidewall of the second wiring pattern; and a first air gap formed inside the first trench on the contact plug.

[0007] According to exemplary embodiments of the present disclosure, a semiconductor device is provided, the semiconductor device comprising: a substrate; a first interlayer insulating layer disposed on the substrate; a first trench formed within the first interlayer insulating layer; a contact plug disposed within the first trench; a first wiring pattern disposed on the contact plug; a second wiring pattern disposed on the first interlayer insulating layer and horizontally spaced from the first wiring pattern; a second interlayer insulating layer disposed on the first interlayer insulating layer and surrounding each sidewall of the first wiring pattern and each sidewall of the second wiring pattern; and a first air gap and a second air gap formed within the first trench on the contact plug and horizontally spaced from each other. The height from the upper surface of the contact plug to the upper surface of the first interlayer insulating layer is greater than the horizontal spacing between the first trench and the second wiring pattern. The width of the first wiring pattern in the horizontal direction increases toward the contact plug.

[0008] According to exemplary embodiments of the present disclosure, a method for manufacturing a semiconductor device is provided, the method comprising: forming a first interlayer insulating layer including a trench on a substrate; forming a contact plug inside the trench; forming a first wiring pattern on the contact plug; forming a second interlayer insulating layer on the first interlayer insulating layer surrounding a sidewall of the first wiring pattern; forming an air gap in a vertical direction between the contact plug and the second interlayer insulating layer inside the trench; and forming a third interlayer insulating layer on the second interlayer insulating layer. The upper surface of the air gap is formed to be lower than the upper surface of the first interlayer insulating layer.

[0009] However, the aspects of this disclosure are not limited to those set forth herein. These and other aspects of this disclosure will become more apparent to those skilled in the art from the following detailed description of the disclosure. Attached Figure Description

[0010] The above and other aspects and features of this disclosure will become more apparent from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings, wherein:

[0011] Figure 1 These are diagrams used to explain semiconductor devices according to some embodiments of this disclosure;

[0012] Figure 2 yes Figure 1 A magnified view of region R1;

[0013] Figure 3 These are diagrams used to explain semiconductor devices according to some other embodiments of this disclosure;

[0014] Figure 4 These are diagrams used to explain semiconductor devices according to some other embodiments of this disclosure;

[0015] Figure 5yes Figure 4 A magnified view of region R2;

[0016] Figure 6 These are diagrams used to explain semiconductor devices according to some other embodiments of this disclosure;

[0017] Figure 7 These are diagrams used to explain semiconductor devices according to some other embodiments of this disclosure;

[0018] Figure 8 yes Figure 7 A magnified view of region R3;

[0019] Figure 9 These are diagrams used to explain semiconductor devices according to some other embodiments of this disclosure;

[0020] Figure 10 These are diagrams used to explain semiconductor devices according to some other embodiments of this disclosure;

[0021] Figure 11 yes Figure 10 A magnified view of region R4;

[0022] Figure 12 These are diagrams used to explain semiconductor devices according to some other embodiments of this disclosure;

[0023] Figures 13 to 18 This is an intermediate stage diagram used to explain a method for manufacturing a semiconductor device according to some embodiments of the present disclosure; and

[0024] Figures 19 to 22 This is an intermediate stage diagram used to explain a method for manufacturing a semiconductor device according to some other embodiments of this disclosure. Detailed Implementation

[0025] In the following text, reference will be made to Figure 1 and Figure 2 A semiconductor device according to some embodiments of the present disclosure is described.

[0026] Figure 1 This is a diagram used to explain a semiconductor device according to some embodiments of the present disclosure. Figure 2 yes Figure 1 A magnified view of region R1.

[0027] Reference Figure 1 and Figure 2A semiconductor device according to some embodiments of the present disclosure includes a substrate 100, a first interlayer insulating layer 110, a contact plug 120, a first wiring pattern 130, a second wiring pattern 135, a second interlayer insulating layer 140, an air gap 150, a third interlayer insulating layer 160, a via 170, a fourth interlayer insulating layer 180, a third wiring pattern 190, and a fourth wiring pattern 195.

[0028] Although substrate 100 may have a structure in which a substrate and an epitaxial layer are stacked, this disclosure is not limited thereto. Substrate 100 may be a silicon substrate, a gallium arsenide substrate, a silicon germanium substrate, a ceramic substrate, a quartz substrate, a glass substrate for a display, or may be an SOI (semiconductor on insulator) substrate.

[0029] Furthermore, although not shown, the substrate 100 may include conductive patterns. While the conductive patterns may be metal wiring, contacts, etc., and may be the gate electrode of a transistor, the source / drain electrode of a transistor, a diode, etc., this disclosure is not limited thereto.

[0030] In some embodiments, the substrate 100 may include a fin transistor (FinFET) with a channel region comprising a fin pattern shape, or a transistor (MBCFET) comprising nanowires or nanosheets. TM (Multi-channel field-effect transistor), tunneling transistor (tunneling FET), planar transistor, bipolar junction transistor, or laterally diffused metal-oxide-semiconductor (LDMOS) transistor. Additionally, in some other embodiments, substrate 100 may include NCFET (negative capacitance field-effect transistor) or VFET (vertical field-effect transistor).

[0031] The first interlayer insulating layer 110 may be disposed on the substrate 100. The first interlayer insulating layer 110 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material. Although the low dielectric constant material may include, for example, FOX (flowable oxide), TOSZ (Tonen SilaZen), USG (undoped silica glass), BSG (borosilicate glass), PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), PETEOS (plasma-enhanced tetraethyl orthosilicate), FSG (fluorosilicate glass), CDO (carbon-doped silica), degelatin, aerogel, amorphous fluorinated carbon, OSG (organosilicon glass), parylene, BCB (bisbenzocyclobutene), SiLK, polyimide, porous polymer materials, or combinations thereof, this disclosure is not limited thereto.

[0032] The first trench T1 can be formed inside the first interlayer insulation layer 110. For example, the first trench T1 can penetrate the first interlayer insulation layer 110 in the vertical direction DR2.

[0033] The contact plug 120 may be disposed inside the first trench T1. The sidewalls of the contact plug 120 may be surrounded by a first interlayer insulating layer 110. For example, the contact plug 120 may be electrically connected to a conductive pattern disposed inside the substrate 100.

[0034] although Figure 1 The contact plug 120 is shown to be formed from a single membrane, but this is for illustrative purposes only and the disclosure is not limited thereto. For example, the contact plug 120 may be formed from two or more membranes. In this case, the contact plug 120 may include a barrier layer disposed along the sidewalls and bottom surface of the first trench T1 and a filler layer disposed on the barrier layer.

[0035] The barrier layer of the contact plug 120 may include at least one of, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tantalum carbonitride (TaCN), tungsten (W), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), and combinations thereof. The filling layer of the contact plug 120 may include at least one of, for example, copper (Cu), silver (Ag), cobalt (Co), tantalum (Ta), indium (In), tin (Sn), zinc (Zn), manganese (Mn), titanium (Ti), magnesium (Mg), chromium (Cr), germanium (Ge), strontium (Sr), platinum (Pt), aluminum (Al), zirconium (Zr), molybdenum (Mo), ruthenium (Ru), and combinations thereof. However, this disclosure is not limited thereto.

[0036] The upper surface 120a of the contact plug 120 may be formed to be lower than the upper surface 110a of the first interlayer insulation layer 110. For example, at least a portion of the first interlayer insulation layer 110 may be exposed to the first trench T1 on the upper surface 120a of the contact plug 120.

[0037] The first wiring pattern 130 may be disposed on the upper surface 120a of the contact plug 120. The first wiring pattern 130 may contact the contact plug 120. At least a portion of the first wiring pattern 130 may be disposed inside the first trench T1.

[0038] The sidewalls of the first wiring pattern 130 may have an inclined profile. For example, the width of the first wiring pattern 130 in the horizontal direction DR1 may increase toward the contact plug 120. After the first wiring pattern 130 is formed by a patterning process, a second interlayer insulating layer 140 may be formed. Therefore, the inclined profile of the sidewalls of the first wiring pattern 130 may be formed as described above.

[0039] although Figure 1The illustration shows that the width of the first wiring pattern 130 in the horizontal direction DR1 increases toward the contact plug 120, but this disclosure is not limited thereto. In some other embodiments, the width of the first wiring pattern 130 in the horizontal direction DR1 may decrease toward the contact plug 120.

[0040] The first wiring pattern 130 may include a first barrier layer 131 and a first wiring layer 132. The first barrier layer 131 may form the lower surface of the first wiring pattern 130. The first barrier layer 131 may contact the upper surface 120a of the contact plug 120. For example, the first barrier layer 131 may be conformally formed on the upper surface 120a of the contact plug 120.

[0041] The first barrier layer 131 may include, for example, one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tantalum carbonitride (TaCN), tungsten (W), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), and combinations thereof. However, this disclosure is not limited thereto.

[0042] The first wiring layer 132 may be disposed on the first barrier layer 131. The first wiring layer 132 may include at least one of, for example, carbon (C), silver (Ag), cobalt (Co), tantalum (Ta), indium (In), tin (Sn), zinc (Zn), manganese (Mn), titanium (Ti), magnesium (Mg), chromium (Cr), germanium (Ge), strontium (Sr), platinum (Pt), aluminum (Al), and zirconium (Zr). However, this disclosure is not limited thereto.

[0043] The second wiring pattern 135 may be disposed on the upper surface 110a of the first interlayer insulating layer 110. The second wiring pattern 135 may be spaced apart from the first wiring pattern 130 in the horizontal direction DR1. For example, the second wiring pattern 135 may be electrically connected to a conductive pattern disposed inside the substrate 100.

[0044] The sidewalls of the second wiring pattern 135 may have an inclined profile similar to that of the sidewalls of the first wiring pattern 130. For example, the width of the second wiring pattern 135 in the horizontal direction DR1 may increase toward the first interlayer insulating layer 110. After the second wiring pattern 135 is formed by a patterning process, a second interlayer insulating layer 140 may be formed. Therefore, the inclined profile of the sidewalls of the second wiring pattern 135 may be formed as described above.

[0045] although Figure 1The illustration shows that the width of the second wiring pattern 135 in the horizontal direction DR1 increases toward the first interlayer insulating layer 110, but this disclosure is not limited thereto. In some other embodiments, the width of the second wiring pattern 135 in the horizontal direction DR1 may decrease toward the first interlayer insulating layer 110.

[0046] The second wiring pattern 135 may include a first barrier layer and a first wiring layer. The first barrier layer of the second wiring pattern 135 may be formed on the lower surface of the second wiring pattern 135. The first barrier layer of the second wiring pattern 135 may be in contact with the upper surface 110a of the first interlayer insulating layer 110. For example, the first barrier layer of the second wiring pattern 135 may be conformally formed on the upper surface 110a of the first interlayer insulating layer 110.

[0047] In an example embodiment, the materials of the first barrier layer and the first wiring layer forming the second wiring pattern 135 may be the same as the materials of the first barrier layer 131 and the first wiring layer 132 forming the first wiring pattern 130 as described above.

[0048] For example, the second wiring pattern 135 may be spaced apart from the first trench T1 by a first gap P1 in the horizontal direction DR1. The first height H1 from the upper surface 120a of the contact plug 120 to the upper surface 110a of the first interlayer insulation layer 110 in the vertical direction DR2 may be greater than the first gap P1 between the first trench T1 and the second wiring pattern 135 in the horizontal direction DR1.

[0049] The second interlayer insulation layer 140 may be disposed on the first interlayer insulation layer 110. The second interlayer insulation layer 140 may surround a portion of the sidewall of the first wiring pattern 130 and each of the sidewalls of the second wiring pattern 135. For example, the second interlayer insulation layer 140 may surround portions of both sidewalls of the first wiring pattern 130 and both sidewalls of the second wiring pattern 135.

[0050] The upper surface of the second interlayer insulating layer 140 may be formed on the same plane as the upper surface of the first wiring pattern 130 and the upper surface of the second wiring pattern 135. The second interlayer insulating layer 140 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material.

[0051] An air gap 150 may be formed on the upper surface 120a of the contact plug 120 within the first groove T1. An air gap 150 may also be formed between the upper surface 120a of the contact plug 120 and the second interlayer insulation layer 140 on at least one of the sidewalls of the first wiring pattern 130. The term "air" as discussed herein may refer to atmospheric air or other gases that may be present during the manufacturing process. It should be understood that an "air gap" may include a gap containing air or other gases (e.g., gases present during manufacturing) or may include a gap in which a vacuum is formed.

[0052] For example, air gap 150 may include a first air gap 151 and a second air gap 152. The first air gap 151 may be spaced apart from the second air gap 152 in the horizontal direction DR1. The first air gap 151 may be formed on a first sidewall 130s1 of the first wiring pattern 130. The second air gap 152 may be formed on a second sidewall 130s2 of the first wiring pattern 130 opposite to the first sidewall 130s1 of the first wiring pattern 130. For example, at least a portion of the first wiring pattern 130 may be disposed between the first air gap 151 and the second air gap 152.

[0053] The first air gap 151 can be an empty space surrounded by the upper surface 120a of the contact plug 120, the first interlayer insulation layer 110, the first sidewall 130s1 of the first wiring pattern 130, and the second interlayer insulation layer 140. Furthermore, the second air gap 152 can be an empty space surrounded by the upper surface 120a of the contact plug 120, the first interlayer insulation layer 110, the second sidewall 130s2 of the first wiring pattern 130, and the second interlayer insulation layer 140.

[0054] The upper surface of the air gap 150 can be formed to be lower than the upper surface 110a of the first interlayer insulation layer 110. For example, the upper surface 151a of the first air gap 151 can be formed to be lower than the upper surface 110a of the first interlayer insulation layer 110. Furthermore, the upper surface of the second air gap 152 can be formed to be lower than the upper surface 110a of the first interlayer insulation layer 110.

[0055] A third interlayer insulating layer 160 may be disposed on the second interlayer insulating layer 140. The third interlayer insulating layer 160 may cover the upper surface of the first wiring pattern 130 and the upper surface of the second wiring pattern 135. The third interlayer insulating layer 160 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material.

[0056] The second trench T2 can be formed inside the third interlayer insulation layer 160. For example, the second trench T2 can penetrate the third interlayer insulation layer 160 in the vertical direction DR2.

[0057] Via 170 can be disposed inside the second trench T2. The sidewalls of via 170 can be surrounded by a third interlayer insulating layer 160. For example, via 170 can contact the first wiring pattern 130.

[0058] although Figure 1 The via 170 is shown to be formed from a single membrane, but this is for illustrative purposes only, and the present disclosure is not limited thereto. For example, the via 170 may be formed from two or more membranes. In this case, the via 170 may include a via blocking layer disposed along the sidewalls and bottom surface of the second trench T2, and a via filling layer disposed on the via blocking layer.

[0059] The via barrier layer may include, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tantalum carbonitride (TaCN), tungsten (W), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), and combinations thereof. The via filling layer may include, for example, copper (Cu), silver (Ag), cobalt (Co), tantalum (Ta), indium (In), tin (Sn), zinc (Zn), manganese (Mn), titanium (Ti), magnesium (Mg), chromium (Cr), germanium (Ge), strontium (Sr), platinum (Pt), aluminum (Al), zirconium (Zr), molybdenum (Mo), ruthenium (Ru), and combinations thereof. However, this disclosure is not limited thereto.

[0060] For example, the upper surface of the via 170 may be formed on the same plane as the upper surface of the third interlayer insulating layer 160. However, this disclosure is not limited thereto.

[0061] The third wiring pattern 190 can be disposed on the upper surface of the via 170. The third wiring pattern 190 can contact the via 170. The third wiring pattern 190 can be electrically connected to the conductive pattern disposed inside the substrate 100 through the via 170, the first wiring pattern 130 and the contact plug 120.

[0062] although Figure 1 The diagram shows that the width of the third wiring pattern 190 in the horizontal direction DR1 increases toward the via 170, but this disclosure is not limited thereto. In some other embodiments, the width of the third wiring pattern 190 in the horizontal direction DR1 may decrease toward the via 170.

[0063] The third wiring pattern 190 may include a second barrier layer 191 and a second wiring layer 192. The second barrier layer 191 may form the lower surface of the third wiring pattern 190. The second barrier layer 191 may contact the upper surface of the via 170. For example, the second barrier layer 191 may be conformally formed on the upper surface of the via 170. However, this disclosure is not limited thereto.

[0064] The second barrier layer 191 may include, for example, one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tantalum carbonitride (TaCN), tungsten (W), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), and combinations thereof. However, this disclosure is not limited thereto.

[0065] The second wiring layer 192 may be disposed on the second barrier layer 191. The second wiring layer 192 may include at least one of, for example, copper (Cu), silver (Ag), cobalt (Co), tantalum (Ta), indium (In), tin (Sn), zinc (Zn), manganese (Mn), titanium (Ti), magnesium (Mg), chromium (Cr), germanium (Ge), strontium (Sr), platinum (Pt), aluminum (Al), zirconium (Zr), molybdenum (Mo), ruthenium (Ru), and combinations thereof. However, this disclosure is not limited thereto.

[0066] The fourth wiring pattern 195 can be disposed on the upper surface of the third interlayer insulation layer 160. The fourth wiring pattern 195 can be spaced apart from the third wiring pattern 190 in the horizontal direction DR1.

[0067] although Figure 1 The illustration shows that the width of the fourth wiring pattern 195 in the horizontal direction DR1 increases toward the third interlayer insulating layer 160, but this disclosure is not limited thereto. In some other embodiments, the width of the fourth wiring pattern 195 in the horizontal direction DR1 may decrease toward the third interlayer insulating layer 160.

[0068] The fourth wiring pattern 195 may include a second barrier layer and a second wiring layer. The second barrier layer of the fourth wiring pattern 195 may form the lower surface of the fourth wiring pattern 195. The second barrier layer of the fourth wiring pattern 195 may contact the upper surface of the third interlayer insulating layer 160. For example, the second barrier layer of the fourth wiring pattern 195 may be conformally formed on the upper surface of the third interlayer insulating layer 160. However, this disclosure is not limited thereto.

[0069] In an example embodiment, the materials of the second barrier layer and the second wiring layer forming the fourth wiring pattern 195 may be the same as the materials of the second barrier layer 191 and the second wiring layer 192 forming the third wiring pattern 190 as described above.

[0070] A fourth interlayer insulation layer 180 may be disposed on the third interlayer insulation layer 160. The fourth interlayer insulation layer 180 may surround each of the sidewalls of the third wiring pattern 190 and the sidewalls of the fourth wiring pattern 195. For example, the fourth interlayer insulation layer 180 may surround both sidewalls of the third wiring pattern 190 and both sidewalls of the fourth wiring pattern 195.

[0071] The upper surface of the fourth interlayer insulating layer 180 may be formed on the same plane as the upper surface of the third wiring pattern 190 and the upper surface of the fourth wiring pattern 195. The fourth interlayer insulating layer 180 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material.

[0072] In a semiconductor device according to some embodiments of the present disclosure, the reliability of the semiconductor device can be improved because a first wiring pattern 130 is formed on a contact plug 120 on a portion of its upper part is etched to ensure an isolation margin between the first wiring pattern 130 and a second wiring pattern 135 adjacent to the first wiring pattern 130.

[0073] In the following text, reference will be made to Figure 3 Semiconductor devices according to some other embodiments of this disclosure are described. For ease of explanation, the description will primarily focus on... Figure 1 and Figure 2 The differences are shown in the semiconductor device.

[0074] Figure 3 This is a diagram used to explain a semiconductor device according to some other embodiments of the present disclosure.

[0075] Reference Figure 3 In some other embodiments of the semiconductor device according to this disclosure, an air gap 250 may be formed on only one sidewall of the first wiring pattern 230. Specifically, the air gap 250 may be formed on the first sidewall 230s1 of the first wiring pattern 230. The second sidewall 230s2 of the first wiring pattern 230, opposite to the first sidewall 230s1, may contact the first interlayer insulating layer 110.

[0076] although Figure 3 The second interlayer insulating layer 140 is shown not disposed between the second sidewall 230s2 of the first wiring pattern 230 and the first interlayer insulating layer 110, but this disclosure is not limited thereto. In some other embodiments, the second interlayer insulating layer 140 may also be disposed in a portion of the space between the second sidewall 230s2 of the first wiring pattern 230 and the first interlayer insulating layer 110.

[0077] The first wiring pattern 230 may include a first barrier layer 231 and a first wiring layer 232. The first barrier layer 231 may form a sidewall of the first wiring pattern 230 that contacts the first interlayer insulation layer 110, and also form a lower surface of the first wiring pattern 230 that contacts the contact plug 120. The first barrier layer 231 may contact the upper surface 120a of the contact plug 120 and the first interlayer insulation layer 110. The first wiring layer 232 may be disposed on the first barrier layer 231.

[0078] In the following text, reference will be made to Figure 4 and Figure 5 Semiconductor devices according to some other embodiments of this disclosure are described. For ease of explanation, the description will primarily focus on... Figure 1 and Figure 2 The differences are shown in the semiconductor device.

[0079] Figure 4 This is a diagram used to explain a semiconductor device according to some other embodiments of the present disclosure. Figure 5 yes Figure 4 A magnified view of region R2.

[0080] Reference Figure 4 and Figure 5 In some other embodiments of the semiconductor device according to this disclosure, the contact plug 320 may include a first portion 321 and a second portion 322 protruding vertically from the first portion 321. Each of the first portion 321 and the second portion 322 of the contact plug 320 may be disposed within the first trench T1.

[0081] The sidewall of the first portion 321 of the contact plug 320 can contact the first interlayer insulation layer 110. The sidewall of the second portion 322 of the contact plug 320 can be spaced apart from the first interlayer insulation layer 110.

[0082] An air gap 150 may be formed between the upper surface of the first portion 321 of the contact plug 320 and the second interlayer insulating layer 140 on two sidewalls of the second portion 322 of the contact plug 320. For example, an air gap 150 may be formed between each sidewall of the second portion 322 of the contact plug 320 and the first interlayer insulating layer 110. The air gap 150 may include a first air gap 151 and a second air gap 152. The first air gap 151 may be spaced apart from the second air gap 152 in the horizontal direction DR1.

[0083] The first air gap 151 can be an empty space surrounded by the upper surface of the first portion 321 of the contact plug 320, the first interlayer insulation layer 110, the first sidewall of the second portion 322 of the contact plug 320, and the second interlayer insulation layer 140. Furthermore, the second air gap 152 can be an empty space surrounded by the upper surface of the first portion 321 of the contact plug 320, the first interlayer insulation layer 110, the second sidewall of the second portion 322 of the contact plug 320, and the second interlayer insulation layer 140. Here, the second sidewall of the second portion 322 of the contact plug 320 refers to the sidewall opposite to the first sidewall of the second portion 322 of the contact plug 320.

[0084] The upper surface 151a of the air gap 150 may be formed to be lower than the upper surface 110a of the first interlayer insulating layer 110. Furthermore, the upper surface 151a of the air gap 150 may be formed to be lower than the upper surface of the second portion 322 of the contact plug 320. A portion of the sidewall of the second portion 322 of the contact plug 320 may contact the second interlayer insulating layer 140. However, this disclosure is not limited thereto.

[0085] The first wiring pattern 330 can be disposed on the upper surface of the second portion 322 of the contact plug 320. The inclined profile of the sidewall of the first wiring pattern 330 can be continuously formed with the inclined profile of the sidewall of the second portion 322 of the contact plug 320. The lower surface of the first wiring pattern 330 can be formed on the same plane as the lower surface of the second wiring pattern 135.

[0086] The first wiring pattern 330 may include a first barrier layer 331 and a first wiring layer 332. The first barrier layer 331 may form the lower surface of the first wiring pattern 330. The first barrier layer 331 may contact the upper surface of the second portion 322 of the contact plug 320. For example, the first barrier layer 331 may be conformally formed on the upper surface of the second portion 322 of the contact plug 320. The first wiring layer 332 may be disposed on the first barrier layer 331.

[0087] For example, the second wiring pattern 135 may be spaced apart from the first trench T1 by a first gap P1 in the horizontal direction DR1. The first height H1 from the upper surface of the first portion 321 of the contact plug 320 to the upper surface 110a of the first interlayer insulation layer 110 in the vertical direction DR2 may be greater than the first gap P1 between the first trench T1 and the second wiring pattern 135 in the horizontal direction DR1.

[0088] In the following text, reference will be made to Figure 6 Semiconductor devices according to some other embodiments of this disclosure are described. For ease of explanation, the description will primarily focus on... Figure 1 and Figure 2 The differences are shown in the semiconductor device.

[0089] Figure 6 This is a diagram used to explain a semiconductor device according to some other embodiments of the present disclosure.

[0090] Reference Figure 6 In some other embodiments of the semiconductor device according to this disclosure, the contact plug 420 may include a first portion 421 and a second portion 422 protruding from the first portion 421 in the vertical direction DR2. Each of the first portion 421 and the second portion 422 of the contact plug 420 may be disposed inside the first trench T1.

[0091] An air gap 450 may be formed on only one sidewall of the second portion 422 of the contact plug 420, between the upper surface of the first portion 421 of the contact plug 420 and the second interlayer insulating layer 140. An air gap 450 may also be formed on the first sidewall of the second portion 422 of the contact plug 420. An air gap 450 may also be formed between the first sidewall of the second portion 422 of the contact plug 420 and the first interlayer insulating layer 110. The second sidewall of the second portion 422 of the contact plug 420, opposite to the first sidewall, may contact the first interlayer insulating layer 110.

[0092] The air gap 450 can be an empty space surrounded by the upper surface of the first part 421 of the contact plug 420, the first interlayer insulation layer 110, the first sidewall of the second part 422 of the contact plug 420, and the second interlayer insulation layer 140.

[0093] although Figure 6 The second interlayer insulation layer 140 is shown not disposed between the second sidewall of the first wiring pattern 430 and the first interlayer insulation layer 110, but this disclosure is not limited thereto. In some other embodiments, the second interlayer insulation layer 140 may be disposed in a portion of the space between the second sidewall of the first wiring pattern 430 and the first interlayer insulation layer 110.

[0094] The upper surface of the air gap 450 may be formed to be lower than the upper surface 110a of the first interlayer insulation layer 110. Furthermore, the upper surface of the air gap 450 may be formed to be lower than the upper surface of the second portion 422 of the contact plug 420. A portion of the first sidewall of the second portion 422 of the contact plug 420 may contact the second interlayer insulation layer 140. However, this disclosure is not limited thereto.

[0095] The first wiring pattern 430 can be disposed on the upper surface of the second portion 422 of the contact plug 420. The inclined profile of the first sidewall of the first wiring pattern 430 can be continuously formed with the inclined profile of the first sidewall of the second portion 422 of the contact plug 420. The lower surface of the first wiring pattern 430 can be formed on the same plane as the lower surface of the second wiring pattern 135.

[0096] The first wiring pattern 430 may include a first barrier layer 431 and a first wiring layer 432. The first barrier layer 431 may form the lower surface of the first wiring pattern 430. The first barrier layer 431 may contact the upper surface of the second portion 422 of the contact plug 420. For example, the first barrier layer 431 may be conformally formed on the upper surface of the second portion 422 of the contact plug 420. The first wiring layer 432 may be disposed on the first barrier layer 431.

[0097] In the following text, reference will be made to Figure 7 and Figure 8 Semiconductor devices according to some other embodiments of this disclosure are described. For ease of explanation, the description will primarily focus on... Figure 1 and Figure 2 The differences are shown in the semiconductor device.

[0098] Figure 7 This is a diagram used to explain a semiconductor device according to some other embodiments of the present disclosure. Figure 8 yes Figure 7 A magnified view of region R3.

[0099] Reference Figure 7 and Figure 8 In some other embodiments of the semiconductor device according to the present disclosure, a third air gap 551 and a fourth air gap 552 may be formed on the upper surface of the via 570.

[0100] Via 570 may be disposed within the second trench T2. The upper surface of via 570 may be formed to be lower than the upper surface of the third interlayer insulating layer 160. For example, at least a portion of the third interlayer insulating layer 160 may be exposed to the second trench T2 on the upper surface of via 570.

[0101] The sidewalls of the third wiring pattern 590 can have a sloping profile. For example, the width of the third wiring pattern 590 in the horizontal direction DR1 can increase toward the via 570. After the third wiring pattern 590 is formed by the patterning process, a fourth interlayer insulating layer 180 can be formed. Therefore, the sloping profile of the sidewalls of the third wiring pattern 590 can be formed as described above.

[0102] The third wiring pattern 590 may include a second barrier layer 591 and a second wiring layer 592. The second barrier layer 591 may form the lower surface of the third wiring pattern 590. The second barrier layer 591 may contact the upper surface of the via 570. For example, the second barrier layer 591 may be conformally formed on the upper surface of the via 570.

[0103] In an example embodiment, the materials of the second barrier layer 591 and the second wiring layer 592 forming the third wiring pattern 590 may be the same as the materials of the second barrier layer 191 and the second wiring layer 192 forming the third wiring pattern 190 as described above.

[0104] The fourth wiring pattern 195 can be disposed on the upper surface 160a of the third interlayer insulation layer 160. The fourth wiring pattern 195 can be spaced apart from the third wiring pattern 590 in the horizontal direction DR1.

[0105] For example, the fourth wiring pattern 195 may be spaced apart from the second trench T2 by a second distance P2 in the horizontal direction DR1. The second height H2 from the upper surface of the via 570 to the upper surface 160a of the third interlayer insulating layer 160 in the vertical direction DR2 may be greater than the second distance P2 between the second trench T2 and the fourth wiring pattern 195 in the horizontal direction DR1.

[0106] Each of the third air gap 551 and the fourth air gap 552 may be formed inside the second trench T2 on the upper surface of the via 570. The third air gap 551 may be spaced apart from the fourth air gap 552 in the horizontal direction DR1. The third air gap 551 and the fourth air gap 552 may be formed between the upper surface of the via 570 and the fourth interlayer insulating layer 180 on the two sidewalls of the third wiring pattern 590.

[0107] For example, a third air gap 551 may be formed on a first sidewall of a third wiring pattern 590. A fourth air gap 552 may be formed on a second sidewall of a third wiring pattern 590 opposite to the first sidewall. For example, at least a portion of the third wiring pattern 590 may be disposed between the third air gap 551 and the fourth air gap 552.

[0108] The third air gap 551 can be an empty space surrounded by the upper surface of the via 570, the third interlayer insulation layer 160, the first sidewall of the third wiring pattern 590, and the fourth interlayer insulation layer 180. Furthermore, the fourth air gap 552 can be an empty space surrounded by the upper surface of the via 570, the third interlayer insulation layer 160, the second sidewall of the third wiring pattern 590, and the fourth interlayer insulation layer 180. Each of the upper surfaces 551a of the third air gap 551 and the fourth air gap 552 can be formed to be lower than the upper surface 160a of the third interlayer insulation layer 160.

[0109] In the following text, reference will be made to Figure 9 Semiconductor devices according to some other embodiments of this disclosure are described. For ease of explanation, the description will primarily focus on... Figure 7 and Figure 8 The differences are shown in the semiconductor device.

[0110] Figure 9 This is a diagram used to explain a semiconductor device according to some other embodiments of the present disclosure.

[0111] Reference Figure 9 In some other embodiments of the semiconductor device according to this disclosure, the third air gap 651 may be formed on only one sidewall of the third wiring pattern 690. Specifically, the third air gap 651 may be formed on the first sidewall of the third wiring pattern 690. The second sidewall of the third wiring pattern 690, opposite to the first sidewall, may contact the third interlayer insulating layer 160.

[0112] although Figure 9 The fourth interlayer insulation layer 180 is shown not disposed between the second sidewall of the third wiring pattern 690 and the third interlayer insulation layer 160, but this disclosure is not limited thereto. In some other embodiments, the fourth interlayer insulation layer 180 may be disposed in a portion of the space between the second sidewall of the third wiring pattern 690 and the third interlayer insulation layer 160.

[0113] The third wiring pattern 690 may include a second barrier layer 691 and a second wiring layer 692. The second barrier layer 691 may form a sidewall of the third wiring pattern 690 that contacts the third interlayer insulating layer 160 and a lower surface of the third wiring pattern 690 that contacts the via 570. The second barrier layer 691 may contact the upper surface of the via 570 and the third interlayer insulating layer 160. The second wiring layer 692 may be disposed on the second barrier layer 691.

[0114] In the following text, reference will be made to Figure 10 and Figure 11 Semiconductor devices according to some other embodiments of this disclosure are described. For ease of explanation, the description will primarily focus on... Figure 7 and Figure 8 The differences are shown in the semiconductor device.

[0115] Figure 10 This is a diagram used to explain a semiconductor device according to some other embodiments of the present disclosure. Figure 11 yes Figure 10 A magnified view of region R4.

[0116] Reference Figure 10 and Figure 11In a semiconductor device according to some other embodiments of the present disclosure, a via 770 may include a first portion 771 and a second portion 772 protruding from the first portion 771 in a vertical direction DR2. Each of the first portion 771 and the second portion 772 of the via 770 may be disposed inside a second trench T2.

[0117] The sidewall of the first portion 771 of the via 770 can contact the third interlayer insulating layer 160. The sidewall of the second portion 772 of the via 770 can be spaced apart from the third interlayer insulating layer 160.

[0118] The third air gap 551 and the fourth air gap 552 may be formed between the upper surface of the first portion 771 of the via 770 and the fourth interlayer insulating layer 180 on the two sidewalls of the second portion 772 of the via 770. For example, each of the third air gap 551 and the fourth air gap 552 may be formed between the two sidewalls of the second portion 772 of the via 770 and the third interlayer insulating layer 160.

[0119] The third air gap 551 can be an empty space surrounded by the upper surface of the first portion 771 of the via 770, the third interlayer insulation layer 160, the first sidewall of the second portion 772 of the via 770, and the fourth interlayer insulation layer 180. Furthermore, the fourth air gap 552 can be an empty space surrounded by the upper surface of the first portion 771 of the via 770, the third interlayer insulation layer 160, the second sidewall of the second portion 772 of the via 770, and the fourth interlayer insulation layer 180. Here, the second sidewall of the second portion 772 of the via 770 refers to the sidewall opposite to the first sidewall of the second portion 772 of the via 770.

[0120] Each of the upper surfaces 551a of the third air gap 551 and the fourth air gap 552 may be formed to be lower than the upper surface 160a of the third interlayer insulating layer 160. Furthermore, each of the upper surfaces 551a of the third air gap 551 and the fourth air gap 552 may be formed to be lower than the upper surface of the second portion 772 of the via 770. A portion of the sidewall of the second portion 772 of the via 770 may contact the fourth interlayer insulating layer 180. However, this disclosure is not limited thereto.

[0121] The third wiring pattern 790 can be disposed on the upper surface of the second portion 772 of the via 770. The inclined profile of the sidewall of the third wiring pattern 790 can be continuously formed with the inclined profile of the sidewall of the second portion 772 of the via 770. The lower surface of the third wiring pattern 790 can be formed on the same plane as the lower surface of the fourth wiring pattern 195.

[0122] The third wiring pattern 790 may include a second barrier layer 791 and a second wiring layer 792. The second barrier layer 791 may form the lower surface of the third wiring pattern 790. The second barrier layer 791 may contact the upper surface of the second portion 772 of the via 770. For example, the second barrier layer 791 may be conformally formed on the upper surface of the second portion 772 of the via 770. The second wiring layer 792 may be disposed on the second barrier layer 791.

[0123] In the following text, reference will be made to Figure 12 Semiconductor devices according to some other embodiments of this disclosure are described. For ease of explanation, the description will primarily focus on... Figure 7 and Figure 8 The differences are shown in the semiconductor device.

[0124] Figure 12 This is a diagram used to explain a semiconductor device according to some other embodiments of the present disclosure.

[0125] Reference Figure 12 In a semiconductor device according to some other embodiments of the present disclosure, via 870 may include a first portion 871 and a second portion 872 protruding from the first portion 871 in a vertical direction DR2. Each of the first portion 871 and the second portion 872 of via 870 may be disposed inside a second trench T2.

[0126] A third air gap 851 may be formed on only one sidewall of the second portion 872 of the via 870, between the upper surface of the first portion 871 of the via 870 and the fourth interlayer insulating layer 180. A third air gap 851 may also be formed on the first sidewall of the second portion 872 of the via 870. A third air gap 851 may also be formed between the first sidewall of the second portion 872 of the via 870 and the third interlayer insulating layer 160. The second sidewall of the second portion 872 of the via 870, opposite to the first sidewall, may contact the third interlayer insulating layer 160.

[0127] The third air gap 851 can be an empty space surrounded by the upper surface of the first part 871 of the via 870, the third interlayer insulation layer 160, the first sidewall of the second part 872 of the via 870, and the fourth interlayer insulation layer 180.

[0128] although Figure 12 The fourth interlayer insulation layer 180 is shown not disposed between the second sidewall of the third wiring pattern 890 and the third interlayer insulation layer 160, but this disclosure is not limited thereto. In some other embodiments, the fourth interlayer insulation layer 180 may be disposed in a portion of the space between the second sidewall of the third wiring pattern 890 and the third interlayer insulation layer 160.

[0129] The upper surface of the third air gap 851 may be formed to be lower than the upper surface of the third interlayer insulating layer 160. Furthermore, the upper surface of the third air gap 851 may be formed to be lower than the upper surface of the second portion 872 of the via 870. A portion of the first sidewall of the second portion 872 of the via 870 may contact the fourth interlayer insulating layer 180. However, this disclosure is not limited thereto.

[0130] The third wiring pattern 890 can be disposed on the upper surface of the second portion 872 of the via 870. The inclined profile of the first sidewall of the third wiring pattern 890 can be continuously formed with the inclined profile of the first sidewall of the second portion 872 of the via 870. The lower surface of the third wiring pattern 890 can be formed on the same plane as the lower surface of the fourth wiring pattern 195.

[0131] The third wiring pattern 890 may include a second barrier layer 891 and a second wiring layer 892. The second barrier layer 891 may form the lower surface of the third wiring pattern 890. The second barrier layer 891 may contact the upper surface of the second portion 872 of the via 870. For example, the second barrier layer 891 may be conformally formed on the upper surface of the second portion 872 of the via 870. The second wiring layer 892 may be disposed on the second barrier layer 891.

[0132] In an example embodiment, the materials of the second barrier layer 891 and the second wiring layer 892 forming the third wiring pattern 890 may be the same as the materials of the second barrier layer 591 and the second wiring layer 592 forming the third wiring pattern 590 as described above.

[0133] In the following text, reference will be made to Figure 1 , Figures 13 to 18 Methods for manufacturing a semiconductor device according to some embodiments of the present disclosure are described.

[0134] Figures 13 to 18 This is an intermediate stage diagram used to explain a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0135] Reference Figure 13 A first interlayer insulating layer 110 can be formed on the substrate 100. Subsequently, a first trench T1 extending in the vertical direction DR2 can be formed inside the first interlayer insulating layer 110. A portion of the substrate 100 can be exposed through the first trench T1.

[0136] Subsequently, a pre-contact plug 120P can be formed inside the first trench T1. For example, the pre-contact plug 120P can completely fill the first trench T1.

[0137] Reference Figure 14The upper portion of the pre-contact plug 120P can be completely etched. The portion of the pre-contact plug 120P retained inside the first trench T1 can form the contact plug 120. The upper surface of the contact plug 120 can be formed to be lower than the upper surface of the first interlayer insulating layer 110.

[0138] Reference Figure 15 A first barrier material layer 131M can be formed on the upper surface of the first interlayer insulating layer 110 and the upper surface of the contact plug 120. For example, the first barrier material layer 131M can be formed conformally. However, this disclosure is not limited thereto.

[0139] Subsequently, a first wiring material layer 132M can be formed on the first barrier material layer 131M. The first trench T1 can be completely filled by the contact plug 120, the first barrier material layer 131M, and the first wiring material layer 132M.

[0140] Reference Figure 16 A patterning process can be performed on the first barrier material layer 131M and the first wiring material layer 132M. Through the patterning process, a first wiring pattern 130 can be formed on the contact plug 120, and a second wiring pattern 135 can be formed on the first interlayer insulation layer 110.

[0141] A portion of the first wiring pattern 130 may be formed within the first trench T1. The second wiring pattern 135 may be spaced apart from the first wiring pattern 130 in the horizontal direction DR1. Each of the first wiring pattern 130 and the second wiring pattern 135 may include a first barrier layer 131 and a first wiring layer 132.

[0142] The second wiring pattern 135 can be spaced apart from the first trench T1 by a first spacing in the horizontal direction DR1. Figure 2 P1). On the upper surface of the contact plug 120 in the vertical direction DR2 ( Figure 2 (120a) to the upper surface of the first interlayer insulation layer 110 ( Figure 2 The first height of 110a) Figure 2 H1) can be greater than the first spacing between the first trench T1 and the second wiring pattern 135 in the horizontal direction DR1. Figure 2 (P1).

[0143] Reference Figure 17 A second interlayer insulating layer 140 may be formed on the first interlayer insulating layer 110. The second interlayer insulating layer 140 may surround a portion of the sidewall of the first wiring pattern 130 and the sidewall of the second wiring pattern 135. For example, the second interlayer insulating layer 140 may surround portions of two sidewalls of the first wiring pattern 130 and two sidewalls of the second wiring pattern 135.

[0144] In this configuration, air gaps 150 can be formed on the two sidewalls of the first wiring pattern 130 located inside the first trench T1. Specifically, a first air gap 151 can be formed inside the first trench T1 between the first sidewall 130s1 of the first wiring pattern 130 and the first interlayer insulation layer 110. A second air gap 152 can be formed inside the first trench T1 between the second sidewall 130s2 of the first wiring pattern 130 and the first interlayer insulation layer 110.

[0145] A portion of the second interlayer insulation layer 140 may be formed within the first trench T1. For example, the upper surface of the air gap 150 may be formed to be lower than the upper surface of the first interlayer insulation layer 110. However, this disclosure is not limited thereto.

[0146] Reference Figure 18 A third interlayer insulating layer 160 can be formed on the second interlayer insulating layer 140. Subsequently, a second trench T2 extending in the vertical direction DR2 can be formed inside the third interlayer insulating layer 160. For example, the second trench T2 can expose a portion of the upper surface of the first wiring pattern 130.

[0147] Subsequently, a via 170 can be formed inside the second trench T2. For example, the via 170 can completely fill the second trench T2.

[0148] Refer again Figure 1 A third wiring pattern 190 and a fourth wiring pattern 195 can be formed on the third interlayer insulating layer 160. For example, the third wiring pattern 190 and the fourth wiring pattern 195 can be formed by a patterning process. The width of each of the third wiring pattern 190 and the fourth wiring pattern 195 in the horizontal direction DR1 can increase toward the via 170 and the third interlayer insulating layer 160, respectively.

[0149] Subsequently, a fourth interlayer insulating layer 180 may be formed on the third interlayer insulating layer 160. The fourth interlayer insulating layer 180 may surround each of the sidewalls of the third wiring pattern 190 and the sidewalls of the fourth wiring pattern 195. For example, the fourth interlayer insulating layer 180 may surround both sidewalls of the third wiring pattern 190 and both sidewalls of the fourth wiring pattern 195.

[0150] In some other embodiments, the third wiring pattern 190 and the fourth wiring pattern 195 can also be formed by an inlay process. In this case, the width of each of the third wiring pattern 190 and the fourth wiring pattern 195 in the horizontal direction DR1 can be reduced toward the via 170 and the third interlayer insulating layer 160, respectively.

[0151] In the following text, reference will be made to Figure 4 , Figures 19 to 22Methods for manufacturing a semiconductor device according to some other embodiments of the present disclosure are described.

[0152] Figures 19 to 22 This is an intermediate stage diagram used to explain a method for manufacturing a semiconductor device according to some other embodiments of this disclosure.

[0153] Reference Figure 19 A first interlayer insulating layer 110 can be formed on the substrate 100. Subsequently, a first trench T1 extending in the vertical direction DR2 can be formed inside the first interlayer insulating layer 110. A portion of the substrate 100 can be exposed through the first trench T1.

[0154] Subsequently, a pre-contact plug 120P can be formed inside the first trench T1. For example, the pre-contact plug 120P can completely fill the first trench T1. Subsequently, a first barrier material layer 331M and a first wiring material layer 332M can be sequentially formed on the first interlayer insulation layer 110 and the pre-contact plug 120P.

[0155] Reference Figure 20 A patterning process can be performed on the first barrier material layer 331M and the first wiring material layer 332M. Through the patterning process, a first wiring pattern 330 can be formed on the pre-contact plug 120P, and a second wiring pattern 135 can be formed on the first interlayer insulation layer 110.

[0156] In addition, a portion of the upper part of the pre-contact plug 120P can be etched using a patterning process to form the contact plug 320.

[0157] The contact plug 320 may include a first portion 321 and a second portion 322 protruding from the first portion 321 along a vertical direction DR2. The portion of the pre-contact plug 120P that contacts the first interlayer insulating layer 110 can be etched using a patterning process to form the second portion 322 of the contact plug 320. The second portion 322 of the contact plug 320 may be spaced apart from the first interlayer insulating layer 110 in the horizontal direction DR1.

[0158] Reference Figure 21 A second interlayer insulating layer 140 may be formed on the first interlayer insulating layer 110. The second interlayer insulating layer 140 may surround the sidewalls of the first wiring pattern 330 and the sidewalls of the second wiring pattern 135. For example, the second interlayer insulating layer 140 may surround both sidewalls of the first wiring pattern 330 and both sidewalls of the second wiring pattern 135.

[0159] In this configuration, air gaps 150 can be formed on the two sidewalls of the second portion 322 of the contact plug 320 within the first groove T1. Specifically, a first air gap 151 can be formed between the first sidewall of the second portion 322 of the contact plug 320 and the first interlayer insulation layer 110 within the first groove T1. A second air gap 152 can be formed between the second sidewall of the second portion 322 of the contact plug 320 and the first interlayer insulation layer 110 within the first groove T1.

[0160] A portion of the second interlayer insulation layer 140 may be formed within the first trench T1. For example, the upper surface of the air gap 150 may be formed to be lower than the upper surface of the first interlayer insulation layer 110. However, this disclosure is not limited thereto.

[0161] Reference Figure 22 A third interlayer insulating layer 160 can be formed on the second interlayer insulating layer 140. Subsequently, a second trench T2 extending in the vertical direction DR2 can be formed inside the third interlayer insulating layer 160. For example, the second trench T2 can expose a portion of the upper surface of the first wiring pattern 330.

[0162] Subsequently, a via 170 can be formed inside the second trench T2. For example, the via 170 can completely fill the second trench T2.

[0163] Refer again Figure 4 A third wiring pattern 190 and a fourth wiring pattern 195 can be formed on the third interlayer insulating layer 160. For example, the third wiring pattern 190 and the fourth wiring pattern 195 can be formed by a patterning process. The width of each of the third wiring pattern 190 and the fourth wiring pattern 195 in the horizontal direction DR1 can increase toward the via 170 and the third interlayer insulating layer 160, respectively.

[0164] Subsequently, a fourth interlayer insulating layer 180 may be formed on the third interlayer insulating layer 160. The fourth interlayer insulating layer 180 may surround each of the sidewalls of the third wiring pattern 190 and the sidewalls of the fourth wiring pattern 195. For example, the fourth interlayer insulating layer 180 may surround both sidewalls of the third wiring pattern 190 and both sidewalls of the fourth wiring pattern 195.

[0165] In some other embodiments, the third wiring pattern 190 and the fourth wiring pattern 195 can also be formed by an inlay process. In this case, the width of each of the third wiring pattern 190 and the fourth wiring pattern 195 in the horizontal direction DR1 can be reduced toward the via 170 and the third interlayer insulating layer 160, respectively.

[0166] In summarizing the detailed description, those skilled in the art will understand that many variations and modifications can be made to the preferred embodiments without substantially departing from the principles of this disclosure. Therefore, it will be understood that the foregoing is illustrative of various exemplary embodiments and is not to be construed as limiting oneself to the specific exemplary embodiments disclosed, and that modifications to the disclosed exemplary embodiments and other exemplary embodiments are intended to be included within the scope of the appended claims.

Claims

1. A semiconductor device, the semiconductor device comprising: Base; The first interlayer insulation layer is disposed on the substrate; The first trench is formed inside the first interlayer insulation layer; The contact plug is located inside the first groove; The first wiring pattern is set on the contact plug; The second wiring pattern is disposed on the first interlayer insulation layer and is spaced apart from the first wiring pattern in the horizontal direction; A second interlayer insulation layer is disposed on the first interlayer insulation layer and surrounds at least a portion of each sidewall of the first wiring pattern and each sidewall of the second wiring pattern; as well as The first air gap is formed inside the first groove on the contact plug.

2. The semiconductor device according to claim 1, wherein, The first air gap is formed in the vertical direction on at least one of the sidewalls of the first wiring pattern between the contact plug and the second interlayer insulation layer.

3. The semiconductor device according to claim 2, wherein, The first air gap is formed on the first sidewall of the first wiring pattern, and The second sidewall of the first wiring pattern, which is opposite to the first sidewall of the first wiring pattern, is in contact with the first interlayer insulation layer.

4. The semiconductor device according to claim 1, wherein, The contact plug includes a first portion and a second portion protruding vertically from the first portion, and The first air gap is formed between the second part of the contact plug and the first interlayer insulation layer.

5. The semiconductor device according to claim 4, wherein, The first air gap is formed on the first sidewall of the second part of the contact plug, and In this context, the second sidewall of the second part of the contact plug, which is opposite to the first sidewall of the second part of the contact plug, is in contact with the first interlayer insulation layer.

6. The semiconductor device according to claim 1, wherein, The height from the upper surface of the contact plug to the upper surface of the first interlayer insulation layer is greater than the horizontal spacing between the first trench and the second wiring pattern.

7. The semiconductor device according to claim 1, wherein, The upper surface of the first air gap is formed to be lower than the upper surface of the first interlayer insulation layer.

8. The semiconductor device according to claim 1, wherein, The width of the first wiring pattern increases in the horizontal direction toward the contact plug.

9. The semiconductor device according to claim 1, further comprising: The third interlayer insulation layer is disposed on the second interlayer insulation layer; The second trench is formed inside the third interlayer insulation layer; A via is provided inside the second trench; The third wiring pattern is set on the via; The fourth wiring pattern is set on the third interlayer insulation layer and is spaced apart from the third wiring pattern in the horizontal direction; A fourth interlayer insulation layer is disposed on the third interlayer insulation layer and surrounds each sidewall of the third wiring pattern and each sidewall of the fourth wiring pattern; as well as The second air gap is formed inside the second groove on the via.

10. The semiconductor device according to claim 9, wherein, The second air gap is formed on at least one sidewall of the third wiring pattern and is located in the vertical direction between the via and the fourth interlayer insulation layer.

11. The semiconductor device according to claim 9, wherein, The via includes a first portion and a second portion protruding vertically from the first portion, and The second air gap is formed horizontally between the second part of the via and the third interlayer insulation layer.

12. The semiconductor device according to claim 9, wherein, The height from the top surface of the via to the top surface of the third interlayer insulation layer is greater than the horizontal spacing between the second trench and the fourth wiring pattern.

13. A semiconductor device, the semiconductor device comprising: Base; The first interlayer insulation layer is disposed on the substrate; The first trench is formed inside the first interlayer insulation layer; The contact plug is located inside the first groove; The first wiring pattern is set on the contact plug; The second wiring pattern is disposed on the first interlayer insulation layer and is spaced apart from the first wiring pattern in the horizontal direction; A second interlayer insulation layer is disposed on the first interlayer insulation layer and surrounds each sidewall of the first wiring pattern and each sidewall of the second wiring pattern; as well as The first air gap and the second air gap are formed inside the first groove on the contact plug and are spaced apart from each other in the horizontal direction. Wherein, the height from the upper surface of the contact plug to the upper surface of the first interlayer insulation layer is greater than the horizontal spacing between the first trench and the second wiring pattern, and The width of the first wiring pattern increases in the horizontal direction toward the contact plug.

14. The semiconductor device according to claim 13, wherein, At least a portion of the first wiring pattern is disposed between the first air gap and the second air gap.

15. The semiconductor device according to claim 13, wherein, The contact plug includes a first portion and a second portion protruding vertically from the first portion, and The second part of the contact plug is located between the first air gap and the second air gap.

16. The semiconductor device of claim 13, further comprising: The third interlayer insulation layer is disposed on the second interlayer insulation layer; The second trench is formed inside the third interlayer insulation layer; A via is provided inside the second trench; The third wiring pattern is set on the via; The fourth wiring pattern is set on the third interlayer insulation layer and is spaced apart from the third wiring pattern in the horizontal direction; A fourth interlayer insulation layer is disposed on the third interlayer insulation layer and surrounds each sidewall of the third wiring pattern and each sidewall of the fourth wiring pattern; as well as The third and fourth air gaps are formed inside the second groove on the via and are spaced apart from each other in the horizontal direction.

17. A method for manufacturing a semiconductor device, the method comprising: A first interlayer insulating layer, including trenches, is formed on the substrate; A contact plug is formed inside the trench; A first wiring pattern is formed on the contact plug; A second interlayer insulation layer is formed on the first interlayer insulation layer, surrounding the sidewalls of the first wiring pattern; An air gap is formed vertically inside the trench between the contact plug and the second interlayer insulation layer; as well as A third interlayer insulation layer is formed on the second interlayer insulation layer. The upper surface of the air gap is formed to be lower than the upper surface of the first interlayer insulation layer.

18. The method according to claim 17, wherein, The steps for forming the contact plug inside the trench include: Pre-contact plugs forming the interior of the filling groove; and The upper part of the pre-contact plug is completely etched to form a contact plug with an upper surface that is lower than the upper surface of the first interlayer insulation layer.

19. The method of claim 17, wherein, The steps for forming the contact plug inside the trench include: Pre-contact plugs forming the interior of the filling groove; and The step of forming a first wiring pattern on the contact plug includes etching the portion of the pre-contact plug that contacts the first interlayer insulating layer to form a contact plug comprising a first portion and a second portion protruding from the first portion in a vertical direction.

20. The method of claim 17, further comprising: A second wiring pattern, spaced horizontally from the first wiring pattern, is formed on the first interlayer insulating layer. The height from the upper surface of the contact plug to the upper surface of the first interlayer insulation layer is greater than the horizontal spacing between the trench and the second wiring pattern.

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