Method for manufacturing semiconductor device, semiconductor device, and memory system

Abstract

The application provides a semiconductor device manufacturing method, a semiconductor device and a memory system. The manufacturing method comprises: forming a first stop layer on a substrate; performing an oxidation resistance treatment on a surface of the first stop layer away from the substrate to form an oxidation resistance on the treated surface of the first stop layer; forming a stack layer on the first stop layer after the oxidation resistance treatment; forming a first channel hole penetrating through the stack layer along a thickness direction of the stack layer and extending into the substrate; performing an oxidation treatment on the first stop layer through the first channel hole to obtain a second channel hole; and forming a storage channel structure in the second channel hole, so that the stack layer can be prevented from generating a bulging phenomenon and an internal stress concentration phenomenon.

Description

[Technical Field]

[0001] This invention relates to the field of semiconductor technology, and more specifically to a method for manufacturing a semiconductor device, a semiconductor device, and a memory system. [Background Technology]

[0002] 3D memory is an emerging type of memory that overcomes the limitations of 2D or planar memory by stacking memory chips together. Unlike placing memory cells on a single surface, 3D memory technology vertically stacks multiple layers of memory cells. Based on this technology, storage devices with storage capacities several times greater than comparable memory technologies can be created. This technology allows for accommodating higher storage capacities in a smaller space, resulting in significant cost savings, reduced energy consumption, and substantial performance improvements.

[0003] In the fabrication of 3D memory, the fabrication of the memory channel structure becomes increasingly difficult as the number of stacked layers increases. During the fabrication of the memory channel structure, bulging of the stacked layers is prone to occur, affecting memory performance. [Summary of the Invention]

[0004] The present invention provides a method for manufacturing a semiconductor device, a semiconductor device and a memory system, which can reduce the bulging phenomenon of stacked layers and improve the performance of semiconductor devices.

[0005] On one hand, embodiments of this application provide a method for fabricating a semiconductor device, including:

[0006] A first stop layer is formed on the substrate;

[0007] The surface of the first stop layer facing away from the substrate is subjected to an antioxidant treatment to form antioxidants on the treated surface of the first stop layer;

[0008] A stacked layer is formed on the first stop layer after antioxidant treatment;

[0009] A first channel hole is formed that extends through the stacked layer along the thickness direction of the stacked layer and into the substrate;

[0010] The first stop layer is oxidized through the first channel hole to obtain the second channel hole;

[0011] A storage channel structure is formed in the second channel hole.

[0012] In some embodiments, the antioxidant treatment includes a nitrogen-containing surface treatment, wherein the antioxidant includes nitrides.

[0013] In some embodiments, prior to the step of forming a stacked layer on the first stop layer after the antioxidant treatment, the method further includes:

[0014] A spacer layer is formed on the first stop layer after antioxidant treatment;

[0015] A second stop layer is formed on the spacer layer, and the material of the first stop layer is different from the material of the second stop layer.

[0016] In some embodiments, the step of forming a second stop layer on the spacer layer further includes:

[0017] The surface of the second stop layer facing away from the substrate is subjected to an anti-oxidation treatment.

[0018] In some embodiments, the step of forming the first stop layer on the substrate further includes:

[0019] The first stop layer is doped.

[0020] In some embodiments, the material of the first stop layer and / or the second stop layer comprises polycrystalline silicon.

[0021] In some embodiments, the stacked layer includes a gate sacrificial layer, and after the step of forming the storage channel structure in the second via, the method further includes:

[0022] A gate line gap is formed, which penetrates the stacked layer along the thickness direction of the stacked layer and extends into the substrate;

[0023] Remove the gate sacrificial layer to obtain the gate void;

[0024] A gate structure is formed in the gate void, and a gate line slot structure is formed in the gate line slot.

[0025] In some implementations, the first stop layer and the substrate are in direct contact.

[0026] On the other hand, embodiments of this application also provide a semiconductor device, including:

[0027] Semiconductor structure;

[0028] A first stop layer is located on the semiconductor structure, and the surface of the first stop layer facing away from the semiconductor structure is covered with an antioxidant.

[0029] The stacked structure located on the first stop layer;

[0030] It extends through the stacked structure along the thickness direction and into the memory channel structure within the semiconductor structure.

[0031] In some embodiments, the semiconductor device further includes a spacer layer and a second stop layer disposed between the first stop layer and the stacked structure and stacked thereon, the spacer layer being disposed on the first stop layer and the second stop layer being disposed on the spacer layer, the material of the second stop layer being different from the material of the first stop layer.

[0032] In some embodiments, the surface of the second stop layer facing away from the semiconductor structure is covered with an antioxidant.

[0033] In some embodiments, the upper surface of the portion of the first stop layer that contacts the semiconductor structure is horizontal.

[0034] On the other hand, embodiments of this application also provide a memory system, the memory system including at least one of the above-described semiconductor devices and a controller coupled to the semiconductor device, the controller being used to control the semiconductor device to store data.

[0035] The semiconductor device fabrication method, semiconductor device, and memory system provided in this application embodiment involve forming a first stop layer on a substrate and performing an anti-oxidation treatment on the surface of the first stop layer away from the substrate. Then, a stacked layer is formed on the anti-oxidation treated first stop layer, and a first channel hole is formed extending through the stacked layer along its thickness direction into the substrate. Subsequently, the first stop layer is oxidized through the first channel hole to obtain a second channel hole, and a memory channel structure is formed in the second channel hole. This avoids warping of the first stop layer during oxidation, thereby not only releasing the etching load effect of the first channel hole but also preventing bulging and internal stress concentration in the stacked layer. [Attached Image Description]

[0036] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 This is a schematic flowchart of a method for fabricating a semiconductor device according to an embodiment of this application;

[0038] Figures 2a to 2f This is a cross-sectional view of the semiconductor device under different process steps in the manufacturing method provided in the embodiments of this application;

[0039] Figure 3 yes Figure 2d An enlarged schematic diagram of section M in the middle;

[0040] Figure 4a This is a cross-sectional view of another semiconductor device provided in an embodiment of this application;

[0041] Figure 4b yes Figure 4a An enlarged schematic diagram of part N in the middle;

[0042] Figure 5 This is a schematic diagram of the memory system provided in an embodiment of this application.

Detailed Implementation Methods

[0043] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be particularly noted that the following embodiments are for illustrative purposes only and do not limit the scope of the invention. Similarly, the following embodiments are only some, not all, embodiments of the present invention, and all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0044] In this description, it should be understood that the terms "center," "lateral," "upper," "lower," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first" or "second" may explicitly or implicitly include one or more of that feature.

[0045] In this description, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0046] Understandably, the meanings of “on”, “above”, and “above” in this text should be interpreted in the broadest sense, so that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0047] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments. Unless the context clearly indicates otherwise, the singular forms “a” and “an” as used herein are also intended to include the plural. “A plurality” means two or more. It should also be understood that the terms “comprising” and / or “including” as used herein specify the presence of the stated features, integers, steps, operations, units, and / or components, without excluding the presence or addition of one or more other features, integers, steps, operations, units, components, and / or combinations thereof.

[0048] This application provides a method for fabricating a semiconductor device, a semiconductor device, and a memory system.

[0049] Please see Figure 1 , Figure 1 This is a schematic flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this application. The semiconductor device can be an array wafer memory device or a device bonded to a CMOS peripheral circuit. The method for fabricating this semiconductor device includes the following steps S101-S106, wherein:

[0050] Step S101: Form a first stop layer on the substrate;

[0051] Step S102: Perform an anti-oxidation treatment on the surface of the first stop layer away from the substrate to form an antioxidant on the treated surface of the first stop layer;

[0052] Step S103: Form a stacked layer on the first stop layer after the antioxidant treatment;

[0053] Step S104: Form a first channel hole that extends through the stacked layer along the thickness direction of the stacked layer and into the substrate;

[0054] Step S105: Oxidize the first stop layer through the first channel hole to obtain the second channel hole;

[0055] Step S106: Form a storage channel structure in the second channel hole.

[0056] It should be understood that the steps shown in the above manufacturing method are not exclusive, and other steps may be performed before, after, or between any of the steps shown.

[0057] In this embodiment, by forming the first stop layer on the substrate, the lower surface of the first stop layer will not warp during subsequent oxidation processing (pre-sealing of the first channel via). By performing an anti-oxidation treatment on the surface of the first stop layer facing away from the substrate, the upper surface of the first stop layer will not be affected during subsequent oxidation processing and will not warp. In the subsequent oxidation process, water molecules can enter the first stop layer through its side surface, thereby oxidizing it and sealing the first channel via at that location. This not only releases the etching load effect of the first channel via but also prevents warping of the first stop layer, thus avoiding bulging of the stacked layers and improving the reliability of the semiconductor device.

[0058] Please see Figures 2a to 2f , Figures 2a to 2f This is a cross-sectional structural diagram of the semiconductor device 10 under different process steps in the above-described fabrication method. The following will combine... Figures 2a to 2f Further describe the above steps S101-S106, wherein:

[0059] Step S101: Form a first stop layer 12 on the substrate 11.

[0060] For example, in Figure 2a In this process, the first stop layer 12 is in direct contact with the substrate 11. The material of the substrate 11 may include at least one of single-crystal silicon (Si), single-crystal germanium (Ge), III-V compound semiconductor materials, II-VI compound semiconductor materials, or other semiconductor materials known in the art. The first stop layer 12 mainly serves as a sealing position when the first channel via is pre-sealed. Its material may include polycrystalline silicon, and may also include other materials that can undergo oxidation reactions but will not be removed during subsequent removal of oxides and nitrides. The first stop layer 12 may be formed on the substrate 11 using thin film deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0061] In some embodiments, to increase the oxidation rate of the first stop layer 12, the oxidation rate of the first stop layer 12 can be increased, for example by doping. In this case, step S101 may further include: performing a doping treatment on the first stop layer 12.

[0062] The doping can be p-type doping. The doping process can be ion implantation, and after doping, lattice damage caused by ion implantation can be repaired using processes such as laser annealing.

[0063] Step S102: Perform an anti-oxidation treatment on the surface of the first stop layer 12 that is away from the substrate 11 to form an antioxidant on the treated surface of the first stop layer 12.

[0064] Among them, the antioxidant treatment can be set according to the requirements. It is mainly used to form antioxidants on the treated surface, so that the treated surface is not affected or is minimally affected in subsequent oxidation processes.

[0065] In some embodiments, the antioxidant treatment includes a nitrogen-containing surface treatment to form nitrides on the treated surface. This nitrogen-containing surface treatment may include nitriding (NH3 treatment), a chemical thermal treatment process in which nitrogen atoms diffuse into the surface layer of a workpiece at a certain temperature in a certain medium. The material of the antioxidant depends on the specific process of the antioxidant treatment. For example, when the antioxidant treatment includes nitriding, the antioxidant includes nitrides, and when the material of the first stop layer 12 is polycrystalline silicon, the antioxidant is silicon nitride.

[0066] In some implementations, please refer to Figure 2b After step S102 above, the method for manufacturing the semiconductor device 10 may further include:

[0067] A spacer layer 13 is formed on the first stop layer 12 after the antioxidant treatment;

[0068] A second stop layer 14 is formed on the spacer layer 13, and the material of the first stop layer 12 is different from the material of the second stop layer 14.

[0069] The spacer layer 13 may be made of an oxide, such as silicon oxide, or a combination of oxides and nitrides, such as silicon oxide and silicon nitride. The material of the second stop layer 14 may be completely different from the material of the first stop layer 12, or partially different. For example, both may include polycrystalline silicon, but the first stop layer 12 and the second stop layer 14 may have different doped materials.

[0070] It should be noted that during the subsequent oxidation treatment of the first stop layer 12, the oxidation of the second stop layer 14 should be avoided as much as possible, so that it can serve as an etching stop layer when removing oxides and nitrides later. In some embodiments, this can be achieved by making the oxidation rate of the first stop layer 12 much greater than the oxidation rate of the second stop layer 14. In this way, when the first stop layer 12 is rapidly oxidized, the second stop layer 14 can be minimally oxidized, or even not oxidized at all. Specifically, the difference in oxidation rates between the two can be achieved through doping, for example, by doping the first stop layer 12 while leaving the second stop layer 14 undoped, or by applying different concentrations and types of doping to both.

[0071] In some embodiments, the second stop layer 14 may be further subjected to an antioxidant treatment to minimize the risk of warping during subsequent oxidation treatment. That is, the step of forming the second stop layer 14 on the spacer layer 13 may further include:

[0072] The surface of the second stop layer 14 facing away from the substrate 11 is subjected to an anti-oxidation treatment.

[0073] The second stop layer 14 and the first stop layer 12 can be treated with the same antioxidant treatment or with different antioxidant treatments; no restrictions are imposed here.

[0074] Step S103: Form a stacked layer 15 on the first stop layer 12 after the anti-oxidation treatment.

[0075] Among them, Figure 2c In this configuration, when the semiconductor device includes a second stop layer 14, a stacked layer 15 is located on the second stop layer 14. The stacked layer 15 may include a plurality of gate spacer layers 151 and gate sacrificial layers 152 stacked together, and may be formed using thin-film deposition processes such as CVD, PVD, ALD, or any combination thereof. The thicknesses of the plurality of gate spacer layers 151 may be the same or different, and the thicknesses of the plurality of gate sacrificial layers 152 may be the same or different. The material of the gate spacer layers 151 includes silicon oxide or other insulating materials, and the material of the gate sacrificial layers 152 includes silicon nitride.

[0076] It is easy to understand that different numbers of stacking layers in stacking layer 15 correspond to different stacking heights. For example, the number of stacking layers can be 8, 32, 64, 128, etc. The more stacking layers there are, the higher the integration and the more storage cells are formed. The number of stacking layers and the stacking height of stacking layer 15 can be designed according to actual storage needs. This application does not impose specific restrictions on this.

[0077] Step S104: Form a first channel hole q1 that extends through the stacked layer 15 along the thickness direction of the stacked layer 15 and into the substrate 11.

[0078] Among them, Figure 2c In the process, the first channel hole q1 can be formed using, for example, a dry / wet etching process.

[0079] Step S105: Oxidize the first stop layer 12 around the first channel hole q1 to obtain the second channel hole q2.

[0080] Among them, Figure 2dIn this context, the second channel hole q2 can be considered as the first channel hole q1 with a sealing effect due to the reduced aperture of the first channel hole q1 at the first stop layer 12. The first stop layer 12 can be oxidized via the first channel hole q1, thereby pre-sealing the first channel hole q1 at the first stop layer 12 and releasing the etching load effect of the first channel hole q1. This oxidation process can include wet oxidation, which refers to a redox reaction occurring in a liquid state under certain conditions, generally with water as the main carrier. Typically, after oxidizing the surrounding first stop layer 12 through the first channel hole q1, oxide O, such as silicon oxide, will be formed on the substrate 11 surface within the first channel hole q1 and within the first stop layer 12 surrounding the first channel hole q1. At this time, the first stop layer 12 can be considered to include the protruding portion protruding from the first channel hole q1, and the portion that directly contacts the substrate 11 (which can be considered as the non-protruding portion that does not protrude from the first channel hole q1).

[0081] It is easy to understand that since the oxidation rate of the first stop layer 12 is greater than that of the second stop layer 14, when the first stop layer 12 is oxidized through the first channel hole q1, the oxidation process time and selectivity can be controlled so that the first stop layer 12 around the first channel hole q1 is completely oxidized into oxide O, while only a very small amount of the second stop layer 14 is oxidized, or even not oxidized at all.

[0082] It should be emphasized that, in this embodiment, on the one hand, since the lower surface of the first stop layer 12 is located on the semiconductor substrate 11, and the semiconductor material has a relatively high density, water molecules are not easily able to enter or be easily deformed. Therefore, when water molecules enter the first stop layer 12 through the side surface of the first stop layer 12 in the first channel hole q1, please refer to... Figure 2d and Figure 3In this context, the x and -x directions are generally the extension directions of the gate line slots, the y and -y directions are generally the arrangement directions of the gate line slots, and the z direction is generally the thickness direction of the stacked layer 15. Although the first stop layer 12 will expand in volume along the -x and x directions, it is difficult for it to expand in volume along the -y direction. On the other hand, since the upper surface of the first stop layer 12 has undergone anti-oxidation treatment, it is difficult for the upper surface of the first stop layer 12 to oxidize, and thus it is also difficult for the first stop layer 12 to expand in volume along the y direction. It can be considered that the upper surface of the portion of the first stop layer 12 that is in direct contact with the substrate 11 is horizontal. This horizontality means that the projection of the upper surface in the longitudinal direction (y and -y directions) is approximately a straight line, that is, the fluctuation range of the projection in the longitudinal direction is within the error range. In other words, during the oxidation process, the interior of the first stop layer 12 will rapidly expand and deform along the -x and x directions, but it is difficult to expand and deform along the y and -y directions. Therefore, the first stop layer 12 will not warp due to expansion and deformation along the y or -y directions, thereby avoiding the bulging phenomenon of the stacked layer 15 due to the warping of the first stop layer 12, which would affect the normal progress of subsequent manufacturing processes.

[0083] For other implementations, please refer to Figure 4a and Figure 4b , Figure 4a A cross-sectional view of another semiconductor device 20 is shown. Figure 4b yes Figure 4aEnlarged schematic diagram at point N. The semiconductor device 20 includes a substrate 21, a first stop layer 22, a second stop layer 23, and a stacked layer 24 stacked sequentially. Spacer layers S are provided between the first stop layer 22 and the substrate 21, and between the first stop layer 22 and the second stop layer 23. The oxidation rate of the first stop layer 22 is greater than that of the second stop layer 23. The second channel hole and the first channel hole q1 penetrate the stacked layer 24 and extend into the substrate 21. When the first stop layer 22 is oxidized through the first channel hole q1 via the second channel hole, water molecules enter the first stop layer 22 and undergo oxidation reactions within the first stop layer 22, as well as on its upper and lower surfaces, generating oxide O. Since the first stop layer 22 is located between two spacer layers S, which are typically made of silicon oxide or silicon nitride, water molecules can easily enter. Therefore, during the oxidation reaction, the volume of the first stop layer 22 expands along the -x and x directions, and along the y and -y directions, thus pre-sealing the first channel hole q1 and solving the gouging problem commonly encountered during channel hole formation. However, the volume expansion of the first stop layer 22 in the y and -y directions causes warping, which not only leads to bulging in the stacked layer 24 but also causes localized stress concentration within the film layers of the stacked layer 24, affecting the normal progress of subsequent manufacturing processes. The method for manufacturing the semiconductor device 10 provided in this embodiment (i.e., steps S101-S106) can at least partially solve these technical problems.

[0084] Step S106: Form a storage channel structure 16 in the second channel hole q2.

[0085] Among them, Figure 2e In this configuration, the storage channel structure 16 may include a stacked storage functional layer 161, a channel layer 162, and an insulating layer 163. A thin-film deposition process, such as CVD, PVD, ALD, or any combination thereof, may be used to sequentially deposit a barrier layer, a charge trapping layer, a tunneling oxide layer (i.e., the storage functional layer 161), the channel layer 162, and an insulating material along the inner wall of the second channel via q2. The materials for the barrier layer, charge trapping layer, tunneling oxide layer, and channel layer 162 may be silicon oxide, silicon nitride, silicon oxide, and polysilicon, respectively, to form an "ONOP" structure. In some embodiments, the insulating material includes silicon oxide, and one or more air gaps may be formed during the insulating material filling process by controlling the channel filling process to alleviate structural stress.

[0086] Please see Figure 2fThe substrate 11 may include a core region AA and a step region SS. The core region AA may be located on both sides of the step region SS, or the step region SS may also be located on both sides of the core region AA; there is no specific limitation. The memory channel structure 16 is generally located in the core region AA and is mainly used to realize the memory function of the semiconductor device 10.

[0087] In some embodiments, after forming the storage channel structure 16, a dummy channel structure 17 may also be formed. The dummy channel structure 17 may be located in the step area SS and is mainly used to provide mechanical support. The storage channel structure 16 and the dummy channel structure 17 are arranged at intervals, and their number and arrangement can be determined according to the actual storage needs.

[0088] In some embodiments, the substrate 11 may further include a peripheral region BB. After forming the storage channel structure 16, a step structure may be formed in the step region SS, and a step-fill structure covering the step structure may be formed in the step region SS and the peripheral region BB. This step structure is the step-shaped structural portion of the stacked layer 15 after etching. Specifically, the step structure can be formed by etching the stacked layer 15 multiple times. Subsequently, deposition processes such as CVD, PVD, or plasma-assisted deposition processes, as well as planarization processes such as Chemical Mechanical Polishing (CMP), can be used to form the step-fill structure covering the step structure. The material of the step-fill structure mainly includes insulating materials such as silicon oxide.

[0089] In some embodiments, after forming the memory channel structure 16, it is also necessary to prepare a gate line gap for subsequent gate replacement, and perform gate replacement through the gate line gap, that is, in Figure 2f In addition to step S106, the method for manufacturing the semiconductor device 10 may further include:

[0090] A gate line slot is formed, which penetrates the stacked layer 15 along the thickness direction of the stacked layer 15 and extends into the substrate 11;

[0091] Remove the gate sacrificial layer 152 to obtain the gate void;

[0092] A gate structure 154 is formed in the gate gap, and a gate line gap structure 18 is formed in the gate line gap.

[0093] The stacked layer 15 after forming the gate structure 154 can be considered as the stacked structure 15' to distinguish the two. The depth of the gate gap within the substrate 11 can be the same as or different from that of the memory channel structure 16. The gate structure 154 may include a conductive material, such as any one or more combinations of tungsten, cobalt, copper, aluminum, doped crystalline silicon, or silicides, and the material of the gate gap structure 18 may include a conductive material or an insulating material. The gate sacrificial layer 152 in the stacked layer 15 can be removed using, for example, a dry / wet etching process to form the gate gap.

[0094] It is easy to understand that, under normal circumstances, Figure 2f The grid line slot structure 18 and the storage channel structure 16, as well as the grid line slot structure 18 and the dummy channel structure 17, are located at different cross-sections, which are represented by wavy lines to show them in the same cross-sectional view.

[0095] In some embodiments, a contact structure 19 may also be prepared in the peripheral region BB. The contact structure 19 may penetrate the step-filled structure and extend into the second stop layer 14. The material used to make the contact structure may include a metallic material, such as tungsten.

[0096] It should be noted that in this embodiment, the virtual channel structure 17, the grid line gap structure 18, and the contact structure 19 are usually fabricated after the storage channel structure 16. However, in other embodiments, their fabrication order can be determined according to process requirements, and no restrictions are imposed here.

[0097] In some embodiments, after forming the contact structure 19, a common source structure (not shown) electrically connected to the memory channel structure 16 can also be fabricated. Specifically, the substrate 11 can be removed first, and then nitrides and oxides (mainly removing the ONO structure in the memory channel structure 16) can be removed using the second stop layer 14 as the etching stop position to expose the channel layer 162 at the bottom of the memory channel structure 16. Then, a semiconductor layer is formed to encapsulate the exposed channel layer 162 as the common source structure. The material of the semiconductor layer includes polysilicon.

[0098] In summary, the semiconductor device 10 provided in this application embodiment forms a first stop layer 12 on a substrate 11 and performs an anti-oxidation treatment on the surface of the first stop layer 12 away from the substrate 11. Then, a stacked layer 15 is formed on the first stop layer 12 after the anti-oxidation treatment, and a first channel hole q1 is formed that penetrates the stacked layer 15 along the thickness direction of the stacked layer 15 and extends into the substrate 11. Then, the first stop layer 12 around the first channel hole q1 is oxidized to obtain a second channel hole q2, and a storage channel structure 16 is formed in the second channel hole q2. This can prevent the first stop layer 12 from warping when the first channel hole q1 is sealed in advance. This not only releases the etching load effect of the first channel hole q1, but also avoids bulging and internal stress concentration in the stacked layer 15, ensuring that the manufacturing process of the semiconductor device 10 can proceed normally and improving the reliability of the semiconductor device 10.

[0099] Based on the above-described method for fabricating semiconductor device 10, this application also provides a semiconductor device 10, which can be fabricated using any of the above-described methods. Please refer to [link to relevant documentation]. Figure 2f , Figure 2f This is a cross-sectional view of a semiconductor device 10 provided in an embodiment of this application. The semiconductor device 10 includes a semiconductor structure; a first stop layer 12 located on the semiconductor structure, the surface of the first stop layer 12 facing away from the semiconductor structure being covered with an antioxidant; a stacked structure 15' located on the first stop layer 12; and a memory channel structure 16 extending through the stacked structure 15' along the thickness direction of the stacked structure 15' and into the semiconductor structure.

[0100] In some embodiments, the semiconductor structure may be the substrate 11 described above, or it may be the semiconductor layer described above as a common source structure, depending on the actual manufacturing process.

[0101] In some embodiments, the upper surface of the portion of the first stop layer 12 that contacts the semiconductor structure is horizontal.

[0102] In some embodiments, the semiconductor device 10 may further include a spacer layer 13 and a second stop layer 14 stacked between the first stop layer 12 and the stacked structure 15', wherein the spacer layer 13 is located on the first stop layer 12 and the second stop layer 14 is located on the spacer layer 13, and the material of the first stop layer 12 is different from the material of the second stop layer 14.

[0103] In some embodiments, the surface of the second stop layer 14 facing away from the semiconductor structure is covered with an antioxidant. In some embodiments, the antioxidant is obtained by performing an antioxidant treatment on the surface of the first stop layer 12 facing away from the semiconductor structure. The antioxidant treatment is mainly used to ensure that the treated surface is unaffected or minimally affected during the oxidation process. The antioxidant treatment may include a nitrogen-containing surface treatment, such as nitriding, and the antioxidant may include a nitride.

[0104] In some embodiments, the stacked structure 15' further includes a step structure, and the semiconductor device 10 further includes a step-fill structure covering the step structure.

[0105] In some embodiments, the semiconductor device 10 may further include a dummy channel structure 17, a gate line gap structure 18, and a contact structure 19. The gate line gap structure 18 and the dummy channel structure 17 both penetrate the stacked structure 15' along the thickness direction of the stacked structure 15' and extend into the semiconductor structure. The contact structure 19 penetrates the step-filled structure along the thickness direction of the step-filled structure and extends into the second stop layer 14.

[0106] It should be understood that the structure and fabrication process of each component of the semiconductor device 10 in the embodiments of this application can be referred to the above-described embodiments of the semiconductor device fabrication method, and will not be repeated here.

[0107] Furthermore, embodiments of this application also provide a memory system. Please refer to [link to relevant documentation]. Figure 5 , Figure 5 This is a schematic diagram of the memory system provided in an embodiment of this application. The memory system 100 includes at least one of the aforementioned semiconductor devices 10 and a controller 30 electrically connected to the semiconductor device 10. The controller 30 is used to control the semiconductor device 10 to store data. The controller 30 is also connected to an external host, which can transmit user instructions and stored data to the controller 30. The user instructions may include write instructions, erase instructions, and read instructions, etc. The controller 30 can determine which storage location in the semiconductor device 10 to write, erase, and read based on these instructions.

[0108] In the examples of this application, the semiconductor device 10 is not limited to a three-dimensional NAND semiconductor device. Without departing from the disclosure or teachings of this application, the semiconductor device 10 may be implemented as other types of non-volatile semiconductor devices that can retain the stored data when the power is disconnected.

[0109] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A first stop layer is formed on the substrate; The surface of the first stop layer facing away from the substrate is subjected to an antioxidant treatment to form antioxidants on the treated surface of the first stop layer; A stacked layer is formed on the first stop layer after antioxidant treatment; A first channel hole is formed that extends through the stacked layer along the thickness direction of the stacked layer and into the substrate; The first stop layer is oxidized through the first channel hole to obtain the second channel hole; A storage channel structure is formed in the second channel hole.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The antioxidant treatment includes nitrogen-containing surface treatment, and the antioxidants include nitrides.

3. The method for fabricating a semiconductor device according to claim 1, characterized in that, Prior to the step of forming a stacked layer on the first stop layer after antioxidant treatment, the method further includes: A spacer layer is formed on the first stop layer after antioxidant treatment; A second stop layer is formed on the spacer layer, and the material of the first stop layer is different from the material of the second stop layer.

4. The method for fabricating a semiconductor device according to claim 3, characterized in that, The step of forming a second stop layer on the spacer layer further includes: The surface of the second stop layer facing away from the substrate is subjected to an anti-oxidation treatment.

5. The method for fabricating a semiconductor device according to claim 3, characterized in that, The step of forming the first stop layer on the substrate further includes: The first stop layer is doped.

6. The method for fabricating a semiconductor device according to claim 3, characterized in that, The material of the first stop layer and / or the second stop layer includes polycrystalline silicon.

7. The method for fabricating a semiconductor device according to claim 1, characterized in that, The stacked layer includes a gate sacrificial layer, and after the step of forming the storage channel structure in the second channel via, it further includes: A gate line gap is formed, which penetrates the stacked layer along the thickness direction of the stacked layer and extends into the substrate; Remove the gate sacrificial layer to obtain the gate void; A gate structure is formed in the gate void, and a gate line slot structure is formed in the gate line slot.

8. The method for fabricating a semiconductor device according to claim 1, characterized in that, The first stop layer is in direct contact with the substrate.

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