Three-dimensional memory and methods of making the same, memory systems

Abstract

The application provides a three-dimensional memory and a manufacturing method thereof. The three-dimensional memory comprises a dielectric structure of an alternating stack of a sacrificial layer and an insulating layer under a conductive structure of a step region, and no conductive material, so that even if a contact hole is etched through, no short circuit of a gate line is caused, the difficulty of forming the contact hole is reduced, and the performance of the three-dimensional memory is improved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and more particularly to a three-dimensional memory and its manufacturing method, and a storage system. Background Technology

[0002] With the development of integrated circuits, semiconductor memories need to have higher integration density. Traditional two-dimensional and planar semiconductor memories, limited by the properties of semiconductor materials, have reached a critical point in terms of storage density, and the quality of the products is also highly dependent on the masking process. Therefore, it is very difficult to increase the integration density.

[0003] Three-dimensional memory (3D NAND flash memory) has been increasingly widely used in electronic products due to its advantages such as low power consumption and high integration density. In 3D memory, such as NAND flash memory, the memory array can include a core region and a staircase structure (SS). The staircase structure provides contacts for leading out the gate lines from each layer of the memory array. In the manufacturing process of 3D memory, contact holes are etched into each stage of the staircase structure in the staircase region, and then conductive material is used to fill the contact holes to form contacts, thereby leading out the electrical signals of the gate lines.

[0004] In actual production, as the number of steps in 3D memory increases, the depth difference of the contact holes formed by each step also increases. During the contact hole etching step, due to the large depth difference, when the deepest contact hole (located in the lowest layer and closest to the substrate) is just etched to its position, the shallowest contact hole (located in the highest layer and furthest from the substrate) may experience punch-through, leading to a short circuit. To avoid over-etching of the shallowest contact hole, contact holes corresponding to different areas of the gate layer are usually etched in segments. This method requires multiple photolithography and etching steps, resulting in high costs and time, which seriously affects the mass production rate. Furthermore, the more layers of memory cells are stacked, the more photolithography and etching processes are required, and the higher the material costs become.

[0005] Therefore, how to avoid short circuits caused by etching through-through has become a technical problem that urgently needs to be solved. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a three-dimensional memory and a method for manufacturing the same, which can avoid short circuits caused by etching through-through.

[0007] To address the aforementioned problems, the present invention provides a method for manufacturing a three-dimensional memory, comprising: forming a stacked structure including stacked insulating layers and sacrificial layers, the stacked structure further comprising a step region, the step region including a first region and a second region arranged along a second direction, a plurality of steps being provided in the first region, each step extending along the second direction, and at each step, the upper surface of the sacrificial layer serving as the step top surface; forming a transition layer on the step top surface, the transition layers on different step top surfaces being insulated from each other; forming a cover layer above the step; removing the sacrificial layer of the second region and a portion of the sacrificial layer of the first region facing the second region to expose a portion of the lower surface of the transition layer; removing the transition layer to form a space between each step top surface and the cover layer; and filling the space with a conductive material to form a conductive structure on each step top surface.

[0008] In one embodiment, the transition layer is removed using an etching process.

[0009] In one embodiment, the etching process has a higher etching rate for the transition layer than for the sacrificial layer.

[0010] In one embodiment, the transition layer is a polycrystalline silicon layer.

[0011] In one embodiment, the step of forming a transition layer on the top surface of each step further includes: forming a transition material layer on the top surface and sidewall of each step; removing the transition material layer from the sidewall of each step, with the remaining transition material layer on the top surface of each step serving as the transition layer.

[0012] In one embodiment, during the step of removing the transition layer to form a space between the top surface of each step and the cover layer, the transition layer is partially retained on the side away from the second region, forming a spacer structure.

[0013] In one embodiment, the method further includes the following steps: forming a grid line gap in the stepped region, the grid line gap penetrating the stacked structure; removing the sacrificial layer of the second region, a portion of the sacrificial layer of the first region facing the second region, and the transition layer through the grid line gap.

[0014] In one embodiment, the step of removing the sacrificial layer of the second region, the portion of the sacrificial layer of the first region facing the second region, and the transition layer through the gate wire gap further includes: removing the sacrificial layer of the second region from the gate wire gap to form a trench; removing the portion of the sacrificial layer of the first region facing the second region from the trench to expose the lower surface of the transition layer portion; and removing the transition layer.

[0015] In one embodiment, the method further includes the following steps: filling the gaps in the grid lines with conductive material to form a conductive layer in the second region of the stepped region, forming a conductive structure in the first region of the stepped region, wherein the conductive layer extends to the first region and is electrically connected to a portion of the conductive structure.

[0016] In one embodiment, the method further includes the following steps: forming a contact hole penetrating the cover layer to the conductive structure; and filling the contact hole with a conductive material to form a conductive contact portion.

[0017] In one embodiment, the stacked structure further includes a core region, and the stepped region and the core region are arranged along a first direction. The method further includes the following steps: forming a gate line slot in the core region, the gate line slot penetrating the stacked structure; removing the sacrificial layer of the core region through the gate line slot; and filling the gate line slot with a conductive material to form a gate line in the core region.

[0018] This application embodiment also provides a three-dimensional memory, including a stepped region, the stepped region including a first region and a second region arranged along a second direction; the first region includes: a first stacked structure including a stacked first insulating layer and a sacrificial layer, the first stacked structure including a plurality of steps, the steps extending along the second direction, the upper surface of the sacrificial layer serving as the top surface of the steps; a conductive structure disposed on the top surface of the steps, the conductive structures on different top surfaces of the steps being insulated from each other; a cover layer covering the top of the steps; a contact portion penetrating the cover layer to the conductive structure and having conductivity; the second region includes: a second stacked structure including a stacked second insulating layer and a conductive layer, the conductive layer extending to a predetermined position in the first region and connected to a portion of the conductive structure.

[0019] In one embodiment, the system further includes a core region, wherein the stepped region and the core region are arranged along a first direction, and the core region includes a third stacked structure, wherein the third stacked structure includes a stacked third insulating layer and a gate line, and the gate line is connected to the conductive layer.

[0020] In one embodiment, the first insulating layer, the second insulating layer, and the third insulating layer are on the same layer, as are the sacrificial layer, the gate line, and the conductive layer. On the side of the first region facing the second region, in the direction of stacking of the first stacked structure, the conductive layer partially overlaps with the conductive structure.

[0021] In one embodiment, the conductive layer is connected to the sacrificial layer.

[0022] In one embodiment, the contact portion is misaligned with the conductive layer extending into the first region in the direction of stacking of the first stacked structure.

[0023] In one embodiment, the length of the overlapping region between the conductive layer and the conductive structure is 50–100 nm.

[0024] In one embodiment, in the stepped area, a grid line slot structure is provided on the side of the second region away from the first region.

[0025] In one embodiment, a grid line slot structure is provided on both sides of the core area.

[0026] In one embodiment, in the step area, on the side of the first region away from the second region, the top surface of the step is provided with a spacing structure.

[0027] In one embodiment, the three-dimensional memory includes a plurality of storage blocks arranged along a second direction, each storage block including a first region and a second region, and the first and second regions of adjacent storage blocks are arranged symmetrically about the boundary of the storage blocks.

[0028] In one embodiment, when the first regions of the step areas of two adjacent memory blocks are set close together, the two adjacent memory blocks share the same spacing structure in the step area.

[0029] In one embodiment, when the second regions of two adjacent memory blocks are positioned close together, the two adjacent memory blocks share the same gate slot structure in the stepped region.

[0030] This application also provides a storage system including a three-dimensional memory and a controller as described above, wherein the controller is coupled to the three-dimensional memory and is used to control the storage of data in the three-dimensional memory.

[0031] In this embodiment of the invention, the conductive structure is located only on the top surface of the step, and below it is an insulating structure with sacrificial and insulating layers stacked alternately. There are no gate lines or conductive layers. Therefore, even if the contact hole is etched through during subsequent contact hole formation, it will not cause a short circuit in the gate line, which reduces the difficulty of contact hole formation and improves the performance of the three-dimensional memory. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of the existing three-dimensional memory step region;

[0033] Figure 2 This is a schematic diagram of the steps of a three-dimensional memory manufacturing method provided in an embodiment of the present invention;

[0034] Figures 3-34 This is a partial schematic diagram of a semiconductor structure formed by some steps of a method for manufacturing a three-dimensional memory according to an embodiment of the present invention.

[0035] Figure 35This is a top view of the structure of a three-dimensional memory provided in another embodiment of the present invention. Detailed Implementation

[0036] As described in the background section, the number of steps in a three-dimensional memory is constantly increasing, and the depth difference of the contact holes formed by each step is also constantly increasing. Figure 1 As shown, this is a schematic diagram of the stepped region structure of an existing three-dimensional memory. When the contact hole 100A at the deepest point (the step located at the bottom layer and close to the substrate) is just etched to the point where it exposes its corresponding gate line 110A, the contact hole 100B at the shallowest point (the step located at the top layer and far from the substrate) may be etched through. That is, the contact hole 100B is etched through its corresponding gate line 110B, and may even reach the next layer gate line 110C. In this case, when conductive material is deposited in the contact hole to form a contact portion, the contact portion formed in the contact hole 100B will connect the gate line 110B and the gate line 110C, causing a short circuit.

[0037] In view of the above reasons, the present invention provides a three-dimensional memory and a method for fabricating the same. The three-dimensional memory and its fabrication method of the present invention can avoid short circuits caused by contact hole etching through-holes, thus greatly improving the performance of the three-dimensional memory.

[0038] The three-dimensional memory manufacturing method of the present invention can form a conductive structure on the top surface of the step. Each conductive structure is underlaid with a stacked insulating layer and a sacrificial layer. Therefore, even if the contact hole is etched through during the etching process, it will not cause problems such as... Figure 1 The gate line short circuit shown improves the performance of the 3D memory.

[0039] The embodiments of the three-dimensional memory and its manufacturing method provided by the present invention will be described in detail below with reference to the accompanying drawings.

[0040] Figure 2 This is a schematic diagram illustrating the steps of a three-dimensional memory manufacturing method according to an embodiment of the present invention. Please refer to [link / reference]. Figure 2The method for manufacturing the three-dimensional memory includes: step S20, forming a stacked structure, the stacked structure including stacked insulating layers and sacrificial layers, the stacked structure further including a step region, the step region including a first region and a second region arranged along a second direction, a plurality of steps being provided in the first region, and each step extending along the second direction, the upper surface of the sacrificial layer serving as the top surface of the step at each step; step S21, forming a transition layer at the top surface of the step, the transition layers at different top surfaces of the steps being insulated from each other; step S22, forming a cover layer above the step; step S23, removing the sacrificial layer of the second region and a portion of the sacrificial layer of the first region facing the second region to expose a portion of the lower surface of the transition layer; step S24, removing the transition layer to form a space between each top surface of the step and the cover layer; step S25, filling the space with conductive material to form a conductive structure at each top surface of the step.

[0041] Figures 3-34 This is a partial schematic diagram of a semiconductor structure formed by some steps of a method for manufacturing a three-dimensional memory according to an embodiment of the present invention. The following will be combined with... Figures 2 to 34 The specific processes for each step in the manufacturing method of the above-mentioned three-dimensional memory are explained in detail.

[0042] Please refer to step S20. Figure 3 , Figure 4 Figure 5 and Figure 6 ,in, Figure 3 This is a top view. Figure 4 Including along Figure 3 Schematic diagram of the cross section of line AA in the middle. Figure 5 along Figure 3 Schematic diagram of the cross section of the BB line. Figure 6 For along Figure 3 A cross-sectional schematic diagram of the CC line shows a stacked structure 310, which includes a stacked insulating layer 311 and a sacrificial layer 312.

[0043] In this embodiment, the stacking structure 310 is divided along a first direction (e.g., Figure 3 The three-dimensional memory consists of a core region AA and a stepped region SS arranged in the X-direction. The core region AA provides the storage array for the three-dimensional memory, and the stepped region SS provides the contact portions for leading out the gate layers in each layer of the storage array. The stepped region SS may be located on one side of the core region AA or between two core regions AA. In this embodiment, the example is that the stepped region SS is located on one side of the core region AA.

[0044] Furthermore, in this embodiment, the step region SS includes areas along the second direction (e.g., Figure 3The first region SS1 and the second region SS2 are arranged in the Y direction. Multiple steps 320 are provided in the first region SS1, and each step 320 is arranged along the second direction (e.g., in the Y direction). Figure 3 Extending in the Y direction, multiple steps 320 are arranged sequentially along the first direction (X direction), and at each step 320, the upper surface of the sacrificial layer 312 serves as the top surface of the step.

[0045] This embodiment provides a method for forming the stacked structure 310. Specifically, the method includes the following steps:

[0046] Alternating layers of sacrificial layer 312 and insulating layer 311 are formed on substrate 300. The alternating stacking of sacrificial layer 312 and insulating layer 311 means that after forming a sacrificial layer 312, an insulating layer 311 is formed on the surface of the sacrificial layer 312, and then the steps of forming sacrificial layer 312 and insulating layer 311 on the sacrificial layer 312 are repeated sequentially. In this embodiment, the lowest layer is the sacrificial layer 312, that is, the sacrificial layer 312 is disposed on substrate 300, and the highest layer is the insulating layer 311.

[0047] The substrate 300 can be made of single-crystal silicon (Si), single-crystal germanium (Ge), or silicon-germanium (GeSi), or silicon carbide (SiC); it can also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or other materials, such as gallium arsenide or other III-V compounds. In this embodiment, the substrate 300 is made of single-crystal silicon (Si). The insulating layer 311 can be made of silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide nitride, and the sacrificial layer 312 can be made of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, amorphous silicon, amorphous carbon, or polycrystalline silicon. In this embodiment, the insulating layer 311 is made of silicon oxide, and the sacrificial layer 312 is made of silicon nitride. The insulating layer 311 and the sacrificial layer 312 are formed using a chemical vapor deposition process.

[0048] In the first region SS1 (e.g.) Figure 3 , Figure 5 and Figure 6 As shown, the sacrificial layer 312 and the insulating layer 311 are patterned to form steps 320, at least a portion of the upper surface of the sacrificial layer 312 is exposed at each step 320. The sacrificial layer 312 and the insulating layer 311 can be subjected to repeated etch-trimming processes to form multiple steps 320 in the first region SS1. In this embodiment, the second region SS2 is not patterned; that is, the second region SS2 does not include steps.

[0049] Furthermore, in this embodiment, each step 320 comprises only one layer, which consists of an insulating layer 311 and a sacrificial layer 312 below it. However, in other embodiments of the invention, each step 320 may also comprise two or more layers, with at least a portion of the upper surface of the top sacrificial layer exposed. For example, in some embodiments, the step comprises two layers, each consisting of an insulating layer and a sacrificial layer below it, with at least a portion of the upper surface of the top sacrificial layer exposed. It is understood that, depending on the design of the three-dimensional memory, different steps may comprise the same or different layers.

[0050] The method for forming the stacked structure 310 described above is only one example provided by the present invention. It is understood that other known methods may also be used to form the stacked structure 310, and the present invention does not limit this.

[0051] Please continue to step S21, where a transition layer 330 is formed on the top surface of the step, and the transition layers 330 on different top surfaces of the steps are insulated from each other. The upper surface of the sacrificial layer 312 is the top surface of the step, and this step forms the transition layer 330 on the upper surface of the sacrificial layer 312. The transition layers 330 on the top surfaces of different steps 320 are insulated from each other.

[0052] Specifically, in this embodiment, the method for forming the transition layer 330 includes the following steps:

[0053] Please see Figure 7 , Figure 8 , Figure 9 and Figure 10 ,in, Figure 7 This is a top view. Figure 8 For along Figure 7 Schematic diagram of the cross section of line AA in the middle. Figure 9 For along Figure 7 Schematic diagram of the cross section of the BB line. Figure 10 For along Figure 7 A cross-sectional schematic diagram of the CC line shows a transition material layer 400 formed on the top surface and sidewalls of each step 320. In this step, the transition material layer 400 covers not only the upper surface of the exposed sacrificial layer 312 of each step 320, but also the sidewalls of each step 320. The sidewalls of the step 320 include the sidewalls of the insulating layer 311 and the sacrificial layer 312 exposed on the side of each step. In this embodiment, due to semiconductor process limitations, the transition layer material 400 covers not only the first region SS1 of the step region, but also the second region SS2 of the step region and the core region AA. In other embodiments, the transition layer material 400 may only cover the first region SS1 of the step region.

[0054] In some embodiments of the present invention, a transition material layer 400 may be formed on the top surface and sidewalls of each step 320 by one or more deposition processes, including but not limited to atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), or any combination thereof. For example, the transition material layer 400 may be formed by an atomic layer deposition process.

[0055] Please see Figure 11 , Figure 12 , Figure 13 and Figure 14 ,in, Figure 11 This is a top view. Figure 12 For along Figure 11 Schematic diagram of the cross section of line AA in the middle. Figure 13 For along Figure 11 Schematic diagram of the cross section of the BB line. Figure 14 For along Figure 11 A cross-sectional diagram of the CC line shows the transition material layer 400 removed, with the transition material layer on the top surface of each step 320 retained as the transition layer 330. In this step, after removing the transition material layer 400, the transition material layers 400 on the top surfaces of adjacent steps 320 are truncated and separated, forming unconnected transition layers 330. The transition layers 330 on the top surfaces of different steps 330 are insulated from each other to prevent subsequent short circuits.

[0056] After this step, a gap exists between the transition layer 330 and the sidewall of the step 320. Furthermore, in this embodiment, the side of the transition layer 330 facing the second region SS2 is spaced from the insulating layer 311 of the second region SS2.

[0057] In some embodiments, when the transition material layer 400 on the sidewall of each step 320 is removed, the transition material layer 400 on the top surface of the step 320 may also be thinned due to the removal method. Therefore, the thickness of the final transition layer 330 on the top surface of the step 320 may be less than the thickness of the transition material layer 400 on the top surface of the step 320.

[0058] In some embodiments, the method for removing the transition material layer 400 from the sidewall of each step 320 includes, but is not limited to, dry etching or wet etching.

[0059] Please refer to step S22 and Figure 15 , Figure 16 , Figure 17 , Figure 18 ,in, Figure 15 This is a top view. Figure 16 For along Figure 15 Schematic diagram of the cross section of line AA in the middle. Figure 17 For along Figure 15 Schematic diagram of the cross section of the BB line. Figure 18 For along Figure 15 A cross-sectional schematic diagram of the CC line shows a covering layer 340 formed above the step 320.

[0060] The covering layer 340 not only covers the transition layer 330 on the top surface of the step 320, but also fills the gap between the transition layer 330 and the sidewall of the step 320. In this embodiment, the covering layer 340 covers not only the step area SS, but also the core area AA. In other embodiments, the covering layer 340 may also cover the step area SS and part of the core area AA, or only the step area SS.

[0061] In some embodiments, the capping layer 340 may be formed by atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), or any combination thereof. For example, in this embodiment, the capping layer 340 is formed using chemical vapor deposition.

[0062] In some embodiments, the material of the capping layer 340 may be one of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide nitride. For example, in this embodiment, the material of the capping layer 340 is silicon oxide.

[0063] Please refer to step S23, remove the sacrificial layer of the second region SS2 and a portion of the sacrificial layer 312 of the first region SS1 facing the second region SS2 to expose a portion of the lower surface of the transition layer 330.

[0064] In this embodiment, please refer to Figure 19 This is a top view schematic diagram, showing a grid line gap 360 that penetrates the stacked structure 310. Figure 19 In the diagram, the step 320 is obscured by the covering layer 340, therefore, the step 320 is drawn with a dashed line.

[0065] In this embodiment, grid line slots 360 are formed in both the stepped region SS and the core region AA. In the stepped region SS, the grid line slots 360 are located on the side of the second region SS2 away from the first region SS1, and no grid line slots are provided on the side of the first region SS1. In some embodiments, the grid line slot located in the second region SS2 is connected to the grid line slot located in the core region AA, that is, they are the same grid line slot.

[0066] The manufacturing method includes: (see details) Figure 20 , Figure 21 and Figure 22 , Figure 20 It is along Figure 19Schematic diagram of the cross section of line AA in the middle. Figure 21 It is along Figure 19 Schematic diagram of the cross section of the BB line. Figure 22 It is along Figure 19 A cross-sectional schematic diagram of the CC line shows that in the core region AA, the sacrificial layer 312 is removed through the grid line slot 360 located in the core region AA to form a first trench 460. In the step region SS, the sacrificial layer 312 of the second region is removed through the grid line slot 360 located in the step region SS to form a second trench 470. A portion of the sacrificial layer 312 of the first region SS1 adjacent to the second region SS2 is removed from the second trench 470 to expose a portion of the lower surface of the transition layer 330. That is, a portion of the sacrificial layer 312 below the transition layer 330 is removed, while another portion of the sacrificial layer 312 below the transition layer 330 is retained.

[0067] Please refer to step S24 to remove the transition layer 330 (illustrated in...). Figure 21 This creates a space 350 between the top surface of each step 320 and the covering layer 340. Specifically, the space 350 is formed between the sacrificial layer 312 and the covering layer 340.

[0068] In this embodiment, the transition layer 330 is made of a different material than the sacrificial layer 312. Therefore, during the process of removing the transition layer 330, the etching rate of the etchant on the transition layer 330 can be greater than that on the sacrificial layer 312, allowing for selective removal of the transition layer 330 while retaining the sacrificial layer 312. For example, in this embodiment, the transition layer 330 is a polysilicon layer and the sacrificial layer 312 is a silicon nitride layer. In this case, during the subsequent removal of the transition layer 330, an etchant with a higher etching rate for polysilicon than for silicon nitride can be selected, thereby preventing the sacrificial layer 312 from being removed during the removal of the transition layer 330.

[0069] Specifically, please refer to Figure 23 , Figure 24 , Figure 25 , Figure 26 ,in, Figure 23 This is a top view. Figure 24 For along Figure 23 Schematic diagram of the cross section of line AA in the middle. Figure 25 For along Figure 23 Schematic diagram of the cross section of the BB line. Figure 26 For along Figure 23A cross-sectional schematic diagram of the CC line. The transition layer 330 is removed through the gap formed after removing the sacrificial layer 312, forming the space 350. During the process, the amount of sacrificial layer 312 removed below the transition layer 330 can be controlled to avoid excessive removal of the sacrificial layer 312, which could cause subsequent contact portions to become electrically connected to other layers.

[0070] In some embodiments, on the side of the transition layer 330 away from the second region SS2, the transition layer 330 is partially retained to form a spacer structure 313. That is, the transition layer 330 is not completely removed, and the remaining portion forms the spacer structure 313. The spacer structure 313 can be used as a separator structure between adjacent memory blocks.

[0071] In this embodiment of the invention, in the first region SS1 of the stepped area, the sacrificial layer 312 below the transition layer 330 is partially removed so that the transition layer 330 can be further removed using the grid line gap 360 on the side of the second region SS2. The other part of the sacrificial layer 312 below the transition layer 330 does not need to be removed. Therefore, in the stepped area SS, the grid line gap 360 can be provided only on the side of the second region SS2, and no grid line gap is provided on the side of the first region SS1. This greatly simplifies the process, saves costs, and can also further avoid the collapse of the stepped area due to the presence of the grid line gap.

[0072] Please refer to step S24, where conductive material is filled into the space 350 to form a conductive structure 370 on the top surface of each step 320.

[0073] In this step, the grid gaps can be used as windows to deposit conductive material, forming the conductive structure 370. Furthermore, in this step, the space formed after removing the sacrificial layer in the core region AA and the second region SS2 of the step region is also filled with conductive material. For details, please refer to... Figure 27 , Figure 28 , Figure 29 and Figure 30 ,in, Figure 28 For along Figure 27 A cross-sectional diagram at the location indicated by line AA. Figure 29 For along Figure 27 A cross-sectional diagram at the location indicated by line BB in the middle. Figure 30 For along Figure 27A cross-sectional schematic diagram at the position shown by the CC line shows that the core region AA is filled with conductive material to form a gate line 380, and the second region SS2 of the stepped region is filled with conductive material to form a conductive layer 390. The conductive layer 390 extends to the bottom of the conductive structure 370 in the first region and is connected to a portion of the conductive structure 370, so that the conductive structure 370 is electrically connected to the gate line 380 through the conductive layer 390.

[0074] In the semiconductor structure formed in this step, the conductive structure 370 is only located on the top surface of step 320, and below it is an insulating structure with sacrificial layer 312 and insulating layer 311 stacked alternately. There are no gate lines or conductive layers. Therefore, even if the contact hole is etched through during subsequent contact hole formation, it will not cause problems such as... Figure 1 The short-circuit condition shown reduces the difficulty of forming contact holes and improves the performance of the 3D memory.

[0075] Furthermore, in some embodiments of the present invention, the method for manufacturing the three-dimensional memory further includes the following steps:

[0076] Please see Figure 31 , Figure 32 , Figure 33 and Figure 34 ,in, Figure 31 This is a top view. Figure 32 For along Figure 31 A cross-sectional diagram at the location indicated by line AA. Figure 33 For along Figure 31 A cross-sectional diagram at the location indicated by line BB in the middle. Figure 34 For along Figure 31 A cross-sectional view at the location indicated by line CC shows a contact hole (not shown in the figure) penetrating the cover layer 340 to the conductive structure 370. In some embodiments, the contact hole can be formed first by photolithography and etching processes; a conductive material is then filled into the contact hole to form a conductive contact portion 410. For example, a conductive material such as titanium nitride or tungsten alloy is filled into the contact hole to form the contact portion 410. The contact portion 410 is electrically connected to the conductive structure 370 of the corresponding layer, and the conductive structure 370 is electrically connected to the gate line 380, thereby leading out the current of the gate line 380. In the stacking direction of the first stacked structure 440, the contact portion 410 is misaligned with the conductive layer 390 extending to the first region SS1, that is, there is no conductive layer 390 below the contact portion 410, so that even when the contact portion 410 penetrates the conductive structure 370, the contact portion 410 will not be electrically connected to the conductive layer 390.

[0077] The contact hole needs to extend to the top surface of the conductive structure 370 of the corresponding layer so that the contact portion 410 can be electrically connected to the conductive structure 370 of the corresponding layer. Even if etching occurs during the formation of the contact hole, causing the contact portion 410 formed in the contact 410 to extend into the conductive structure 370 or even through the conductive structure 370 to the underlying insulating layer or sacrificial layer, the contact portion 410 will only be electrically connected to the conductive structure 370 of the corresponding layer, and will not be electrically connected to the conductive structure 370, conductive layer 390, or gate line 380 of other layers, effectively avoiding gate line electrical connections between different layers and greatly improving the stability of the memory. In some embodiments of the present invention, in the first region SS1 of the step region, since part of the sacrificial layer 312 is not removed, the risk of the step region collapsing is reduced, and in subsequent steps, it is not necessary to form a pseudo-channel for supporting the step region, further simplifying the process.

[0078] Some embodiments of the present invention also provide a three-dimensional memory formed using the manufacturing method described above. Please refer to... Figures 3-34 The three-dimensional memory includes a stepped region SS, the stepped region SS including a region along a second direction (e.g., Figure 3 The first region SS1 and the second region SS2 are arranged in the X direction.

[0079] The first region SS1 includes a first stacked structure 430, a conductive structure 370, a cover layer 340, and a contact portion 410.

[0080] The first stacked structure 430 includes stacked first insulating layers (such as...) Figure 5 The first stacked structure 430 includes an insulating layer 311 and a sacrificial layer 312. The first stacked structure 430 includes a plurality of steps 320, the steps 320 being along the second direction (e.g., the insulating layer 311 shown) and the sacrificial layer 312. Figure 3 Extending in the Y direction, the upper surface of the sacrificial layer 312 serves as the top surface of the step. Further, in this embodiment, each step 320 comprises only one layer, consisting of an insulating layer 311 and a sacrificial layer 312 below it. In other embodiments of the invention, each step 320 may also comprise two or more layers, with at least a portion of the upper surface of the topmost sacrificial layer exposed. For example, in some embodiments, the step comprises two layers, each consisting of an insulating layer and a sacrificial layer below it, with at least a portion of the upper surface of the topmost sacrificial layer exposed. It is understood that, depending on the design of the three-dimensional memory, different steps may comprise the same or different layers.

[0081] The upper surface of the sacrificial layer 312 serves as the top surface of the step 320, and the conductive structure 370 is disposed on the upper surface of the sacrificial layer 312, that is, the conductive structure 370 is formed on the top surface of the step 320. The conductive structures 370 on different top surfaces of the steps 320 are insulated from each other to avoid short circuits. Furthermore, in this embodiment, there is a gap between the conductive structure 370 and the sidewall of the step 320.

[0082] The covering layer 340 covers the top of the step 320. The covering layer 340 not only covers the conductive structure 370, but also fills the gap between the conductive structure 370 and the sidewall of the step 320.

[0083] The contact portion 410 extends through the cover layer 340 to the conductive structure 370 and is conductive. The contact portion 410 and the conductive structure 370 are electrically connected.

[0084] In the three-dimensional memory, the conductive structure 370 is located only on the top surface of the step 320, below which is an insulating structure with sacrificial layer 312 and first insulating layer stacked alternately. There are no other conductive components (e.g., gate lines or conductive layers). Therefore, even if the contact portion 410 extends into the conductive structure 370 or even through the conductive structure 370 to the first insulating layer or sacrificial layer below, the contact portion 410 will only be electrically connected to the conductive structure 370 of the corresponding layer, and will not be electrically connected to the conductive structure 370 of other layers. This effectively avoids gate line electrical connections between different layers and greatly improves the stability of the memory.

[0085] The second region SS2 includes a second stacked structure 450. The second stacked structure 450 includes stacked second insulating layers (such as...). Figure 4 The insulating layer 311 and the conductive layer 390 are shown. The conductive layer 390 extends to a predetermined position in the first region SS1 and is connected to a portion of the conductive structure 370. That is, the conductive layer 390 and the conductive structure 370 partially overlap. In some embodiments, the overlapping area of ​​the conductive layer 390 and the conductive structure 370 (e.g., Figure 34 The length of the area indicated by the middle arrow D is 50-100 nm, which can ensure good contact between the conductive layer and the conductive structure 370 and also prevent the conductive structure 370 from collapsing.

[0086] Furthermore, the three-dimensional memory also includes a core region AA, and the stepped region SS is along a first direction (e.g., ...). Figure 3 The core region AA is arranged in the X direction as shown, and includes a third stacked structure 440, which includes stacked third insulating layers (such as...). Figure 4The insulating layer 311 shown is connected to the gate line 380, and the gate line 380 is connected to the conductive layer 390.

[0087] In this configuration, the first insulating layer, the third insulating layer, and the second insulating layer are on the same layer; the sacrificial layer 312, the gate line 380, and the conductive layer 390 are also on the same layer. On the side of the first region SS1 adjacent to the second region SS2, the conductive layer 390 extends to a predetermined position in the first region SS1 and connects with a portion of the conductive structure 370, such that the gate line 380 is electrically connected to the conductive structure 370 through the conductive layer 390. Furthermore, in the stacking direction of the first stacked structure 430, the contact portion 410 is misaligned with the conductive layer 390 extending to the first region SS1, so that even when the contact portion 410 penetrates the conductive structure 370, the contact portion 410 will not be electrically connected to the conductive layer 390.

[0088] Furthermore, in the stepped region SS, a grid line slot 360 is provided on the side of the second region SS2 away from the first region SS1, while the grid line slot is not provided on the side of the first region SS1. An isolation layer and conductive material can be deposited in the grid line slot 360 to form a grid line slot structure (not shown in the figure). That is, in the stepped region SS, a grid line slot structure is provided on the side of the second region SS2 away from the first region SS1.

[0089] In this embodiment, grid line slots 360 are provided on the side of the second region SS1 away from the first region SS1 in the stepped area and in the core region AA, and grid line slot structures are formed within the grid line slots 360. In some embodiments, the grid line slot located in the second region SS2 is connected to the grid line slot located in the core region AA, that is, the two are the same grid line slot.

[0090] The gate gap structure can serve as the array common source of a three-dimensional memory, which is connected to the source region in the substrate. During the erase operation, an operating voltage is applied to the selected memory transistor, making the potential of the channel layer of the selected memory transistor greater than the potential of its gate. Under the influence of the potential difference between the channel layer and the gate, electrons in the charge storage layer of the selected memory transistor are driven to move into the channel layer. Simultaneously, holes are injected into the channel layer from the array common source under the influence of the voltage. The holes injected into the channel layer recombine with the electrons injected from the charge storage layer into the channel layer, thereby erasing the data of the selected memory transistor.

[0091] Furthermore, in the step area SS, on the side of the first area SS1 away from the second area SS2, a spacing structure 313 is provided on the top surface of the step. The spacing structure 313 can be used as a separation structure between adjacent storage blocks.

[0092] The three-dimensional memory provided in this embodiment of the invention will not be electrically connected to the conductive structure 370, conductive layer 390 and gate line 380 of other layers even if the contact portion 410 extends into the conductive structure 370 or even through the conductive structure 370 to the insulating layer or sacrificial layer below. This effectively avoids the electrical connection of gate lines between different layers and greatly improves the stability of the memory.

[0093] In one embodiment, the three-dimensional memory includes a plurality of memory blocks arranged along a second direction. The stepped area of ​​each memory block includes the first region and the second region, and the first region and the second region of adjacent memory blocks are arranged symmetrically about the boundary of the memory blocks.

[0094] Specifically, such as Figure 35 As shown, this is another top view schematic diagram of the three-dimensional memory structure of this application, wherein the three-dimensional memory includes multiple storage blocks arranged along a second direction (Y direction in the figure). Figure 35 The diagram schematically illustrates three storage blocks: a first storage block 50, a second storage block 51, and a third storage block 52. The step area SS of the first storage block 50 includes a first region SS10 and a second region SS20; the step area of ​​the second storage block 51 includes a first region SS11 and a second region SS21; and the step area SS of the third storage block 52 includes a first region SS12 and a second region SS22.

[0095] In this embodiment, the second region SS20 of the step area of ​​the first storage block 50 and the second region SS21 of the step area of ​​the second storage block 51 are arranged adjacent to each other, and the first region SS10 of the step area of ​​the first storage block 50 and the first region SS11 of the step area of ​​the second storage block 51 are respectively arranged on both sides of the first storage block 50 and the second storage block 51; the first region SS11 of the step area of ​​the second storage block 51 and the first region SS12 of the step area of ​​the third storage block 52 are arranged adjacent to each other, and the second region SS21 of the step area of ​​the second storage block 51 and the second region SS22 of the step area of ​​the third storage block 52 are respectively arranged on both sides of the second storage block 51 and the third storage block 52.

[0096] The adjacent first storage block 50 and second storage block 51 are symmetrically arranged with the boundary line E as the axis of symmetry. Specifically, the first region SS10 of the step area of ​​the first storage block 50 and the first region SS11 of the step area of ​​the second storage block 51 are symmetrically arranged with the boundary line E as the axis of symmetry, and the second region SS20 of the step area of ​​the first storage block 50 and the second region SS21 of the step area of ​​the second storage block 51 are symmetrically arranged with the boundary line E as the axis of symmetry. The adjacent second storage block 51 and third storage block 52 are symmetrically arranged with the boundary line F as the axis of symmetry. Specifically, the first region SS11 of the step area of ​​the second storage block 51 and the first region SS12 of the step area of ​​the third storage block 52 are symmetrically arranged with the boundary line F as the axis of symmetry, and the second region SS21 of the step area of ​​the second storage block 51 and the second region SS22 of the step area of ​​the third storage block 53 are symmetrically arranged with the boundary line F as the axis of symmetry.

[0097] In some embodiments, when the second regions of the step regions of two adjacent memory blocks are arranged close together, the two adjacent memory blocks share the same gate line slot structure in the step region. Specifically, in this embodiment, the second region SS20 of the step region of the first memory block 50 and the second region SS21 of the step region of the second memory block 51 are arranged close together. Therefore, the second region SS20 and the second region SS21 share the same gate line slot structure. In the above preparation method, the sacrificial layer of the second region SS20 and the second region SS21 is also removed through the same gate line slot 360.

[0098] In some embodiments, when the first regions of the step areas of two adjacent storage blocks are arranged close together, the two adjacent storage blocks share the same spacing structure in the step area. Specifically, in this embodiment, if the first region SS11 of the step area of ​​the second storage block 51 and the first region SS12 of the step area of ​​the third storage block 52 are arranged close together, then the second storage block 51 and the third storage block 52 share the same spacing structure 313, which can serve as a separator between the step areas of the second storage block 51 and the third storage block 52.

[0099] Furthermore, in some embodiments, the core regions of adjacent memory blocks also share the same gate slot structure on their adjacent sides. That is, for a three-dimensional memory, in the stepped region, different memory blocks can be distinguished by using gate slot structures and spacing structures, and in the core region, different memory blocks can be distinguished by using gate slot structures.

[0100] It is understood that the boundary line E and the boundary line F are only for illustrative purposes, and in actual semiconductor processes, the boundary line E and the boundary line F may not exist.

[0101] Since the content and structure involved in the manufacturing method can be fully or partially applied to three-dimensional memory, related or similar content will not be described in detail here.

[0102] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for manufacturing a three-dimensional memory, characterized in that, include: A stacked structure is formed, the stacked structure including stacked insulating layers and sacrificial layers, the stacked structure also including a step region, the step region including a first region and a second region arranged along a second direction, a plurality of steps are provided in the first region, and each step extends along the second direction, and at each step, the upper surface of the sacrificial layer serves as the top surface of the step; A transition layer is formed on the top surface of each step, and the transition layers on different top surfaces of the steps are insulated from each other; A covering layer is formed above the steps; Remove the sacrificial layer in the second region and a portion of the sacrificial layer in the first region facing the second region, while retaining a portion of the sacrificial layer in the first region facing away from the second region, so as to expose only the lower surface of the transition layer portion; Remove the transition layer to create a space between the top surface of each step and the cover layer; as well as The space is filled with conductive material to form a conductive structure on the top surface of each step, and a portion of the conductive structure includes a stacked portion of the insulating layer and a portion of the sacrificial layer below a portion of the conductive structure.

2. The method for manufacturing a three-dimensional memory according to claim 1, characterized in that, The transition layer is removed using an etching process.

3. The method for manufacturing a three-dimensional memory according to claim 2, characterized in that, The etching process has a higher etching rate for the transition layer than for the sacrificial layer.

4. The method for manufacturing a three-dimensional memory according to claim 1, characterized in that, The transition layer is a polycrystalline silicon layer.

5. The method for manufacturing a three-dimensional memory according to claim 1, characterized in that, The step of forming a transition layer on the top surface of each step further includes: A transition material layer is formed on the top surface and sidewalls of each step; The transition material layer on the sidewall of each step is removed, and the remaining transition material layer on the top surface of each step is used as the transition layer.

6. The method for manufacturing a three-dimensional memory according to claim 1, characterized in that, In the step of removing the transition layer to form a space between the top surface of each step and the cover layer, the transition layer is partially retained on the side of the transition layer away from the second region, forming a spacer structure.

7. The method for manufacturing a three-dimensional memory according to claim 1, characterized in that, Further steps include the following: A grid line gap is formed in the stepped area, and the grid line gap penetrates the stacked structure; The sacrificial layer of the second region, the partial sacrificial layer of the first region facing the second region, and the transition layer are removed through the grid line gaps.

8. The method for manufacturing a three-dimensional memory according to claim 7, characterized in that, The step of removing the sacrificial layer of the second region, the partial sacrificial layer of the first region facing the second region, and the transition layer through the grid gap further includes: The sacrificial layer in the second region is removed from the grid line gap to form a trench; Remove a portion of the sacrificial layer from the trench on the side of the first region facing the second region to expose a portion of the lower surface of the transition layer; Remove the transition layer.

9. The method for manufacturing a three-dimensional memory according to claim 8, characterized in that, It also includes the following steps: The grid gaps are filled with conductive material to form a conductive layer in the second region of the stepped area and a conductive structure in the first region of the stepped area. The conductive layer extends to the first region and is electrically connected to a portion of the conductive structure.

10. The method for manufacturing a three-dimensional memory according to claim 9, characterized in that, Further steps include the following: Forming contact holes that penetrate the cover layer to the conductive structure; The contact hole is filled with conductive material to form a conductive contact portion.

11. The method for manufacturing a three-dimensional memory according to claim 1, characterized in that, The stacked structure further includes a core region, and the stepped region and the core region are arranged along a first direction. The method further includes the following steps: A gate line gap is formed in the core region, and the gate line gap penetrates the stacked structure; The sacrificial layer in the core region is removed through the gate wire gaps; Conductive material is filled through the gaps in the grid lines to form grid lines in the core region.

12. A three-dimensional memory, comprising a stepped region, characterized in that, The stepped area includes a first region and a second region arranged along the second direction; The first region includes: A first stacked structure includes a first insulating layer and a sacrificial layer stacked together. The first stacked structure includes a plurality of steps extending along a second direction, and the upper surface of the sacrificial layer serves as the top surface of the step. A conductive structure is disposed on the top surface of the step, and the conductive structures on different top surfaces of the step are insulated from each other. A portion of the conductive structure includes a first insulating layer and a sacrificial layer stacked below it. A covering layer, covering the area above the steps; The contact portion extends through the cover layer to the conductive structure and is conductive; The second region includes: The second stacked structure includes a stacked second insulating layer and a conductive layer, wherein the conductive layer extends to a predetermined position in the first region and is connected to the corresponding conductive structure.

13. The three-dimensional memory according to claim 12, characterized in that, It also includes a core region, the stepped region and the core region are arranged along a first direction, the core region includes a third stacked structure, the third stacked structure includes a stacked third insulating layer and a gate line, the gate line is connected to the conductive layer.

14. The three-dimensional memory according to claim 13, characterized in that, The first insulating layer, the second insulating layer, and the third insulating layer are on the same layer, as are the sacrificial layer, the gate line, and the conductive layer. On the side of the first region facing the second region, in the direction of stacking of the first stacked structure, the conductive layer partially overlaps with the conductive structure.

15. The three-dimensional memory according to claim 14, characterized in that, The conductive layer is connected to the sacrificial layer.

16. The three-dimensional memory according to claim 14, characterized in that, In the direction of stacking of the first stacked structure, the contact portion is misaligned with the conductive layer extending into the first region.

17. The three-dimensional memory according to claim 14, characterized in that, The length of the overlapping region between the conductive layer and the conductive structure is 50~100nm.

18. The three-dimensional memory according to claim 13, characterized in that, In the stepped area, a grid line slot structure is provided on the side of the second region away from the first region.

19. The three-dimensional memory according to claim 18, characterized in that, A grid line slot structure is provided on both sides of the core area.

20. The three-dimensional memory according to claim 12, characterized in that, In the stepped area, on the side of the first area away from the second area, a spacer structure is provided on the top surface of the step.

21. The three-dimensional memory according to claim 20, characterized in that, The three-dimensional memory includes a plurality of memory blocks arranged along a second direction. Each memory block step region includes the first region and the second region, and the first region and the second region of adjacent memory block step regions are arranged symmetrically about the boundary of the memory blocks.

22. The three-dimensional memory according to claim 21, characterized in that, When the first regions of the step areas of two adjacent storage blocks are set close together, the two adjacent storage blocks share the same spacing structure in the step area.

23. The three-dimensional memory according to claim 21, characterized in that, When the second region of the step area of ​​two adjacent memory blocks is set close together, the two adjacent memory blocks share the same grid line slot structure in the step area.

24. A storage system, characterized in that, The invention includes a three-dimensional memory and a controller as described in any one of claims 12 to 23, wherein the controller is coupled to the three-dimensional memory and is used to control the storage of data in the three-dimensional memory.

Images