Integrated circuit device and electronic system including the same

Abstract

An integrated circuit device and an electronic system are provided. The integrated circuit device includes a semiconductor substrate having a cell region and a dummy region outside the cell region; a plurality of gate electrodes and a plurality of insulating layers located in the cell region, extending in a first direction and a second direction parallel to a main surface of the semiconductor substrate, and alternately stacked in a third direction perpendicular to the main surface of the semiconductor substrate, the first direction and the second direction crossing each other; and a plurality of dummy molding layers and a plurality of dummy insulating layers alternately stacked in the third direction in the dummy region, wherein a carbon concentration of an upper dummy molding layer of the plurality of dummy molding layers is less than a carbon concentration of a lower dummy molding layer of the plurality of dummy molding layers, the lower dummy molding layer being between the upper dummy molding layer and the main surface of the semiconductor substrate.

Description

[0001] Cross-reference of related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2021-0021137, filed on February 17, 2021, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present invention relate to an integrated circuit device and an electronic system including the integrated circuit device, and more specifically, to an integrated circuit device including a non-volatile vertical memory device and an electronic system including the integrated circuit device. Background Technology

[0004] To improve performance and cost-effectiveness, it may be necessary to increase the integration density of integrated circuit devices. Specifically, the integration density of memory devices is a factor determining the cost-effectiveness of a product. Since the integration density of a two-dimensional memory device can be determined by the area occupied by a unit memory cell, it may be affected by the level of fine patterning technology. However, it may require expensive equipment to form fine patterns, and the area of ​​a chip die is limited; therefore, although the integration density of two-dimensional memory devices is generally increasing, it may still be finite. Summary of the Invention

[0005] The present invention provides an integrated circuit device and an electronic system including the integrated circuit device, wherein the integrated circuit device is manufactured by performing an ultraviolet annealing process on the upper molding layer in the vertical memory device, thereby effectively suppressing over-etching defects that may occur due to impurities in the process of forming the vias.

[0006] According to one aspect of the present invention, an integrated circuit device is provided, the integrated circuit device comprising: a semiconductor substrate having a cell region and a dummy region located outside the cell region; a plurality of gate electrodes and a plurality of insulating layers extending in the cell region in a first direction and a second direction parallel to a main surface of the semiconductor substrate, and alternately stacked in a third direction perpendicular to the main surface of the semiconductor substrate, the first direction and the second direction intersecting each other; a plurality of dummy molding layers and a plurality of dummy insulating layers alternately stacked in the dummy region in a third direction; a plurality of channel structures passing through the plurality of gate electrodes and the plurality of insulating layers in the cell region; and a plurality of dummy structures passing through the plurality of dummy molding layers and the plurality of dummy insulating layers in the dummy region, wherein the plurality of dummy molding layers are arranged at the same horizontal height as the plurality of gate electrodes in the third direction, the plurality of dummy insulating layers are arranged at the same horizontal height as the plurality of insulating layers in the third direction, and the carbon concentration of an upper dummy molding layer among the plurality of dummy molding layers is less than the carbon concentration of a lower dummy molding layer among the plurality of dummy molding layers, the lower dummy molding layer being between the upper dummy molding layer and the main surface of the semiconductor substrate.

[0007] According to another aspect of the present invention, an integrated circuit device is provided, the integrated circuit device comprising: a semiconductor substrate having a cell region and a dummy region; a plurality of gate electrodes and a plurality of insulating layers, which are alternately stacked in the cell region in a direction perpendicular to the main surface of the semiconductor substrate; a plurality of dummy molding layers and a plurality of dummy insulating layers, which are alternately stacked in the dummy region in a direction perpendicular to the main surface; and a channel via through the plurality of gate electrodes and the plurality of insulating layers in the cell region and a dummy via through the plurality of dummy molding layers and the plurality of dummy insulating layers in the dummy region, wherein, in at least one of the plurality of dummy molding layers, the carbon concentration at each of the upper and lower interfaces of the at least one dummy molding layer is greater than the carbon concentration at the central portion of the at least one dummy molding layer.

[0008] According to another aspect of the present invention, an electronic system is provided, comprising: a main substrate; an integrated circuit device on the main substrate; and a controller electrically connected to the integrated circuit device on the main substrate, wherein the integrated circuit device comprises: a semiconductor substrate having a cell region and a dummy region outside the cell region; a plurality of gate electrodes and a plurality of insulating layers extending in the cell region in a first direction and a second direction parallel to the main surface of the semiconductor substrate, and alternately stacked in a third direction perpendicular to the main surface of the semiconductor substrate, the first direction and the second direction intersecting each other; a plurality of dummy molding layers and a plurality of dummy insulating layers, which... The components are alternately stacked in the third-party upward direction in the dummy region; multiple channel structures that pass through multiple gate electrodes and multiple insulating layers in the cell region; and multiple dummy structures that pass through multiple dummy molding layers and multiple dummy insulating layers in the dummy region, wherein the multiple dummy molding layers are arranged at the same horizontal height as the multiple gate electrodes in the third-party upward direction, the multiple dummy insulating layers are arranged at the same horizontal height as the multiple insulating layers in the third-party upward direction, and the carbon concentration of the upper dummy molding layer in the multiple dummy molding layers is less than the carbon concentration of the lower dummy molding layer in the multiple dummy molding layers, the lower dummy molding layer being between the upper dummy molding layer and the main surface of the semiconductor substrate. Attached Figure Description

[0009] Embodiments of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 These are block diagrams of integrated circuit devices according to some embodiments of the present invention;

[0011] Figure 2 This is an equivalent circuit diagram of a memory cell array of an integrated circuit device according to some embodiments of the present invention;

[0012] Figure 3 This is a plan view illustrating components of an integrated circuit device according to some embodiments of the concept of the present invention;

[0013] Figure 4 It is along Figure 3 A sectional view taken from line IV-IV'. Figure 5 yes Figure 4 A magnified view of region V. Figure 6 yes Figure 4 An enlarged view of area VI, and Figure 7 yes Figure 4 Enlarged view of section VII;

[0014] Figures 8 to 10 These are cross-sectional views of integrated circuit devices according to other embodiments of the present invention;

[0015] Figure 11 and Figure 12 This is a flowchart of a method for manufacturing an integrated circuit device according to some embodiments of the present invention;

[0016] Figures 13A to 13E This is a cross-sectional view illustrating a method of manufacturing an integrated circuit device according to some embodiments of the concept of the present invention, based on the process steps.

[0017] Figure 14 This is a diagram illustrating an electronic system including an integrated circuit device according to some embodiments of the concept of the present invention;

[0018] Figure 15 This is a perspective view illustrating an electronic system including an integrated circuit device according to some embodiments of the present invention; and

[0019] Figure 16 and Figure 17 These are cross-sectional views illustrating various semiconductor packages including integrated circuit devices according to embodiments of the present invention. Detailed Implementation

[0020] It will be understood that although the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. Thus, for example, a first element, first component, or first part discussed below may be named a second element, second component, or second part without departing from the teachings of the inventive concept. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It should be noted that aspects described with respect to one embodiment may be incorporated into different embodiments, although they are not specifically described therein. That is, features of all embodiments and / or any embodiment may be combined in any manner and / or combination. Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0021] Figure 1 This is a block diagram of an integrated circuit device 10 according to some embodiments of the present invention.

[0022] Reference Figure 1 The integrated circuit device 10 may include a memory cell array 20 and peripheral circuitry 30.

[0023] The memory cell array 20 may include multiple memory cell blocks BLK1, BLK2, ..., and BLKn (where n is an integer of 3 or greater). Each of the multiple memory cell blocks BLK1, BLK2, ..., and BLKn may include multiple memory cells. The multiple memory cell blocks BLK1, BLK2, ..., and BLKn may be connected to the peripheral circuitry 30 via bit lines BL, word lines WL, serial select lines SSL, and ground select lines GSL.

[0024] The memory cell array 20 can be connected to the page buffer 34 via bit lines BL and to the row decoder 32 via word lines WL, string select lines SSL, and ground select lines GSL. In the memory cell array 20, each of the plurality of memory cells included in the plurality of memory cell blocks BLK1, BLK2, ..., and BLKn may include flash memory cells. The memory cell array 20 may include a three-dimensional (3D) memory cell array. The 3D memory cell array may include a plurality of NAND strings, and each of the plurality of NAND strings may include a plurality of memory cells vertically stacked and connected to multiple word lines WL.

[0025] Peripheral circuitry 30 may include a line decoder 32, a page buffer 34, data input / output (I / O) circuitry 36, and control logic 38. Although not shown in the figures, peripheral circuitry 30 may also include various circuits, such as voltage generation circuitry configured to generate various voltages used in operating the integrated circuit device 10, error correction circuitry configured to correct errors in data read from the memory cell array 20, and I / O interfaces.

[0026] The peripheral circuit 30 can receive address ADDR, command CMD and control signal CTRL from outside the integrated circuit device 10, and can send data DATA to external devices outside the integrated circuit device 10 and receive data DATA from external devices outside the integrated circuit device 10.

[0027] The configuration of the peripheral circuit 30 will be described in detail below.

[0028] The row decoder 32 can be configured to select at least one memory cell block from a plurality of memory cell blocks BLK1, BLK2, ..., and BLKn in response to an external address ADDR, and can be configured to select the word line WL, serial select line SSL, and ground select line GSL of the selected memory cell block. The row decoder 32 can provide a voltage for performing memory operations on the word line WL of the selected memory cell block.

[0029] Page buffer 34 can be connected to memory cell array 20 via bit line BL. During programming operations, page buffer 34 can be configured to operate as a write driver, applying a voltage to bit line BL based on the data DATA stored in memory cell array 20; and during read operations, page buffer 34 can be configured to operate as a sense amplifier, sensing the data DATA stored in memory cell array 20. Page buffer 34 can be configured to operate based on control signal PCTL provided from control logic 38.

[0030] Data I / O circuit 36 ​​can be connected to page buffer 34 via multiple data lines DLs. During programming operations, data I / O circuit 36 ​​can be configured to receive data DATA from the memory controller (not shown) and, based on the column address C_ADDR provided from control logic 38, provide program data DATA to page buffer 34. During read operations, data I / O circuit 36 ​​can be configured to provide read data DATA stored in page buffer 34 to the memory controller based on the column address C_ADDR provided from control logic 38. Data I / O circuit 36 ​​can be configured to pass addresses or commands input to it to control logic 38 or row decoder 32.

[0031] Control logic 38 can be configured to receive commands CMD and control signals CTRL from the memory controller. Control logic 38 can be configured to provide row address R_ADDR to row decoder 32 and column address C_ADDR to data I / O circuitry 36. Control logic 38 can be configured to generate various internal control signals used in the integrated circuit device 10 in response to the control signal CTRL. For example, control logic 38 can be configured to adjust the voltage levels provided to word line WL and bit line BL when performing memory operations (such as programming or erasing operations).

[0032] Figure 2 This is an equivalent circuit diagram of a memory cell array (MCA) of an integrated circuit device according to some embodiments of the present invention.

[0033] Reference Figure 2 The equivalent circuit diagram of a vertical NAND flash memory with a vertical channel structure is shown.

[0034] A memory cell array (MCA) may include multiple memory cell strings (MS). The MCA may include multiple bit lines (BL), multiple word lines (WL), at least one string select line (SSL), at least one ground select line (GSL), and a common-source line (CSL).

[0035] Multiple memory cell strings (MS) can be formed between multiple bit lines (BL) and a common-source line (CSL). The accompanying drawings show an example where each of the multiple memory cell strings (MS) includes two string select lines (SSL), but embodiments of the inventive concept are not limited thereto. For example, each of the multiple memory cell strings (MS) may include one string select line (SSL).

[0036] Multiple memory cell strings (MS) can each include a string select transistor (SST), a ground select transistor (GST), and multiple memory cell transistors (MC1, MC2, ..., MCn-1 and MCn). The drain region of the string select transistor (SST) can be connected to the bit line (BL), and the source region of the ground select transistor (GST) can be connected to the common-source line (CSL). The common-source line (CSL) can be a region that is commonly connected to the source regions of multiple ground select transistors (GST).

[0037] The serial select transistor SST can be connected to the serial select line SSL, and the ground select transistor GST can be connected to the ground select line GSL. Multiple memory cell transistors MC1, MC2, ..., MCn-1 and MCn can be connected to multiple word lines WL respectively.

[0038] Figure 3 This is a plan view illustrating components of an integrated circuit device 100 according to some embodiments of the present invention. Figure 4 It is along Figure 3 A sectional view taken from line IV-IV'. Figure 5 yes Figure 4 A magnified view of region V. Figure 6 yes Figure 4 Enlarged view of area VI, Figure 7 yes Figure 4 Enlarged view of section VII.

[0039] Reference Figures 3 to 7 The integrated circuit device 100 may include a memory cell area MCR, a connection area CON, and a dummy area DR.

[0040] The memory cell region MCR can be formed with a reference. Figure 2 The area described is a vertical channel structure NAND type memory cell array MCA. The connection area CON may be a region in which pad portions PADs are formed for electrical connections between the memory cell array MCA formed in the memory cell area MCR and peripheral circuit areas (not shown). The dummy area DR may be located outside the memory cell array MCA and the connection area CON, and may be a region in which dummy structures such as test patterns are formed.

[0041] Semiconductor substrate 101 may include semiconductor materials, such as group IV semiconductors, group III-V compound semiconductors, or group II-VI oxide semiconductors. For example, group IV semiconductors may include silicon (Si), germanium (Ge), or silicon-germanium. Semiconductor substrate 101 may be provided as a bulk wafer or a wafer on which an epitaxial layer is formed. In other embodiments, semiconductor substrate 101 may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate.

[0042] Gate stack GS can be on semiconductor substrate 101 parallel to the main surface of semiconductor substrate 101 (in Figure 4 In a cross-sectional view, it may extend in a first direction (X direction) and a second direction (Y direction) of the upper surface of the semiconductor substrate 101. The gate stack GS may include a plurality of gate electrodes 130 and a plurality of insulating layers 140, which may be alternately arranged in a third direction (Z direction) perpendicular to the upper surface of the semiconductor substrate 101. In addition, an upper insulating layer 150 may be disposed in the uppermost portion of the gate stack GS1.

[0043] Each of the gate electrodes 130 may include a buried conductive layer 132 and an insulating pad 134 surrounding or adjacent to the upper, bottom, and side surfaces of the buried conductive layer 132. For example, the buried conductive layer 132 may include a metal such as tungsten, a metal silicide such as tungsten silicide, doped polysilicon, or a combination thereof. In some embodiments, the insulating pad 134 may include a high-k material such as alumina.

[0044] Multiple gate electrodes 130 may correspond to the ground select line GSL, the word line WL, and at least one string select line SSL, which constitute the above reference. Figure 2 The memory cell string MS is described above. For example, the lowest of the plurality of gate electrodes 130 can be used as the ground select line GSL, the highest of the plurality of gate electrodes 230 can be used as the string select line SSL, and the remaining gate electrodes 130 can be used as word lines WL. Therefore, a memory cell string MS in which the ground select transistor GST, the string select transistor SST, and the memory cell transistors MC1, MC2, ..., MCn-1 and MCn are connected in series can be provided.

[0045] In some embodiments, carbon (C) and / or hydrogen (H) may exist as impurities at a specific concentration at the interface between the gate electrode 130 and the insulating layer 140. During the manufacturing process of the integrated circuit device 100, in the replacement process of forming the gate electrode 130 by replacing the molding layer 130M with an electrode layer, these impurities may be formed by the components of the molding layer 130M (see Figure 13B This is caused by residues from the material.

[0046] On the semiconductor substrate 101, a plurality of word line dices 170 may extend in a first direction (X direction). Gate stacks GS disposed between a pair of word line dices 170 may form a block, and the pair of word line dices 170 may define the width of the gate stacks GS in a second direction (Y direction). Each of the word line dices 170 may include an insulating spacer 172 and an insulating separation layer 174. That is, the word line dices 170 may include an insulating structure. A plurality of common source regions (CSRs) may be formed on the semiconductor substrate 101. The plurality of common source regions (CSRs) may be impurity regions doped with a high concentration of impurities.

[0047] Multiple channel structures 160 may extend from the upper surface of the semiconductor substrate 101 through the gate stack GS in a third direction (Z direction) within the memory cell region MCR. The multiple channel structures 160 may be arranged to be spaced apart from each other at specific intervals in a first direction (X direction) and a second direction (Y direction). The multiple channel structures 160 may be arranged in a zigzag or staggered pattern, but embodiments of the present invention are not limited thereto. In some embodiments, the distance between adjacent multiple channel structures 160 may be a first distance D1.

[0048] Each of the plurality of channel structures 160 may be formed to extend within a channel via 160H passing through a gate stack GS. Each of the plurality of channel structures 160 may include a gate insulating layer 162, a channel layer 164, a buried insulating layer 166, and a conductive plug 168. The gate insulating layer 162 and the channel layer 164 may be sequentially disposed on the sidewalls of the channel via 160H. For example, the gate insulating layer 162 may be conformally disposed on the sidewalls of the channel via 160H, and the channel layer 164 may be conformally disposed on the sidewalls and bottom of the channel via 160H. The buried insulating layer 166 may be disposed on the channel layer 164 to at least partially fill the remaining space of the channel via 160H. The conductive plug 168 may be disposed on the upper side of the channel via 160H to physically contact the channel layer 164 and block the entrance (e.g., the uppermost end) of the channel via 160H. In other embodiments, the embedded insulating layer 166 may be omitted, and the channel layer 164 may have a columnar shape that at least partially fills the remainder of the channel hole 160H.

[0049] Multiple channel structures 160 can physically contact the semiconductor substrate 101. In some embodiments, a channel layer 164 can be disposed at the bottom of the channel via 160H1 to physically contact the upper surface of the semiconductor substrate 101. In other embodiments, a contact semiconductor layer (not shown) with a specific height can be formed on the semiconductor substrate 101 at the bottom of the channel via 160H, and the channel layer 164 can be electrically connected to the semiconductor substrate 101 through the contact semiconductor layer.

[0050] The gate insulating layer 162 may have a structure comprising a tunneling dielectric layer 162A, a charge storage layer 162B, and a barrier dielectric layer 162C arranged sequentially on the outer wall of the channel layer 164. The relative thicknesses of the tunneling dielectric layer 162A, the charge storage layer 162B, and the barrier dielectric layer 162C constituting the gate insulating layer 162 are not limited to those shown in the figures and may be modified differently.

[0051] The tunneling dielectric layer 162A may include silicon oxide, hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, etc. The charge storage layer 162B is a region in which electrons passing through the tunneling dielectric layer 162A from the channel layer 164 can be stored, and may include silicon nitride, boron nitride, boron silicon nitride, or doped polycrystalline silicon. The barrier dielectric layer 162C may include silicon oxide, silicon nitride, and / or a metal oxide having a higher dielectric constant than silicon oxide.

[0052] In a block, the uppermost gate electrode 130 can be divided into two parts in a planar view by a series-separated insulating layer (not shown). These two parts can constitute the above reference. Figure 2 The aforementioned string select line SSL.

[0053] In the connection region CON, the gate electrode 130 may extend to form a pad portion PAD at its end, and the covering insulating layer 120 may be located on the pad portion PAD and at least partially cover the pad portion PAD. In the connection region CON, the length of the plurality of gate electrodes 130 in the first direction (X direction) may be reduced in the third direction (Z direction) away from the upper surface of the semiconductor substrate 101. That is, in the connection region CON, the plurality of gate electrodes 130 may have a stepped structure.

[0054] Contact plugs (CNTs) that pass through the insulating layer 120 and connect to the pad portion PAD of the gate electrode 130 can be arranged in the connection area CON. The contact plugs (CNTs) can be tapered cylindrical in shape with a width that narrows in the third direction (Z direction) from their upper to lower regions.

[0055] Bit line contact BLC can pass through upper insulating layer 150 to physically contact conductive plug 168 of channel structure 160, and bit line BL, which physically contacts bit line contact BLC, can extend in a second direction (Y direction) on upper insulating layer 150. Additionally, conductive line ML can be formed in connection area CON on upper insulating layer 150. Although not shown in the figures, upper support layers can also be formed between upper insulating layer 150 and bit line BL, and between upper insulating layer 150 and conductive line ML.

[0056] The dummy stack DS can extend on the dummy region DR of the semiconductor substrate 101 in a first direction (X direction) and a second direction (Y direction) parallel to the main surface of the semiconductor substrate 101. The dummy stack DS may include a plurality of dummy molding layers 131 and a plurality of dummy insulating layers 141, and the plurality of dummy molding layers 131 and the plurality of dummy insulating layers 141 may be alternately arranged in a third direction (Z direction) perpendicular to the upper surface of the semiconductor substrate 101. In addition, an upper insulating layer 150 may be disposed in the uppermost portion of the dummy stack DS.

[0057] Multiple dummy structures 161 may extend from the upper surface of the semiconductor substrate 101 through the dummy stack DS in a third direction (Z direction) within the dummy region DR. The multiple dummy structures 161 may be arranged to be separated from each other at specific intervals in a first direction (X direction) and a second direction (Y direction). The multiple dummy structures 161 may be arranged in a zigzag or staggered pattern, but embodiments of the present invention are not limited thereto. In some embodiments, the distance between multiple adjacent dummy structures 161 may be a second distance D2.

[0058] Multiple dummy molding layers 131 may be arranged at the same horizontal height as multiple gate electrodes 130 in the third direction (Z direction), and multiple dummy insulating layers 141 may be arranged at the same horizontal height as multiple insulating layers 140 in the third direction (Z direction). The multiple dummy insulating layers 141 may comprise the same material as the multiple insulating layers 140. This may be due to the replacement of molding layers 130M with electrode layers according to the manufacturing process of the integrated circuit device 100 (see...). Figure 13B The replacement process for forming the gate electrode 130.

[0059] In some embodiments, the carbon (C) concentration of the upper dummy molding layer 131 (i.e., the upper dummy molding layer) as a plurality of dummy molding layers 131 may be less than the carbon (C) concentration of the lower dummy molding layer 131 (i.e., the lower dummy molding layer) as a plurality of dummy molding layers 131. This feature may be due to a process in which impurities such as carbon (C) are removed from the upper dummy molding layer 131 by performing an ultraviolet annealing process on the dummy molding layer 131 according to the process of manufacturing the integrated circuit device 100. For example, in Figure 4 In the cross-sectional view, the carbon (C) concentration of the upper dummy molding layer 131 can be from about 0% to about 80% of the carbon (C) concentration of the lower dummy molding layer 131. In other embodiments, impurities such as carbon (C) can be removed by performing a plasma process utilizing oxygen (O2) on the upper dummy molding layer 131.

[0060] In some embodiments, the carbon (C) in the dummy region DR can have a sinusoidal concentration distribution in the third direction (Z direction) starting from the main surface of the semiconductor substrate 101, for example, see Figure 7 In other words, in one of the plurality of dummy molding layers 131, the carbon (C) concentration of each of the upper interface 131T and the lower interface 131B can be greater than the carbon (C) concentration of the central portion 131C. For example, the carbon (C) concentration of the upper interface 131T can be about 5 times or more than the carbon (C) concentration of the central portion 131C. Furthermore, the carbon (C) concentration of the upper interface 131T can be greater than the carbon (C) concentration of the lower interface 131B, wherein the lower interface 131B is located between the upper interface 131T and the main surface of the substrate 101.

[0061] In some embodiments, each of the plurality of gate electrodes 130 may include a first conductive material such as tungsten, and at least a portion of the sidewall of each of the plurality of dummy molding layers 131 may contact the first conductive material. That is, the plurality of dummy molding layers 131 may correspond to a molded layer 130M in which a molded layer 130M is retained (see Figure 13B A portion of the area, and can be arranged to correspond with the area formed in which the molding layer 130M has been removed (see...). Figure 13B Some portions of the multiple gate electrodes 130 in the region are in physical contact.

[0062] Multiple dummy structures 161 may be formed to extend through the dummy stack DS within the dummy via 161H. Each of the multiple dummy structures 161 may include a dummy gate insulating layer 162D, a dummy channel layer 164D, a dummy buried insulating layer 166D, and a dummy conductive plug 168D.

[0063] Here, the first distance D1 between multiple adjacent channel structures 160 can be smaller than the second distance D2 between multiple adjacent dummy structures 161. Because the multiple dummy structures 161 are not used as memory cells in the integrated circuit device 100, the multiple dummy structures 161 can be arranged at intervals of the second distance D2, and the multiple dummy structures 161 are sufficiently separated from each other by the intervals of the second distance D2. Therefore, because the etchant used in the replacement process may not completely remove the molding layer 130M located in the dummy region DR (see... Figure 13B Therefore, a portion of the molding layer 130M will be retained as a dummy molding layer 131 on the sidewalls of some dummy structures 161.

[0064] With advancements in process technology, as the height of the gate stack GS increases, the aspect ratio (i.e., the ratio of the height to the width of the channel structure 160) can be increased. Specifically, in a structure where the gate stack GS includes multiple gate electrodes 130, the aspect ratio of the channel structure 160 can be further increased. Additionally, the channel via 160H can have a tapered columnar shape whose width narrows from its upper region to its lower region in the third direction (Z direction), such as... Figure 4The cross-sectional view is shown. Therefore, the first distance D1 between the multiple adjacent channel structures 160 is within the error range of the process margin.

[0065] In this scenario, during the manufacturing process of a typical integrated circuit device, and more specifically, during the etching process for forming vias, the presence of carbon (C) and / or hydrogen (H) impurities at the interface between the molding layer and the insulating layer may transfer more ion energy to the upper molding layer, and fluorine (F) radicals may cross the upper interface of the upper molding layer, leading to over-etching. Subsequently, when a channel structure is formed in a via that has already been over-etched, defects may occur where adjacent channel structures come into contact with each other.

[0066] To address this issue, in some embodiments of the integrated circuit device 100 according to the present invention, the presence of substances in the upper molding layer 130M can be effectively removed by performing a low-temperature annealing process using ultraviolet light on the molding layer 130M (see [reference]). Figure 13B Carbon (C) and / or hydrogen (H) impurities at the interface between the molding layer 130M and the insulating layer 140. Therefore, by suppressing over-etching at the interface of the upper molding layer 130M, defects that cause adjacent channel structures 160 to physically contact each other can be significantly reduced.

[0067] Analysis has been performed on the change in carbon (C) concentration based on the temperature of the annealing process utilizing ultraviolet light. Therefore, an application of a low-temperature annealing process performed below approximately 400°C has been designed, which reduces the concentration of impurities present at the interface between the molding layer 130M and the insulating layer 140 without affecting other material layers.

[0068] As a result, the integrated circuit device 100 according to some embodiments of the present invention can be manufactured by performing a low-temperature annealing process using ultraviolet light on the upper molding layer (that is, the upper molding layer 130M) in the vertical memory device, thereby effectively suppressing over-etching defects that may occur due to impurities in the process of forming the channel vias 160H. Therefore, the occurrence of defects in the physical contact between adjacent channel structures 160 can be effectively reduced, thereby improving product reliability.

[0069] Figures 8 to 10 These are cross-sectional views of integrated circuit devices 200, 300, and 400, respectively, according to other embodiments of the present invention.

[0070] Most of the constituent elements and materials constituting the integrated circuit devices 200, 300 and 400 described below are the same as those referenced above. Figures 3 to 7The descriptions are substantially the same or similar. Therefore, for ease of description, the description of the embodiments will focus on the differences from the integrated circuit device 100 described above.

[0071] Reference Figure 8 The integrated circuit device 200 may include a peripheral circuit structure PS and a cell array structure CS arranged at a higher vertical level than the peripheral circuit structure PS.

[0072] According to an embodiment, the integrated circuit device 200 may have a cell array structure CS arranged on a peripheral circuit structure PS, forming a cell-on-periphery (COP) structure. A base structure 110 may be arranged between the peripheral circuit structure PS and the cell array structure CS.

[0073] The peripheral circuit structure PS may include peripheral circuit transistors 60TR and peripheral circuit wiring 70 disposed on a semiconductor substrate 101. In the semiconductor substrate 101, an active region AC may be defined by a device isolation layer 102, and a plurality of peripheral circuit transistors 60TR may be formed on the active region AC. Each of the plurality of peripheral circuit transistors 60TR may include a peripheral circuit gate 60G and a source / drain region 62 disposed on either side of the peripheral circuit gate 60G in the semiconductor substrate 101.

[0074] The peripheral circuit wiring 70 may include a plurality of peripheral circuit contacts 72 and a plurality of peripheral circuit metal layers 74. An interlayer insulating layer 80, covering and at least partially covering the peripheral circuit transistor 60TR and the peripheral circuit wiring 70, may be disposed on the semiconductor substrate 101. The plurality of peripheral circuit metal layers 74 may have a multilayer structure comprising a plurality of metal layers disposed at different vertical horizontal heights. In the figures, the plurality of peripheral circuit metal layers 74 are shown to have the same height. However, in other embodiments, the peripheral circuit metal layers 74 disposed at some horizontal heights (e.g., disposed at the top horizontal height) may be formed to have a higher height than the peripheral circuit metal layers 74 disposed at other horizontal heights.

[0075] In this embodiment, the peripheral circuit structure PS may include a dummy transistor 61TR disposed in a dummy region DR on the semiconductor substrate 101. The dummy region DR may be located outside the memory cell array MCA and the connection region CON, and may be a region in which a dummy structure such as the dummy transistor 61TR is formed.

[0076] Reference Figure 9 The integrated circuit device 300 may include a first gate stack GS1 located at the bottom and a second gate stack GS2 located at the top.

[0077] In the integrated circuit device 300 of this embodiment, the first gate stack GS1 may include a plurality of first gate electrodes 130 and a plurality of first insulating layers 140, which may be alternately arranged in a third direction (Z direction) perpendicular to the upper surface of the base structure 110. In addition, a first upper insulating layer 150 may be disposed in the uppermost portion of the first gate stack GS1.

[0078] The second gate stack GS2 may include a plurality of second gate electrodes 230 and a plurality of second insulating layers 240, and the plurality of second gate electrodes 230 and the plurality of second insulating layers 240 may be alternately arranged on the first gate stack GS1 in the third direction (Z direction). In addition, a second upper insulating layer 250 may be disposed in the uppermost portion of the second gate stack GS2.

[0079] Multiple channel structures 160 may be formed to extend inside a first channel hole 160H1 passing through a first gate stack GS1 and a second channel hole 160H2 passing through a second gate stack GS2. The multiple channel structures 160 may have a shape that protrudes outward from the boundary portion between the first channel hole 160H1 and the second channel hole 160H2.

[0080] Multiple channel structures 160 can pass through the base structure 110, which includes an upper base layer 110U and a lower base layer 110L, and physically contact the semiconductor substrate 101. Therefore, the channel layer 164 can be electrically connected to the lower base layer 110L without being in direct physical contact with the semiconductor substrate 101.

[0081] In this embodiment, the plurality of dummy structures 161 formed in the dummy region DR may be formed to extend inside the first dummy hole 161H1 passing through the first dummy stack DS1 and the second dummy hole 161H2 passing through the second dummy stack DS2. The plurality of dummy structures 161 may have a shape that protrudes outward from the boundary portion between the first dummy hole 161H1 and the second dummy hole 161H2.

[0082] Reference Figure 10 The integrated circuit device 400 may have a chip-to-chip structure.

[0083] In the integrated circuit device 400 of this embodiment, an upper chip including a cell array structure CS is manufactured, and a lower chip including a peripheral circuit structure PS is manufactured. Then, the upper chip and the lower chip are connected to each other by a bonding method.

[0084] In some embodiments, the bonding method may refer to a method in which bonding pads formed in the uppermost portion of the upper chip and bonding pads formed in the uppermost portion of the lower chip are physically in contact with each other. The bonding method may be implemented using metal-to-metal bonding structures, through-silicon vias (TSVs), back via stacks (BVSs), eutectic bonding structures, ball grid array (BGA) bonding structures, multiple wirings, and / or combinations thereof.

[0085] The peripheral circuit structure PS may include a circuit substrate 301, an interlayer insulating layer 310, a plurality of circuit elements 360, a first metal layer 330 connected to each of the plurality of circuit elements 360, and a second metal layer 340 formed on the first metal layer 330.

[0086] The interlayer insulating layer 310 may be disposed on the circuit substrate 301 to be located on and at least partially cover the plurality of circuit elements 360, the first metal layer 330 and the second metal layer 340, and may include an insulating material.

[0087] The lower bonding pad 370 can be formed on the second metal layer 340 in the word line bonding region BA1. In the word line bonding region BA1, the lower bonding pad 370 of the peripheral circuit structure PS can be electrically connected to the upper bonding pad 470 of the cell array structure CS by bonding method.

[0088] The cell array structure CS can provide at least one memory block. The cell array structure CS may include a cell substrate 401 and a common source line CSL. Multiple word lines 430 and multiple insulating layers 440 may be stacked on the cell substrate 401 in the third direction (Z direction).

[0089] In the bit line bonding region BA2, the channel structure 460 can pass through the word line 430, the insulating layer 440, the serial select line and the ground select line in the third direction (Z direction).

[0090] In the word line bonding region BA1, word lines 430 may extend parallel to the upper surface of the cell substrate 401 and may be connected to a plurality of contact plugs CNTs. The word lines 430 and contact plugs CNTs may be connected to each other in pad portions PADs provided by extending at least some of the word lines 430 to different lengths.

[0091] The common source contact 480 can be disposed in the outer pad bonding area PA. The common source contact 480 may include a conductive material such as metal, metal compound or polysilicon, and can be electrically connected to the common source line CSL.

[0092] The first input / output pad 350 and the second input / output pad 450 can be arranged in the outer pad bonding area PA. A lower layer 320, which is formed on the lower surface of the circuit substrate 301 and at least partially covers the lower surface of the circuit substrate 301, can be formed below the circuit substrate 301, and the first input / output pad 350 can be formed on the lower layer 320. An upper layer 420, which is formed on the upper surface of the unit substrate 401 and at least partially covers the upper surface of the unit substrate 401, can be formed on the unit substrate 401, and the second input / output pad 450 can be arranged on the upper layer 420.

[0093] In this embodiment, multiple dummy molding layers 431 and multiple dummy insulating layers 441 can be arranged alternately in the dummy region DR. In addition, multiple dummy structures 461 can be formed to pass through the multiple dummy molding layers 431 and multiple dummy insulating layers 441.

[0094] Figure 11 and Figure 12 This is a flowchart illustrating a method for manufacturing an integrated circuit device according to some embodiments of the present invention.

[0095] Embodiments of the present invention can be implemented in a variety of different ways. For example, a process sequence may be performed differently than that described below. For example, two processes described consecutively may be performed substantially simultaneously, or they may be performed in the reverse order of that described below.

[0096] Reference Figure 11 The method S10 for manufacturing an integrated circuit device may include process steps from the first operation S110 to the seventh operation S170.

[0097] The method S10 for manufacturing an integrated circuit device may include a first operation S110 of forming a sacrificial gate stack on a semiconductor substrate, a second operation S120 of performing a low-temperature annealing process using ultraviolet light on the upper layer of the sacrificial gate stack, a third operation S130 of forming a connection region by sequentially patterning the sacrificial gate stack, a fourth operation S140 of forming a channel via and a dummy via by patterning the sacrificial gate stack, a fifth operation S150 of forming a plurality of gate electrodes by removing a plurality of molding layers and at least partially filling an electrode layer, a sixth operation S160 of forming a plurality of contact plugs in the connection region, and a seventh operation S170 of forming bit lines and conductive lines.

[0098] The following reference Figures 13A to 13E The technical features of each of the first operation S110 to the seventh operation S170 are described in detail.

[0099] Reference Figure 12 The method S20 for manufacturing an integrated circuit device may include process steps from the first operation S210 to the seventh operation S270.

[0100] The method S20 for manufacturing an integrated circuit device may include a first operation S210 of forming a sacrificial gate stack on a semiconductor substrate, a second operation S220 of performing an oxygen-based plasma process on the upper layer of the sacrificial gate stack, a third operation S230 of forming a connection region by sequentially patterning the sacrificial gate stack, a fourth operation S240 of forming a channel via and a dummy via by patterning the sacrificial gate stack, a fifth operation S250 of forming a plurality of gate electrodes by removing a plurality of molding layers and at least partially filling electrode layers, a sixth operation S250 of forming a plurality of contact plugs in the connection region, and a seventh operation S270 of forming bit lines and conductive lines.

[0101] Figures 13A to 13E This is a cross-sectional view illustrating a method for manufacturing an integrated circuit device according to some embodiments of the concept of the present invention, based on the process steps.

[0102] Reference Figure 13A A sacrificial gate stack (SGS) can be formed on the semiconductor substrate 101.

[0103] The sacrificial gate stack SGS can be formed by alternately forming a plurality of insulating layers 140 and a plurality of molding layers 130M on the main surface or top surface of the semiconductor substrate 101.

[0104] In some embodiments, the plurality of insulating layers 140 may comprise insulating materials such as silicon oxide and / or silicon oxynitride. The plurality of molding layers 130M may comprise materials different from those of the plurality of insulating layers 140. The plurality of molding layers 130M may comprise silicon nitride, silicon oxynitride, and / or polycrystalline silicon doped with impurities.

[0105] In this case, carbon (C) and / or hydrogen (H) may be present as impurities at a specific concentration at the interface between the multiple insulating layers 140 and the multiple molding layers 130M.

[0106] Reference Figure 13B An annealing process can be performed to make the impurity concentration of the upper molded layer 130M of the multiple molded layers 130M less than the impurity concentration of the lower molded layers 130M.

[0107] In the process of manufacturing the integrated circuit device 100, according to an embodiment of the present invention, by performing a low-temperature annealing process using ultraviolet light (UV) on the molding layer 130M at a specific location (e.g., the upper molding layer 130M), impurities present at the interface between the plurality of insulating layers 140 and the plurality of molding layers 130M can be removed or reduced. For example, the annealing process can be performed such that the carbon (C) concentration of the upper molding layer 130M is about 0% to about 80% of the carbon (C) concentration of the lower molding layer 130M.

[0108] In addition, in order to break the bonding combination of impurities such as carbon (C) and / or hydrogen (H) from the molding layer 130M and degas the impurities in gaseous form, a low-temperature annealing process utilizing ultraviolet (UV) can be performed in the upper layer of the sacrificial gate stack SGS after the molding layer 130M is formed and before the insulating layer 140 is formed.

[0109] Reference Figure 13C The pad portion PAD can be formed by sequentially patterning the sacrificial gate stack SGS in the connection region CON.

[0110] The sacrificial gate stack SGS may include a memory cell region MCR and a connection region CON, and may include a pad portion PAD at the end of the molding layer 130M in the connection region CON.

[0111] Next, the overlay insulating layer 120 can be formed on and at least partially cover the pad portion PAD. The overlay insulating layer 120 may include insulating materials such as silicon oxide, silicon nitride, and / or silicon oxynitride.

[0112] Reference Figure 13D The channel via 160H and the dummy via 161H can be formed by patterning the sacrificial gate stack SGS.

[0113] In the sacrificial gate stack SGS, a channel via 160H can be formed by removing a portion of the memory cell region MCR, and a dummy via 161H can be formed by removing a portion of the dummy region DR.

[0114] With the development of process technology, as the height of the sacrificial gate stack (SGS) increases, the aspect ratio of the via 160H can be increased, and the spacing between adjacent vias 160H can be within the tolerance range of the process margin.

[0115] In this scenario, during the etching process of the via 160H in the fabrication of a typical integrated circuit device, more ion energy is transferred to the upper molding layer 130M due to carbon (C) and / or hydrogen (H) impurities present at the interface between the molding layer 130M and the insulating layer 140. Consequently, fluorine (F) radicals can penetrate the upper interface of the upper molding layer 130M, leading to over-etching.

[0116] Therefore, in the process of manufacturing an integrated circuit device according to an embodiment of the present invention, a low-temperature annealing process using ultraviolet light can be performed on the upper molding layer 130M, thereby suppressing over-etching at the interface of the upper molding layer 130M and significantly reducing over-etching defects of the via 160H.

[0117] Reference Figure 13E A channel structure 160 can be formed on the inner wall of the channel hole 160H, and a virtual structure 161 can be formed on the inner wall of the virtual hole 161H.

[0118] This can be achieved by removing the sacrificial gate stack SGS (see Figure 13D A portion of the letter line cut opening (WLH) is used to form the letter line cut opening. This can be achieved by removing multiple molded layers 130M (see [link to molded layer]) exposed on the sidewalls of the letter line cut opening (WLH). Figure 13B The gate electrode 130 is formed by replacing the molding layer 130M with the electrode layer (see [reference]). Figure 13B The replacement process forms the gate electrode 130. Therefore, the sacrificial gate stack (SGS, see...) Figure 13D It can be transformed into a gate stack GS.

[0119] However, because the etchant used in the replacement process may not completely remove the molding layer 130M located in the dummy region DR (see... Figure 13B Therefore, a portion of the molding layer 130M can be retained as a dummy molding layer 131 on the sidewall of some dummy structure 161.

[0120] Return to reference Figure 4 An upper insulating layer 150 can be formed on the gate stack GS, and a bit line contact BLC can be formed through the upper insulating layer 150. Next, a bit line BL electrically connected to the bit line contact BLC and a conductive line ML electrically connected to the contact plug CNT can be formed on the upper insulating layer 150. In other words, by performing the above process, the integrated circuit device 100 according to an embodiment of the present invention can be completed.

[0121] Figure 14 This is a diagram illustrating an electronic system 1000 including an integrated circuit device according to some embodiments of the present invention.

[0122] Reference Figure 14 The electronic system 1000 according to the embodiment may include an integrated circuit device 1100 and a controller 1200 electrically connected to the integrated circuit device 1100.

[0123] Electronic system 1000 may include a storage device having one or more integrated circuit devices 1100 or an electronic device including a storage device. For example, electronic system 1000 may include a solid-state drive (SSD) device, a universal serial bus (USB) device, a computing system, a medical device, or a communication device that includes at least one integrated circuit device 1100.

[0124] Integrated circuit device 1100 may include a non-volatile vertical memory device. For example, integrated circuit device 1100 may include a device containing the above-referenced... Figures 3 to 10 The NAND flash memory device is at least one of the described integrated circuit devices 100, 200, 300, and 400. Integrated circuit device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F. In some embodiments, the first structure 1100F may be disposed on one side of the second structure 1100S.

[0125] The first structure 1100F may include a peripheral circuit structure, which includes a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. The second structure 1100S may include a memory cell structure, which includes a bit line BL, a common-source line CSL, multiple word lines WL, a first gate upper line UL1 and a second gate upper line UL2, a first gate lower line LL1 and a second gate lower line LL2, and multiple memory cell strings CSTR between the bit line BL and the common-source line CSL.

[0126] In the second structure 1100S, each of the plurality of memory cell strings CSTRs may include a plurality of lower transistors LT1 and LT2 adjacent to the common source line CSL, a plurality of upper transistors UT1 and UT2 adjacent to the bit line BL, and a plurality of memory cell transistors MCTs disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of lower transistors LT1 and LT2 and the number of upper transistors UT1 and UT2 may be varied in different embodiments according to the present invention.

[0127] In some embodiments, upper transistors UT1 and UT2 may include string select transistors, and lower transistors LT1 and LT2 may include ground select transistors. A first lower gate line LL1 and a second lower gate line LL2 may be the gate electrodes of lower transistors LT1 and LT2, respectively. A word line WL may be the gate electrode of a memory cell transistor MCT, and a first upper gate line UL1 and a second upper gate line UL2 may be the gate electrodes of upper transistors UT1 and UT2, respectively.

[0128] The common-source line CSL, the first lower gate line LL1 and the second lower gate line LL2, multiple word lines WL, and the first upper gate line UL1 and the second upper gate line UL2 can be electrically connected to the decoder circuit 1110 via multiple first connection wirings 1115 extending upward from the interior of the first structure 1100F to the second structure 1100S. Multiple bit lines BL can be electrically connected to the page buffer 1120 via multiple second connection wirings 1125 extending upward from the interior of the first structure 1100F to the second structure 1100S.

[0129] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 can perform control operations on at least one of the plurality of memory cell transistors (MCTs). The decoder circuit 1110 and the page buffer 1120 can be controlled by logic circuit 1130.

[0130] Integrated circuit device 1100 can communicate with controller 1200 via input / output (I / O) pads 1101 electrically connected to logic circuit 1130. I / O pads 1101 can be electrically connected to logic circuit 1130 via I / O connection wiring 1135 extending upward from the interior of first structure 1100F to second structure 1100S.

[0131] The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface (I / F) 1230. In some embodiments, the electronic system 1000 may include a plurality of integrated circuit devices 1100, in which case the controller 1200 may control the plurality of integrated circuit devices 1100.

[0132] Processor 1210 can control the overall operation of electronic system 1000, including controller 1200. Processor 1210 can operate on firmware and can control NAND controller 1220 to access integrated circuit device 1100. NAND controller 1220 may include NAND interface 1221, which manages communication with integrated circuit device 1100. Control commands for controlling integrated circuit device 1100, data to be written into multiple memory cell transistors (MCTs) of integrated circuit device 1100, and data to be read from multiple memory cell transistors (MCTs) of integrated circuit device 1100 can be transferred through NAND interface 1221. Host interface 1230 can provide communication functionality between electronic system 1000 and external host. When a control command is received from an external host through host interface 1230, processor 1210 can control integrated circuit device 1100 in response to the control command.

[0133] Figure 15 This is a perspective view illustrating an electronic system 2000 including an integrated circuit device according to some embodiments of the present invention.

[0134] Reference Figure 15 The electronic system 2000 according to the embodiment may include a motherboard 2001, a controller 2002 mounted on the motherboard 2001, one or more semiconductor packages 2003 and DRAM 2004.

[0135] The motherboard 2001 may include a connector 2006, which includes a plurality of pins coupled to an external host. The number and arrangement of the pins in the connector 2006 may vary based on the communication interface between the electronic system 2000 and the external host. In some embodiments, the electronic system 2000 may communicate with the external host via one or more interfaces, such as USB, Peripheral Component Interconnect High Speed ​​(PCI-Express), Serial Advanced Technology Attachment (SATA), and M-Phy for Universal Flash Storage (UFS). In some embodiments, the electronic system 2000 may operate based on power supplied from the external host via the connector 2006. The electronic system 2000 may also include a power management integrated circuit (PMIC) that distributes power supplied from the external host to a controller 2002 and a semiconductor package 2003. The semiconductor package 2003 and DRAM 2004 may be connected to the controller 2002 via a plurality of wiring patterns 2005 disposed on the motherboard 2001.

[0136] The controller 2002 can write data into or read data from the semiconductor package 2003, and can improve the operating speed of the electronic system 2000.

[0137] DRAM 2004 may include a buffer memory for reducing the speed difference between an external host and semiconductor package 2003; the buffer memory is a data storage space. DRAM 2004 included in electronic system 2000 can operate as a cache memory and can provide space for arbitrarily storing data during control operations performed on semiconductor package 2003. When DRAM 2004 is included in electronic system 2000, controller 2002 may also include a DRAM controller for controlling DRAM 2004, in addition to a NAND controller for controlling semiconductor package 2003.

[0138] Semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b, which are separated from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a semiconductor package having a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, a plurality of semiconductor chips 2200 on the package substrate 2100, an adhesive layer 2300 disposed on the bottom surface of each of the plurality of semiconductor chips 2200, a connection structure 2400 electrically connecting the plurality of semiconductor chips 2200 to the package substrate 2100, and a molding layer 2500 on the package substrate 2100 and covering at least partially the plurality of semiconductor chips 2200 and the connection structure 2400.

[0139] The package substrate 2100 may include a printed circuit board (PCB) including a plurality of package-on-pads 2130. Each of the plurality of semiconductor chips 2200 may include an I / O pad 2201. The I / O pad 2201 may correspond to Figure 14 I / O pad 1101. Each of the plurality of semiconductor chips 2200 may include a plurality of gate stacks 3210 and a plurality of channel structures 3220. Each of the plurality of semiconductor chips 2200 may include the above-referenced Figures 3 to 10 At least one of the described integrated circuit devices 100, 200, 300 and 400.

[0140] In some embodiments, the connection structure 2400 may include bonding wires electrically connecting I / O pads 2201 to pads 2130 on the package. Therefore, in the first semiconductor package 2003a and the second semiconductor package 2003b, a plurality of semiconductor chips 2200 may be electrically connected to each other via bonding wires and to the pads 2130 on the package substrate 2100. In some embodiments, in the first semiconductor package 2003a and the second semiconductor package 2003b, a plurality of semiconductor chips 2200 may be electrically connected to each other via a connection structure including through-silicon vias (TSVs) instead of a bonding wire-based connection structure 2400.

[0141] In some embodiments, the controller 2002 and the plurality of semiconductor chips 2200 may be included in a package. In some embodiments, the controller 2002 and the plurality of semiconductor chips 2200 may be mounted on a separate insertion substrate different from the motherboard 2001, and the controller 2002 and the plurality of semiconductor chips 2200 may be electrically connected to each other via wiring formed on the insertion substrate.

[0142] Figure 16 and Figure 17 These are cross-sectional views illustrating semiconductor packages 3003 and 4003, each including an integrated circuit device, according to some embodiments of the present invention.

[0143] In detail, Figure 16 and Figure 17 In the middle, it is shown that along Figure 15 The configuration of the sectional view intercepted by line A-A'.

[0144] Reference Figure 16 In the semiconductor package 3003, the package substrate 2100 may include a PCB.

[0145] The package substrate 2100 may include a body portion 2120 and a plurality of package pads 2130 disposed on the upper surface of the body portion 2120 (see...). Figure 15 Multiple lower pads 2125 arranged on or exposed through the bottom surface of the main body 2120, and multiple internal wirings 2135 electrically connecting multiple upper pads 2130 to the multiple lower pads 2125 in the main body 2120. The multiple upper pads 2130 can be electrically connected to multiple connection structures 2400 (see...). Figure 15 Multiple lower pads 2125 can be connected to multiple conductive connection portions 2800. Figure 15 Multiple wiring patterns 2005 on the motherboard 2001 of the electronic system 2000 shown.

[0146] Each of the plurality of semiconductor chips 2200 may include a semiconductor substrate 3010, a first structure 3100 and a second structure 3200 stacked sequentially on the semiconductor substrate 3010. The first structure 3100 may include a peripheral circuit region having a plurality of peripheral wirings 3110. The first structure 3100 may include as referenced above. Figure 8 The peripheral circuit transistor 60TR is described. In the accompanying drawings, the first structure 3100 is shown to have features such as... Figure 8 The diagram shows the structure of the peripheral circuit region of the integrated circuit device 200. However, embodiments of the present invention are not limited thereto.

[0147] The second structure 3200 may include a common source line 3205, a gate stack 3210 on the common source line 3205, a channel structure 3220 passing through the gate stack 3210, and a bit line 3240 electrically connected to the channel structure 3220. The gate stack 3210 may include... Figure 9The first gate stack GS1 and the second gate stack GS2 are shown. The first gate stack GS1 and the second gate stack GS2 may include a plurality of gate electrodes 130. In addition, each of the plurality of semiconductor chips 2200 may include a plurality of contact plugs CNTs electrically connected to the gate electrodes 130.

[0148] Each of the plurality of semiconductor chips 2200 may include a through-wire 3245 electrically connected to a plurality of peripheral wirings 3110 of the first structure 3100 and extending into the interior of the second structure 3200. The through-wire 3245 may be disposed outside the gate stack 3210. In other embodiments, the semiconductor package 3003 may also include through-wires passing through the gate stack 3210. Each of the plurality of semiconductor chips 2200 may also include I / O pads 2201 electrically connected to the plurality of peripheral wirings 3110 of the first structure 3100 (see...). Figure 15 ).

[0149] Reference Figure 17 The configuration of semiconductor package 4003 is similar to that of reference. Figure 16 The semiconductor package 3003 is configured as described. However, the semiconductor package 4003 includes a plurality of semiconductor chips 2200a.

[0150] Each of the plurality of semiconductor chips 2200a may include a semiconductor substrate 4010, a first structure 4100 on the semiconductor substrate 4010 and a second structure 4200 on the first structure 4100, the second structure 4200 being bonded to the first structure 4100 by a wafer bonding method.

[0151] The first structure 4100 may include a peripheral circuit region, which includes peripheral wiring 4110 and a plurality of first bonding structures 4150. (See reference...) Figure 8 As described, the first structure 4100 may include a peripheral circuit transistor 60TR. In the accompanying drawings, the first structure 4100 is shown to have... Figure 8 The peripheral circuit region of the integrated circuit device 200 shown has the same structure. However, embodiments of the present invention are not limited thereto.

[0152] The second structure 4200 may include a common source line 4205, a gate stack 4210 between the common source line 4205 and the first structure 4100, and a channel structure 4220 passing through the gate stack 4210. The gate stack 4210 may include... Figure 9 The first gate stack GS1 and the second gate stack GS2 are shown. The first gate stack GS1 and the second gate stack GS2 may include a plurality of gate electrodes 130. In addition, each of the plurality of semiconductor chips 2200a may include a plurality of contact plugs CNTs electrically connected to the gate electrodes 130.

[0153] Additionally, each of the plurality of semiconductor chips 2200a may include a plurality of second bonding structures 4250, each electrically connected to a plurality of gate electrodes 130 of the gate stack 4210. For example, some of the plurality of second bonding structures 4250 may be configured to be connected to a bit line 4240 electrically connected to a channel structure 4220. Other of the plurality of second bonding structures 4250 may be configured to be electrically connected to the gate electrodes 130 via a plurality of contact plugs CNTs.

[0154] The plurality of first bonding structures 4150 of the first structure 4100 and the plurality of second bonding structures 4250 of the second structure 4200 can be bonded to each other while being physically in contact with each other. The bonding portions of the plurality of first bonding structures 4150 and the plurality of second bonding structures 4250 may include metal (e.g., copper (Cu)), but embodiments of the present invention are not limited thereto.

[0155] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made herein without departing from the spirit and scope of the appended claims.

Claims

1. An integrated circuit device, comprising: A semiconductor substrate having a cell region and a dummy region located outside the cell region; Multiple gate electrodes and multiple insulating layers are located in the cell region, extending in a first direction and a second direction parallel to the main surface of the semiconductor substrate, and alternately stacked in a third direction perpendicular to the main surface of the semiconductor substrate, wherein the first direction and the second direction intersect each other; Multiple dummy molding layers and multiple dummy insulating layers are alternately stacked in the dummy region in the third direction; Multiple channel structures that pass through the multiple gate electrodes and the multiple insulating layers in the cell region; as well as Multiple dummy structures that pass through the multiple dummy molding layers and the multiple dummy insulating layers in the dummy region. The plurality of dummy molding layers are arranged at the same horizontal height as the plurality of gate electrodes in the third direction. Wherein, the plurality of dummy insulating layers are arranged at the same horizontal height as the plurality of insulating layers in the third direction, and Wherein, the carbon concentration of the upper dummy molding layer among the plurality of dummy molding layers is less than the carbon concentration of the lower dummy molding layer among the plurality of dummy molding layers, and the lower dummy molding layer is located between the upper dummy molding layer and the main surface of the semiconductor substrate.

2. The integrated circuit device according to claim 1, wherein, The carbon concentration of the upper dummy molding layer is 0% to 80% of the carbon concentration of the lower dummy molding layer.

3. The integrated circuit device according to claim 1, wherein, In the dummy region, the carbon concentration of the plurality of dummy molding layers and the plurality of dummy insulating layers is distributed in a sinusoidal form from the main surface of the semiconductor substrate in the third direction.

4. The integrated circuit device according to claim 1, wherein, Carbon and hydrogen exist as impurities at the interface between the plurality of gate electrodes and the plurality of insulating layers.

5. The integrated circuit device according to claim 1, wherein, In at least one of the plurality of dummy molding layers, the carbon concentration at each of the upper and lower interfaces of the at least one dummy molding layer is greater than the carbon concentration at the central portion of the at least one dummy molding layer.

6. The integrated circuit device according to claim 5, wherein, The carbon concentration at the upper interface of the at least one dummy molding layer is greater than the carbon concentration at the lower interface of the at least one dummy molding layer, and the lower interface of the at least one dummy molding layer is between the upper interface of the at least one dummy molding layer and the main surface of the semiconductor substrate.

7. The integrated circuit device according to claim 5, wherein, The carbon concentration at the upper interface of the at least one dummy molding layer is five times or more the carbon concentration at the central portion of the at least one dummy molding layer, and the lower interface of the at least one dummy molding layer is between the upper interface of the at least one dummy molding layer and the main surface of the semiconductor substrate.

8. The integrated circuit device according to claim 1, wherein, The distance between adjacent channel structures in the plurality of channel structures is less than the distance between adjacent dummy structures in the plurality of dummy structures.

9. The integrated circuit device according to claim 1, wherein, Each of the plurality of gate electrodes includes a first conductive material. At least some portions of the sidewalls of the plurality of dummy molded layers are in physical contact with the first conductive material.

10. The integrated circuit device according to claim 1, wherein, The plurality of gate electrodes and the plurality of insulating layers constitute a gate stack. The integrated circuit device further includes a peripheral circuit structure disposed between the semiconductor substrate and the gate stack.

11. An integrated circuit device, comprising: A semiconductor substrate having cell regions and dummy regions; Multiple gate electrodes and multiple insulating layers are alternately stacked in the cell region in a direction perpendicular to the main surface of the semiconductor substrate; Multiple dummy molding layers and multiple dummy insulating layers are alternately stacked in the dummy region in the direction perpendicular to the main surface of the semiconductor substrate; as well as The vias and dummy vias are provided, wherein the vias pass through the plurality of gate electrodes and the plurality of insulating layers in the cell region, and the dummy vias pass through the plurality of dummy molding layers and the plurality of dummy insulating layers in the dummy region. In at least one of the plurality of dummy molding layers, the carbon concentration at each of the upper and lower interfaces of the at least one dummy molding layer is greater than the carbon concentration at the central portion of the at least one dummy molding layer.

12. The integrated circuit device according to claim 11, wherein, The upper interface of the at least one dummy molding layer is the surface where the lower surface of the first dummy insulating layer and the upper surface of the at least one dummy molding layer are physically in contact with each other. The lower interface of the at least one dummy molding layer is the surface where the lower surface of the at least one dummy molding layer and the upper surface of the second dummy insulating layer among the plurality of dummy insulating layers are in physical contact with each other.

13. The integrated circuit device according to claim 11, wherein, The plurality of dummy molding layers are arranged at the same horizontal height as the plurality of gate electrodes in the direction perpendicular to the main surface of the semiconductor substrate, and The carbon concentration of the upper dummy molding layer among the plurality of dummy molding layers is less than the carbon concentration of the lower dummy molding layer among the plurality of dummy molding layers, and the lower dummy molding layer is located between the upper dummy molding layer and the main surface of the semiconductor substrate.

14. The integrated circuit device according to claim 13, wherein, In the cell region and the dummy region, an annealing process utilizing ultraviolet light is performed at the horizontal height where the upper dummy molding layer is arranged, in the direction perpendicular to the main surface of the semiconductor substrate.

15. The integrated circuit device according to claim 13, wherein, In the cell region and the dummy region, an oxygen-utilizing plasma process is performed at the horizontal height where the upper dummy molding layer is arranged, in the direction perpendicular to the main surface of the semiconductor substrate.

16. The integrated circuit device according to claim 11, wherein, The plurality of insulating layers and the plurality of dummy insulating layers comprise the same material. The plurality of dummy molding layers include materials different from those of the plurality of dummy insulating layers. The plurality of gate electrodes comprise a conductive material, and The sidewalls of the plurality of dummy molded layers are in physical contact with the conductive material.

17. The integrated circuit device according to claim 11, wherein, The channel hole and the dummy hole each have a tapered column shape whose width narrows from their upper region to their lower region, the lower region being between the upper region and the main surface of the semiconductor substrate.

18. The integrated circuit device of claim 11, further comprising: A circuit substrate having peripheral circuitry and a first bonding pad located above the peripheral circuitry; as well as The second bonding pad is disposed above the plurality of gate electrodes and the plurality of insulating layers. The first bonding pad and the second bonding pad are in physical contact with each other.

19. An electronic system comprising: Main substrate; An integrated circuit device located on the main substrate; as well as The controller is electrically connected to the integrated circuit device on the main substrate. The integrated circuit device includes: A semiconductor substrate having a cell region and a dummy region located outside the cell region; Multiple gate electrodes and multiple insulating layers are located in the cell region, extending in a first direction and a second direction parallel to the main surface of the semiconductor substrate, and alternately stacked in a third direction perpendicular to the main surface of the semiconductor substrate, wherein the first direction and the second direction intersect each other; Multiple dummy molding layers and multiple dummy insulating layers are alternately stacked in the dummy region in the third direction; Multiple channel structures that pass through the multiple gate electrodes and the multiple insulating layers in the cell region; and Multiple dummy structures that pass through the multiple dummy molding layers and the multiple dummy insulating layers in the dummy region. The plurality of dummy molding layers are arranged at the same horizontal height as the plurality of gate electrodes in the third direction. Wherein, the plurality of dummy insulating layers are arranged at the same horizontal height as the plurality of insulating layers in the third direction, and Wherein, the carbon concentration of the upper dummy molding layer among the plurality of dummy molding layers is less than the carbon concentration of the lower dummy molding layer among the plurality of dummy molding layers, and the lower dummy molding layer is located between the upper dummy molding layer and the main surface of the semiconductor substrate.

20. The electronic system according to claim 19, wherein, The main substrate includes a wiring pattern that electrically connects the integrated circuit device to the controller. In the dummy region, the carbon concentration of the plurality of dummy molding layers and the plurality of dummy insulating layers is distributed in a sinusoidal form from the main surface of the semiconductor substrate in the third direction.

Images