Image sensing device

Abstract

An image sensing device can include a substrate including a photoelectric conversion layer configured to generate a photocharge corresponding to an intensity of incident light in response to the incident light; a plurality of doped regions disposed along a migration path of the photocharge and doped with a dopant at different doping concentrations; and a gate dielectric layer disposed above the substrate and having a gate dielectric layer portion overlapping the plurality of doped regions, the gate dielectric layer portion having a varying thickness that increases along the migration path of the photocharge.

Description

Technical Field

[0001] The techniques and implementations disclosed in this patent document generally relate to an image sensing device including pixels, said pixels including transistors configured to transmit photocharge to sensing nodes. Background Technology

[0002] Image sensing devices are used to capture optical images by converting light into electrical signals using photosensitive semiconductor materials that react to light. With the development of the automotive, medical, computer, and communications industries, the demand for high-performance image sensing devices is increasing in various fields such as smartphones, digital cameras, game consoles, IoT (Internet of Things), robotics, security cameras, and medical miniature cameras.

[0003] Image sensing devices can be broadly categorized into CCD (Charge-Coupled Device) image sensing devices and CMOS (Complementary Metal-Oxide-Semiconductor) image sensing devices. CCD image sensing devices offer better image quality, but they tend to consume more power and are larger in size compared to CMOS image sensing devices. CMOS image sensing devices are smaller and consume less power than CCD image sensing devices. Furthermore, CMOS sensors are manufactured using CMOS fabrication technology, allowing photosensitive elements and other signal processing circuitry to be integrated onto a single chip, enabling the production of miniaturized image sensing devices at a lower cost. For these reasons, CMOS image sensing devices are being developed for many applications, including mobile devices. Summary of the Invention

[0004] Various embodiments of the disclosed technology relate to image sensing devices with enhanced photocharge transfer characteristics.

[0005] In one embodiment, an image sensing device may include: a substrate including a photoelectric conversion layer configured to generate photocharge corresponding to the intensity of incident light in response to incident light; a plurality of doped regions disposed along a photocharge migration path and doped with dopants of different doping concentrations; and a gate dielectric layer disposed above the substrate and having gate dielectric layer portions overlapping the plurality of doped regions, the gate dielectric layer portions having a varying thickness that increases along the photocharge migration path.

[0006] In one embodiment, an image sensing device may include: a first region disposed in a substrate and configured to generate photocharge in response to incident light; a second region and a third region disposed along a photocharge migration path and having a doping concentration decreasing along the photocharge migration path; a fourth region configured to accumulate photocharge transmitted through the second and third regions; and a gate dielectric layer having portions overlapping the second and third regions, said portions having a thickness increasing along the photocharge migration path.

[0007] According to the implementation of the disclosed technology, the thickness of the gate dielectric layer can be adjusted along the direction of photocharge migration, which can reduce dark current and improve photocharge transport efficiency.

[0008] In addition, various effects can be provided that can be understood directly or indirectly through this document. Attached Figure Description

[0009] Figure 1 This is a block diagram illustrating an image sensing device according to an embodiment of the disclosed technology.

[0010] Figure 2 This is an example Figure 1 The diagram shows an implementation of the pixels included in the pixel array.

[0011] Figure 3 This is an example Figure 2 A diagram illustrating an embodiment of the cross-section of the pixel shown.

[0012] Figure 4 This is an example Figure 2 A diagram of another embodiment of the cross-section of the pixel shown.

[0013] Figure 5 This is a diagram illustrating the potential distribution during the photocharge transport period in the comparative example.

[0014] Figure 6 This is a graph illustrating the potential distribution during the photocharge transport period in an embodiment of the disclosed technology. Detailed Implementation

[0015] This patent document provides implementations and examples of an image sensing device including pixels with adjustable sensitivity, which essentially solves one or more problems caused by limitations and drawbacks of related technologies. Some implementations of the disclosed technology involve an image sensing device in which pixels with adjustable sensitivity are efficiently arranged. The disclosed technology provides various implementations of an image sensing device capable of obtaining the capacitance required for a low-sensitivity mode by changing the pixel layout structure without increasing the size of each pixel or using capacitors that may generate noise.

[0016] Embodiments of the disclosed technology will now be described in detail, with examples of embodiments shown in the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the drawings to refer to the same or similar components. While this disclosure is readily adaptable to various modifications and alternatives, specific embodiments are illustrated by way of example in the accompanying drawings.

[0017] Figure 1 This is a block diagram illustrating an image sensing device 100 according to an embodiment of the disclosed technology.

[0018] Reference Figure 1 The image sensing device 100 may include a pixel array 110, a row driver 120, a correlated dual sampler (CDS) 130, an analog-to-digital converter (ADC) 140, an output buffer 150, a column driver 160, and a timing controller 170. This is discussed by way of example only. Figure 1 The components of the image sensing device 100 shown are described, and this patent document covers many other changes, substitutions, variations, alterations and modifications.

[0019] Pixel array 110 may include a plurality of unit imaging pixels arranged in rows and columns. In one example, the plurality of unit imaging pixels may be arranged as a two-dimensional pixel array including rows and columns. In another example, the plurality of unit imaging pixels may be arranged as a three-dimensional pixel array. The plurality of unit imaging pixels may convert optical signals into electrical signals on a unit pixel basis or on a pixel group basis, wherein unit pixels in a pixel group share at least certain internal circuitry. Pixel array 110 may receive drive signals including a row selection signal, a pixel reset signal, and a transmission signal from row driver 120. Once the drive signals are received, the corresponding unit imaging pixels in pixel array 110 may be activated to perform operations corresponding to the row selection signal, pixel reset signal, and transmission signal.

[0020] The row driver 120 can activate the pixel array 110 to perform specific operations on imaging pixels in a corresponding row based on command and control signals provided by a controller circuit such as a timing controller 170. In some implementations, the row driver 120 can select one or more imaging pixels arranged in one or more rows of the pixel array 110. The row driver 120 can generate a row selection signal to select one or more rows among a plurality of rows. The row driver 120 can sequentially enable a pixel reset signal for resetting the imaging pixel corresponding to at least one selected row and a transmission signal for the pixel corresponding to at least one selected row. Thus, a reference signal and an image signal, which are analog signals generated by each imaging pixel of the selected row, can be sequentially transmitted to the CDS 130. The reference signal can be an electrical signal provided to the CDS 130 when the sensing node (e.g., a floating diffusion node) of the imaging pixel is reset, while the image signal can be an electrical signal provided to the CDS 130 when photocharge generated by the imaging pixel accumulates in the sensing node. The reference signal, indicating the unique reset noise of each pixel, and the image signal, indicating the incident light intensity, can be collectively referred to as pixel signals as needed.

[0021] CMOS image sensors can use Correlated Double Sampling (CDS) to eliminate the difference between two samples by sampling the pixel signal twice, thereby removing unwanted pixel offset values ​​known as fixed-pattern noise. In one example, Correlated Double Sampling (CDS) removes unwanted pixel offset values ​​by comparing the pixel output voltage obtained before and after the photocharge generated by the incident light accumulates in the sensing node, making it possible to measure only the pixel output voltage based on the incident light. In some embodiments of the disclosed art, CDS 130 can sequentially sample and hold the voltage levels of the reference signal and the image signal provided from the pixel array 110 to each of the multiple column lines. That is, CDS 130 can sample and hold the voltage levels of the reference signal and the image signal corresponding to each column of the pixel array 110.

[0022] In some implementations, CDS 130 can transmit the reference signal and image signal of each column as correlated double-sampled signals to ADC 140 based on control signals from timing controller 170.

[0023] ADC 140 is used to convert analog CDS signals into digital signals. In some implementations, ADC 140 can be implemented as a ramp-comparison type ADC. A ramp-comparison type ADC may include comparator circuitry for comparing analog pixel signals with a reference signal such as a ramp signal that is rising or falling, and a timer for counting until the voltage of the ramp signal matches the analog pixel signal. In some embodiments of the disclosed art, ADC 140 may convert the correlated double-sampled signals generated by CDS 130 for each column into digital signals and output such digital signals. ADC 140 may perform counting and calculation operations based on the correlated double-sampled signals for each column and the ramp signal provided from timing controller 170. In this way, ADC 140 may eliminate or reduce noise such as reset noise generated from imaging pixels when generating digital image data.

[0024] The ADC 140 may include multiple column counters. Each column of the pixel array 110 is coupled to a column counter, and image data can be generated by converting the correlated double-sampled signals received from each column into digital signals using the column counters. In another embodiment of the disclosed technology, the ADC 140 may include a global counter to convert the correlated double-sampled signals corresponding to columns into digital signals using a global code provided from the global counter.

[0025] Output buffer 150 can temporarily hold column-based image data provided from ADC 140 for output image data. In one example, output buffer 150 outputs image data provided from ADC 140 and stored in output buffer 150 based on control signals from timing controller 170. Output buffer 150 can provide an interface to compensate for data rate or transmission rate differences between image sensing device 100 and other devices.

[0026] Once a control signal is received from the timing controller 170, the column driver 160 can select a column of the output buffer and sequentially output the image data temporarily stored in the selected column of the output buffer 150. In some implementations, once an address signal is received from the timing controller 170, the column driver 160 can generate a column selection signal based on the address signal and select a column of the output buffer 150, outputting image data from the selected column of the output buffer 150 as an output signal.

[0027] The timing controller 170 can control the operation of the row driver 120, ADC 140, output buffer 150 and column driver 160.

[0028] The timing controller 170 can provide the row driver 120, CDS 130, ADC 140, output buffer 150, and column driver 160 with clock signals required for the operation of the various components of the image sensing device 100, control signals for timing control, and address signals for selecting rows or columns. In embodiments disclosed in the art, the timing controller 170 may include logic control circuitry, phase-locked loop (PLL) circuitry, timing control circuitry, communication interface circuitry, etc.

[0029] Figure 2 This is an example Figure 1 A diagram illustrating an implementation of the pixels included in the pixel array shown.

[0030] Reference Figure 2 Pixel 200 corresponds to Figure 1 The pixel array 110 includes one implementation of a unit pixel that can convert the intensity of incident light into an electrical signal. Pixel 200 may be a color-sensing pixel configured to convert the intensity of incident light corresponding to a specific wavelength (e.g., red, blue, or green) into an electrical signal, or a distance-sensing pixel configured to convert the intensity of modulated light reflected from and incident on a target object into an electrical signal. In this implementation, pixel 200 corresponds to a color-sensing pixel having a 4-TR (transistor) structure. However, other implementations are also possible, and the disclosed techniques can be applied to various pixels, each including a transfer transistor configured to transfer photocharge generated from a photoelectric conversion element in response to light intensity to a floating diffusion region.

[0031] Pixel 200 may include photoelectric conversion element PD, transmission transistor TX, floating diffusion region FD, reset transistor RX, drive transistor DX, and selection transistor SX.

[0032] A photoelectric conversion element (PD) can be connected between a ground terminal and a transmission transistor (TX), and generates and accumulates photocharge corresponding to the intensity of incident light based on the photoelectric effect. The ground terminal can be a terminal configured to provide a ground voltage. The photoelectric conversion element (PD) can be implemented as a photodiode, phototransistor, photogate, pinned photodiode, or a combination thereof. Figure 2 In this example, a photodiode is exemplified as a photoelectric conversion element PD. The photocharge accumulated by the photoelectric conversion element PD can be transferred to the floating diffusion region FD via the transfer transistor TX.

[0033] A transfer transistor TX can be connected between the photoelectric conversion element PD and the floating diffusion region FD, and is turned on according to the transfer signal TG applied to its gate. When the transfer signal TG has an activation voltage (or a logic high level), the transfer transistor TX can conduct to transfer the photocharge accumulated in the photoelectric conversion element PD to the floating diffusion region FD. When the transfer signal TG has an inactive voltage (or a logic low level), the transfer transistor TX can be turned off to prevent the transfer of the photocharge accumulated in the photoelectric conversion element PD to the floating diffusion region FD.

[0034] The floating diffusion region (FD) can be configured to store photocharge, enabling the photocharge to be converted into a voltage. The floating diffusion region (FD) can be implemented as a junction capacitor. For example, the floating diffusion region (FD) can be doped with impurities of a second conductivity type (e.g., n-type) within a substrate having a first conductivity type (e.g., p-type).

[0035] A reset transistor RX can be connected between the power supply voltage VDD and the floating diffusion region FD, and is turned on according to a pixel reset signal RG applied to its gate. The power supply voltage VDD can indicate a predetermined voltage (e.g., 2.5V) supplied to the pixel array 110. When the pixel reset signal RG has an active voltage (or a logic high level), the reset transistor RX can be turned on to discharge the accumulated photocharge in the floating diffusion region FD as the power supply voltage VDD, thereby resetting the floating diffusion region FD to the power supply voltage VDD. When the pixel reset signal RG has an inactive voltage (or a logic low level), the reset transistor RX can be turned off to electrically isolate the floating diffusion region FD from the power supply voltage VDD.

[0036] The driving transistor DX can be connected between the power supply voltage VDD and the selection transistor SX, and has a gate connected to the floating diffusion region FD. Therefore, the driving transistor DX can transmit an electrical signal to the selection transistor SX corresponding to the potential of the floating diffusion region FD.

[0037] The select transistor SX can perform the function of selecting the pixels to be read in units of rows of the pixel array 110. The select transistor SX can be turned on according to the row select signal SEL applied to its gate, and output an electrical signal as an output voltage Vout, which is provided by the drive transistor DX and corresponds to the potential of the floating diffusion region FD.

[0038] Pixel 200 can operate in multiple operation periods. In implementations, the multiple operation periods may include a reset period, a first readout period, a photocharge accumulation period, a photocharge transfer period, and a second readout period. Multiple operation periods can be processed sequentially, or at least some operation periods can be processed simultaneously in parallel. In some implementations, the multiple operation periods can be modified in various ways.

[0039] The reset period indicates the time during which the floating diffusion region FD is reset to the power supply voltage VDD. During the reset period, the reset transistor RX can be turned on to reset the floating diffusion region FD to the power supply voltage VDD. At this time, the transfer transistor TX can also be turned on to transfer the photocharge accumulated in the photoelectric conversion element PD to the floating diffusion region FD, thereby discharging the photocharge.

[0040] The first readout period indicates the time during which an electrical signal corresponding to the potential of the reset floating diffusion region FD is output as the output voltage Vout. That is, the first readout period can occur immediately after the reset period. During the first readout period, the selection transistor SX can be turned on. The output voltage Vout output during the first readout period can indicate a reference... Figure 1 The reference signal described.

[0041] The photocharge accumulation period indicates the time during which the photoelectric conversion element (PD) generates and accumulates photocharge in response to the intensity of incident light. During the photocharge accumulation period, the transmission transistor (TX) can be turned off, allowing the photocharge generated by the photoelectric conversion element (PD) to accumulate within the PD.

[0042] The photocharge transfer period indicates the time during which the photocharge accumulated in the photoelectric conversion element PD is transferred to the floating diffusion region FD via the transfer transistor TX. During the photocharge transfer period, the reset transistor RX can be turned off, and the transfer transistor TX can be turned on, causing the photocharge accumulated in the photoelectric conversion element PD to migrate and accumulate in the floating diffusion region FD.

[0043] The second readout period can be specified as the period during which an electrical signal corresponding to the potential of the floating diffusion region FD, where photocharge has accumulated, is output as the output voltage Vout. That is, the second readout period can be executed immediately after the photocharge transfer period. During the second readout period, the selection transistor SX can be turned on. The output voltage Vout output during the second readout period can indicate a reference... Figure 1 The image signal described.

[0044] Figure 3 This is an example Figure 2 A diagram illustrating an embodiment of the cross-section of the pixel shown.

[0045] Figure 3 Examples include Figure 2 The image sensing device shown has a cross-section 300 consisting of a photoelectric conversion element PD, a transmission transistor TX, and a floating diffusion region FD.

[0046] Referring to section 300, the image sensing device may include a substrate 310, a photoelectric conversion layer 320, a pinning layer 330, a floating diffusion region 340, a gate dielectric layer 350, and a gate 360. The photoelectric conversion layer 320 and the pinning layer 330 may correspond to photoelectric conversion elements PD, the floating diffusion region 340 may correspond to floating diffusion regions FD, and the gate dielectric layer 350 and the gate 360 ​​may correspond to the gate of a transmission transistor TX. The gate dielectric layer 350 and the gate 360 ​​may be formed or disposed in a wiring layer above the substrate 310. The pinning layer 330 and the floating diffusion region 340 may respectively correspond to the two ends of the transmission transistor TX.

[0047] The substrate 310 may have a front side and a back side. Figure 3 The top surface of the substrate 310 shown can represent the front side, while the bottom surface of the substrate 310 can represent the back side. The pixel 200 can have a back illumination structure that receives incident light through the back side or a front illumination structure that receives incident light through the front side.

[0048] The substrate 310 may be formed as a p substrate or a p epitaxial layer obtained by epitaxially growing p-type impurities in the p substrate, and includes a photoelectric conversion layer 320, a pinning layer 330 and a floating diffusion region 340 as impurity layers doped in the substrate 310.

[0049] The photoelectric conversion layer 320 can absorb incident light and generate and accumulate photocharge 325 corresponding to the intensity of the incident light. The photoelectric conversion layer 320 can be a region doped with n-type impurities or include regions doped with n-type impurities.

[0050] The pinning layer 330 may be or include a region along the surface (e.g., the front side) of the substrate 310 doped with a higher concentration of p-type impurities than the substrate 310, and is used to suppress the generation of dark current. The pinning layer 330 may be formed between the surface of the substrate 310 and the photoelectric conversion layer 320. In some implementations, the pinning layer 330 has substantially the same width as the photoelectric conversion layer 320. In some implementations, the pinning layer 330 has an area substantially corresponding to that of the photoelectric conversion layer 320. In some implementations, either the photoelectric conversion layer 320 or the pinning layer 330 may have a wider width than the other. At least a portion of the pinning layer 330 may overlap with the gate dielectric layer 350 and the gate 360 ​​forming the transmission transistor TX.

[0051] Dark currents, generated by the defect electron flow during the etching process, can flow on the surface of substrate 310, thus producing unexpected noise. When the pinning layer 330 is not formed and the photoelectric conversion layer 320 is abutting against or close to the surface of substrate 310, the photocharge 325 of the photoelectric conversion layer 320 can contribute to the dark current, thereby generating noise in the pixel signal. Specifically, under low-brightness conditions with relatively low incident light intensity, this noise can primarily affect the pixel signal.

[0052] By forming a pinning layer 330 on the surface of the substrate 310, the holes in the pinning layer 330 can suppress the flow of defect electrons, thereby reducing dark current. Increasing the doping concentration of the pinning layer 330 can improve the dark current reduction effect. However, if the doping degree of the pinning layer 330 is too high and the doping concentration difference between the pinning layer 330 and the region in which the channel of the transport transistor TX is formed (i.e., the region between the pinning layer 330 and the floating diffusion region 340) increases significantly, the efficiency of transferring the photocharge 325 of the photoelectric conversion layer 320 to the channel of the transport transistor TX through the pinning layer 330 may decrease, thereby degrading the hysteresis characteristics of the transport transistor TX.

[0053] Therefore, in the implementation of the disclosed technology, the pinning layer 330 can be divided into a first doped region 332, a second doped region 334, a third doped region 336, and a fourth doped region 338. The first doped region 332 to the third doped region 336 can overlap with the gate dielectric layer 350, and the fourth doped region 338 can be non-overlapping with the gate dielectric layer 350.

[0054] Among the first doped regions 332 to the fourth doped regions 338, the fourth doped region 338 may have the highest impurity doping concentration, and the impurity doping concentration can decrease from the first doped region 332 to the third doped region 336. In some implementations, the impurity doping concentration can decrease in a stepwise manner from the first doped region 332 to the third doped region 336. The third doped region 336 may have a higher doping concentration than the substrate 310. When the transmission transistor TX is turned on, the photocharge 325 of the photoelectric conversion layer 320 can be transmitted through... Figure 3 The migration path shown is directed toward the floating diffusion region 340. Therefore, the photocharge 325 can migrate through the internal region of the pinning layer 330 that overlaps with the gate 360 ​​of the transport transistor TX. Since the first doped regions 332 to the third doped regions 336 arranged along the migration path have doping concentrations that decrease, for example, in a stepped manner, the hysteresis characteristics of the transport transistor TX can be improved. Furthermore, the fourth doped region 338, located away from the migration path of the photocharge 325, can have the highest doping concentration, thereby further improving the dark current reduction effect of the pinning layer 330.

[0055] Figure 3An embodiment is illustrated where the pinning layer 330 is formed into four regions with different doping concentrations. However, the number of regions with different doping concentrations in the pinning layer 330 is not limited to four, and other implementations are also possible. Therefore, the pinning layer 330 may include N regions with different doping concentrations, where N is a positive integer other than 4.

[0056] The floating diffusion region 340 may be formed in a substrate 310 containing a first conductivity type (p-type) impurity and doped with a second conductivity type (n-type) impurity. The floating diffusion region 340 may have a junction capacitance associated with the substrate 310 and accumulate photocharge 325 transmitted through the channel of the transmission transistor TX. At least a portion of the floating diffusion region 340 may overlap with each of the gate dielectric layer 350 and the gate 360 ​​forming the transmission transistor TX.

[0057] The gate dielectric layer 350 electrically isolates the gate 360 ​​abutting against the gate dielectric layer 350 from the substrate 310, the pinning layer 330, and the floating diffusion region 340. In some implementations, the gate dielectric layer 350 may be or include an oxide layer. In some implementations, other dielectric materials besides oxide layers may be used to implant the gate dielectric layer 350.

[0058] One side of the gate dielectric layer 350 may overlap with the floating diffusion region 340, while the other side of the gate dielectric layer 350 may overlap with the pinning layer 330.

[0059] The gate dielectric layer 350 may include a first dielectric region 352, a second dielectric region 354, and a third dielectric region 356 with different thicknesses. In some implementations, the gate dielectric layer 350 may have a thickness that increases along the migration path of the photocharge 325. In some implementations, the thickness of the gate dielectric layer may increase in a stepped manner, but other implementations are also feasible. Figure 3 In the implementation shown, the first dielectric region 352 to the third dielectric region 356 and the floating diffusion region 340 can be arranged in a direction parallel to the surface of the substrate 310.

[0060] The first dielectric region 352 may overlap with the first doped region 332 and has a first thickness T1. The second dielectric region 354 may overlap with the second doped region 334 and has a second thickness T2 greater than the first thickness T1. The third dielectric region 356 may overlap with the third doped region 336, the substrate 310, and the floating diffusion region 340 and has a third thickness T3 greater than the second thickness T2.

[0061] Gate 360 ​​may be disposed above the first dielectric region 352 to the third dielectric region 356 and configured to receive a transmission signal TG. Since the first dielectric region 352 to the third dielectric region 356 have different thicknesses, the transmission signal TG applied to gate 360 ​​affects the pinning of photocharge at different levels, as discussed below.

[0062] During the photocharge accumulation period, gate 360 ​​can receive a transmission signal TG having a first voltage. The first voltage can correspond to a deactivation voltage that turns off the transmission transistor TX. For example, the first voltage can be a negative voltage. In an embodiment, the deactivation voltage used for transmitting the signal TG during periods other than the photocharge accumulation period can be a ground voltage.

[0063] When a first voltage is applied to the gate 360, holes within the pinning layer 330 can accumulate (or pin) around the boundary between the pinning layer 330 and the gate dielectric layer 350, thereby reducing dark current. Since the doping concentration increases from the third doped region 336 to the first doped region 332, the number of holes increases from the first doped region 332 to the third doped region 336. The thickness of the gate dielectric layer 350 decreases from the third dielectric region 356 towards the first dielectric region 352; therefore, the voltage applied to the gate 360 ​​acts more strongly on the first doped region 332 compared to the third doped region 336. Because the voltage acts more strongly on the first doped region 332, which has more holes than the second doped region 334 and the third doped region 336, where relatively fewer holes exist, the holes from the first doped region 332 to the third doped region 336 can be effectively pinned. If the gate dielectric layer 350 has a single thickness (e.g., T3), holes may not be effectively pinned in regions containing a relatively large number of holes (e.g., the region corresponding to the first doped region 332), which may result in dark current.

[0064] In some implementations, a microlens (not shown) can be disposed below the photoconversion layer 320 to converge incident light toward the center of the photoconversion layer 320. Due to the microlens, photocharge 325 can be concentrated around the center of the photoconversion layer 320. By reducing the thickness of the gate dielectric layer 350 from the third dielectric region 356 toward the first dielectric region 352 relatively close to the center of the photoconversion layer 320, holes can be effectively pinned by the gate 360 ​​into the first doped region 332 relatively close to the center of the photoconversion layer 320. Therefore, dark current generated by the photocharge 325 concentrated around the center of the photoconversion layer 320 can be reduced.

[0065] During the photocharge transfer period, gate 360 ​​can receive a transfer signal TG with a second voltage. The second voltage can correspond to the activation voltage that turns on the transfer transistor TX. For example, the second voltage can be a positive voltage.

[0066] When a second voltage is applied to the gate 360, the photocharge 325 accumulated in the photoconversion layer 320 can be drawn upwards to the pinning layer 330 and pass through the pinning layer 330. Then, the photocharge 325 can migrate to the floating diffusion region 340 through the channel of the transport transistor TX formed below the gate dielectric layer 350 between the pinning layer 330 and the floating diffusion region 340.

[0067] As described above, due to the microlens, the photocharge 325 can be concentrated and accumulated around the center of the photoelectric conversion layer 320. The thickness of the gate dielectric layer 350 can be reduced from the third dielectric region 356 toward the first dielectric region 352, which is relatively close to the center of the photoelectric conversion layer 320, so that the photocharge 325 that converges at the center of the photoelectric conversion layer 320 through the gate 360 ​​can be effectively drawn upward toward the pinning layer 330.

[0068] As described above, the first doped regions 332 to the third doped regions 336 can have doping concentrations that decrease, for example, in a stepped manner, to improve the hysteresis characteristics of the transmission transistor TX. Therefore, the first doped regions 332 to the third doped regions 336 can have potentials that decrease, for example, in a stepped manner. The first doped region 332, with a relatively high doping concentration, can have a higher potential than the photoconversion layer 320, thereby forming a potential pocket to interrupt the smooth migration of photocharge 325 from the photoconversion layer 320 to the first doped region 332. However, according to an embodiment, a first dielectric region 352 having a first thickness T1 less than the third thickness T3 can be disposed above the first doped region 332, thereby increasing the influence of the gate voltage 360. Therefore, the potential of the first doped region 332 can be reduced to eliminate the potential pocket. Furthermore, to prevent the formation of a potential pocket between the second doped region 334 and the first doped region 332 whose potential is reduced by the first dielectric region 352 having a first thickness T1, a second dielectric region 354 having a second thickness T2 less than the third thickness T3 can be disposed above the second doped region 334, thereby reducing the potential of the second doped region 334. Additionally, the second thickness T2 can be set to a value greater than the first thickness T1, such that no potential pocket is formed between the third doped region 336 and the second doped region 334 whose potential is reduced by the second dielectric region 354 having a second thickness T2. Therefore, the first thickness T1 to the third thickness T3 can be determined experimentally to prevent the formation of a potential pocket in the migration path of the photocharge 325 without degrading the hysteresis characteristics of the transmission transistor TX.

[0069] According to the embodiment, the pinning layer overlapping the gate of the transmission transistor TX can be formed with a doping concentration that decreases, for example, toward the floating diffusion region 340 in a stepped manner, and its thickness can be provided to be, for example, an increase toward the floating diffusion region 340 in a stepped manner to correspond to the concentration of the pinning layer of the gate dielectric layer, so as to reduce dark current and improve photocharge transport efficiency.

[0070] Gate 360 ​​can receive the transmission signal TG and control the potential of the lower region of gate dielectric layer 350. In some implementations, gate 360 ​​can be a polysilicon electrode or a metal electrode. Other implementations are also possible, so gate 360 ​​can be implemented in various ways.

[0071] Figure 4 This is an example Figure 2 A diagram illustrating another embodiment of the cross-section of a pixel.

[0072] Figure 4 It shows including Figure 2 The image sensing device shown has a cross-section 400 consisting of a photoelectric conversion element PD, a transmission transistor TX, and a floating diffusion region FD.

[0073] Referring to section 400, the image sensing device may include a substrate 410, a photoelectric conversion layer 420, a pinning layer 430, a floating diffusion region 440, a gate dielectric layer 450, a gate 460, and a silicon region 470. The photoelectric conversion layer 420 and the pinning layer 430 may correspond to photoelectric conversion elements PD, the floating diffusion region 440 may correspond to floating diffusion regions FD, and the gate dielectric layer 450 and the gate 460 may correspond to the gate of a transmission transistor TX. The pinning layer 430 and the floating diffusion region 440 may respectively correspond to the two ends of the transmission transistor TX.

[0074] The floating diffusion region 440, the gate dielectric layer 450, the gate 460, and the silicon region 470 can be formed or disposed in the wiring layer above the substrate 410.

[0075] Because the functions, structures, and materials of the substrate 410, photoelectric conversion layer 420, pinning layer 430, floating diffusion region 440, gate dielectric layer 450, and gate 460 are similar to those already referenced... Figure 3 The substrate 310, photoelectric conversion layer 320, pinning layer 330, floating diffusion region 340, gate dielectric layer 350 and gate 360 ​​described are similar in function, structure and material, so the following description will focus on the differences between them.

[0076] In section 400, the floating diffusion region 440 may not be formed in the substrate 410, but rather formed above the substrate 410 and spaced apart from it. In this implementation, since the floating diffusion region 440 and the channel of the transmission transistor TX are disposed above the substrate 410 rather than in the substrate 410, the photoelectric conversion layer 420 can occupy a larger area, thereby improving the photoelectric conversion efficiency.

[0077] The pinning layer 430 can be formed across a region between one surface of the substrate 410 and the photoelectric conversion layer 420. The size (or area) of the pinning layer 430 can correspond to the size (or area) of the photoelectric conversion layer 420. In some implementations, with Figure 3 Unlike the pinning layer 330, the pinning layer 430 can have a constant doping concentration. In some implementations, the pinning layer 430 can have different portions with different doping concentrations. For example, the pinning layer 430 may include a first impurity region formed below the bottom of the silicon region 470 and having a first doping concentration, and a second impurity region that does not overlap with the silicon region 470 and has a second doping concentration different from the first doping concentration. In some implementations, the first doping concentration may be lower than the second doping concentration. In some implementations, the second impurity region may be located near the edge of the silicon region 470 or at other locations. By using pinning layers 430 with different doping concentrations, it is possible to prevent the degradation of the hysteresis characteristics of the transmission transistor TX.

[0078] A floating diffusion region 440 can be formed above the substrate 410, spaced apart from the substrate 410 by a predetermined distance. The floating diffusion region 440 can be configured to overlap with the central axis of the photoelectric conversion layer 420 or the optical axis of the microlens (not shown) to focus the incident light onto the photoelectric conversion layer 420. Since the photocharge 425 converges at the center of the photoelectric conversion layer 420, this is to improve the photocharge transport efficiency by setting the floating diffusion region 440 near the area where the photocharge 425 converges.

[0079] A silicon region 470 may be disposed between the pinning layer 430 formed in the substrate 410 and the floating diffusion region 440 formed above the substrate 410.

[0080] Silicon region 470 can form a channel according to the operation of the transfer transistor TX, enabling the transfer of photocharge 425 accumulated in photoconversion layer 420 to floating diffusion region 440. When the transfer transistor TX is turned on, the channel can be formed adjacent to dielectric regions 452, 454, and 456 located on the side of silicon region 470. To form such a channel, silicon region 470 may include impurities of a first conductivity type (e.g., p-type).

[0081] The silicon region 470 may be surrounded by a gate dielectric layer 450. Although not shown, in a plan view, the gate dielectric layer 450 may have an annular shape surrounding at least part or all of the silicon region 470.

[0082] Silicon region 470 may include a first doped region 472, a second doped region 474, and a third doped region 476. The first doped region 472 to the third doped region 476 may be doped with impurities of different doping concentrations and have, for example, a doping concentration that decreases in a stepwise manner from the first doped region 472 to the third doped region 476, which allows for improvement of the hysteresis characteristics of the transmission transistor TX.

[0083] The gate dielectric layer 450 can electrically isolate the gate 460 from the substrate 410, the pinning layer 430, and the silicon region 470. The gate dielectric layer 450 may include a first dielectric region 452, a second dielectric region 454, a third dielectric region 456, and a fourth dielectric region 458.

[0084] The first dielectric region 452 to the third dielectric region 456 can be stacked between the pinned layer 430 and the floating diffusion region 440, and have different thicknesses. Figure 4 In the implementation shown, the first dielectric region 452 to the third dielectric region 456 and the floating diffusion region 440 can be disposed in a vertical direction perpendicular to the surface of the substrate 410.

[0085] The first dielectric region 452 may overlap with the first doped region 472 and has a fourth thickness T4. The second dielectric region 454 may overlap with the second doped region 474 and has a fifth thickness T5 greater than the fourth thickness T4. The third dielectric region 456 may overlap with the third doped region 476 and has a sixth thickness T6 greater than the fifth thickness T5. Therefore, the width of the silicon region 470 can decrease from the first doped region 472 toward the third doped region 476.

[0086] A gate 460 configured to receive a transmission signal TG can be positioned to abut against the side surfaces of the first dielectric region 452 to the third dielectric region 456. A silicon region 470 is configured to be surrounded by the first dielectric region 452 to the third dielectric region 456, and the effect of the voltage applied to the gate 460 can be increased as the respective dielectric regions have a smaller thickness.

[0087] The fourth dielectric region 458 can be disposed between the gate 460 and the pinning layer 430, and has the same fourth thickness as the first dielectric region 452. However, other implementations are also possible.

[0088] During the photocharge accumulation period, gate 460 can receive a transmission signal TG with a first voltage. The first voltage can correspond to the deactivation voltage that turns off the transmission transistor TX. For example, the first voltage can be a negative voltage.

[0089] When a first voltage is applied to the gate 460, holes in the pinned layer 430 can accumulate (or pin) around the boundary between the pinned layer 430 and the gate dielectric layer 450, thereby reducing dark current.

[0090] The floating diffusion region 440 can receive a positive bias voltage to increase the potential of the floating diffusion region 440, so that the photocharge 425 of the photoelectric conversion layer 420 does not migrate to the floating diffusion region 440 during the photocharge accumulation period.

[0091] During the photocharge transfer period, gate 460 can receive a transfer signal TG with a second voltage. The second voltage can correspond to the activation voltage that turns on the transfer transistor TX. For example, the second voltage can be a positive voltage.

[0092] When the second voltage is applied to the gate 460, the photocharge 425 accumulated in the photoconversion layer 420 can be drawn upward to the pinning layer 430 and pass through the pinning layer 430. Then, the photocharge 425 can migrate to the floating diffusion region 440 through the channel of the transport transistor TX formed in the silicon region 470 inside the gate dielectric layer 450.

[0093] The floating diffusion region 440 can receive a negative bias voltage to reduce the potential of the floating diffusion region 440, so that the photocharge 425 of the photoelectric conversion layer 420 can smoothly migrate to the floating diffusion region 440 during the photocharge transmission period.

[0094] As described above, the first doped region 472 to the third doped region 476 can have a doping concentration that decreases in a stepped manner to improve the hysteresis characteristics of the transmission transistor TX. Therefore, the first doped region 472 to the third doped region 476 can have a potential that decreases in a stepped manner. In this case, the first doped region 472, with a relatively high doping concentration, can have a higher potential than the photoconversion layer 420 and the pinning layer 430, thereby forming a potential pocket to interrupt the smooth migration of photocharge 425 from the photoconversion layer 420 to the first doped region 472. However, according to an embodiment, a first dielectric region 452 having a fourth thickness T4 less than the sixth thickness T6 can be provided on the side surface of the first doped region 472, increasing the influence of the gate voltage 460. Therefore, the potential of the first doped region 472 can be reduced to remove the potential pocket. Furthermore, to prevent the formation of a potential pocket between the second doped region 474 and the first doped region 472 whose potential is reduced by the first dielectric region 452 having a fourth thickness T4, a second dielectric region 454 having a fifth thickness T5 less than a sixth thickness T6 can be disposed on the side surface of the second doped region 474, thereby reducing the potential of the second doped region 474. Moreover, the fifth thickness T5 can be set to a value greater than the fourth thickness T4, such that no potential pocket is formed between the third doped region 476 and the second doped region 474 whose potential is reduced by the second dielectric region 454 having a fifth thickness T5. That is, the fourth thickness T4 to the sixth thickness T6 can be determined experimentally to prevent the formation of a potential pocket in the migration path of the photocharge 425 without degrading the hysteresis characteristics of the transmission transistor TX.

[0095] According to the embodiment, the silicon region 470 overlapping with the gate of the transmission transistor TX can be formed with a doping concentration that decreases toward the floating diffusion region 440 in a stepped manner, and a gate dielectric layer with a thickness that increases toward the floating diffusion region 440 in a stepped manner to correspond to the concentration of the silicon region 470 can be provided to improve the photocharge transport efficiency.

[0096] The gate 460 can receive the transmission signal TG and control the potential of the bottom and side regions of the gate dielectric layer 450. The gate 460 can be a polysilicon electrode or a metal electrode, but other implementations are also feasible.

[0097] Figure 5 This illustrates when... Figure 3 or Figure 4 The graphs shown depict the potential distribution during the photocharge transport period when the gate dielectric layer 350 or 450 has a uniform thickness (e.g., T3 or T6) (hereinafter referred to as the Comparative Example). Figure 6 This illustrates when the gate dielectric layer 350 or 450 has a structure based on, for example... Figure 3 or Figure 4 The graph shown illustrates the potential distribution during the photocharge transport period when the thickness varies.

[0098] Figure 5 The first region ① to the fifth region ⑤ shown can correspond to Figure 3 and Figure 4 The first region ① to the fifth region ⑤ are shown in the diagram. Therefore, the first region ① may correspond to the photoelectric conversion layer 320 or 420, the second region ② may correspond to the region 332 or 472 with a relatively high doping concentration, the third region ③ may correspond to the region 334 or 474 with a medium doping concentration, the fourth region ④ may correspond to the region 336 or 476 with a relatively low doping concentration, and the fifth region ⑤ may correspond to the floating diffusion region 340 or 440.

[0099] Figure 5 The potential distribution shown corresponds to the case where the transmission signal TG applied to the transmission transistor TX has an activation voltage. Therefore, based on the transmission signal TG with the activation voltage, the photocharge accumulated in the first region ① can be transferred to the fifth region ⑤ through the second region ② to the fourth region ④.

[0100] In order to improve the hysteresis characteristics of the transmission transistor TX, the second region ② to the fourth region ④ can have a doping concentration that decreases in a stepwise manner, and thus have a potential that decreases in a stepwise manner.

[0101] In the comparative example, since the second region ②, with its relatively high doping concentration, can have a higher potential than the first region ①, a potential pocket can be formed to interrupt the smooth migration of photocharge from the first region ① to the second region ②. Due to the potential pocket, some photocharge may remain in the first region ①, thereby generating noise in the pixel signal.

[0102] Figure 6 Examples are shown where the gate dielectric layer 350 or 450 has the following characteristics: Figure 3 or Figure 4 In the implementation, the potential distribution during the photocharge transport period corresponds to the case where the thickness increases in a stepped manner, for example, in the direction of photocharge migration.

[0103] A dielectric region 352 or 452 with a relatively small thickness can be configured to overlap with the second region ②, thereby increasing the influence of the voltage on the gate 360 ​​or 460. Therefore, the potential of the second region ② can be reduced to eliminate potential pockets. Furthermore, the thickness of the dielectric region 354 or 454 overlapping with the third region ③ can be adjusted to have a potential that decreases in a stepped manner from the second region ② to the fourth region ④, thereby improving the hysteresis characteristics of the transmission transistor TX.

[0104] Under the control of the timing controller 170, the line driver 120 generates and provides... Figures 2 to 6 The control signals for the pixels described herein (e.g., transmission signal TG, pixel reset signal RG, row selection signal SEL, positive bias or negative bias, etc.).

[0105] Although various embodiments have been described above, variations and other embodiments of the described embodiments can be made based on the content disclosed / exemplified in this patent document.

[0106] Cross-references to related applications

[0107] This patent document claims priority and benefit to Korean Application No. 10-2021-0020218, filed with the Korean Intellectual Property Office on February 16, 2021, the entire contents of which are incorporated herein by reference.

Claims

1. An image sensing device, the image sensing device comprising: A substrate comprising a photoelectric conversion layer that generates a photocharge corresponding to the intensity of the incident light in response to incident light; Multiple doped regions are arranged along the migration path of the photocharge and are doped with dopants of different doping concentrations; A gate dielectric layer disposed above the substrate and having a gate dielectric layer portion overlapping the plurality of doped regions, the gate dielectric layer portion having a varying thickness that increases along the migration path of the photocharge; as well as A gate, which is disposed on the gate dielectric layer and overlaps with a portion of the plurality of doped regions. Wherein, the doping concentration of the portion of the plurality of doped regions overlapping with the gate decreases in a stepwise manner along the migration path of the photocharge, and Wherein, the portion of the plurality of doped regions overlapping with the gate overlaps with the portion of the gate dielectric layer whose thickness decreases in a stepwise manner in the opposite direction of the migration path of the photocharge, such that the effect of the voltage applied to the gate increases as the gate dielectric layer has a smaller thickness, thereby reducing the potential of the portion of the plurality of doped regions.

2. The image sensing device according to claim 1, wherein, The plurality of doped regions include a first doped region, a second doped region, and a third doped region disposed along the migration path of the photocharge, and The gate dielectric layer includes a first dielectric region overlapping with the first doped region, a second dielectric region overlapping with the second doped region, and a third dielectric region overlapping with the third doped region.

3. The image sensing device according to claim 2, wherein, The first dielectric region has a first thickness that is smaller than the thickness of the second dielectric region, and The second dielectric region has a second thickness that is less than the thickness of the third dielectric region.

4. The image sensing device according to claim 2, wherein, The first doped region has a first doping concentration that is higher than that of the second doped region, and The second doped region has a second doping concentration that is higher than that of the third doped region.

5. The image sensing device according to claim 2, wherein, The gate receives a transmission signal for transferring the photocharge to the floating diffusion region to accumulate the photocharge. The first dielectric region to the third dielectric region abut against the gate.

6. The image sensing device according to claim 5, wherein, During the photocharge accumulation period when the photocharge is generated and accumulated in the photoconversion layer, the transmission signal supplied to the gate has a negative voltage that turns off the transmission transistor.

7. The image sensing device according to claim 5, wherein, During the photocharge transfer period, which involves transferring the photocharge from the photoconversion layer to the floating diffusion region, the transfer signal supplied to the gate has a positive voltage that turns on the transfer transistor.

8. The image sensing device according to claim 2, wherein, The first to the third doped regions are included in a pinning layer disposed between the photoelectric conversion layer and one surface of the substrate.

9. The image sensing device according to claim 8, wherein, The pinning layer has an area corresponding to that of the photoelectric conversion layer.

10. The image sensing device according to claim 8, wherein, The pinning layer further includes a fourth doped region that does not overlap with the gate dielectric layer, and The fourth doped region has a higher doping concentration than the first doped region.

11. The image sensing device according to claim 8, wherein, The third doped region has a higher doping concentration than the substrate.

12. The image sensing device according to claim 2, wherein, The first to the third doped regions are included in a silicon region disposed between the photoelectric conversion layer and a floating diffusion region spaced at a predetermined distance from a surface of the substrate.

13. The image sensing device according to claim 12, wherein, The silicon region is surrounded by the gate dielectric layer.

14. The image sensing device according to claim 12, wherein, The silicon region has a width that decreases from the first doped region to the third doped region.

15. The image sensing device according to claim 12, wherein, During the photocharge accumulation period when the photocharge is generated and accumulated in the photoelectric conversion layer, the floating diffusion region receives a positive bias voltage so that the photocharge does not migrate to the floating diffusion region.

16. The image sensing device according to claim 12, wherein, During the photocharge transmission period when the photocharge is transmitted from the photoelectric conversion layer to the floating diffusion region, the floating diffusion region receives a negative bias voltage so that the photocharge migrates smoothly to the floating diffusion region.

17. An image sensing device, the image sensing device comprising: A first region is disposed in the substrate and generates photocharge in response to incident light; The second and third regions are arranged along the migration path of the photocharge and have a doping concentration that decreases in a stepwise manner along the migration path of the photocharge. A fourth region is configured to accumulate photocharge transmitted through the second and third regions; A gate dielectric layer having a portion overlapping the second region and the third region, the portion of the gate dielectric layer having a thickness that increases along the migration path of the photocharge; as well as A gate electrode is disposed on the gate dielectric layer and overlaps with the second region and the third region. Wherein, the second region and the third region overlapping with the gate overlap with the portion of the gate dielectric layer whose thickness decreases in the stepwise direction in the opposite direction of the migration path of the photocharge, such that the effect of the voltage applied to the gate increases as the gate dielectric layer has a smaller thickness, thereby reducing the potential of the second region and the third region.

18. The image sensing device according to claim 17, wherein, The first region and the second region are constructed and connected such that during the photocharge transport period from the photoelectric conversion element to the floating diffusion region, the first region has a higher potential than the second region.

19. The image sensing apparatus according to claim 17, wherein, The second region, the third region, and the fourth region are arranged along a direction parallel to the surface of the substrate.

20. The image sensing device according to claim 17, wherein, The second region, the third region, and the fourth region are arranged along a direction perpendicular to the surface of the substrate.

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