Noise reduction circuit for voltage regulator

Abstract

A voltage regulator circuit includes a regulator output, an amplifier activated in response to a first signal and deactivated in response to a second signal, an error amplifier having a first input to receive a reference voltage, a second input to receive a feedback voltage, and an output generating a difference with respect to the reference voltage and the feedback voltage, an active discharge transistor discharging a current electronic signal at the regulator output in response to a falling slope of the electronic signal, and a first switch at the output of the amplifier in an open state in response to receipt of the second signal to open a coupling capacitor path between the regulator output and the reference voltage to cancel an effect of noise on the reference voltage in response to the falling slope of the electronic signal.

Description

Technical Field

[0001] This disclosure generally relates to an integrated electronic semiconductor device including a voltage regulator, and more specifically, to a circuit that minimizes noise at the regulator output without affecting the reference voltage at the voltage regulator input. Background Technology

[0002] Electronic devices, and virtually every device, contain voltage regulators to control and regulate the voltage from the power source to the load, especially to provide circuitry for monitoring and limiting the current to the load. In modern electronic devices, multiple regulators can be implemented as integrated circuits (ICs) on a computer chip. Here, multiple regulators may share a reference voltage. It is desirable that the output of any one of the multiple regulators does not affect the reference voltage; for example, the reference voltage should not change due to recoil noise. Summary of the Invention

[0003] As will be understood, the disclosed embodiments include at least the following embodiments. In one embodiment, a power management integrated circuit includes: a voltage regulator circuit, the voltage regulator circuit including: a regulator output, the regulator output outputting an electronic signal having a rising slope and a falling slope; a differential error amplifier, the differential error amplifier being activated in response to a first signal and deactivated in response to a second signal, the differential error amplifier having a first input for receiving a reference voltage, a second input for receiving a feedback voltage, and generating a differential output with respect to the reference voltage and the feedback voltage in response to the first signal; an active discharge transistor, the active discharge transistor discharging the current electronic signal at the regulator output in response to the falling slope of the electronic signal; and a first switch at the output of the differential error amplifier, the first switch being in an open state in response to receiving the second signal to disconnect the coupling capacitor path between the regulator output and the reference voltage, thereby canceling the effect of noise on the reference voltage in response to the falling slope of the electronic signal; and a load circuit electrically coupled to the regulator output, the load circuit receiving a regulated voltage corresponding to the reference voltage with a reduced noise source.

[0004] Alternative embodiments of power management integrated circuits include one or any combination of the following features.

[0005] The power management integrated circuit further includes a second switch having a gate terminal coupled to the output of the differential error amplifier, a source terminal sharing a common input voltage with the differential error amplifier, and a drain terminal coupled between the first switch and the regulator output. The second switch (204) includes a power metal-oxide-semiconductor field-effect transistor (MOSFET).

[0006] The power management integrated circuit further includes a feedback circuit comprising a voltage divider and a feedforward capacitor, the feedforward capacitor generating a feedback signal, the feedback signal being output to the differential error amplifier for controlling the output based on the difference between the reference voltage and the feedback signal.

[0007] The voltage divider includes a first resistor and a second resistor, used to adjust the output of the differential error amplifier to a voltage greater than or equal to the reference voltage.

[0008] The feedforward capacitor is coupled between the positive input of the differential error amplifier and the junction between the first and second resistors, in parallel with the first resistor of the voltage divider, which is also coupled to the positive input of the differential error amplifier.

[0009] The feedforward capacitor helps to reduce the slope of the electronic signal without affecting the reference voltage.

[0010] The voltage regulator circuit further includes a capacitor and a resistor connected in parallel with the first switch and the voltage divider, which are coupled in series, wherein the active discharge transistor discharges the capacitor when the voltage regulator circuit is deactivated.

[0011] The power management integrated circuit further includes a coupling capacitor path between the regulator output and the reference voltage, the coupling capacitor path including the feedforward capacitor and the first resistor connected to the second input of the differential error amplifier, wherein the coupling capacitor path is disconnected by the first switch before the regulator output is discharged by the active charging transistor.

[0012] The falling slope of the electronic signal affects the reference voltage through the feedforward capacitor and the internal parasitic capacitor between the first and second inputs of the amplifier, and wherein the reference voltage is unaffected by the output voltage when the first switch is in the open state.

[0013] In another embodiment, a voltage regulator circuit of a power management integrated circuit includes: a regulator output that outputs an electronic signal having a rising slope and a falling slope; a differential error amplifier that is activated in response to a first signal and deactivated in response to a second signal, the differential error amplifier having a first input for receiving a reference voltage, a second input for receiving a feedback voltage, and generating a differential output with respect to the reference voltage and the feedback voltage in response to the first signal; an active discharge transistor that discharges the current electronic signal at the regulator output in response to the falling slope of the electronic signal; a first switch at the output of the differential error amplifier that is open in response to receiving the second signal to disconnect a coupling capacitor path between the regulator output and the reference voltage, thereby canceling the effect of noise on the reference voltage in response to the falling slope of the electronic signal; and a load circuit electrically coupled to the regulator output that receives a regulated voltage corresponding to the reference voltage with a reduced noise source.

[0014] Alternative embodiments of the voltage regulator circuit include one or any combination of the following features.

[0015] The voltage regulator circuit further includes a second switch having a gate terminal coupled to the output of the differential error amplifier, a source terminal sharing a common input voltage with the differential error amplifier, and a drain terminal coupled between the first switch and the regulator output. The second switch (204) includes a power metal-oxide-semiconductor field-effect transistor (MOSFET).

[0016] The voltage regulator circuit further includes a feedback circuit, which includes a voltage divider and a feedforward capacitor. The feedforward capacitor generates a feedback signal, which is output to the differential error amplifier for controlling the output based on the difference between the reference voltage and the feedback signal.

[0017] The voltage divider includes a first resistor and a second resistor, used to adjust the output of the differential error amplifier to a voltage greater than or equal to the reference voltage.

[0018] The feedforward capacitor is coupled between the positive input of the differential error amplifier and the junction between the first and second resistors, in parallel with the first resistor of the voltage divider, which is also coupled to the positive input of the differential error amplifier.

[0019] The feedforward capacitor helps to reduce the slope of the electronic signal without affecting the reference voltage.

[0020] The voltage regulator circuit further includes a capacitor and a resistor connected in parallel with the first switch and the voltage divider, which are coupled in series, wherein the active discharge transistor discharges the capacitor when the voltage regulator circuit is deactivated.

[0021] The voltage regulator circuit further includes a coupling capacitor path between the regulator output and the reference voltage, the coupling capacitor path including the feedforward capacitor and the first resistor connected to the second input of the differential error amplifier, wherein the coupling capacitor path is disconnected by the first switch before the regulator output is discharged by the active charging transistor.

[0022] The falling slope of the electronic signal affects the reference voltage through the feedforward capacitor and the internal parasitic capacitor between the first and second inputs of the amplifier, and wherein the reference voltage is unaffected by the output voltage when the first switch is in the open state.

[0023] In another embodiment, a noise reduction method for a voltage regulator circuit includes: disabling the voltage regulator circuit; turning a first switch at the output of the voltage regulator circuit to a turn-off position; discharging an electronic signal through an active discharge transistor coupled to the output of the voltage regulator circuit; and disconnecting a coupling capacitor path between the output and a reference voltage at the input of the voltage regulator circuit before discharging the regulator output through an active charging transistor. Attached Figure Description

[0024] This invention is illustrated by way of example and is not limited to the accompanying drawings, in which similar reference numerals indicate similar elements. Elements in the drawings are shown for simplicity and clarity, and these elements are not necessarily drawn to scale.

[0025] Figure 1 It is a block diagram of a conventional integrated circuit that includes multiple voltage regulators communicating with the load circuit.

[0026] Figure 2 This is a schematic diagram of a power management integrated circuit (PMIC) including a voltage regulator circuit according to some embodiments.

[0027] Figure 3 This is a flowchart illustrating an example operating sequence for reducing backlash noise in an amplifier circuit according to some embodiments.

[0028] Figures 4A-4E Commonly, it is a sequence diagram, including descriptions Figure 2 The diagram shows a set of related waveforms representing the operation of the voltage regulator circuit. Detailed Implementation

[0029] The output voltage of a regulator in an integrated circuit can fluctuate due to noise, which can affect other regulators in parallel configurations and arrangements. For example... Figure 1 As shown, conventional integrated circuits include a reference voltage V shared from voltage reference circuit 112. REF Multiple voltage regulators 102, which regulate the voltage from the power supply and use the voltage as the output voltage V. OUT The output is given to load circuit 108, such as an analog-to-digital converter (ADC) circuit or other converters configured to provide a regulated DC output voltage to load circuit 108. However, noise may occur at the output of a particular voltage regulator 102, which can affect the reference voltage shared by the voltage regulators. Therefore, due to the presence of noise at the output of another voltage regulator, voltage regulator 102 may not be able to accurately process the received input reference voltage.

[0030] Various techniques are known for reducing noise from the output of a voltage regulator. One technique is to include a low-pass filter at the output of the voltage reference circuit 112 to mitigate noise from the output. However, this configuration does not eliminate unwanted noise.

[0031] Another technique involves adding buffers, which can be more effective than low-pass filters at eliminating noise from the output. However, in highly integrated, low-power chips, buffers require additional, unwanted power and chip resources, such as placement area. Other kickback noise reduction techniques also require additional circuitry; providing additional filters and buffers requires additional power consumption to draw additional bias current to mitigate noise from the load circuitry. Such circuitry at the regulator output also provides additional offset, which can further affect the accuracy of the circuitry, for example, by causing variations in the output voltage.

[0032] In simple terms, embodiments of the present invention include additional circuitry to eliminate noise from the output of the voltage regulator, which can be adapted to highly integrated computer chips with low power requirements and layout space. In this way, the voltage regulator can prevent or reduce signal interference in the load circuitry, and thus reduce the risk of instability in integrated electronic semiconductor devices that include one or more voltage regulator circuits, regardless of whether they share a common reference voltage.

[0033] Figure 2 This is a schematic diagram of a voltage regulator circuit 200 according to some embodiments. One application includes an implementation of a computer chip or related integrated circuit. For example, refer to... Figure 2The power management integrated circuit (PMIC) includes a voltage regulator circuit 200. The PMIC 10 may include a processor core, memory, input / output (I / O) components, and peripheral components (not shown), which receive signals for generating a reference voltage V. REF The PMIC 10 provides the power, activation signal ON, and other voltages for supplying power to the voltage regulator circuit 200. It can be implemented in various automotive, industrial, and consumer applications and performs a variety of voltage regulation functions. The voltage regulator circuit 200 is configured and arranged to control the load circuit (e.g., ...). Figure 1 The output of the load circuit 108 shown. In some embodiments, the voltage regulator circuit 200 includes an amplifier 202, a feedback circuit including a voltage divider 206 and a feedforward capacitor 208, a first switch 210, and an active discharge transistor 212.

[0034] In some embodiments, the first switch 210 may include transistors or the like that that can be turned on and off. The first switch 210 is activated when it receives a first signal (ON) corresponding to an ON state, and turned off when it receives a second signal (OFF). The first switch 210 has an input connected to the output (OUT) of the voltage regulator circuit 200. Therefore, when the regulator circuit 200 is in the OFF state, the first switch 210 is turned off to minimize noise from the output (OUT) of the voltage regulator circuit 200.

[0035] In some embodiments, amplifier 202 is a differential error amplifier, which has the capability to directly receive a reference voltage V. REF The amplifier 202 has an inverting input terminal and a non-inverting input terminal coupled to a voltage divider 206. In some embodiments, the voltage divider 206 includes resistors R1 and R2 for adjusting the output of the amplifier 202 to be greater than or equal to a reference voltage V. REF Any voltage, and provides a feedback signal, so that amplifier 202 can be adjusted according to the reference voltage V. REF The output of amplifier 202 is controlled by the difference between the input voltage and the feedback signal received at the non-inverting input. Amplifier 202 can amplify the input voltage using an amplification factor set according to the ratio of the first resistor R1 and the second resistor R2 of voltage divider 206 to the feedforward capacitor 208.

[0036] In some embodiments, amplifier 202 further includes a voltage source input 221 coupled to the drain of a second switch 204 (e.g., a MOSFET (Metal-O-Semiconductor Field-Effect Transistor)) and an on / off signal 222, as well as voltage sources providing a first signal (ON / OFF). The second switch 204 is located at the output of amplifier 202. Amplifier 202 controls the gate of the second switch 204 via a negative feedback loop extending from the output. In some embodiments, the second switch 204 includes a p-channel FET transistor or other power MOSFET circuitry biased directly from the input to the input voltage (VIN) of amplifier 202. In some embodiments, the gate of the second switch 204 may be based on a reference voltage V. REF The error voltage output is received from the differential amplifier 202 by the voltage difference between the voltage output from the feedback circuit, which includes resistors R1 and R2 of voltage divider 206 and feedforward capacitor 208.

[0037] Feedforward capacitor 208 is part of the feedback circuit and is configured and arranged to couple to the positive input of amplifier 202. Feedforward capacitor 208 is coupled to the junction between resistors R1 and R2 in parallel with resistor R1 of voltage divider 206, which is also coupled to the positive input of amplifier 202, to provide improved loop stability to the circuit. During operation, feedforward capacitor 208 contributes to the output drop slope. Feedforward capacitor 208 affects frequency stability and fast transient response during normal operation or load transients. In the absence of capacitor 208, loop frequency compensation and fast transient response are affected.

[0038] An active discharge transistor 212 may be coupled in parallel with capacitor 205 and resistor 207 between second switch 204 and regulator output OUT. The active discharge transistor 212 may discharge the capacitor in conjunction with voltage divider 206. In some embodiments, if second switch 204 is in the off state, active discharge transistor 212 may discharge capacitor 205 regardless of switch 210. When the regulator is off or in the OFF state, active discharge transistor 212 may discharge the output of regulator 200. In some embodiments, inverter 203 provides input to the gate of active discharge transistor 212, specifically inverting the ON signal that is also output to first switch 210 and amplifier 202. Therefore, inverter 203 inverts the ON signal to active discharge transistor 212. Thus, in some embodiments, when first switch 210 and amplifier 202 receive a '1' value for the ON signal, the gate of active discharge transistor 212 receives a '0' value. Additionally, when the regulator circuit 200 is deactivated, for example, when the first switch 210 and amplifier 202 receive the '0' value of the ON signal, the active discharge transistor 212 receives the '1' value and is activated, discharging the output of the regulator 200.

[0039] Figure 3 This is a flowchart illustrating an example sequence of operations for reducing recoil noise in an amplifier circuit according to some embodiments. Reference may be made when describing method 300. Figure 2 Voltage regulator circuit 200.

[0040] In box 302, turn off or deactivate regulator 200. Here, as... Figure 2 and 4B As shown, an ON signal is applied to amplifier 202, first switch 210, and inverter 203. When the ON signal is in a low state (e.g., 0 value), regulator 200 can be turned off.

[0041] In block 304, the first switch 210 is turned off, disconnected, or otherwise activated because the first switch 210 receives the same ON signal as the amplifier 202. Therefore, the amplifier 202 and the first switch 210 are deactivated simultaneously, as shown below. Figure 4B and 4C As shown. Conversely, when, for example, in Figures 4A-4E When the ON signal is high between the indicated times T1 and T4, amplifier 202 and first switch 210 are both active. Deactivate or deactivate first switch 210 to minimize noise from the output (OUT) of regulator 200.

[0042] In block 306, before the active charging transistor 212 discharges to the regulator output, the first switch 210 disconnects the output (OUT) from the reference voltage V.REF The coupling capacitor path between (during the time interval between T4 and T5, also see...) Figure 4C-4E For example, the coupling capacitor path includes a coupling capacitor 208 and a resistor R1 connected to the positive input of amplifier 202.

[0043] In block 308, after disconnecting the coupling capacitor and the R1 path, the active discharge transistor 212 discharges to the output (OUT) because the regulator 200 is turned off, for example... Figure 4C-4E The time period between T4 and T5 is shown.

[0044] In box 310, control is achieved via regulator 200, for example... Figure 4D The falling slope of the output (OUT) shown at time T4 causes the output falling slope to affect the reference voltage V through the feedforward capacitor 208 and the internal parasitic capacitance between the positive and negative inputs of the amplifier 202 during the discharge of the active charging transistor 212 when the regulator 200 is turned off. REF Here, the first switch 210 between the output (OUT) and the feedforward capacitor 208 is disconnected. Therefore, as... Figure 4E As shown in T5, during the disabled period, the falling slope of the electronic signal (e.g., the output voltage) at the regulator output (OUT) does not affect the reference voltage V. REF .

[0045] Figures 4A-4E Commonly includes instructions Figure 2 The timing diagram of the operation of the voltage regulator circuit 200 is as follows: Figure 4A As shown, at the reference voltage V REF The timing diagram is executed during the period when the level is constant high. Figure 4A Showing information about the reference voltage V REF There is no recoil noise. During the period when the first signal (ON) is output in the ON state at time T1, the first switch 210 is closed or otherwise activated to form an electronic connection path from the second switch 204 at the output of amplifier 202 to the voltage divider 206 and the output (OUT). Here, amplifier 202 is also turned on via the ON signal. Furthermore, in Figure 4D At time T2, as shown, the active discharge transistor 212 is turned off due to the time delay of inverter 203. (As...) Figure 4E As shown, at time T3, the rising slope of the output (OUT) appears. Here, amplifier 202 can control the slew rate of the output. When regulator 200 is activated, amplifier 202 is slowly enabled, and thus the delay time T2 and rise time T3 are determined by the slew rate of amplifier 202.

[0046] At time T4, the second output signal (OFF) or the first signal (ON) transitions to a low state. This disconnects or otherwise activates the first switch 210. During the period when the second output signal (OFF) is output (T4-T5), the disconnected first switch 210 disconnects the regulator output (OUT) from the reference voltage (V). REF The coupling capacitors and R1 path between the two circuits are, for example, RC circuits 206 and 208. Additionally, at time T5, the active discharge transistor 212 is turned on because the inverter 203 outputs a high value upon receiving the second signal (OFF). The inverter 203 causes a time delay (T4-T5). In response to the active discharge transistor 212 outputting a high value, the regulator output (OUT) transitions from a high state to a low state at T5. However, the falling slope of the signal at the output (OUT) or any noise generated at the output (OUT) does not affect the reference voltage (V). REF Instead of directly discharging the regulator output through the active discharge transistor 212, the first switch 210 disconnects the output (OUT) from the reference voltage (V). REF The coupling capacitors between the inputs and outputs and the path of R1. More specifically, in some embodiments, during discharge, the output drop slope affects the reference voltage (V) through the feedforward capacitor 208 and the internal parasitic capacitor between the positive and negative inputs of amplifier 202. REF In other words, the signal path extends from the output (OUT) to the active discharge transistor 212, and the path from the output (OUT) via capacitor 208 to the positive input of amplifier 202 is interrupted by the open first switch 210. Because the first switch 210 is open or closed, the falling slope of the output (OUT) during the disabled period does not affect the reference voltage (V). REF ).

[0047] While the invention has been described herein with reference to specific embodiments, various modifications and changes may be made without departing from the scope of the invention as set forth in the appended claims. Therefore, the specification and figures should be considered illustrative rather than restrictive, and all such modifications are contemplated to be included within the scope of the invention. It is not intended that any advantage, benefit, or solution to the problem described herein with respect to specific embodiments be construed as a critical, necessary, or essential feature or element of any or all claims.

[0048] Unless otherwise stated, terms such as “first” and “second” are used to arbitrarily distinguish the elements described by such terms. Therefore, these terms are not necessarily intended to indicate the temporal or other priority order of these elements.

Claims

1. A power management integrated circuit, characterized in that, include: Voltage regulator circuit, the voltage regulator circuit comprising: The regulator outputs an electronic signal with an upward slope and a downward slope. A differential error amplifier that is activated in response to a first signal and deactivated in response to a second signal, the differential error amplifier having a first input for receiving a reference voltage, a second input for receiving a feedback voltage, and a differential output that generates a difference between the reference voltage and the feedback voltage in response to the first signal; An active discharge transistor, which discharges at the regulator output in response to a first signal and a second signal; and A first switch coupled to the regulator output, the first switch being in an open state in response to the receipt of the second signal, thereby disconnecting the coupling capacitor path between the regulator output and the reference voltage, and thus counteracting the effect of noise on the reference voltage in response to the falling slope of the electronic signal; and Electrically coupled to the load circuit of the regulator output, the load circuit receiving an electronic signal with a reduced noise source corresponding to the reference voltage.

2. The power management integrated circuit according to claim 1, characterized in that, Additionally, a second switch is included, the second switch having a gate terminal coupled to the output of the differential error amplifier, a source terminal sharing a common input voltage with the differential error amplifier, and a drain terminal coupled to the first switch and the output of the regulator.

3. The power management integrated circuit according to claim 2, characterized in that, The second switch includes a power metal-oxide-semiconductor field-effect transistor.

4. The power management integrated circuit according to claim 1, characterized in that, The coupling capacitor path includes a feedforward capacitor; The system also includes a voltage divider, which comprises a first resistor and a second resistor, the first resistor being connected in parallel with a feedforward capacitor.

5. The power management integrated circuit according to claim 4, characterized in that, The voltage divider is used to adjust the output of the differential error amplifier to a voltage greater than or equal to the reference voltage.

6. The power management integrated circuit according to claim 5, characterized in that, The feedforward capacitor is coupled between the second input of the differential error amplifier and the junction between the first and second resistors.

7. The power management integrated circuit according to claim 4, characterized in that, The feedforward capacitor contributes to the falling slope of the electronic signal without affecting the reference voltage.

8. The power management integrated circuit according to claim 5, characterized in that, The voltage regulator circuit further includes a capacitor and a resistor connected in parallel with the first switch and the voltage divider, which are coupled in series, wherein the active discharge transistor discharges the capacitor when the voltage regulator circuit is deactivated.

9. A voltage regulator circuit for a power management integrated circuit, characterized in that, include: The regulator outputs an electronic signal with an upward slope and a downward slope. A differential error amplifier that is activated in response to a first signal and deactivated in response to a second signal, the differential error amplifier having a first input for receiving a reference voltage, a second input for receiving a feedback voltage, and a differential output that generates a difference between the reference voltage and the feedback voltage in response to the first signal; An active discharge transistor that discharges at the regulator output in response to a first signal and a second signal of the electronic signal; as well as A first switch coupled to the regulator output, which is in an open state in response to the receipt of the second signal, disconnects the coupling capacitor path between the regulator output and the reference voltage, thereby counteracting the effect of noise on the reference voltage in response to the falling slope of the electronic signal.

10. A noise reduction method for a voltage regulator circuit, characterized in that, include: Disable the voltage regulator circuit; Turn the first switch at the output of the voltage regulator circuit to the off position; The electronic signal is discharged through the active discharge transistor coupled to the output of the voltage regulator circuit. as well as Before discharging the regulator output through the active discharge transistor, the first switch disconnects the coupling capacitor path between the output and the reference voltage at the input of the voltage regulator circuit.

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