Method and related apparatus for optimizing flash memory grains

Abstract

This application provides a method and related apparatus for optimizing flash memory chips. The method involves suspending a portion of the non-volatile flash memory interface (NFI) bus of the flash memory chip during its operational process; identifying channels requiring optimization from the suspended channels; determining optimization parameters for each channel based on training data; and optimizing each channel based on its optimization parameters. This technical solution allows for the optimization of a portion of the NFI bus during normal flash memory chip operation. In other words, other channels can remain in normal working order. This enables optimization of the NFI bus channels without disk failure.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a method and related apparatus for optimizing flash memory chips. Background Technology

[0002] Flash memory chips with high read / write (I / O) rates typically provide a better user experience. Increasing the bus speed of the NAND flash interface (NFI) is an effective way to improve I / O speed. However, as the NFI bus speed increases, the ideal data width decreases, leading to reduced bus link reliability and causing failures such as data loss.

[0003] The solution to single-channel, single-bit errors on the NFI bus is to retransmit the data from the channel where the error occurred. However, as the number of NFI bus channels increases, the probability of single-bit errors also increases. Furthermore, retransmitting data severely impacts the read / write performance of the flash memory chips, degrading the user experience. Summary of the Invention

[0004] This application provides a method and related apparatus for optimizing flash memory chips, which can optimize some channels in the NFI bus without disk loss.

[0005] In a first aspect, embodiments of this application provide a method for optimizing flash memory chips. The method includes: during the service operation of the flash memory chip, suspending N channels in the non-volatile flash interface (NFI) bus of the flash memory chip, where N is an integer greater than or equal to 1 and less than or equal to the total number of channels in the NFI bus; determining at least one channel to be optimized from the N channels; determining optimization parameters for each channel to be optimized based on training data of each channel to be optimized; and optimizing each channel to be optimized based on the optimization parameters.

[0006] The above technical solution can optimize some channels in the NFI bus during normal operation of the flash memory chip. In other words, other channels can remain in normal working condition. This allows for optimization of the NFI bus channels without disk failure.

[0007] In conjunction with the first aspect, in one possible implementation of the first aspect, determining at least one channel to be optimized from N channels includes: performing a margin test on the nth channel among the N channels to obtain the margin of the nth channel, where n is an integer from 1 to N; determining whether the margin of the nth channel satisfies a margin condition, which includes at least one of a timing margin condition and a voltage margin condition; if the margin of the nth channel does not satisfy the margin condition, then determining that the nth channel belongs to the channel to be optimized.

[0008] The above technical solution can identify the channels that need optimization, thus preparing for subsequent optimization.

[0009] In conjunction with the first aspect, in one possible implementation of the first aspect, the optimization parameters include read optimization voltage and write optimization voltage, and the training data for each channel to be optimized includes K read margins and K write margins for each channel to be optimized, where K is a positive integer greater than 1. Determining the optimization parameters for each channel to be optimized based on the training data of each channel to be optimized includes: determining the average value of the K read margins as the read optimization voltage; and determining the average value of the K write margins as the write optimization voltage.

[0010] By defining specific read optimization parameters, the read reference voltage of the channel can be optimized; similarly, by defining specific write optimization parameters, the write reference voltage of the channel can be optimized. Optimizing both the read and write reference voltages reduces the probability of transmission errors between the flash memory controller and the NAND flash chips, thereby improving storage performance.

[0011] In conjunction with the first aspect, in one possible implementation of the first aspect, the K read margins are K read timing margins, the K write margins are K write timing margins, the K read timing margins correspond one-to-one with the K voltage levels, the K write timing margins correspond one-to-one with the K voltage levels, and the optimized read voltage is determined by the following formula:

[0012]

[0013] Where Vrx_best represents the optimal voltage for this read, V k This represents the k-th voltage level out of the K voltage levels, T rxk This represents the k-th read timing margin among the K read timing margins, where k = 1, ..., K; the write optimization voltage is determined by the following formula: Where Vtx_best represents the optimized voltage, V k This represents the k-th voltage level out of the K voltage levels, T txk This represents the k-th write timing margin among the K write timing margins.

[0014] In conjunction with the first aspect, in one possible implementation of the first aspect, the K read margins are K read voltage margins, the K write margins are K write voltage margins, the K read voltage margins correspond one-to-one with the K data latch signal DQS delay levels, the K write voltage margins correspond one-to-one with the K DQS delay levels, the read optimized voltage is the arithmetic average of the K read voltage margins, and the write optimized voltage is the arithmetic average of the K write voltage margins.

[0015] In conjunction with the first aspect, in one possible implementation of the first aspect, the optimization parameters include read-optimized DQS timing optimization parameters and write-optimized DQS timing optimization parameters. The training data for each channel to be optimized includes read-direction training data and write-direction training data. Determining the optimization parameters for each channel to be optimized based on the training data of each of the at least one channel to be optimized includes: determining the read-optimized DQS timing optimization parameters based on the read-direction training data, wherein the read-direction training data includes the left boundary and right boundary obtained through read-direction timing training. The read-optimized DQS timing optimization parameters are used to adjust the DQS delay line to a first center position, which is the average of the left and right boundaries obtained through read-direction timing training. Based on the write-direction training data, the write-optimized DQS timing optimization parameters are determined. The write-direction training data includes the left and right boundaries obtained through write-direction timing training. These parameters are used to adjust the DQS delay line to a second center position, which is the average of the left and right boundaries obtained through write-direction timing training.

[0016] The above scheme optimizes the timing margin by adjusting the position of the delay line of the DQS signal, thereby maximizing the effective width of the timing margin of the receiver signal, as well as the setup and hold time margins, to meet the specifications and avoid bit errors during data reading and writing, which could lead to data loss.

[0017] Secondly, embodiments of this application provide an electronic device that includes units for implementing the first aspect or any possible implementation of the first aspect.

[0018] Thirdly, embodiments of this application provide a solid-state drive, including: an SSD controller, which is coupled to flash memory via a non-volatile flash memory interface bus, and the SSD controller is also used to couple to a memory, read and execute instructions and / or program code in the memory to perform the first aspect or any possible implementation of the first aspect.

[0019] Fourthly, embodiments of this application provide a chip system including logic circuitry for coupling with an input / output interface to transmit data via the input / output interface, thereby executing the first aspect or any possible implementation thereof.

[0020] Fifthly, embodiments of this application provide a computer-readable storage medium storing program code that, when executed on a computer, causes the computer to perform the first aspect or any possible implementation thereof.

[0021] In a sixth aspect, embodiments of this application provide a computer program product comprising: computer program code, which, when executed on a computer, causes the computer to perform as in the first aspect or any possible implementation thereof. Attached Figure Description

[0022] Figure 1 A schematic diagram illustrating a possible application scenario of an embodiment of this application is shown.

[0023] Figure 2 A schematic diagram of the flash memory controller and NAND flash chips is shown.

[0024] Figure 3 These are schematic diagrams of DQS-N and DQS-P.

[0025] Figure 4 This is a schematic diagram for writing the reference voltage.

[0026] Figure 5 Is it like this? Figure 1 A schematic diagram of NAND flash chips in an electronic device is shown.

[0027] Figure 6 This is a schematic flowchart of a method for optimizing flash memory chips according to an embodiment of this application.

[0028] Figure 7 This is a schematic diagram of the connection between the flash memory controller and the die.

[0029] Figure 8 This is a flowchart for timing margin testing.

[0030] Figure 9 This is a schematic diagram of a flash memory controller.

[0031] Figure 10 This is a schematic flowchart of voltage margin testing.

[0032] Figure 11 This is a schematic flowchart illustrating voltage margin optimization based on embodiments of this application.

[0033] Figure 12 This is a schematic flowchart illustrating timing margin optimization based on embodiments of this application.

[0034] Figure 13 This is a schematic flowchart of a method for optimizing flash memory chips according to an embodiment of this application.

[0035] Figure 14 This is a schematic structural block diagram of an electronic device provided according to an embodiment of this application. Detailed Implementation

[0036] The technical solutions in this application will now be described with reference to the accompanying drawings.

[0037] In this application, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0038] To facilitate a better understanding of the technical solution of this application by those skilled in the art, the application scenarios and some related concepts involved in the technical solution of this application will be introduced first.

[0039] Figure 1 A schematic diagram illustrating a possible application scenario of an embodiment of this application is shown. For example... Figure 1 As shown, the solid-state disk (SSD) 100 includes an SSD controller 110 and a NAND flash memory 130.

[0040] The SSD controller 110 includes a host interface controller 111, a processor 112, and a flash memory controller 113. The host interface controller 111, processor 112, and flash memory controller 113 are connected via a bus 114. It is understood that the SSD controller, in addition to... Figure 1 In addition to the host interface controller 111, processor 112 and flash memory controller 113 shown, other modules may also be included, such as a cache controller, an error correcting code (ECC) module, etc.

[0041] The host interface controller, also known as the front end, is responsible for communication between the host and the SSD. Commands and data transfers flow to and from the SSD via the front end bus. The host can be a computer, mobile phone, base station, vehicle computer (also known as an electronic control unit, ECU), etc. The front end interface can be a high-speed serial computer extended bus standard (Peripheral Component Interconnect Express, PCIe) interface, a mini serial advanced technology attachment (mSATA) interface, an M.2 (or next generation form factor, NGFF) interface, or other user-defined interfaces.

[0042] Processor 112 may include one or more central processing unit (CPU) cores. Processor 112 is responsible for functions such as computation and system scheduling. In addition to the CPU core, processor 112 may also include some peripheral modules, such as universal asynchronous receiver / transmitter (UART), general-purpose input / output (GPIO) modules, temperature sensors, timers, etc.

[0043] The flash memory controller 113 is responsible for managing the writing and reading of data to and from the NAND flash 130. The flash memory controller 113 is connected to the NAND flash 130 via the NFI bus 120.

[0044] The following is combined Figure 2 The flash memory controller 113 is described below.

[0045] Figure 2 A schematic diagram of the flash memory controller and NAND flash chips is shown. Figure 1 The NAND flash 130 shown includes multiple NAND flash chips. Figure 2 The NAND flash chip 131 shown can be any one of the multiple NAND flash chips included in NAND flash 130.

[0046] like Figure 2As shown, the flash memory controller 113 is connected to the NAND flash chip 131 via an NFI bus 120. The NFI bus 120 includes multiple data signal lines (e.g., Figure 2 The data signal lines L0 to L7 and multiple timing lines (such as...) Figure 1 (The timing signal lines LS-P and LS-N in the middle).

[0047] Data signal lines L0 to L7 can transmit eight data signals (DQ) in parallel. For example, data signal line L0 can transmit DQ0, data signal line L1 can transmit DQ1, ..., data signal line L7 can transmit DQ7. It should be understood that DQ is a periodic digital signal, and therefore can carry data. For example, DQ can transmit 1 bit of data in one cycle, specifically, 1 bit of data "0" can be transmitted in a low-level cycle and 1 bit of data "1" can be transmitted in a high-level cycle. Since data signal lines L0 to L7 can transmit eight DQ signals in parallel, a total of 8 bits of data are transmitted in one cycle.

[0048] It is understandable that, since DQ is a digital signal, the receiving end of DQ needs a clock signal with the same period as DQ to correctly distinguish the period of DQ, thereby correctly identifying the level state of DQ and thus correctly acquiring the data carried by DQ. In view of this, the NFI bus 120 may also include timing signal lines LS-N and LS-P, which can transmit data strobe signal (DQS).

[0049] Specifically, timing signal line LS-N can transmit DQS-N, and timing signal line LS-P can transmit DQS-P. Here, DQS-N and DQS-P are inverted signals. For example, DQS-N and DQS-P can be... Figure 3 As shown. DQS includes DQS-N and DQS-P. DQS can serve as a clock signal corresponding to DQ, and has the same transmitting and receiving ends as DQ. It can trigger the receiving end of DQ to recognize the level state of DQ. For ease of description, the embodiments of this application will hereby refer to DQS-N and DQS-P as DQS.

[0050] It should be noted that bidirectional data transmission between the flash memory controller 113 and the NAND flash chip 131 can be achieved through the NFI bus 120. For example, during the process of the flash memory controller 113 writing data to the NAND flash chip 131, the flash memory controller 113 can act as the transmitter of DQS and DQ, and the NAND flash chip 131 can act as the receiver of DQS and DQ. During the process of the flash memory controller 113 reading data from the NAND flash chip 131, the NAND flash chip 131 can act as the transmitter of DQS and DQ, and the flash memory controller 113 can act as the receiver of DQS and DQ.

[0051] For ease of description, in the embodiments of this application, "Write DQ" and "Write DQS" will be used to refer to the DQ and DQS sent by the flash memory controller 113 to the NAND flash chip 131 during the process of writing data to the NAND flash chip 131, respectively; and "Read DQ" and "Read DQS" will be used to refer to the DQ and DQS sent by the NAND flash chip 131 to the flash memory controller 113 during the process of reading data from the NAND flash chip 131, respectively. Specifically, "Write DQ" includes "Write DQ0" to "Write DQ7", and "Read DQ" includes "Read DQ0" to "Read DQ7".

[0052] Next, the specific implementations of writing and reading data will be explained separately:

[0053] Scenario 1: Flash controller 113 writes data to NAND flash chip 131

[0054] The processor 110 can invoke the flash memory controller 113 to write data to the NAND flash chip 131. The specific implementation of the processor 110 invoking the flash memory controller 113 can refer to the prior art, and the embodiments of this application do not impose many limitations on it.

[0055] Under the call of the processor 112, the flash memory controller 113 can write data to the NAND flash chip 131. Specifically, the flash memory controller 113 can send write DQ0 to write DQ7 to the NAND flash chip 131 through data signal lines L0 to L7, where write DQ0 to write DQ7 sent by the flash memory controller 113 can carry the target write data to be written to the NAND flash chip 131.

[0056] During the process of writing data to the NAND flash chip 131 by the flash controller 113, the flash controller 113 also sends a write DQS to the NAND flash chip 131. The write DQS can trigger the NAND flash chip 131 to identify the level states of write DQ0 to write DQ7. The NAND flash chip 131 can then store the data carried by write DQ0 to write DQ7 according to the identified level states, thereby realizing the writing of data to the NAND flash chip 131.

[0057] Generally, in the write DQS sent by the flash controller 113 to the NAND flash chip 131, the intersection point between write DQS-N and write DQS-P (such as...) Figure 3 (As shown) can be used as a trigger point to trigger NAND flash chip 131 to recognize the level state of write DQ. That is, when NAND flash chip 131 determines that the received write DQS is at the crossover point, NAND flash chip 131 can recognize the level state of the current write DQ0 to write DQ7, and thus can write the target write data carried by write DQ0 to write DQ7 into NAND flash chip 131.

[0058] For example, if the target data to be written is 11010011, it corresponds to the same intersection in the write DQS. At this time, the data carried by write DQ0 to write DQ7 are as follows: write DQ0 can carry "1", write DQ1 can carry "1", write DQ2 can carry "0", write DQ3 can carry "1", write DQ4 can carry "0", write DQ5 can carry "0", write DQ6 can carry "1", and write DQ7 can carry "1".

[0059] When the NAND flash chip 131 determines that the received write DQS is at a crossover point, it can identify the level states of the received write DQ0 to write DQ7. In the example above, write DQ0 is high (carrying "1"), write DQ1 is high (carrying "1"), write DQ2 is low (carrying "0"), write DQ3 is high (carrying "1"), write DQ4 is low (carrying "0"), write DQ5 is low (carrying "0"), write DQ6 is high (carrying "1"), and write DQ7 is high (carrying "1"). The NAND flash chip 131 can then store the target write data "11010011" based on the identified level states of write DQ0 to write DQ7.

[0060] Scenario 2: Flash controller 113 reads data from NAND flash chip 131

[0061] The processor 110 can invoke the flash memory controller 113 to read data from the NAND flash chip 131. The specific implementation of the processor 110 invoking the flash memory controller 113 can refer to the prior art, and the embodiments of this application do not impose any restrictions on it.

[0062] When invoked by the processor 110, the flash memory controller 113 can instruct the NAND flash chip 131 to send target read data to the flash memory controller 113, thereby enabling the flash memory controller 113 to read the target read data from the NAND flash chip 131. The specific implementation of the flash memory controller 113 instructing the NAND flash chip 131 can refer to existing technologies, and this application embodiment does not impose further limitations on it.

[0063] NAND flash chip 131 can send read DQ0 to read DQ7 to flash controller 113 via data signal lines L0 to L7. Read DQ0 to read DQ7 can carry the target read data sent to flash controller 113. While sending read DQ0 to read DQ7 to flash controller 113, NAND flash chip 131 also sends read DQS to flash controller 113. Flash controller 113 can identify the level state of read DQ0 to read DQ7 based on read DQS, and obtain the target read data carried by read DQ0 to read DQ7 based on the identified level state, thereby realizing data reading from NAND flash chip 131.

[0064] The specific implementation of Read DQS and Read DQ0 to Read DQ7 is similar to that in Scenario 1 above, and will not be repeated here. The difference is that in the Read DQS sent by NAND flash chip 131 to flash controller 113, the midpoint between two adjacent intersections can usually be used as the trigger point for flash controller 113 to identify the level state of Read DQ0 to Read DQ7. That is, when NAND flash chip 131 determines that the received Read DQS is at the midpoint, flash controller 113 can identify the current level state of Read DQ0 to Read DQ7 to obtain the target read data carried by Read DQ0 to Read DQ7.

[0065] As can be seen from Scenario 1 and Scenario 2 above, whether the flash memory controller 113 and the NAND flash chip 131 can accurately transmit data is closely related to whether the relative timing positions of the DQS and DQ transmitted in the same direction are aligned. Among them, the DQS and DQ transmitted in the same direction can be understood as read DQS and read DQ, or write DQS and write DQ.

[0066] by Figure 3Taking the write DQS and write DQ as examples, the write DQ can be any write DQ from write DQ0 to write DQ7. The crossover point of write DQS serves as the trigger point, and the cycle of the write DQ corresponding to this crossover point refers to the specific write DQ cycle in which the crossover point occurs. Figure 3 As can be seen, the trigger point (crossover point) of a write DQS divides the corresponding write DQ cycle into two parts: the part before the trigger point is the setup time, and the part after the trigger point is the hold time. Assume that the start time of any write DQ cycle received by the NAND flash chip 131 is t1, and the end time of that write DQ cycle is t2. Between t1 and t2, the time point at which the write DQS received by the NAND flash chip 131 is at the trigger point is t0. In this case, the time period between t1 and t0 can be called the setup time, and the time period between t0 and t2 can be called the hold time.

[0067] Sufficient setup time for writing DQ is beneficial for improving the accuracy of data transmission. Specifically, since writing DQ is a digital signal, the level state of writing DQ often changes; that is, within any given cycle, writing DQ may be at a low level or a high level. Between two adjacent cycles, the level state of writing DQ may remain unchanged, change from low to high, or change from high to low.

[0068] Typically, high and low levels are relative to a reference voltage. That is, if the write voltage of DQ is lower than the reference voltage, then the write voltage of DQ is low; if the write voltage of DQ is higher than the reference voltage, then the write voltage of DQ is high. When the write voltage of DQ changes, a certain delay is often required to complete the level transition. For example, ... Figure 3 As shown, the write DQ level reaches the reference voltage at tmin and tmax.

[0069] Taking the transition from a low level in the previous cycle to a high level in the current cycle as an example, if the setup time is insufficient, such as t0 being between t1 and tmin, the write DQ level at t0 may not have fully risen to a high level greater than the reference voltage. In this case, the NAND flash chip 131 may mistakenly interpret it as a low level for the write DQ in the current cycle. That is, the write DQ in the current cycle should be high, but because t0 is between t1 and tmin and the level has not fully risen to a high level greater than the reference voltage, it is mistakenly identified as low, leading to errors in the data written to the NAND flash chip 131. Therefore, to ensure the accuracy of data transmission between the flash controller 113 and the NAND flash chip 131, the setup time needs to be sufficiently long.

[0070] Sufficient hold time for the write DQ also helps improve the accuracy of data transmission. Specifically, the NAND flash chip 131 needs a certain delay to recognize the level state of the write DQ. Taking the transition from a high level in the current cycle to a low level in the next cycle as an example, the NAND flash chip 131 begins to recognize the level state of the write DQ at time t0. If the hold time is insufficient, such as if t0 is between tmax and t2, the level of the write DQ may drop below the reference voltage (the write DQ will be low in the next cycle) during the period when the NAND flash chip 131 recognizes the level state of the write DQ. This causes the NAND flash chip 131 to mistakenly recognize the level of the current cycle as low, resulting in errors in the data written to the NAND flash chip 131. In other words, the level of the write DQ in the current cycle should be high, but because t0 is between tmax and t2 and the level drops below the reference voltage, it is mistakenly perceived as low. Therefore, to ensure the accuracy of data transmission between the flash controller 113 and the NAND flash chip 131, the hold time needs to be long enough.

[0071] In summary, to improve the accuracy of data transmission between the flash memory controller 113 and the NAND flash chip 131, both the hold time and setup time for writing the DQ need to be relatively long. Insufficient hold or setup time for writing the DQ will reduce the accuracy of data transmission between the flash memory controller 113 and the NAND flash chip 131, increasing the bit error rate.

[0072] Generally, the reference voltage in the flash memory controller 113 and the NAND flash chip 131 is the same. That is, for Figure 3 The time interval between write DQS and write DQ, tmin and t1 can also be called the minimum setup time applicable to NAND flash chip 131, and the time interval between tmax and t2 can also be called the minimum hold time applicable to memory chip t2.

[0073] Within a write DQ cycle, the difference between the setup time of write DQS and the minimum setup time applicable to the NAND flash chip 131 can be called the timing margin of the write DQ setup time, and the difference between the hold time of write DQS and the minimum hold time applicable to the NAND flash chip 131 can be called the timing margin of the write DQ hold time. The minimum of the timing margins of the write DQ setup time and the hold time can be understood as the timing margin of the write DQ. For example... Figure 3 In the DQ, the timing margin is the minimum of the difference between t1 and tmin, and the difference between tmax and t2.

[0074] Generally, the time interval between tmin and tmax is primarily determined by the performance of the NAND flash chip 131. In other words, for the flash controller 113, the requirements for chip setup time and hold time are determined by the chip's performance and are not adjustable. However, the timing margin can be optimized through timing training. Through timing training, the flash controller 113 can adjust the time point t0 corresponding to the crossover point of the write DQS to the middle position between tmin and tmax, meaning the timing margin for the write DQ setup time is equal to the timing margin for the hold time. Therefore, the timing margin for the write DQ can be maximized, thereby optimizing the accuracy of data transmission from the flash controller 113 to the NAND flash chip 131 from the perspective of timing margin.

[0075] Similarly, during the process of the flash memory controller 113 reading data from the NAND flash chip 131, the difference between the hold time of the read DQ sent by the NAND flash chip 131 to the flash memory controller 113 and the minimum hold time applicable to the flash memory controller 113 can also be called the timing margin of the read DQ hold time. The difference between the read DQ setup time and the minimum setup time applicable to the flash memory controller 113 can also be called the timing margin of the read DQ setup time. The timing margin of the read DQ can be understood as the minimum of the timing margins of the read DQ hold time and setup time. When the timing margins of the hold time and setup time in the read DQ sent by the NAND flash chip 131 to the flash memory controller 113 are equal, the timing margin of the read DQ can reach its maximum value. In this case, the accuracy of data transmission from the NAND flash chip 131 to the flash memory controller 113 can be optimized from the perspective of timing margin.

[0076] To improve the timing margin of read DQ and write DQ, thereby improving the accuracy of data transmission between flash controller 113 and NAND flash chip 131, it is often necessary to align the relative timing positions of DQ and DQS transmitted in the same direction. This process is also often referred to as memory training.

[0077] In this embodiment, "alignment" can be understood as follows: in DQS and DQ transmissions in the same direction, the timing margin of the hold time of DQ is equal to the timing margin of the setup time, or the timing margin of the hold time of DQ is not much different from the timing margin of the setup time, so that DQ has sufficient timing margins for both hold time and setup time. The timing margin of the setup time of DQ is relative to the minimum setup time applicable to the receiver, and the timing margin of the hold time of DQ is also relative to the minimum hold time applicable to the receiver. In other words, "alignment" ensures that the setup time of DQ is not less than the minimum setup time applicable to the receiver, and that the hold time of DQ is not less than the minimum hold time applicable to the receiver.

[0078] The receiving end can be either a NAND flash chip 131 or a flash controller 113. The minimum setup time and minimum hold time applicable to the receiving end can be determined based on factors such as the structure and performance of the receiving end. If the setup time of the DQ is less than the minimum setup time applicable to the receiving end, or the hold time of the DQ is less than the minimum hold time applicable to the receiving end, the receiving end will be unable to correctly identify the data carried by the DQ.

[0079] Furthermore, as mentioned above, the determination of high and low levels is obtained by comparing with a reference voltage. Figure 4 As shown, starting from t0, the write level is higher than the write reference voltage Vref. Under these conditions, the NAND flash chip 131 can determine that the write level is high, thus determining that the written data is 1. Starting from t1, the write level is lower than the write reference voltage Vref. Under these conditions, the NAND flash chip 131 can determine that the write level is low, thus determining that the written data is 0. Starting from t2, the write level is higher than the write reference voltage Vref. Under these conditions, the NAND flash chip 131 can determine that the write level is high, thus determining that the written data is 1.

[0080] Assume the write reference voltage Vref is greater than the maximum write level (i.e.) Figure 4 If the write reference voltage Vref is less than the minimum write level (i.e., V1 as shown), then the NAND flash chip 131 will consider the write level to be low. In this case, the NAND flash chip 131 will determine that all written data is 0. Alternatively, suppose the write reference voltage Vref is less than the minimum write level (i.e., Vref is less than the minimum write level). Figure 4 If V2 is shown, then the NAND flash chip 131 will consider the write level to be high. In this case, the NAND flash chip 131 will determine that all written data is 1.

[0081] The voltage margin for the write direction is the difference between the reference voltage and the write level. For example... Figure 4The difference between Vref and V2 shown is the voltage margin in the write direction.

[0082] For the same reason, during the process of the flash controller 113 reading data from the NAND flash chip 131, the difference between the reference voltage and the read level is the read direction voltage margin.

[0083] Figure 5 Is it like this? Figure 1 A schematic diagram of NAND flash chips in an electronic device is shown.

[0084] Flash memory can be divided into NOR flash memory and NAND flash memory. Compared to NOR flash memory, NAND flash memory has advantages such as larger capacity, lower price, and faster read and write speeds, and is therefore widely used. Currently, NAND flash memory can be used in solid-state drives (SSDs), secure digital cards (SD cards), add-in cards (AIDs), etc. NAND flash memory can also be used as a storage medium in electronic devices such as mobile phones and tablets.

[0085] The structure of NAND flash memory can be divided into devices, targets, dies, planes, blocks, pages, and cells, from largest to smallest.

[0086] like Figure 5 The NAND flash chip 131 shown is a device. A device is a packaged NAND flash unit, also known as a package, flash memory chip, or NAND flash chip. A storage device (such as an SSD) can have one or more devices, and a device can contain one or more targets. A target can contain one or more dies.

[0087] For example, such as Figure 5 The NAND flash chip 131 shown includes two targets, target 510 and target 520. Each target includes four dies: target 510 includes dies 511, 512, 513, and 514, and target 520 includes dies 521, 522, 523, and 524.

[0088] A die can also be called a logical unit (LUN). A die can contain one or more planes. Each plane can consist of a large number of block pages, each block page can consist of a large number of page pages, and each page can consist of a large number of cells.

[0089] The number of channels in a flash memory directly reflects the concurrent read / write capability of a solid-state drive (SSD). A channel can have one or more dies. Each device can support one or more channels.

[0090] For example, such as Figure 5 The NAND flash chip 131 shown also includes an input / output interface 501, channels 502, 503, 504 and 505, wherein channel 502 is connected to die 511 and die 512, channel 503 is connected to die 513 and die 514, channel 504 is connected to die 521 and die 522, and channel 505 is connected to die 523 and die 524.

[0091] The input / output interface 501 of the NAND flash chip 131 can be connected to the flash memory controller via the NFI bus to receive commands from the flash memory controller. Based on the received commands, it can read data stored in the NAND flash chip 131, write data to the NAND flash chip 131, or delete data from the NAND flash chip 131. For example, if the NAND flash chip 131 receives a read command to read data stored in die 511, then the data stored in die 511 can be read through channel 502, and then the read data can be sent to the flash memory controller. Similarly, if the NAND flash chip 131 receives a write command to write data to die 524, then the data can be written to die 524 through channel 505.

[0092] The data interface of the NAND flash chip is not limited in this application embodiment; it can be SDR, NV-DDR, NV-DDR2, or NV-DDR3.

[0093] The ideal data width of the NFI bus refers to the time required to transmit a single data transfer under ideal transmission conditions. An ideal transmission environment means that transmission losses are not considered during data transmission. For example, with an NFI bus transmission rate of 400 megabits per second (MT / s), the time required for each data transmission is 400 × 10^10 times. 8One-fifth of a second, that is, the ideal data width for each data transmission is 2.5ns.

[0094] The ideal data width of the NFI bus is related to the performance, capacity, and speed specifications of the flash memory chips. The NFI bus's transfer rate is inversely proportional to its ideal data width. Therefore, as the NFI bus transfer rate increases, the ideal data width decreases accordingly. For example, if the NFI bus transfer rate is 400MT / s, the ideal data width is 2.5ns; if the transfer rate is 800MT / s, the ideal data width is 1.25ns; if the transfer rate is 1200MT / s, the ideal data width is 0.83ns; and if the transfer rate is 1600MT / s, the ideal data width is 0.625ns.

[0095] like Figure 3 As shown, the difference between t2 and t1 represents the effective data width. A smaller ideal data width on the NFI bus means a smaller difference between t2 and t1. Correspondingly, the differences between t1 and tmin, and between tmax and t2, will also decrease, leading to a smaller timing margin. Furthermore, in actual data transmission, the data sent by the transmitter with the ideal data width is attenuated through the transmission channel, resulting in a smaller actual data width received by the receiver. Under these circumstances, the NFI bus is more susceptible to external factors such as temperature and voltage, leading to reliability issues in the NFI bus channel and causing data transmission problems, such as data transmission errors.

[0096] The concepts of effective width and margin effective width are explained below.

[0097] The effective width can be defined as the actual signal width received by the receiver after the data of ideal width at the transmitting end reaches the receiving end through the transmission channel and is attenuated. The margin effective width refers to the signal width correctly sampled by the receiver when the preset ideal signal width of the data at the transmitting end reaches the receiving end after transmission. Compared to the effective width, the margin effective width is the remaining time after removing the data setup time and data hold time.

[0098] For example, a total of n bits can be transmitted in one DQS cycle. For instance, at a transmission rate of 400Mbps, which is 4×10⁸ bits per second, the time taken to transmit each bit is 1s / (4×10⁸) = 2.5ns. That is, the ideal signal width corresponding to each bit is 2.5ns. After passing through the transmission channel to the receiving end, the ideal signal width is reduced, and the effective signal width actually correctly received by the receiving end is 2ns.

[0099] bps is a unit of bit rate, which refers to the rate at which a signal (represented by digital binary bits) is processed or transmitted through a system (device, radio wave, or wire), i.e., the amount of data processed or transmitted per unit of time. The unit is "bits per second" (bit / s or bps). In the field of communications, it can be used to represent connection speed, transmission speed, channel capacity, maximum throughput, and digital bandwidth capacity, etc. This application can be used to represent the bus rate used for transmission between the controller and NAND Flash.

[0100] Furthermore, this "effective margin width" can also be called the effective margin of timing margin. The difference between this and the aforementioned "timing margin" is that this application defines the concept of "effective margin width" to measure "timing margin." Here, "margin" can be translated as "margin," and in this application, "margin" can refer to "effective margin width." Therefore, unless otherwise specified, the timing margin in the embodiments of this application can be understood as the effective width of the timing margin.

[0101] This application provides a method for optimizing flash memory chips. This method optimizes voltage and timing margins during the operational process of the flash memory chips, thereby reducing data transmission error rate and improving the reliability of the flash memory chips.

[0102] As long as the device contains NAND flash chips, it has the following characteristics: Figure 2 The structures shown can all utilize the technical solutions of this application. In other words, the basic solutions of this application can be applied to structures such as... Figure 1 In addition to the SSD shown, it can also be applied to other devices that communicate with NAND flash chips via the NFI bus, such as add-in cards (AIC), secure digital memory cards (SD cards), and electronic devices that use NAND flash chips as storage media (such as mobile phones, tablets, digital cameras, ECUs, etc.).

[0103] Figure 6 This is a schematic flowchart of a method for optimizing flash memory chips according to an embodiment of this application.

[0104] like Figure 6As shown, after completing power-on initialization, timing training, and voltage training, the flash memory chip begins the service operation phase (i.e., it can read data stored in the flash memory chip, write data to the flash memory chip, or delete data from the flash memory chip). During service operation, it is determined whether the trigger conditions are met; if the trigger conditions are not met, monitoring continues; if the trigger conditions are met, one or more channels of the flash memory chip are suspended; after the die in the selected passband becomes idle, a margin test is performed on the selected channel to determine whether the margin of the selected channel meets the requirements; if the margin of the selected channel does not meet the requirements, these channels can be optimized; if the margin of the selected channel meets the requirements, it is determined whether all channels of the flash memory chip have been margin tested; if not, the margin test continues on the remaining channels; if all channels have been margin tested, monitoring continues to determine whether the trigger conditions are met.

[0105] Below, in conjunction with, for example Figure 5 The NAND flash chip 131 shown is for example Figure 6 The schematic flowchart of the method for optimizing flash memory chips provided in the embodiments of this application is introduced below.

[0106] Assuming NAND flash chip 131 is powered on at time t0, completes power-on initialization at time t1, and completes timing and voltage training at time t2, then from time t2 onwards, NAND flash chip 131 can be considered to be in the operational phase. In other words, from time t2 onwards, read / write operations or data deletion can be performed on NAND flash chip 131.

[0107] In some embodiments, working environment data can be monitored to determine whether triggering conditions are met. The working environment data may include temperature and / or humidity, wherein temperature monitoring can be achieved using a temperature sensor, and humidity monitoring can be achieved using a humidity sensor.

[0108] For example, a temperature upper limit can be set; if the monitored temperature is higher than this upper limit, the trigger condition can be determined to be met. Alternatively, an upper temperature limit and a lower temperature limit can be set; if the monitored temperature is higher than the upper limit or lower than the lower limit, the trigger condition can be determined to be met.

[0109] For example, a temperature limit and a humidity limit can be set. If the monitored temperature and humidity both meet the corresponding limits (i.e., the temperature meets the temperature limit and the humidity meets the humidity limit), the trigger condition can be determined to be met. If at least one of the monitored temperature and humidity does not meet the corresponding limit (e.g., the temperature is greater than the temperature limit, but the humidity is less than the humidity limit), the trigger condition can be determined not to be met.

[0110] The temperature compared to the temperature threshold can be the real-time temperature monitored by the temperature sensor, or the average temperature over a period of time. Similarly, the humidity compared to the humidity threshold can be the real-time humidity monitored by the humidity sensor, or the average humidity over a period of time.

[0111] In other embodiments, the operating parameters of the NAND flash chip 131 can be monitored, and the triggering condition can be determined based on the monitored operating parameters. The operating parameters may include one or more of the following: operating voltage, data transfer rate, or the current state of the channel. The operating voltage may be the operating voltage of the NAND flash chip 131 or the interface voltage for data transmission.

[0112] For example, a lower limit for data transfer can be set. If the data transfer amount of the NAND flash chip 131 is less than this lower limit, then the triggering condition can be determined to be met.

[0113] For example, if it is determined that there are idle channels in the NAND flash chip 131 or that the number of idle channels is greater than a preset number, then the triggering condition can be determined to be met.

[0114] In other embodiments, a timer can be set, and if the timer expires, it can be determined that the triggering condition has been met. Furthermore, the timer can be restarted after all channels have completed the margin test.

[0115] In other embodiments, operating environment data, operating parameters, or multiple timers can be monitored simultaneously to determine whether the triggering conditions are met.

[0116] In some embodiments, a trigger condition can be determined to be met only when multiple monitored data simultaneously meet their corresponding conditions. For example, if the storage device temperature and a timer are monitored simultaneously, and the storage device temperature is greater than a preset upper temperature limit and the timer expires, the trigger condition can be determined to be met; if the storage device temperature is greater than the preset upper temperature limit but the timer has not expired, the trigger condition can be determined not to be met.

[0117] In other embodiments, the trigger condition can be determined to be met when any one of the monitored data satisfies a corresponding condition. For example, by simultaneously monitoring the storage device temperature and a timer, if the storage device temperature is greater than a preset upper temperature limit and / or the timer times out, the trigger condition can be determined to be met; if the storage device temperature is less than the preset upper temperature limit and the timer does not time out, the trigger condition can be determined not to be met.

[0118] Once the triggering conditions are met, one or more channels can be suspended.

[0119] In some embodiments, suspended channels may be selected randomly.

[0120] In other embodiments, suspended channels can be selected based on the data transmission volume of the channels. For example, channels that are idle can be selected first, followed by channels that are currently performing read / write operations. Alternatively, channels with lower data transmission volumes can be selected first, followed by channels with higher data traffic volumes.

[0121] If the number of selected pending channels is less than the total number of channels, then the unselected channels will continue to operate normally.

[0122] Assuming Figure 5 Channels 502 and 503 are selected to be suspended. In this case, normal read and write operations can be performed on dies 521 to dies 524 through channels 504 and 505.

[0123] After channels 502 and 503 are suspended, we can wait for the corresponding dies for channels 502 and 503 to become idle. Assuming dies 511 and 512 become idle, we can then perform a margin test on channel 502. After performing a margin test on channel 502, if dies 513 and 514 are idle, then we can perform a margin test on channel 503.

[0124] Margin testing can be divided into timing margin testing and voltage margin testing. Taking channel 502 as an example, margin testing will be introduced.

[0125] In some embodiments, performing a margin test on channel 502 may involve performing a timing margin test only on channel 502. In this case, if channel 502 passes the timing margin test, then it can be determined that channel 502 does not need to be optimized; if channel 502 fails the timing margin test, then it can be determined that channel 502 is a channel that needs to be optimized.

[0126] In other embodiments, performing a margin test on channel 502 may involve only performing a voltage margin test on channel 502. In this case, if channel 502 passes the voltage margin test, it can be determined that channel 502 does not require optimization; if channel 502 fails the voltage margin test, it can be determined that channel 502 is a channel that needs optimization.

[0127] In other embodiments, performing a margin test on channel 502 may involve performing a timing margin test and a voltage margin test on channel 502.

[0128] When channel 502 is subjected to both timing margin test and voltage margin test, there are multiple ways to determine whether channel 502 has passed the margin test.

[0129] For example, in one implementation, channel 502 can only be considered to have passed the margin test if both tests are passed. In other words, if channel 502 fails the timing margin test or fails the voltage margin test, then it can be determined that channel 502 has failed the margin test.

[0130] For example, in another implementation, passing either of the other margin tests is sufficient to determine that channel 502 has passed the margin test. In other words, if channel 502 passes either the timing margin test or the voltage margin test, then it can be determined that channel 502 has passed the margin test. In this case, the two margin tests can be performed sequentially. If the first margin test passes, then the other margin test is unnecessary. For example, if the timing margin test is performed on channel 502 first, and channel 502 passes, then it can be directly determined that channel 502 has passed the margin test, and there is no need to continue with the voltage margin test. If channel 502 fails the timing margin test, then the voltage margin test is performed on channel 502. If channel 502 passes the voltage margin test, then it can be determined that channel 502 has passed the margin test. If channel 502 fails the voltage margin test, then it can be determined that channel 502 has failed the margin test.

[0131] The following is combined Figures 7 to 10 This paper introduces timing margin testing and voltage margin testing.

[0132] Figure 7 This is a schematic diagram showing the connection between the flash memory controller and the die. (Example:) Figure 7 The input / output interface 701 shown is the input / output interface of the flash memory controller. For example... Figure 7 The input / output interfaces shown are the input / output interfaces of the die.

[0133] like Figure 7As shown, the input / output interface 701 includes a voltage divider module 702. The voltage divider module 702 can be used to test timing margins.

[0134] Figure 8 This is a flowchart for timing margin testing. Assume the voltage divider module 702 can set N levels of the reference voltage Vref (N is a positive integer greater than or equal to 2). The voltages of these N levels can be represented as V1, V2, ..., V... N express.

[0135] 801, set the Vref level to V1.

[0136] 802, Determine if the current gear of Vref is less than or equal to V. N If the current level of Vref is less than or equal to the maximum level of the reference voltage V... N Then continue with the subsequent timing margin test steps.

[0137] 803, Write test data to the NAND flash chip.

[0138] Optionally, when writing test data to the NAND flash chip, a lower writing speed can be used. This reduces the probability of errors during writing. For example, Table 1 shows the correspondence between NFI bus operating modes and speeds in embodiments of this application. Different operating modes correspond to different bus speeds.

[0139] Table 1

[0140]

[0141] For example, the bus speed corresponding to the NV-DDR operating mode is 40~200 megabits per second (Mbps), and its corresponding low speed can be 40Mbps or 48Mbps, etc.

[0142] Data written to NAND flash chips can be error-prone, such as 0x5AA55AA5 or 0xA55AA55A. This test data can be written to the cache register within the NAND flash chip. Writing the test data to the cache register of the NAND flash chip, rather than to deeper areas (such as data registers or the NAND flash array), reduces the probability of errors occurring during data transfer within the NAND flash chip.

[0143] 804. Perform a read direction timing margin test and record the effective width of the read direction timing margin.

[0144] After writing test data to the NAND flash chip, the test data written in step 803 can be read. During the reading of the test data, the effective eye width of the DQ signal in the read direction is recorded to obtain the effective width Trx1 of the read direction timing margin for the current gear.

[0145] 805, perform a write direction timing margin test and record the effective width of the write direction timing margin.

[0146] After completing the read direction timing margin test, write test data at the normal rate to perform the write direction timing margin test. During the write test data writing process, record the effective eye width of the DQ signal in the write direction to obtain the effective width Ttx1 of the write direction timing margin for the current gear.

[0147] 806, Set the level of Vref to the next level, i.e., Vref = V n+1 Continue performing read-direction timing margin tests and write-direction timing margin tests to obtain the effective read-direction timing width and the effective write-direction timing width under N gears.

[0148] After obtaining the effective timing widths for the read direction and the write direction at N different settings, it is possible to determine whether the timing margin test has passed based on these effective timing widths. For ease of description, the effective timing widths for the read direction at N different settings can be referred to as the N effective reading timing widths, and the effective timing widths for the write direction at N different settings can be referred to as the N effective writing timing widths.

[0149] In some embodiments, if both the N valid read timing widths and the N valid write timing widths pass the timing margin test, then the channel is considered to have passed the timing margin test. In other words, if any one of the N valid read timing widths and the N valid write timing widths fails the margin test, then the channel is considered to have failed the timing margin test.

[0150] In some embodiments, the effective timing width in the read direction for each of the N gears has a corresponding threshold range. For example, suppose the effective timing widths in the read direction for each of the N gears are Trx1, Trx2, ..., TrxN, where the threshold range for Trx1 is [Th1_Trx1, Th2_Trx1], the threshold range for Trx2 is [Th1_Trx2, Th2_Trx2], ..., the threshold range for TrxN is [Th1_TrxN, Th2_TrxN]. If the effective timing width in the read direction for a certain gear is within the corresponding threshold range, then the effective timing width in the read direction for that gear can be considered to have passed the timing margin test. Similarly, the effective timing width in the write direction for each of the N gears has a corresponding threshold range. For example, suppose the effective timing widths for the write direction of each of the N gears are Ttx1, Ttx2, ..., TtxN, where the threshold range for Ttx1 is [Th1_Ttx1, Th2_Ttx1], the threshold range for Ttx2 is [Th1_Ttx2, Th2_Ttx2], ..., and the threshold range for TtxN is [Th1_TtxN, Th2_TtxN]. If the effective timing width for the write direction of a certain gear is within the corresponding threshold range, then it can be considered that the effective timing width for the write direction of that gear can pass the timing margin test.

[0151] In other embodiments, each of the N timing levels has a lower limit for the effective timing width in the read direction. If the effective timing width in the read direction of a certain level exceeds the lower limit corresponding to that level, then the effective timing width in the read direction of that level can be considered to have passed the timing margin test. Similarly, each of the N timing levels has a lower limit for the effective timing width in the write direction. If the effective timing width in the write direction of a certain level exceeds the lower limit corresponding to that level, then the effective timing width in the write direction of that level can be considered to have passed the timing margin test.

[0152] In other embodiments, if the number of gears that pass the timing margin test exceeds a preset percentage, then the channel can be considered to have passed the timing margin test.

[0153] In some embodiments, the proportions of read and write directions that pass the margin test can be counted separately, and these two proportions are compared with the preset proportion. If both proportions exceed the preset proportion, then the channel can be considered to have passed the timing margin test.

[0154] For example, assuming a preset ratio of 50%, if 75% of the read-direction timing widths pass the timing margin test, and 90% of the write-direction timing widths pass the timing margin test, then the channel can be considered to have passed the timing margin test.

[0155] For example, assuming a preset ratio of 50%, 75% of the read-direction timing widths pass the timing margin test, and 40% of the write-direction timing widths pass the timing margin test. In this case, it can be considered that the channel has not passed the timing margin test.

[0156] In other embodiments, the proportion of total gears that pass the timing margin test can be counted. If the proportion of total gears exceeds the preset proportion, then the channel can be considered to have passed the timing margin test; otherwise, the channel is considered to have failed the timing margin test.

[0157] For example, assuming N equals 10 and the preset ratio is 50%, the effective timing width in the read direction (3 levels) and the effective timing width in the write direction (8 levels) pass the timing margin test. The total percentage of levels passing the timing margin test is (3+8) / (10+10) = 11 / 20. Therefore, the total percentage of levels passing the timing margin test is greater than 50%, and thus, the channel can be considered to have passed the timing margin test.

[0158] In other embodiments, two preset thresholds can be set, which can be referred to as preset timing threshold 1 and preset timing threshold 2, respectively. After determining the N effective read timing widths and N effective write timing widths, the maximum value of the N effective read timing widths (which can be represented by Max_rx) and the maximum value of the N effective write timing widths (which can be represented by Max_tx) can be determined. If Max_rx is not greater than preset timing threshold 1 and Max_tx is not greater than preset timing threshold 2, then the channel can be considered to have passed the timing margin test; if Max_rx is greater than preset timing threshold 1 or Max_tx is greater than preset timing threshold 2, then the channel can be considered to have failed the timing margin test.

[0159] In other embodiments, the maximum value among the N effective read timing widths and N effective write timing widths can be determined. If the maximum value is not greater than a preset threshold, the channel can be considered to have passed the timing margin test; if the maximum value is greater than the preset threshold, the channel can be considered to have failed the timing margin test.

[0160] In the above embodiments, the maximum value of the effective timing width is compared with a preset threshold. In other embodiments, the average value of the effective timing width can also be determined, and the determined average value is compared with a preset threshold to determine whether the channel passes the timing margin test.

[0161] For example, in some embodiments, the average of N effective read timing widths (represented by Avg_rx) and the average of N effective write timing widths (represented by Avg_tx) can be calculated. If Avg_rx is not greater than a preset threshold (represented by preset timing threshold 3) and Avg_tx is not greater than another preset threshold (represented by preset timing threshold 4), then the channel can be considered to have passed the timing margin test; if Avg_rx is greater than preset timing threshold 3 or Avg_tx is greater than preset timing threshold 4, then the channel can be considered to have failed the timing margin test.

[0162] In other embodiments, the average of N effective read timing widths and N effective write timing widths can be calculated. If the average value is not greater than a preset threshold, the channel can be considered to have passed the timing margin test; if the average value is greater than the preset threshold, the channel can be considered to have failed the timing margin test.

[0163] Figure 9 This is a schematic diagram of a flash memory controller. Utilizing, for example... Figure 9 The delay-locked loop (DLL) and delay line (DL) in the DLL / DL module of the flash memory controller shown can be used to perform voltage margin testing.

[0164] Figure 10 This is a schematic flowchart for voltage margin testing. Assuming... Figure 10 The DLL / DL module shown allows setting the delay levels of DQS to N (N is a positive integer greater than or equal to 2). These N delay levels can be represented by T1, T2, ..., T... N express.

[0165] 1001, Set the initial DQS delay level to T1.

[0166] 1002, Determine whether the current DQS delay level is less than or equal to T. N If the current gear position of the DQS delay is less than or equal to the maximum delay gear position T. N Then proceed with the subsequent voltage margin test steps.

[0167] 1003, Write test data to the NAND flash chip.

[0168] and Figure 8 The timing margin test process is similar; test data can also be written to the NAND flash chip at a lower rate. The test data can also be error-prone data. The location for writing the test data can also be a cache register within the NAND flash chip.

[0169] 1004. Perform a reading direction timing margin test and record the reading direction voltage margin.

[0170] After writing test data to the NAND flash chip, the written test data can be read. During the test data reading process, the high level Vrx1h and low level Vrx1l of the current read direction are obtained, and the sum of Vrx1h and Vrx1l is determined as the voltage margin Vrx1 of the current read direction.

[0171] 1005, perform a write direction timing margin test and record the write direction voltage margin.

[0172] During the process of writing test data, the high level Vtx1h and low level Vtx1l of the current gear's write direction are obtained, and the sum of Vtx1h and Vtx1l is determined to be the voltage margin Vtx1 of the current gear's write direction.

[0173] 1006, Set the DQS delay level to the next level, i.e., T. n+1 Continue performing read-direction voltage margin tests and write-direction voltage margin tests to obtain read-direction voltage margins and write-direction voltage margins for N ranges in sequence.

[0174] After obtaining the read voltage margin and the write voltage margin for N ranges, it is possible to determine whether the voltage margin test has been passed based on these N ranges. For ease of description, the read voltage margin for N ranges can be referred to as the N read voltage margin, and the write voltage margin for N ranges can be referred to as the N write voltage margin.

[0175] The method for determining whether a channel passes the voltage margin test is similar to the method for determining whether a channel passes the timing margin test.

[0176] For example, in some embodiments, each voltage margin can be defined by a corresponding threshold range. If N read voltage margins and N write voltage margins are all within the corresponding threshold range, the channel can be determined to have passed the voltage margin test. If one voltage margin is not within the corresponding threshold range, the channel can be determined to have failed the margin test.

[0177] For example, in some embodiments, the maximum value of N read voltage margins can be compared with a preset threshold, and the maximum value of N write voltage margins can be compared with a preset threshold. Based on the comparison results, it can be determined whether the channel passes the margin test.

[0178] For example, in other embodiments, the average value of the voltage margin can be compared with the threshold.

[0179] For details on how to determine whether a channel passes the voltage margin test, please refer to the description of determining whether a channel passes the timing margin test. For the sake of brevity, it will not be repeated here.

[0180] Assuming channel 502 passes the margin test while channel 503 fails, then channel 503 can be determined to be a channel requiring optimization. In this case, channel 502 does not need optimization, but channel 503 needs optimization. The following discussion will focus on... Figures 11 to 12 The channel optimization process will be introduced.

[0181] Channel optimization can be divided into voltage margin optimization and timing margin optimization.

[0182] In some embodiments, voltage margin optimization and timing margin optimization can be performed simultaneously on the channel to be optimized (e.g., channel 503).

[0183] In other embodiments, the channel to be optimized (e.g., channel 503) may only be optimized for voltage margin, or only for timing margin.

[0184] For example, if channel 503 passes the voltage margin test but fails the timing margin test, then timing margin optimization can be performed on channel 503.

[0185] For example, if channel 503 passes the timing margin test but fails the voltage margin test, then voltage margin optimization can be performed on channel 503.

[0186] Figure 11 This is a schematic flowchart illustrating voltage margin optimization based on embodiments of this application.

[0187] 1101, obtain K read margins and K write margins. The K read margins correspond one-to-one with the K gear positions, and the K write margins correspond one-to-one with the K gear positions. K is a positive integer greater than 1.

[0188] As mentioned above, during the timing margin test, the effective width of the read-direction timing margin under N voltage levels and the effective width of the write-direction timing margin under N voltage levels can be extracted.

[0189] In some embodiments, K voltage levels (K is a positive integer greater than 1 and less than N) can be selected from the N voltage levels, along with the effective widths of the read-direction timing margin and the write-direction timing margin corresponding to the K voltage levels. The selected K voltage levels are the K levels in step 1101, the effective widths of the read-direction timing margins corresponding to the K voltage levels are the K read margins in step 1101, and the effective widths of the write-direction timing margins corresponding to the K voltage levels are the K write margins in step 1101.

[0190] There are several ways to select K voltage levels from N voltage levels. For example, K voltage levels can be selected randomly. Alternatively, one can select the K voltage levels corresponding to the effective widths of the K read-direction timing margins, where K can be a preset value or a positive integer calculated based on a preset ratio. Similarly, one can select the K voltage levels corresponding to the effective widths of the K write-direction timing margins, where K can be a preset value or a positive integer calculated based on a preset ratio.

[0191] In other embodiments, the K voltage levels can be the same as the N voltage levels. In other words, step 1101 can directly use the N voltage levels obtained from the timing margin test, as well as the effective width of the read-direction timing margin and the effective width of the write-direction timing margin for each voltage level. In this case, the value of K is the same as that of N.

[0192] If the K ranges are K voltage ranges, then the K read margins can also be called K read timing margins, and the K write margins can also be called K write timing margins.

[0193] As mentioned above, during the voltage margin test, the read-direction voltage margin and write-direction voltage margin can be obtained under the delay levels of N DQS.

[0194] Similarly, in some embodiments, K delay levels (K being a positive integer greater than 1 and less than N) can be selected from the N delay levels of the DQS, along with the read-direction voltage margin and write-direction voltage margin corresponding to the K delay levels. The selected K delay levels are the K levels in step 1101, the read-direction voltage margin corresponding to the K delay levels is the K read margin in step 1101, and the write-direction voltage margin corresponding to the K delay levels is the K write margin in step 1101.

[0195] There are several ways to select K delay levels from N DQS delay levels. For example, you can randomly select K DQS delay levels. Alternatively, you can select the K voltage levels corresponding to the K largest read-direction voltage margins, where K can be a preset value or a positive integer calculated based on a preset ratio. Similarly, you can select the K voltage levels corresponding to the K largest write-direction voltage margins, where K can be a preset value or a positive integer calculated based on a preset ratio.

[0196] In other embodiments, the K delay levels can be the same as the N delay levels of the DQS. In other words, step 1101 can directly use the delay levels of the N DQS obtained from the voltage margin test, as well as the read-direction voltage margin and write-direction voltage margin of the delay level of each DQS. In this case, the value of K is the same as that of N.

[0197] If the K ranges are the delay ranges of the K DQS, then the K read margins can also be called the K read voltage margins, and the K write margins can also be called the K write voltage margins.

[0198] 1102. Based on the K read margins and K write margins obtained in step 1101, determine the optimization parameters.

[0199] The optimal read voltage can be determined based on K read margins, and the optimal write voltage can be determined based on K write margins.

[0200] For example, the optimal voltage can be determined using the following formula:

[0201] , Formula 11.1

[0202] Where Vrx_best represents the optimal voltage for this read, V k T represents the k-th voltage level out of K voltage levels. rxk This represents the k-th read timing margin among the K read timing margins, where k = 1, ..., K.

[0203] The optimal voltage can be determined using the following formula:

[0204] , Formula 11.2

[0205] Where Vtx_best represents the optimized voltage, V k This represents the k-th voltage level out of the K voltage levels, T txk This represents the k-th write timing margin among the K write timing margins.

[0206] For example, the optimal read voltage can be the arithmetic average of the voltage margins in K read directions, that is, the optimal read voltage can be determined by the following formula:

[0207] , Formula 11.3

[0208] Where Vrx_best represents the optimal voltage for this read, V rxk This represents the k-th reading voltage margin among K reading voltage margins, where k = 1, ..., K.

[0209] The write optimization voltage can be the arithmetic average of the voltage margins in K write directions; that is, the optimized voltage can be determined using the following formula:

[0210] , Formula 11.4

[0211] Where Vtx_best represents the optimal voltage for this read, V txk This represents the k-th write voltage margin among K write voltage margins, where k = 1, ..., K.

[0212] In the above embodiments, all read margins and write margins determined in step 1101 are used in determining the read-optimized voltage and write-optimized voltage. In other embodiments, some read margins and write margins determined in step 1101 may also be used in determining the read-optimized voltage and write-optimized voltage. For example, after excluding the maximum and minimum read margins and write margins, the average of the remaining read margins can be used to obtain the read-optimized voltage, and the average of the remaining write margins can be used to obtain the write voltage margin.

[0213] The above embodiments can optimize the read reference voltage and write reference voltage, reduce the probability of transmission errors between the flash memory controller and the NAND flash chip, and improve storage performance.

[0214] Figure 12 This is a schematic flowchart illustrating timing margin optimization based on embodiments of this application.

[0215] 1201, Write test data to the NAND flash chip.

[0216] and Figure 8 The timing margin test process is similar; test data can also be written to the NAND flash chip at a lower rate. The test data can also be error-prone data. The location for writing the test data can also be a cache register within the NAND flash chip.

[0217] 1202, Get the effective width of the timing margin of DQ.

[0218] 1203. Determine the left boundary (L_Boundary) and the right boundary (R_Boundary) based on the effective width of the timing margin. The left boundary is the maximum value among the minimum effective widths of the timing margins of all DQs, and the right boundary is the minimum value among the maximum effective widths of the timing margins of all DQs when aligned with the left boundary.

[0219] 1204. Calculate the first center position based on the left and right boundaries. The first center position is the center of the minimum margin effective width after aligning all DQs during data reading training.

[0220] Wherein, the first center position is the average of the left and right boundaries, i.e., Centring = -(L_Boundary - R_Boundary) / 2.

[0221] 1205. Adjust the delay line DL of DQS to the first center position so that the edge of the DQS signal is located at the center point of the effective width of the DQ margin.

[0222] In addition, the method also includes: assigning the delay line DL value corresponding to the first center position to the DQS register; assigning the DL value of each DQ to the corresponding DQ register, wherein the DL value of each DQ refers to the length that needs to be adjusted to align each DQ with the edge of DQS, and then converting it into the value after converting it into the corresponding scale unit of DQ.

[0223] Optionally, the scale of DQS differs from that of DQ. Specifically, the DQS signal has more scale values, such as 1024 tap numbers, and the time represented by each scale unit is determined by the DQS period, which is the DQS period measured by DLL divided by 1024. The DQ signal has fewer scale values, such as 20 tap numbers, and the time represented by each scale unit is fixed (determined by the precision of the hardware circuit). Furthermore, the scale unit can be set to 5ps, 10ps, 20ps, etc.

[0224] The parameters used to adjust the delay line of DQS to the first center position can be called read-optimized DQS timing optimization parameters.

[0225] 1206, perform write direction margin timing training to obtain the second center position. This second center position is the center of the minimum margin effective width after aligning all DQs during write data training.

[0226] After completing the read-direction training, preset or custom data will be written at a normal rate, and then a read command will be sent to read the data that was just written, and timing training in the write direction will be performed.

[0227] The preset data or custom data written can be the same as or different from the preset data in the reading direction, and this is not limited in the embodiments.

[0228] After the write direction training is completed, the delay line DL corresponding to the second center position is assigned to the DQS register, and the DL value of each DQ is assigned to the corresponding DQ register. The DL value of each DQ refers to the length that needs to be adjusted to align each DQ with the edge of DQS, and then converted into the value after being converted into the corresponding scale unit of DQ.

[0229] The parameters used to adjust the delay line of DQS to the second center position can be called write-optimized DQS timing optimization parameters.

[0230] In the above method, training data is written at a low rate, then a read command is sent to read the training data, and read-direction timing training is performed. Using the left and right boundary values ​​of the effective margin width of each DQ signal on the NFI bus, the first center position of the read training direction is determined. The delay line of the controller-side DQ signal is automatically adjusted to maximize the effective margin width of all DQ signals. The delay line of the DQS signal is then adjusted to this first center position, ensuring that the edge of the DQS signal is located at the optimal sampling point of the DQ signal. Further, custom data is written at a normal rate, then a read command is sent to read the just-written data, and write-direction timing training is performed to determine the second center position. The delay line of the controller's DQ signal is then automatically adjusted to maximize the effective margin width of all received DQ signals, and the controller adjusts the delay line of the DQS signal to this second center position, ensuring that the edge of the DQS signal received by the NAND Flash receiver is located at the optimal sampling point of the DQ signal. In summary, by adjusting the position of the delay line of the DQS signal in the above scheme, the timing margin can be optimized, maximizing the effective width of the timing margin of the receiver signal, as well as the setup and hold time margins. This satisfies the specifications and avoids bit errors during data reading and writing, thus preventing data loss.

[0231] The left and right boundaries can be determined through one of the following three specific implementation methods:

[0232] The first method uses a preset boundary range [a,b] to determine the left and right boundaries;

[0233] The second method: Starting from 1 / 4 of the DQS cycle, adjust the position of DQS to the left and right to determine the left and right boundaries;

[0234] The third method: Starting from the initial scale value, gradually adjust the DQS position from left to right to determine the left and right boundaries.

[0235] Figure 13 This is a schematic flowchart of a method for optimizing flash memory chips according to an embodiment of this application.

[0236] 1301. During the operation of the flash memory chip, N channels in the non-volatile flash interface NFI bus of the flash memory chip are suspended, where N is an integer greater than or equal to 1 and less than or equal to the total number of channels in the NFI bus.

[0237] 1302, determine at least one channel to be optimized from the N channels.

[0238] 1303, Determine the optimization parameters for each of the at least one channels to be optimized based on the training data of each channel to be optimized.

[0239] 1304. Optimize each channel according to its optimization parameters.

[0240] The specific implementation methods for determining the channel to be optimized and the optimization parameters can be found in the above embodiments, and will not be repeated here for the sake of simplicity.

[0241] The above technical solution involves selecting and optimizing a subset of channels from multiple channels during flash memory chip operation. In other words, another subset of channels in the NFI bus is in normal working order. Therefore, channel parameter optimization can be achieved without disk failure. This reduces the dependence of the margin judgment standard on the physical environment and operating state, further compressing the margin judgment standard and leaving more margin for the interface link, thereby supporting higher speeds.

[0242] Figure 14 This is a schematic structural block diagram of an electronic device provided according to an embodiment of this application. For example... Figure 14 The electronic device 1400 shown can be as follows: Figure 1 The SSD 100 shown, or, could be as follows: Figure 1 The SSD controller 110 shown, or, could be as follows: Figure 1 The flash memory controller 113 is shown.

[0243] Processing unit 1401 is used to suspend N channels in the non-volatile flash memory interface NFI bus of the flash memory chip during the service operation of the flash memory chip, where N is an integer greater than or equal to 1 and less than or equal to the total number of channels in the NFI bus.

[0244] The determining unit 1402 is used to determine at least one channel to be optimized from the N channels.

[0245] The determining unit 1402 is further configured to determine the optimization parameters of each channel to be optimized based on the training data of each channel to be optimized in the at least one channel to be optimized.

[0246] The optimization unit 1403 is used to optimize each channel according to the optimization parameters of each channel to be optimized.

[0247] The specific functions and beneficial effects of the processing unit 1401, the determination unit 1402, and the optimization unit 1403 can be found in the above embodiments, and will not be repeated here for the sake of brevity.

[0248] This application also provides a chip system comprising: a logic circuit for coupling with an input / output interface to transmit data through the input / output interface to execute the method shown in the above embodiments.

[0249] The chip system can be as follows: Figure 1 The flash memory controller 113 shown can also be as follows: Figure 1 The SSD controller 110 shown is shown.

[0250] This application also provides an SSD that includes the above-described chip system.

[0251] The application also provides a computer-readable medium storing program code that, when run on a computer, causes the computer to execute the method shown in the above embodiments.

[0252] In implementation, each step of the above method can be completed by integrated logic circuits in the processor's hardware or by instructions in software. The steps of the method disclosed in the embodiments of this application can be directly implemented by a hardware processor, or by a combination of hardware and software modules in the processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory, and the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method. To avoid repetition, detailed descriptions are omitted here.

[0253] It should be noted that the processor in the embodiments of this application can be an integrated circuit chip with signal processing capabilities. In implementation, each step of the above method embodiments can be completed by the integrated logic circuitry in the processor's hardware or by instructions in software form. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in the embodiments of this application can be directly implemented by a hardware decoding processor, or by a combination of hardware and software modules in the decoding processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method.

[0254] It is understood that the memory in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM). It should be noted that the memory used in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0255] According to the method provided in the embodiments of this application, this application also provides a computer program product, which includes computer program code, which, when run on a computer, causes the computer to perform the method shown in the above embodiments.

[0256] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0257] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0258] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0259] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0260] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0261] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0262] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method of optimizing a flash memory grain, the method comprising: The method includes: During the operation of the flash memory chip, N channels in the non-volatile flash memory interface NFI bus of the flash memory chip are suspended, where N is an integer greater than or equal to 1 and less than or equal to the total number of channels in the NFI bus; Determine at least one channel to be optimized from the N channels; Based on the training data of each of the at least one channels to be optimized, determine the optimization parameters for each channel to be optimized; Based on the optimization parameters of each channel to be optimized, each channel to be optimized is optimized, wherein determining at least one channel to be optimized from N channels includes: A margin test is performed on the nth channel out of the N channels to obtain the margin of the nth channel, where n is an integer from 1 to N. Determine whether the margin of the nth channel meets the margin condition, wherein the margin condition includes at least one of timing margin condition and voltage margin condition; If the margin of the nth channel does not meet the margin condition, then the nth channel is determined to belong to the channel to be optimized.

2. The method of claim 1, wherein, The optimization parameters include read optimization voltage and write optimization voltage. The training data for each channel to be optimized includes K read margins and K write margins for each channel to be optimized, where K is a positive integer greater than 1. The step of determining the optimization parameters for each channel to be optimized based on the training data of each channel to be optimized in the at least one channel to be optimized includes: The average value of the K read margins is determined as the read optimization voltage; The average value of the K write margins is determined as the write optimization voltage.

3. The method as described in claim 2, characterized in that, The K read margins are K read timing margins, the K write margins are K write timing margins, and the K read timing margins correspond one-to-one with the K voltage levels. The K write timing margins also correspond one-to-one with the K voltage levels. The optimized reading voltage is determined by the following formula: Where Vrx_best represents the read optimization voltage, V k T represents the k-th voltage level among the K voltage levels. rxk This represents the k-th read timing margin among the K read timing margins, where k = 1, ..., K; The write optimization voltage is determined by the following formula: ， Where Vtx_best represents the write optimization voltage, V k T represents the k-th voltage level among the K voltage levels. txk This represents the k-th write timing margin among the K write timing margins.

4. The method as described in claim 2, characterized in that, The K read margins are K read voltage margins, the K write margins are K write voltage margins, and the K read voltage margins correspond one-to-one with the K data latch signal DQS delay levels. The K write voltage margins correspond one-to-one with the K DQS delay levels. The optimized read voltage is the arithmetic average of the K read voltage margins. The write optimization voltage is the arithmetic average of the K write voltage margins.

5. The method of any one of claims 1 to 4, wherein, The optimization parameters include read-optimized DQS timing optimization parameters and write-optimized DQS timing optimization parameters. The training data for each channel to be optimized includes read-direction training data and write-direction training data. Determining the optimization parameters for each channel to be optimized based on the training data of each of the at least one channel to be optimized includes: Based on the read direction training data, the read-optimized DQS timing optimization parameters are determined. The read direction training data includes the left and right boundaries obtained through read direction timing training. The read-optimized DQS timing optimization parameters are used to adjust the delay line of the DQS to a first center position, where the first center position is the average value of the left and right boundaries obtained through read direction timing training. Based on the write direction training data, the write-optimized DQS timing optimization parameters are determined. The write direction training data includes the left and right boundaries obtained through write direction timing training. The write-optimized DQS timing optimization parameters are used to adjust the delay line of DQS to a second center position, where the second center position is the average value of the left and right boundaries obtained through write direction timing training.

6. An electronic device, comprising: The electronic device includes: The processing unit is used to suspend N channels in the non-volatile flash memory interface NFI bus of the flash memory chip during the service operation of the flash memory chip, where N is an integer greater than or equal to 1 and less than or equal to the total number of channels in the NFI bus; A determining unit is configured to determine at least one channel to be optimized from the N channels; The determining unit is further configured to determine the optimization parameters of each channel to be optimized based on the training data of each channel to be optimized in the at least one channel to be optimized. The optimization unit is used to optimize each channel to be optimized according to the optimization parameters of each channel to be optimized, wherein the determining unit is specifically used for: A margin test is performed on the nth channel out of the N channels to obtain the margin of the nth channel, where n is an integer from 1 to N. Determine whether the margin of the nth channel meets the margin condition, wherein the margin condition includes at least one of timing margin condition and voltage margin condition; If the margin of the nth channel does not meet the margin condition, then the nth channel is determined to belong to the channel to be optimized.

7. The electronic device of claim 6, wherein, The optimization parameters include read optimization voltage and write optimization voltage. The training data for each channel to be optimized includes K read margins and K write margins for each channel to be optimized, where K is a positive integer greater than 1. The determining unit is specifically used for: The average value of the K read margins is determined as the read optimization voltage; The average value of the K write margins is determined as the write optimization voltage.

8. The electronic device of claim 7, wherein, The K read margins are K read timing margins, the K write margins are K write timing margins, and the K read timing margins correspond one-to-one with the K voltage levels. The K write timing margins also correspond one-to-one with the K voltage levels. The determining unit is specifically used to determine the optimized reading voltage using the following formula: Where Vrx_best represents the read optimization voltage, V k T represents the k-th voltage level among the K voltage levels. rxk This represents the k-th read timing margin among the K read timing margins, where k = 1, ..., K; The determining unit is specifically used to determine the write optimization voltage using the following formula: ， where Vtx_best represents the write-optimized voltage, V k represents the kth voltage step of the K voltage steps, T txk represents the kth write timing margin of the K write timing margins.

9. The electronic device of claim 7, wherein, The K read margins are K read voltage margins, the K write margins are K write voltage margins, and the K read voltage margins correspond one-to-one with the K data latch signal DQS delay levels. The K write voltage margins correspond one-to-one with the K DQS delay levels. The determining unit is specifically used to determine the arithmetic average of the K read voltage margins as the read optimized voltage; and to determine the arithmetic average of the K write voltage margins as the write optimized voltage.

10. The electronic device as claimed in any one of claims 6 to 9, characterized in that, The optimization parameters include read-optimized DQS timing optimization parameters and write-optimized DQS timing optimization parameters. The training data for each channel to be optimized includes read-direction training data and write-direction training data. The determining unit is specifically used for: Based on the read direction training data, the read-optimized DQS timing optimization parameters are determined. The read direction training data includes the left and right boundaries obtained through read direction timing training. The read-optimized DQS timing optimization parameters are used to adjust the delay line of the DQS to a first center position, where the first center position is the average value of the left and right boundaries obtained through read direction timing training. Based on the write direction training data, the write-optimized DQS timing optimization parameters are determined. The write direction training data includes the left and right boundaries obtained through write direction timing training. The write-optimized DQS timing optimization parameters are used to adjust the delay line of DQS to a second center position, where the second center position is the average value of the left and right boundaries obtained through write direction timing training.

11. A solid-state drive (SSD), characterized in that, include: An SSD controller is coupled to flash memory via a non-volatile flash interface (NFI) bus. The SSD controller is also coupled to memory to read and execute instructions and / or program code in the memory to perform the method as described in any one of claims 1-5.

12. A chip system, characterized in that, include: A logic circuit for coupling with an input / output interface, through which data is transmitted to perform the method as described in any one of claims 1-5.

13. A computer readable medium characterized by The computer-readable medium stores program code that, when run on a computer, causes the computer to perform the method as described in any one of claims 1-5.

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