Host storage system including command queuing method and method of adjusting processing speed of multiple queues

Abstract

A method for queuing commands includes: comparing a first virtual time of a first command with a second virtual time of a second command and obtaining a comparison result; determining a standard global virtual time from the first virtual time and the second virtual time based on the comparison result; and sending each of the first command and the second command to one of a first priority queue, a second priority queue, and a third priority queue based on the difference between the first virtual time and the global virtual time, and the difference between the second virtual time and the global virtual time, wherein each of the first priority queue to the third priority queue has a different processing speed from each other.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0024161, filed on February 23, 2021, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of this disclosure relate to a host storage system that includes a command queuing method and a method for adjusting the processing speed of multiple queues. Background Technology

[0004] A host is an entity that can interact with a controller by sending commands that depend on the NVMe specification. The NVMe, or NVMHCI (Non-volatile Memory Host Controller Interface) specification, is a logical device interface specification for accessing non-volatile storage media connected via the PCIe bus.

[0005] NVMe is a scalable host controller interface that meets the needs of enterprise and client systems. Multiple interfaces can exist, such as administrative (Admin) or input / output (I / O) queues, for data transfer between the host and the storage controller (NVMe controller). The NVMe controller is associated with PCIe functionality, which processes commands from the host and sends appropriate responses to the host, depending on the NVMe specification. For example, an NVMe subsystem may include a single PCIe port and multiple namespaces.

[0006] In the past, scheduling utilized host-side computing resources to ensure fairness among users, programs, or processes. Currently, while NVMe provides scheduling capabilities between command queues, this only allocates processing frequency, and therefore NVMe may not guarantee fairness. Therefore, to reduce the use of host-side computing resources, measures should be designed to leverage the scheduling capabilities provided by NVMe to ensure fairness. Summary of the Invention

[0007] Embodiments of this disclosure provide a command queuing method to reduce host core utilization.

[0008] Embodiments of this disclosure also provide a method for adjusting the processing speed of multiple queues, which reduces the utilization of the host core.

[0009] Embodiments of this disclosure also provide a host storage system that reduces the utilization of the host core.

[0010] According to some embodiments of this disclosure, a method for queuing commands is provided, the method comprising: comparing a first virtual time of a first command with a second virtual time of a second command and obtaining a comparison result; determining a standard global virtual time from the first virtual time and the second virtual time based on the comparison result; and sending each of the first command and the second command to one of a first priority queue, a second priority queue, or a third priority queue based on the difference between the first virtual time and the global virtual time, and the difference between the second virtual time and the global virtual time, wherein each of the first priority queue to the third priority queue has a different processing speed from each other.

[0011] According to some embodiments of this disclosure, a method for adjusting the processing speed of multiple queues is provided, the method comprising: sending each of a first command and a second command different from the first command to one of a first priority queue to a third priority queue; calculating a first processing frequency value for the first priority queue to the third priority queue; and adjusting the processing speed of the first priority queue to the third priority queue based on the first processing frequency value.

[0012] According to some embodiments of this disclosure, a host storage system is provided, comprising: a host interface that receives a first command and a second command from a host via an NVMe (Non-Volatile Memory Fast) interface; a WRR arbitration unit that includes a first priority queue to a third priority queue; and an I / O scheduler that sends the first command and the second command to the first priority queue to the third priority queue, wherein the WRR arbitration unit receives from the I / O scheduler the processing frequency for each computation in the priority queue, and executes the commands in the queue in a weighted round-robin manner based on the processing frequency.

[0013] Other features and embodiments will become apparent from the following detailed description, drawings and claims. Attached Figure Description

[0014] Figure 1 This is a block diagram of a host storage system according to some embodiments.

[0015] Figure 2 This is a flowchart of the operation of a host storage system according to some embodiments.

[0016] Figures 3 to 7 The operation of a host storage system according to some embodiments is illustrated. Detailed Implementation

[0017] In the following description, embodiments based on the technical concept of this disclosure will be described with reference to the accompanying drawings.

[0018] Figure 1This is a block diagram of a host storage system according to some embodiments.

[0019] Reference Figure 1 In some embodiments, the host storage system 10 includes a host 100 and a storage device 200. The storage device 200 includes a storage controller 210 and a non-volatile memory (NVM) 220. According to an exemplary embodiment of the present invention, the host 100 includes a host controller 110 and a host memory 120. The host memory 120 serves as a buffer memory for temporarily storing data to be sent to the storage device 200 or for receiving data sent from the storage device 200.

[0020] In some embodiments, the host controller 110 further includes an I / O scheduler 111.

[0021] In some embodiments, the I / O scheduler 111 selectively or dynamically sends I / O commands to the WRR arbitration unit 219.

[0022] In some embodiments, storage device 200 includes a storage medium that stores data in response to a request from host 100. For example, storage device 200 may include at least one of an SSD (Solid State Drive), embedded memory, or removable external memory. If storage device 200 is an SSD, it conforms to the NVMe (Non-Volatile Memory Fast) standard. If storage device 200 is embedded memory or external memory, it conforms to the UFS (Universal Flash Memory) or eMMC (Embedded Multimedia Card) standard. Both host 100 and storage device 200 generate and transmit packets according to the standard protocols employed.

[0023] In some embodiments, when the non-volatile memory 220 of the storage device 200 includes flash memory, the flash memory may include a 2D NAND memory array or a 3D (or vertical) NAND (VNAND) memory array. As another example, the storage device 200 may also include various other types of non-volatile memory. For example, MRAM (magnetic RAM), spin-transfer torque MRAM, conductive bridged RAM (CBRAM), FeRAM (ferroelectric RAM), PRAM (phase RAM), resistive memory (resistive RAM), and various other types of memory may be used as storage device 200.

[0024] In some embodiments, the host controller 110 and the host memory 120 are implemented as separate semiconductor chips. Alternatively, in some embodiments, the host controller 110 and the host memory 120 are integrated on the same semiconductor chip. For example, the host controller 110 is one of a plurality of modules disposed in an application processor, and the application processor is implemented as a system-on-a-chip (SoC). Furthermore, the host memory 120 may be an embedded memory disposed within the application processor, or it may be a non-volatile memory or memory module disposed outside the application processor.

[0025] In some embodiments, host controller 110 manages operations that store data (e.g., recorded data) from a buffer in host memory 120 in non-volatile memory 220 or operations that store data (e.g., read data) from volatile memory 220 in a buffer.

[0026] In some embodiments, the storage controller 210 includes a host interface 211, a memory interface 212, and a core. Additionally, the storage controller 210 includes a flash translation layer (FTL) 214, a packet manager 215, a buffer memory 216, an ECC (Error Correction Code) engine 217, an AES (Advanced Encryption Standard) engine 218, and a WRR (Weighted Round Robin) arbitration unit 219.

[0027] In some embodiments, the storage controller 210 further includes working memory that loads the flash translation layer 214, and when the core performs the flash translation layer, the core controls the data recording and reading operations of the non-volatile memory 220.

[0028] In some embodiments, host interface 211 sends packets to and receives packets from host 100. Packets sent from host 100 to host interface 211 include commands (CMD) or data to be recorded in non-volatile memory 220, and packets sent from host interface 211 to host 100 include responses to commands, data read from non-volatile memory 220, etc. In some embodiments, host interface 211 includes a weighted loop interface according to NVM-Express / v1.4 / section4.13.2 - with urgent priority arbitration specification.

[0029] In some embodiments, memory interface 212 sends data to be recorded in non-volatile memory 220 or receives data read from non-volatile memory 220. Memory interface 212 conforms to standard conventions such as Toggle or ONFI (Open NAND Flash Interface).

[0030] In some embodiments, the core receives a command CMD from the host 100. The core then forwards the command CMD to the I / O scheduler 111. The core determines the priority queues 219a to 219c of the WRR arbitration unit 219 in response to the command CMD.

[0031] In some embodiments, the flash translation layer 214 performs various functions, such as address mapping, wear leveling, and garbage collection. Address mapping changes logical addresses received from host 100 to physical addresses, which are used to actually store data in non-volatile memory 220. Wear leveling ensures that blocks in non-volatile memory 220 are used uniformly to prevent excessive degradation of particular blocks and can be implemented, for example, through firmware techniques that balance the erase counts of physical blocks. Garbage collection ensures available capacity in non-volatile memory 220 by copying valid data from existing blocks to new blocks and then erasing the existing blocks.

[0032] In some embodiments, the packet manager 215 generates packets according to the protocol of the interface discussed with the host 100, or parses various types of information from packets received from the host 100.

[0033] In some embodiments, buffer memory 216 temporarily stores data to be recorded in non-volatile memory 220 or data that has already been read from non-volatile memory 220. Buffer memory 216 may be located inside storage controller 210, or it may be located outside storage controller 210.

[0034] In some embodiments, the ECC engine 217 performs error detection and correction functions on read data read from the non-volatile memory 220. More specifically, the ECC engine 217 generates parity bits on the write data to be written to the non-volatile memory 220, and the generated parity bits are stored in the non-volatile memory 220 along with the write data. When reading data from the non-volatile memory 220, the ECC engine 217 uses the parity bits read from the non-volatile memory 220 along with the read data to detect and correct errors in the read data, and outputs the corrected read data.

[0035] In some embodiments, the AES engine 218 uses a symmetric key algorithm to perform encryption or decryption of at least one of the data input to the storage controller 210.

[0036] In some embodiments, the WRR arbitration unit 219 includes a first priority queue 219a, a second priority queue 219b, and a third priority queue 219c. The WRR arbitration unit 219 receives commands (CMD) from the core into one of the first priority queues 219a to the third priority queue 219c. The WRR arbitration unit 219 adjusts the processing speed of commands or queues based on processing frequency values.

[0037] In some embodiments, a first priority queue 219a queues commands CMD to be processed at the fastest speed, a third priority queue 219c queues commands CMD to be processed at the slowest speed, and a second priority queue 219b queues commands CMD to be processed at an intermediate speed between the fastest and slowest speeds.

[0038] Figure 2 This is a flowchart of the operation of a host storage system according to some embodiments.

[0039] Figures 3 to 7 The operation of a host storage system according to some embodiments is illustrated.

[0040] Reference Figure 2 The command is sent from the host to the I / O scheduler (S100).

[0041] Specifically, in some embodiments, reference is made to Figure 1 The host controller 110 receives a command CMD requesting the execution of an operation by the I / O scheduler 111. The command CMD can be a command within a process, or it can be a command from a different process.

[0042] In some embodiments, the operation includes, for example, inputting data into a non-volatile memory cell of the non-volatile memory 220 addressed to a logical or physical address, or outputting data stored in a non-volatile memory cell of the non-volatile memory 220 addressed to a logical or physical address. However, the embodiments are not limited thereto, and examples of the operation of the non-volatile memory 220 can be modified multiple times as needed.

[0043] Next, in some embodiments, the I / O scheduler determines which priority queue the received command should be sent to (S110).

[0044] Specifically, in some embodiments, reference is made to Figure 1 The I / O scheduler 111 generates inputs and outputs for a command CMD corresponding to the command CMD received from the host 100, which is to be sent to the non-volatile memory 220. Furthermore, the I / O scheduler 111 determines which priority queue in the WRR arbitration unit 219 to send the generated command to.

[0045] Next, in some embodiments, the I / O scheduler sends commands to the priority queue of the WRR arbitration (S120).

[0046] Specifically, in some embodiments, reference will be made to Figure 3 and Figure 5This describes the method by which the I / O scheduler 111 queues commands requested by a process or procedure. Here, "procedure" and "process" have the same meaning and can be referred to as a process. Figure 3 Four processes are shown: Flow1, Flow2, Flow3, and Flow4.

[0047] In some embodiments, the I / O scheduler 111 determines the global virtual time (gvt) from the virtual time of the first process to the fourth process (process 1 to process 4). Virtual time is a value determined by dividing the total amount of input / output services provided by the process by the weight of each process and then leveling it off.

[0048] Furthermore, in some embodiments, the I / O scheduler 111 determines a priority queue for queuing the first to fourth commands (CMD1 to CMD4) based on the determined global virtual time (gvt), taking into account the virtual time (vta to vtd) of each of the first to fourth flows (Flow1 to Flow4) and / or the commands (CMD1 to CMD4) of the first to fourth flows (Flow1 to Flow4). Although a flow (Flow) may be associated with various commands (CMI), or various commands (CMD) may be associated with various flows (Flow), the embodiments are not limited thereto.

[0049] In some embodiments, when the difference between the virtual time (vta to vtd) and the global virtual time (gvt) of the first to fourth commands (CMD1 to CMD4) of the first to fourth processes (Flow1 to Flow4) is greater than a first threshold tl, the I / O scheduler 111 sends the commands of the process to the third priority queue 219c.

[0050] Furthermore, in some embodiments, when the difference between the virtual time (vta to vtd) and the global virtual time (gvt) of the first to fourth processes (Flow1 to Flow4) or the first to fourth commands (CMD1 to CMD4) of the first to fourth processes (Flow1 to Flow4) is less than a second threshold tm, the I / O scheduler 111 sends the commands of the process to the first priority queue 219a. Here, the second threshold (tm) may be less than the first threshold (tl).

[0051] Furthermore, in some embodiments, when the difference between the virtual time (vta to vtd) and the global virtual time (gvt) of the first to fourth flow (Flow1 to Flow4) or the first to fourth command (CMD1 to CMD4) of the first to fourth flow (Flow1 to Flow4) is less than a first threshold (tl) and greater than a second threshold (tm), the I / O scheduler 111 sends the command of the flow to the second priority queue 219b.

[0052] Here, each of the first priority queues 219a to the third priority queue 219c has a different processing speed than the others.

[0053] Reference Figure 3 , Figure 4 and Figure 5 Assume the flow has first to fourth commands (CMD1 to CMD4).

[0054] In some embodiments, each of the first to fourth commands (CMD1 to CMD4) has a first to fourth virtual time (vta to vtd).

[0055] In some embodiments, the I / O scheduler 111 compares a first virtual time to a fourth virtual time (vta to vtd) to determine a standard global virtual time (gvt). Here, the global virtual time (gvt) is the minimum of the first virtual time to the fourth virtual time (vta to vtd). The global virtual time (gvt) is the first virtual time (vta).

[0056] In some embodiments, the I / O scheduler 111 compares the second to fourth virtual times (vtb to vtd) with the first virtual time (vta) which is the global virtual time (gvt), and sends each of the second to fourth commands (CMD2 to CMD4) to one of the first priority queues 219a to the third priority queues 219c.

[0057] Reference Figure 3 and Figure 5 In some embodiments, since the first virtual time (vta) is the global virtual time (gvt), the I / O scheduler 111 sends the first command CMD1 to the first priority queue 219a.

[0058] Reference Figure 3 and Figure 5In some embodiments, when the second virtual time (vtb) is compared with the global virtual time (gvt), since the value obtained by subtracting the global virtual time (gvt) from the second virtual time (vtb) is less than the second threshold (tm), the I / O scheduler 111 sends the second command CMD2 to the first priority queue 219a.

[0059] Reference Figure 3 and Figure 5 In some embodiments, when the third virtual time (vtc) is compared with the global virtual time (gvt), since the value obtained by subtracting the global virtual time (gvt) from the third virtual time (vtb) is greater than the first threshold (tl), the I / O scheduler 111 sends the third command CMD3 to the third priority queue 219c.

[0060] Reference Figure 3 and Figure 5 In some embodiments, when the fourth virtual time (vtd) is compared with the global virtual time (gvt), since the value obtained by subtracting the global virtual time (gvt) from the fourth virtual time (vtd) is greater than the second threshold (tm) and less than the first threshold (tl), the I / O scheduler 111 sends the fourth command CMD4 to the second priority queue 219b.

[0061] In this way, in some embodiments, by comparing the global virtual time (gvt) with the first to fourth virtual times (vta to vtd) in the I / O scheduler 111, and by immediately sending each of the first to fourth commands (CMD1 to CMD4) to one of the first priority queues 219a to the third priority queue 219c, no special processing is required on the host controller 110. Therefore, the use of the host core is reduced.

[0062] In the following text, reference will be made to Figure 6 and Figure 7 Another method is described for I / O scheduler 111 to queue commands CMD received from host 100 into priority queues 219a to 219c.

[0063] The following text will primarily describe and reference... Figure 3 and Figure 5 The differences in the methods of description.

[0064] Reference Figure 6 and Figure 7 In some embodiments, the global virtual time (gvt) is the second virtual time (vtb) of the second command CMD2.

[0065] In some embodiments, the I / O scheduler 111 compares the first to fourth virtual times (vta to vtd) with the second virtual time (vtb) which is the global virtual time (gvt), and sends each of the first to fourth commands (CMD1 to CMD4) to one of the first priority queues 219a to the third priority queues 219c.

[0066] In some embodiments, when the first virtual time (vta) is compared with the global virtual time (gvt), since the value obtained by subtracting the global virtual time (gvt) from the first virtual time (vtb) is greater than the first threshold (tl), the I / O scheduler 111 sends the first command CMD1 to the third priority queue 219c.

[0067] In some embodiments, since the second virtual time (vtb) is the global virtual time (gvt), the I / O scheduler 111 sends the second command CMD2 to the first priority queue 219a.

[0068] In some embodiments, when the third virtual time (vtc) is compared with the global virtual time (gvt), since the value obtained by subtracting the global virtual time (gvt) from the third virtual time (vtc) is greater than the second threshold (tm) and less than the first threshold (tl), the I / O scheduler 111 sends the third command CMD3 to the second priority queue 219b.

[0069] In some embodiments, when the fourth virtual time (vtd) is compared with the global virtual time (gvt), since the value obtained by subtracting the global virtual time (gvt) from the fourth virtual time (vd) is less than the second threshold (tm), the I / O scheduler 111 can send the fourth command CMD4 to the first priority queue 219a.

[0070] Refer again Figure 2 In some embodiments, the I / O scheduler calculates the processing frequency (S130). Furthermore, the I / O scheduler sends the calculated processing frequency to the WRR arbitration unit 219 (S140). The WRR arbitration unit 219 executes commands in the queues in a weighted round-robin manner based on the processing frequency. Additionally, the WRR arbitration unit 219 adjusts the processing speed of multiple queues based on the processing frequency (S150).

[0071] Specifically, a method will be described for the WRR arbitration unit 219, according to some embodiments, to adjust the processing speed of multiple queues based on the processing frequency sent from the I / O scheduler 111.

[0072] In some embodiments, the I / O scheduler 111 calculates a first processing frequency value hn for priority queues 219a to 219c, where n is a natural number. Furthermore, the WRR arbitration unit 219 adjusts the processing speed of priority queues 219a to 219c based on the first processing frequency value (hn) and the increase in virtual time of commands. Here, the first processing frequency value (hn) is obtained by dividing the currently set processing speed of the first priority queue 219a by the processing speed of the third priority queue 219c.

[0073] In some embodiments, the I / O scheduler 111 calculates a second processing frequency value (hn+1) for the first priority queue 219a to the third priority queue 219c of the WRR arbitration unit 219 based on a first processing frequency value (hn). Furthermore, the WRR arbitration unit 219 adjusts the processing speed of the first priority queue 219a to the third priority queue 219c based on the second processing frequency value (hn+1).

[0074] In some embodiments, the second processing frequency value (hn+1) is the virtual time increment of the first command CMD1 by an amount Δvt. max The virtual time increment Δvt of the third command CMD3 min The ratio is calculated by multiplying the first processing frequency value (hn). Among them, the first command CMD1 is the command with the longest virtual time, and the third command CMD3 is the command with the shortest virtual time.

[0075] The second processing frequency value (hn+1) is calculated according to the following formula 1.

[0076] Formula 1:

[0077]

[0078] Here, h n+1 It is the second processing frequency value, h n It is the first processing frequency value, Δvt max It is the virtual time increment of the first command, and Δvt min It is the amount of virtual time increment for the third command.

[0079] However, in some embodiments, if the second processing frequency value (hn+1) calculated according to Formula 1 is too large, the processing speed of multiple queues will not be continuously adjusted.

[0080] In this case, in some embodiments, the process of calculating the second processing frequency value (hn+1) includes the process of calculating the deceleration value (deceleration (f)), and the calculated deceleration value (deceleration (f)) becomes the second processing frequency value (hn+1).

[0081] In some embodiments, the deceleration value (deceleration(f)) is the minimum processing speed adjustment ratio of the multiple queues. That is, the second processing frequency value (hn+1) is the maximum value of the deceleration value (deceleration(f)), as shown in Formula 2 below.

[0082] Formula 2:

[0083] h n+1 =Max(slowdown(f)).

[0084] The deceleration value (deceleration (f)) is calculated according to the following formula 3.

[0085] Formula 3:

[0086]

[0087] Here, ∑l f，h It is the total number of commands sent by process f to the first priority queue, ∑l f，m It is the total number of all commands sent by process f to the second priority queue, ∑l f，l P is the total number of commands sent by process f to the third priority queue. h P is the processing frequency value of the first priority queue. m P1 is the processing frequency value of the second priority queue, and P2 is the processing frequency value of the third priority queue.

[0088] In some embodiments, the I / O scheduler 111 calculates the processing frequency of the first priority queue 219a to the third priority queue 219c and sends the processing frequency to the WRR arbitration unit 219 to adjust the processing speed of the multiple queues, thereby ensuring the fairness of the processing speed.

[0089] For example, in some embodiments, the I / O scheduler 111 calculates a second processing frequency value (hn+1) from the processing frequency of the first priority queue 219a, calculates the square root of the second processing frequency value (hn+1) from the processing frequency of the second priority queue 219b, and calculates the natural number 1 of the processing frequency of the third priority queue 219c, and sends this value to the WRR arbitration unit 219. The queue processing speed is not necessarily limited to three priority queues and can be set in any form to adjust the processing speed difference between two or more priority queues.

[0090] In concluding with the detailed description, those skilled in the art will understand that many variations and modifications can be made to the embodiments without substantially departing from the principles of this disclosure. Therefore, the disclosed embodiments of this disclosure are for general and descriptive purposes only and are not intended to be limiting.

Claims

1. A method for queuing commands in a host storage system, the host storage system comprising a host and a storage device communicating using an NVMe non-volatile memory fast interface, the method comprising: The I / O scheduler receives the first command corresponding to the first process and the second command corresponding to the second process. The I / O scheduler compares the first virtual time of the first process with the second virtual time of the second process and obtains the comparison result. The virtual time of the process is obtained by dividing the total amount of input / output services provided by each process by the weight of each process and then balancing. The I / O scheduler determines a global virtual time from the first virtual time and the second virtual time based on the comparison result, wherein the global virtual time is the minimum value between the first virtual time and the second virtual time; and The I / O scheduler, based on the difference between the first virtual time and the global virtual time, and the difference between the second virtual time and the global virtual time, sends each of the first command and the second command to one of the first priority queue, the second priority queue, or the third priority queue. Each of the first priority queue to the third priority queue has a different processing speed in the storage device.

2. The method for queuing commands according to claim 1, wherein... When the difference between the first virtual time and the global virtual time is greater than a first threshold, the first command is sent to the third priority queue, and When the difference between the first virtual time and the global virtual time is less than the first threshold and less than the second threshold, the first command is sent to the first priority queue.

3. The method for queuing commands according to claim 2, wherein, When the difference between the first virtual time and the global virtual time is greater than the second threshold and less than the first threshold, the first command is sent to the second priority queue.

4. The method for queuing commands according to claim 1 further includes: The I / O scheduler receives the third command corresponding to the third process; The I / O scheduler compares the first virtual time of the first process with the third virtual time of the third process. as well as The I / O scheduler compares the second virtual time of the second process with the third virtual time of the third process. Determining the global virtual time includes determining the minimum virtual time between the first virtual time and the third virtual time.

5. A method for adjusting the processing speed of multiple queues in a digital electronic storage device, the digital electronic storage device communicating with a host via an NVMe non-volatile memory fast interface, the method comprising: The I / O scheduler receives the first command corresponding to the first process and the second command corresponding to the second process. The I / O scheduler compares the first virtual time of the first process with the second virtual time of the second process and obtains the comparison result. The virtual time of the process is obtained by dividing the total amount of input / output services provided by each process by the weight of each process and then balancing. The I / O scheduler determines the global virtual time from the first virtual time and the second virtual time, wherein the global virtual time is the minimum value between the first virtual time and the second virtual time; The I / O scheduler uses the difference between the first virtual time and the global virtual time, and the difference between the second virtual time and the global virtual time, to send each of the first command and the second command to one of the first priority queue, the second priority queue, and the third priority queue. The I / O scheduler calculates the first processing frequency value from the first priority queue to the third priority queue; and The storage device adjusts the processing speed of the first priority queue to the third priority queue based on the first processing frequency value.

6. The method for adjusting the processing speed of multiple queues in a digital electronic storage device according to claim 5, wherein, The first processing frequency value is obtained by dividing the processing speed of the first priority queue by the processing speed of the third priority queue.

7. The method for adjusting the processing speed of multiple queues in a digital electronic storage device according to claim 6, further comprising: By calculating the virtual time increments of the first and second processes, a second processing frequency value from the first priority queue to the third priority queue is calculated from the first processing frequency value. The processing speed of the first priority queue to the third priority queue is further adjusted based on the second processing frequency value.

8. The method for adjusting the processing speed of multiple queues in a digital electronic storage device according to claim 7, wherein, The second processing frequency value is calculated by multiplying the ratio of the increase in virtual time of the first process to the increase in virtual time of the second process by the first processing frequency value.

9. The method for adjusting the processing speed of multiple queues in a digital electronic storage device according to claim 8, wherein, The second processing frequency value is calculated using the following formula: Among them, h n+1 It is the second processing frequency value, h n It is the first processing frequency value, Δvt max It is the increase in virtual time for the first process, and Δvt min This is the increase in virtual time for the second process.

10. The method for adjusting the processing speed of multiple queues in a digital electronic storage device according to claim 5, wherein, Calculating the first processing frequency value includes calculating the deceleration value for each process using the following formula: Where, ∑l f,h It is the total number of all commands sent by process f to the first priority queue, ∑l f,m It is the total number of all commands sent by process f to the second priority queue, ∑l f,l P is the total number of all commands sent by process f to the third priority queue. h P is the processing frequency value of the first priority queue. m It is the processing frequency value of the second priority queue, and P l It is the processing frequency value of the third priority queue.

11. A host storage system, comprising: The host interface is configured to receive a first command corresponding to the first procedure and a second command corresponding to the second procedure from the host via an NVMe non-volatile memory fast interface; The WRR arbitration unit includes a first priority queue, a second priority queue, and a third priority queue; as well as An I / O scheduler is configured to send the first command and the second command to the first priority queue and then to the third priority queue, and to determine a global virtual time from the first virtual time of the first process and the second virtual time of the second process, wherein the virtual time of a process is obtained by dividing the total amount of input / output services provided by each process by the weight of each process and then leveling it, wherein the global virtual time is the minimum of the first virtual time and the second virtual time. The WRR arbitration unit is configured to receive different processing frequencies for each computation in the priority queue from the I / O scheduler, and execute commands in the queue in a weighted round-robin manner based on the processing frequencies. The I / O scheduler is further configured to use the difference between the first virtual time and the global virtual time, and the difference between the second virtual time and the global virtual time, to send each of the first command and the second command to one of the first priority queues to the third priority queue.

12. The host storage system according to claim 11, wherein, The I / O scheduler is configured to calculate a first processing frequency value from the first priority queue to the third priority queue, and The WRR arbitration unit is configured to adjust the processing speed of the first priority queue to the third priority queue based on the first processing frequency value.

13. The host storage system of claim 12, wherein, The I / O scheduler is configured to calculate a second processing frequency value from the first priority queue to the third priority queue, and The WRR arbitration unit is further configured to adjust the processing speed of the first priority queue to the third priority queue based on the second processing frequency value.

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