Display device

Abstract

A display device is provided. The display device includes a display panel, a gate driver, a data driver, and an emission driver. The display panel includes a pixel. The gate driver is configured to provide a gate signal to the pixel. The data driver is configured to provide a data voltage to the pixel. The emission driver is configured to provide an emission signal to the pixel. The pixel includes a light emitting element, a driving switching element, and a bias switching element. The driving switching element is configured to apply a driving current to the light emitting element. The bias switching element is configured to provide a bias voltage to an input electrode of the driving switching element. A frequency of a bias gate signal applied to a control electrode of the bias switching element is greater than a frequency of a data write gate signal applied to the pixel.

Description

Technical Field

[0001] This invention relates to display devices. More specifically, it relates to reducing horizontal line defects in display devices. Background Technology

[0002] Typically, a display device includes a display panel and a display panel driver. The display panel includes multiple gate lines, multiple data lines, multiple emitter lines, and multiple pixels. The display panel driver includes a gate driver, a data driver, an emitter driver, and a drive controller. The gate driver outputs gate signals to the gate lines. The data driver outputs data voltages to the data lines. The emitter driver outputs emitter signals to the emitter lines. The drive controller controls the gate driver, data driver, and emitter driver. Summary of the Invention

[0003] In an embodiment of the display device according to the concept of the present invention, the display device includes a display panel, a gate driver, a data driver, and an emitter driver. The display panel includes pixels. The gate driver is configured to provide a gate signal to the pixel. The data driver is configured to provide a data voltage to the pixel. The emitter driver is configured to provide an emitter signal to the pixel. The pixel includes a light-emitting element, a driving switch element, and a bias switch element. The driving switch element is configured to apply a driving current to the light-emitting element. The bias switch element is configured to provide a bias voltage to the input electrode of the driving switch element. The frequency of the bias gate signal applied to the control electrode of the bias switch element is greater than the frequency of the data write gate signal applied to the pixel.

[0004] In one implementation, the transmit driver can be configured to output a first transmit signal and a second transmit signal to a pixel. The bias voltage can be a high level of the first transmit signal.

[0005] In this implementation, the display panel can be driven at a variable frequency. A first frame having a first frequency may include a first active period and a first blanking period. A second frame having a second frequency different from the first frequency may include a second active period and a second blanking period. The length of the first active period may be substantially the same as the length of the second active period. The length of the first blanking period may be different from the length of the second blanking period.

[0006] In an implementation, a pixel may include a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a storage capacitor, and a programming capacitor. The first transistor includes a control electrode connected to a first node, an input electrode connected to a second node, and an output electrode connected to a third node. The second transistor includes a control electrode configured to receive a data write gate signal, an input electrode configured to receive a data voltage, and an output electrode connected to a fourth node. The third transistor includes a control electrode configured to receive a compensation gate signal, an input electrode connected to the first node, and an output electrode connected to the third node. The fourth transistor includes a control electrode configured to receive a first initialization gate signal, an input electrode configured to receive a reference voltage, and an output electrode connected to the fourth node. The fifth transistor includes... The system comprises: a control electrode configured to receive a first transmission signal, an input electrode configured to receive a high power supply voltage, and an output electrode connected to a second node; a sixth transistor comprising a control electrode configured to receive a second transmission signal, an input electrode connected to a third node, and an output electrode connected to the anode of a light-emitting element; a seventh transistor comprising a control electrode configured to receive a first initialization gate signal, an input electrode configured to receive an initialization voltage, and an output electrode connected to the anode of a light-emitting element; an eighth transistor comprising a control electrode configured to receive a second initialization gate signal, an input electrode configured to receive a bias voltage, and an output electrode connected to a second node; a storage capacitor comprising a first electrode configured to receive a high power supply voltage and a second electrode connected to a first node; and a programming capacitor comprising a first electrode connected to a third node and a second electrode connected to a fourth node. The driving switching element may be the first transistor, and the bias switching element may be the eighth transistor.

[0007] In one implementation, the width of the second initialization gate line configured to apply the second initialization gate signal may be greater than the width of the first initialization gate line configured to apply the first initialization gate signal.

[0008] In an implementation, the resistance of the second initialization gate line configured to apply the second initialization gate signal may be less than the resistance of the first initialization gate line configured to apply the first initialization gate signal.

[0009] In an implementation, a pixel may include a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a storage capacitor, and a programming capacitor. The first transistor includes a control electrode connected to a first node, an input electrode connected to a second node, and an output electrode connected to a third node. The second transistor includes a control electrode configured to receive a data write gate signal, an input electrode configured to receive a data voltage, and an output electrode connected to a fourth node. The third transistor includes a control electrode configured to receive a compensation gate signal, an input electrode connected to the first node, and an output electrode connected to the third node. The fourth transistor includes a control electrode configured to receive a first initialization gate signal, an input electrode configured to receive a reference voltage, and an output electrode connected to the fourth node. The fifth transistor includes... The system comprises: a control electrode configured to receive a first transmission signal, an input electrode configured to receive a high power supply voltage, and an output electrode connected to a second node; a sixth transistor including a control electrode configured to receive a second transmission signal, an input electrode connected to a third node, and an output electrode connected to the anode of a light-emitting element; a seventh transistor including a control electrode configured to receive a first initialization gate signal, an input electrode configured to receive an initialization voltage, and an output electrode connected to the anode of a light-emitting element; an eighth transistor including a control electrode configured to receive a second initialization gate signal, an input electrode configured to receive a first transmission signal, and an output electrode connected to a second node; a storage capacitor including a first electrode configured to receive a high power supply voltage and a second electrode connected to a first node; and a programming capacitor including a first electrode connected to a third node and a second electrode connected to a fourth node. The driving switching element may be the first transistor, and the biasing switching element is the eighth transistor.

[0010] In one implementation, the width of the second initialization gate line configured to apply a second initialization gate signal may be greater than the width of the first initialization gate line configured to apply a first initialization gate signal. Similarly, the width of the first transmit line configured to apply a first transmit signal may be greater than the width of the second transmit line configured to apply a second transmit signal.

[0011] In one embodiment, a first emitter line configured to apply a first emitter signal may be disposed in a source-drain metal layer. A second emitter line configured to apply a second emitter signal may be disposed in a gate metal layer.

[0012] In an implementation, a pixel may include a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a holding capacitor, and a storage capacitor. The first transistor includes a control electrode connected to a first node, an input electrode connected to a second node, and an output electrode connected to a third node. The second transistor includes a control electrode configured to receive a data write gate signal, an input electrode configured to receive a data voltage, and an output electrode connected to a fourth node. The third transistor includes a control electrode configured to receive a compensation gate signal, an input electrode connected to the first node, and an output electrode connected to the third node. The fourth transistor includes a control electrode configured to receive a data initialization gate signal, an input electrode configured to receive an initialization voltage, and an output electrode connected to the first node. The fifth transistor includes a control electrode configured to receive a compensation gate signal, an input electrode configured to receive an initialization voltage, and an output electrode connected to the first node. The transistor comprises: an input electrode for receiving a reference voltage and an output electrode connected to a fourth node; a sixth transistor including a control electrode configured to receive a second transmit signal, an input electrode connected to a third node, and an output electrode connected to the anode of a light-emitting element; a seventh transistor including a control electrode configured to receive an initialization gate signal, an input electrode configured to receive an initialization voltage, and an output electrode connected to the anode of a light-emitting element; an eighth transistor including a control electrode configured to receive an initialization gate signal, an input electrode configured to receive a first transmit signal, and an output electrode connected to a second node; a ninth transistor including a control electrode configured to receive the first transmit signal, an input electrode configured to receive a high power supply voltage, and an output electrode connected to a second node; a holding capacitor including a first electrode configured to receive a high power supply voltage and a second electrode connected to a fourth node; and a storage capacitor including a first electrode connected to a fourth node and a second electrode connected to a first node. The driving switching element may be the first transistor, and the biasing switching element may be the eighth transistor.

[0013] In one implementation, the width of the initialization gate line configured to apply an initialization gate signal may be greater than the width of the data write gate line configured to apply a data write gate signal. The width of the first transmit line configured to apply a first transmit signal may be greater than the width of the second transmit line configured to apply a second transmit signal.

[0014] In one implementation, the gate driver may include a general gate driver configured to generate a gate signal not applied to a bias switching element and a bias gate driver configured to generate a gate signal applied to a bias switching element.

[0015] In one implementation, the width of the bias clock line configured to apply a clock signal to the bias gate driver may be greater than the width of the ordinary clock line configured to apply a clock signal to the ordinary gate driver.

[0016] In one embodiment, a conventional gate driver disposed in the first region may be configured to receive a clock signal via a conventional clock line disposed in the first source-drain metal layer. A bias gate driver disposed in the second region may be configured to receive a clock signal via a bias clock line formed as a double layer in the first source-drain metal layer and the second source-drain metal layer.

[0017] In one implementation, a stage of a conventional gate driver can be configured to receive a first clock signal, a gate high voltage, and a gate low voltage. A stage of a biased gate driver can be configured to receive a second clock signal, different from the first clock signal, a gate high voltage, and a gate low voltage.

[0018] In this implementation, the high level of the first clock signal may be substantially the same as the gate high voltage. The high level of the second clock signal may be greater than the gate high voltage.

[0019] In one implementation, a stage of a conventional gate driver can be configured to receive a clock signal, a first gate high voltage, and a first gate low voltage. A stage of a biased gate driver can be configured to receive a clock signal, a second gate high voltage different from the first gate high voltage, and a second gate low voltage different from the first gate low voltage.

[0020] In one implementation, a bias line configured to apply a bias voltage may extend in a second direction and be commonly connected to a plurality of pixels arranged in a first direction.

[0021] In an implementation, a pixel may include a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a holding capacitor, and a storage capacitor. The first transistor includes a control electrode connected to a first node, an input electrode connected to a second node, and an output electrode connected to a third node. The second transistor includes a control electrode configured to receive a data write gate signal, an input electrode configured to receive a data voltage, and an output electrode connected to a fourth node. The third transistor includes a control electrode configured to receive a compensation gate signal, an input electrode connected to the first node, and an output electrode connected to the third node. The fourth transistor includes a control electrode configured to receive a data initialization gate signal, an input electrode configured to receive an initialization voltage, and an output electrode connected to the first node. The fifth transistor includes a control electrode configured to receive a compensation gate signal, an input electrode configured to receive an initialization voltage, and an output electrode connected to the first node. The transistor comprises an input electrode for receiving a reference voltage and an output electrode connected to a fourth node; a sixth transistor includes a control electrode configured to receive a second transmit signal, an input electrode connected to a third node, and an output electrode connected to the anode of a light-emitting element; a seventh transistor includes a control electrode configured to receive a first initialization gate signal, an input electrode configured to receive an initialization voltage, and an output electrode connected to the anode of a light-emitting element; an eighth transistor includes a control electrode configured to receive a second initialization gate signal, an input electrode configured to receive a bias voltage, and an output electrode connected to a second node; a ninth transistor includes a control electrode configured to receive a first transmit signal, an input electrode configured to receive a high supply voltage, and an output electrode connected to a second node; a holding capacitor includes a first electrode configured to receive a high supply voltage and a second electrode connected to a fourth node; and a storage capacitor includes a first electrode connected to a fourth node and a second electrode connected to a first node. The driving switching element may be the first transistor, and the bias switching element may be the eighth transistor.

[0022] In one implementation, the duration of the high level of the first transmitted signal during the data writing period when the data voltage is written to the pixel may be shorter than the duration of the high level of the first transmitted signal during the self-scanning period when the data voltage is not written to the pixel and the light-emitting element is turned on.

[0023] According to the display device, during the self-scanning period of the display device that supports variable frequency, the biasing operation of applying a bias voltage to the input electrode of the driving transistor can be operated at a high frequency, thereby preventing flicker.

[0024] When biasing operations are performed at high frequencies during the self-scan period, horizontal line defects may occur due to the increased load on the gate drive signal. The width of the horizontal signal line of the pixel related to the bias operation can be made wide to prevent horizontal line defects. Furthermore, the horizontal signal line of the pixel related to the bias operation can be formed using a metal layer with low resistance to prevent horizontal line defects. Additionally, the horizontal signal line of the pixel related to the bias operation can be formed as a double layer of a first source-drain metal layer and a second source-drain metal layer to prevent horizontal line defects. Furthermore, the width of the gate drive signal line applied to the gate driver and related to the bias operation can be made wide to prevent horizontal line defects. Furthermore, the gate drive signal applied to the gate driver and related to the bias operation can be adjusted to prevent horizontal line defects. Attached Figure Description

[0025] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the concept of the present invention.

[0026] Figure 2 It is shown Figure 1 A conceptual diagram of the driving frequency of the display panel.

[0027] Figure 3A It is shown Figure 1 A circuit diagram of an example of the pixels of a display panel.

[0028] Figure 3B It is shown Figure 1 A circuit diagram of an example of the pixels of a display panel.

[0029] Figure 3C It is shown Figure 1 A circuit diagram of an example of the pixels of a display panel.

[0030] Figure 4 It is shown Figure 3A Timing diagram of the driving signals for the pixels.

[0031] Figure 5 It is shown Figure 1 A conceptual diagram of an example of a horizontal line defect displayed on the display panel.

[0032] Figure 6 It is shown Figure 1 A conceptual diagram of an example of a horizontal line defect displayed on the display panel.

[0033] Figure 7A This illustrates applying the gate signal and the emit signal to... Figure 3A A conceptual diagram of the horizontal signal lines of a pixel.

[0034] Figure 7B This illustrates applying the gate signal and the emit signal to... Figure 3B A conceptual diagram of the horizontal signal lines of a pixel.

[0035] Figure 7C This illustrates applying the gate signal and the emit signal to... Figure 3C A conceptual diagram of the horizontal signal lines of a pixel.

[0036] Figure 8 This illustrates applying the gate signal and the emit signal to... Figure 3A A conceptual diagram of the horizontal signal lines of a pixel.

[0037] Figure 9 It is shown Figure 1 A conceptual diagram of the layer structure of the display panel.

[0038] Figure 10 It is shown Figure 1 Block diagram of the gate driver.

[0039] Figure 11 It shows the arrangement of Figure 10 A conceptual diagram of the region of the gate driver.

[0040] Figure 12 It is shown Figure 10 A conceptual diagram of the layer structure of the clock line for the gate driver.

[0041] Figure 13 It is shown Figure 1 A conceptual diagram of the pixels and offset lines of the display panel.

[0042] Figure 14 It is shown Figure 1 Examples of stages in a typical gate driver and Figure 1 A conceptual diagram of an example of a bias gate driver stage in a gate driver.

[0043] Figure 15 It is shown Figure 14 The output signal of the stage of the ordinary gate driver and Figure 14 The waveform of the output signal of the bias gate driver stage.

[0044] Figure 16 It is shown Figure 1 Examples of stages in a typical gate driver and Figure 1 A conceptual diagram of an example of a bias gate driver stage in a gate driver.

[0045] Figure 17 It is shown Figure 1 A circuit diagram of an example of the pixels of a display panel.

[0046] Figure 18 This indicates the application of [something] during the data writing period. Figure 17 A timing diagram of an instance of the input signal of a pixel.

[0047] Figure 19 This shows the application during the self-scanning period. Figure 17 A timing diagram of an instance of the input signal of a pixel.

[0048] Figure 20 This indicates the application of [something] during the data writing period. Figure 17 A timing diagram of an instance of the input signal of a pixel.

[0049] Figure 21 This shows the application during the self-scanning period. Figure 17 A timing diagram of an instance of the input signal of a pixel.

[0050] Figure 22 This indicates the application of [something] during the data writing period. Figure 17 A timing diagram of an instance of the input signal of a pixel.

[0051] Figure 23 This shows the application during the self-scanning period. Figure 17 A timing diagram of an instance of the input signal of a pixel. Detailed Implementation

[0052] Embodiments of the present invention provide a display device capable of preventing horizontal line defects and enhancing display quality in a display device that supports variable frequencies.

[0053] Embodiments of the display device of the present invention include support for variable frequency biasing operation of the input electrodes of the driving transistors that apply bias voltage to the pixels. When the load on the bias transistors used to apply control signals to perform the biasing operation increases, a horizontal line defect may appear in the display panel, indicating a horizontal line to the user.

[0054] Therefore, horizontal line defects can be prevented in display devices that support variable frequencies, thereby enhancing the display quality of the display device.

[0055] The concept of the present invention will be explained in detail below with reference to the accompanying drawings.

[0056] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the concept of the present invention.

[0057] Reference Figure 1 The display device includes a display panel 100 and a display panel driver. The display panel driver includes a drive controller 200, a gate driver 300, a gamma reference voltage generator 400, a data driver 500, and a transmit driver 600.

[0058] The display panel 100 has a display area for displaying images and a peripheral area adjacent to the display area.

[0059] The display panel 100 includes multiple gate lines GWL, GCL, EB1L and EB2L, multiple data lines DL, multiple emitter lines EM1L and EM2L, and multiple pixels electrically connected to the gate lines GWL, GCL, EB1L and EB2L, the data lines DL and the emitter lines EM1L and EM2L. The gate lines GWL, GCL, EB1L and EB2L may extend in a first direction D1, the data lines DL may extend in a second direction D2 intersecting the first direction D1, and the emitter lines EM1L and EM2L may extend in the first direction D1.

[0060] The drive controller 200 receives input image data IMG and input control signals CONT from an external device. For example, the input image data IMG may include red image data, green image data, and blue image data. The input image data IMG may also include white image data. The input image data IMG may also include magenta image data, cyan image data, and yellow image data. The input control signal CONT may include a master clock signal and a data enable signal. The input control signal CONT may also include a vertical synchronization signal and a horizontal synchronization signal.

[0061] The drive controller 200 generates a first control signal CONT1, a second control signal CONT2, a third control signal CONT3, a fourth control signal CONT4, and a data signal DATA based on the input image data IMG and the input control signal CONT.

[0062] The drive controller 200 generates a first control signal CONT1 for controlling the operation of the gate driver 300 based on the input control signal CONT, and outputs the first control signal CONT1 to the gate driver 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0063] The drive controller 200 generates a second control signal CONT2 based on the input control signal CONT for controlling the operation of the data driver 500, and outputs the second control signal CONT2 to the data driver 500. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0064] The drive controller 200 generates a data signal DATA based on the input image data IMG. The drive controller 200 outputs the data signal DATA to the data driver 500.

[0065] The drive controller 200 generates a third control signal CONT3 based on the input control signal CONT for controlling the operation of the gamma reference voltage generator 400, and outputs the third control signal CONT3 to the gamma reference voltage generator 400.

[0066] The drive controller 200 generates a fourth control signal CONT4 for controlling the operation of the transmitter driver 600 based on the input control signal CONT, and outputs the fourth control signal CONT4 to the transmitter driver 600.

[0067] In response to a first control signal CONT1 received from the drive controller 200, the gate driver 300 generates gate signals to drive gate lines GWL, GCL, EB1L, and EB2L. The gate driver 300 can sequentially output the gate signals to the gate lines GWL, GCL, EB1L, and EB2L.

[0068] The gamma reference voltage generator 400 generates a gamma reference voltage VGREF in response to a third control signal CONT3 received from the drive controller 200. The gamma reference voltage generator 400 provides the gamma reference voltage VGREF to the data driver 500. The gamma reference voltage VGREF has a value corresponding to the level of the data signal DATA.

[0069] In one implementation, the gamma reference voltage generator 400 may be located in the drive controller 200 or in the data driver 500.

[0070] The data driver 500 receives a second control signal CONT2 and a data signal DATA from the drive controller 200, and receives a gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 uses the gamma reference voltage VGREF to convert the data signal DATA into a data voltage of analog type. The data driver 500 outputs the data voltage to the data line DL.

[0071] The transmitter driver 600, in response to the fourth control signal CONT4 received from the drive controller 200, generates a transmit signal to drive the transmit lines EM1L and EM2L. The transmitter driver 600 can output the transmit signal to the transmit lines EM1L and EM2L.

[0072] Although for the sake of explanation, in Figure 1 The gate driver 300 is disposed on a first side of the display panel 100 and the emitter driver 600 is disposed on a second side of the display panel 100 opposite to the first side, but the concept of the present invention is not limited thereto. For example, both the gate driver 300 and the emitter driver 600 may be disposed on the first side of the display panel 100. For example, the gate driver 300 and the emitter driver 600 may be integrally formed.

[0073] Figure 2 It is shown Figure 1 A conceptual diagram of the driving frequency of the display panel 100.

[0074] Reference Figure 1 and Figure 2 The display panel 100 can be driven at a variable frequency. A first frame FR1 having a first frequency may include a first active period AC1 and a first blanking period BL1. A second frame FR2 having a second frequency different from the first frequency may include a second active period AC2 and a second blanking period BL2. A third frame FR3 having a third frequency different from the first and second frequencies may include a third active period AC3 and a third blanking period BL3.

[0075] The first activation period AC1 may have a length substantially the same as the second activation period AC2. The first blanking period BL1 may have a length different from the second blanking period BL2.

[0076] The second activation period AC2 may have a length substantially the same as the third activation period AC3. The second blanking period BL2 may have a length different from the third blanking period BL3.

[0077] Display devices supporting variable frequencies may include a data writing period where data voltages are written to pixels and a self-scanning period where only light emission occurs without writing data voltages to pixels. The data writing period may be arranged in the active periods AC1, AC2, and AC3. The self-scanning period may be arranged in the blanking periods BL1, BL2, and BL3.

[0078] Figure 3A It is shown Figure 1 Circuit diagram of an example of a display panel with 100 pixels.

[0079] Reference Figure 1 , Figure 2 and Figure 3A The pixel may include a light-emitting element EE, a driving switch element (e.g., T1) that applies a driving current to the light-emitting element EE, and a bias switch element (e.g., T8) that provides a bias voltage to the input electrode of the driving switch element (e.g., T1). The frequency of the bias gate signal (e.g., EB2) applied to the control electrode of the bias switch element (e.g., T8) may be greater than the frequency of the data write gate signal (e.g., GW) applied to the pixel.

[0080] The transmit driver 600 can output the first transmit signal EM1 and the second transmit signal EM2 to the pixel.

[0081] In this embodiment, a pixel may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a storage capacitor CST, and a programming capacitor CPR. The first transistor T1 includes a control electrode connected to a first node N1, an input electrode connected to a second node N2, and an output electrode connected to a third node N3. The second transistor T2 includes a control electrode for receiving a data write gate signal GW, an input electrode for receiving a data voltage VDATA, and an output electrode connected to a fourth node N4. The third transistor T3 includes a control electrode for receiving a compensation gate signal GC, an input electrode connected to a first node N1, and an output electrode connected to a third node N3. The fourth transistor T4 includes a control electrode for receiving a first initialization gate signal EB1, an input electrode for receiving a reference voltage VREF, and an output electrode connected to a fourth node N4. Transistor T5 includes a control electrode receiving a first transmit signal EM1, an input electrode receiving a high supply voltage ELVDD, and an output electrode connected to the second node N2. Transistor T6 includes a control electrode receiving a second transmit signal EM2, an input electrode connected to the third node N3, and an output electrode connected to the anode of the light-emitting element EE. Transistor T7 includes a control electrode receiving a first initialization gate signal EB1, an input electrode receiving an initialization voltage VINT, and an output electrode connected to the anode of the light-emitting element EE. Transistor T8 includes a control electrode receiving a second initialization gate signal EB2, an input electrode receiving a bias voltage VBIAS, and an output electrode connected to the second node N2. Storage capacitor CST includes a first electrode receiving a high supply voltage ELVDD and a second electrode connected to the first node N1. Programming capacitor CPR includes a first electrode connected to the third node N3 and a second electrode connected to the fourth node N4. The light-emitting element EE may include an anode and a cathode receiving a low supply voltage ELVSS.

[0082] The driving switching element can be the first transistor T1. The bias switching element can be the eighth transistor T8.

[0083] Figure 3B It is shown Figure 1 Circuit diagram of an example of a display panel with 100 pixels.

[0084] Reference Figure 1 , Figure 2 and Figure 3B The transmit driver 600 can output a first transmit signal EM1 and a second transmit signal EM2 to the pixel. In this embodiment, the bias voltage can be the high level of the first transmit signal EM1.

[0085] In this embodiment, a pixel may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a storage capacitor CST, and a programming capacitor CPR. The first transistor T1 includes a control electrode connected to a first node N1, an input electrode connected to a second node N2, and an output electrode connected to a third node N3. The second transistor T2 includes a control electrode for receiving a data write gate signal GW, an input electrode for receiving a data voltage VDATA, and an output electrode connected to a fourth node N4. The third transistor T3 includes a control electrode for receiving a compensation gate signal GC, an input electrode connected to a first node N1, and an output electrode connected to a third node N3. The fourth transistor T4 includes a control electrode for receiving a first initialization gate signal EB1, an input electrode for receiving a reference voltage VREF, and an output electrode connected to a fourth node N4. Transistor T5 includes a control electrode receiving a first transmit signal EM1, an input electrode receiving a high power supply voltage ELVDD, and an output electrode connected to the second node N2. Transistor T6 includes a control electrode receiving a second transmit signal EM2, an input electrode connected to the third node N3, and an output electrode connected to the anode of the light-emitting element EE. Transistor T7 includes a control electrode receiving a first initialization gate signal EB1, an input electrode receiving an initialization voltage VINT, and an output electrode connected to the anode of the light-emitting element EE. Transistor T8 includes a control electrode receiving a second initialization gate signal EB2, an input electrode receiving the first transmit signal EM1, and an output electrode connected to the second node N2. Storage capacitor CST includes a first electrode receiving a high power supply voltage ELVDD and a second electrode connected to the first node N1. Programming capacitor CPR includes a first electrode connected to the third node N3 and a second electrode connected to the fourth node N4. The light-emitting element EE may include an anode and a cathode receiving a low power supply voltage ELVSS.

[0086] The driving switching element can be the first transistor T1. The bias switching element can be the eighth transistor T8.

[0087] Figure 3C It is shown Figure 1 Circuit diagram of an example of a display panel with 100 pixels.

[0088] Reference Figure 1 , Figure 2 and Figure 3C The transmit driver 600 can output a first transmit signal EM1 and a second transmit signal EM2 to the pixel. In this embodiment, the bias voltage can be the high level of the first transmit signal EM1.

[0089] A pixel may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a holding capacitor CHOLD, and a storage capacitor CST. The first transistor T1 includes a control electrode connected to a first node N1, an input electrode connected to a second node N2, and an output electrode connected to a third node N3. The second transistor T2 includes a control electrode for receiving a data write gate signal GW, an input electrode for receiving a data voltage VDATA, and an output electrode connected to a fourth node N4. The third transistor T3 includes a control electrode for receiving a compensation gate signal GC, an input electrode connected to a first node N1, and an output electrode connected to a third node N3. The fourth transistor T4 includes a control electrode for receiving a data initialization gate signal GI, an input electrode for receiving an initialization voltage VINT, and an output electrode connected to a first node N1. The fifth transistor T5 includes a control electrode for receiving the compensation gate signal GC, an input electrode connected to a first node N1, and an output electrode connected to a third node N3. The sixth transistor T6 includes an input electrode for receiving the reference voltage VREF and an output electrode connected to the fourth node N4. The seventh transistor T7 includes a control electrode for receiving the initialization gate signal EB, an input electrode for receiving the initialization voltage VINT, and an output electrode connected to the anode of the light-emitting element EE. The eighth transistor T8 includes a control electrode for receiving the initialization gate signal EB, an input electrode for receiving the first transmission signal EM1, and an output electrode connected to the second node N2. The ninth transistor T9 includes a control electrode for receiving the first transmission signal EM1, an input electrode for receiving the high power supply voltage ELVDD, and an output electrode connected to the second node N2. The holding capacitor CHOLD includes a first electrode for receiving the high power supply voltage ELVDD and a second electrode connected to the fourth node N4. The storage capacitor CST includes a first electrode connected to the fourth node N4 and a second electrode connected to the first node N1. The light-emitting element EE may include an anode and a cathode for receiving a low power supply voltage ELVSS.

[0090] The driving switching element can be the first transistor T1. The bias switching element can be the eighth transistor T8.

[0091] Figure 4 It is shown Figure 3A Timing diagram of the driving signals for the pixels. Figure 5 It is shown Figure 1 A conceptual diagram of an example of a horizontal line defect displayed on the display panel 100. Figure 6 It is shown Figure 1 A conceptual diagram of an example of a horizontal line defect displayed on the display panel 100.

[0092] Reference Figures 1 to 6 The display panel 100 can be driven at a variable frequency. For example, it can be driven at a maximum frequency of 240Hz. When the display panel 100 is driven at a frequency of 240Hz, the data write gate signal GW can have activation pulses in the first time period P1, the third time period P3, the fifth time period P5, and the seventh time period P7 among the first time period P1 to the eighth time period P8, so that the data write operation can be performed in the first time period P1, the third time period P3, the fifth time period P5, and the seventh time period P7. When the display panel 100 is driven at a frequency of 120Hz, the data write gate signal GW can have activation pulses in the first time period P1 and the fifth time period P5, so that the data write operation can be performed in the first time period P1 and the fifth time period P5.

[0093] When the display panel 100 is driven at a frequency of 240Hz, the emission operation EM of the light-emitting element EE can be performed at a frequency of 480Hz, the initialization operation EB1 of the light-emitting element EE can be performed at a frequency of 480Hz, and the bias operation EB2 of the light-emitting element EE can be performed at a frequency of 480Hz.

[0094] As explained above, when the display panel 100 is driven at a frequency of 240Hz and the transmission operation EM is performed at a frequency of 480Hz, it can be said that the display panel 100 operates in two cycles.

[0095] When the display panel 100 is driven at a frequency of 120Hz, the emission operation EM of the light-emitting element EE can be performed at a frequency of 480Hz, the initialization operation EB1 of the light-emitting element EE can be performed at a frequency of 480Hz, and the bias operation EB2 of the light-emitting element EE can be performed at a frequency of 480Hz.

[0096] As explained above, when the display panel 100 is driven at a frequency of 120Hz and the transmission operation EM is performed at a frequency of 480Hz, it can be said that the display panel 100 operates in four cycles.

[0097] A display device supporting variable frequency may include a data writing period in which data voltage is written to pixels and a self-scanning period in which only light emission is performed without writing data voltage to pixels. During the self-scanning period, a biasing operation can be performed by applying a bias voltage to the input electrode of the drive switching element T1. When the load on the bias switching element T8, which performs the biasing operation, increases, a horizontal line defect may appear in the display panel 100 that would otherwise indicate a horizontal line to the user.

[0098] When the display panel 100 operates in two cycles, due to the increase in the load of the gate drive signal of the gate driver 300, such as Figure 5As shown, the horizontal line LD can be displayed in the center of the display panel 100 in the vertical direction.

[0099] Furthermore, when the display panel 100 operates in four cycles, the load on the gate drive signal of the gate driver 300 increases, such as Figure 6 As shown, horizontal lines LD1, LD2, and LD3 can be displayed vertically at 1 / 4, 1 / 2, and 3 / 4 points on the display panel 100.

[0100] Figure 7A This illustrates applying the gate signal and the emit signal to... Figure 3A A conceptual diagram of the horizontal signal lines of a pixel.

[0101] Reference Figures 1 to 7A The horizontal signal lines that apply gate signals and transmit signals to the pixel may include a data write gate line GWL that applies a data write gate signal GW, a compensation gate line GCL that applies a compensation gate signal GC, a first initialization gate line EB1L that applies a first initialization gate signal EB1, a second initialization gate line EB2L that applies a second initialization gate signal EB2, a first transmit line EM1L that applies a first transmit signal EM1, and a second transmit line EM2L that applies a second transmit signal EM2.

[0102] The second initialization gate line EB2L applies a bias voltage to... Figure 3A The bias operation of the input electrode of the driving switching element T1 in the pixel is related to the bias operation, while other horizontal signal lines are not related to the bias operation. In this paper, the horizontal signal lines related to the bias operation may mean lines connected to the control electrode or input electrode of the eighth transistor T8.

[0103] like Figure 7A As shown, the width W2 of the second initialization gate line EB2L associated with the bias operation may be greater than the width W1 of the horizontal signal line unrelated to the bias operation.

[0104] For example, the width W2 of the second initialization gate line EB2L can be greater than the width of the first initialization gate line EB1L.

[0105] Figure 7B This illustrates applying the gate signal and the emit signal to... Figure 3B A conceptual diagram of the horizontal signal lines of a pixel.

[0106] The second initialization gate line EB2L and the first emitter line EM1L are used to apply a bias voltage. Figure 3B The bias operation is related to the input electrode of the driving switching element T1 in the pixel, while the other horizontal signal lines are not related to the bias operation.

[0107] like Figure 7BAs shown, the width W2 of the second initialization gate line EB2L and the first emitter line EM1L, which are related to the bias operation, can be greater than the width W1 of the horizontal signal line, which is not related to the bias operation.

[0108] For example, the width W2 of the second initialization gate line EB2L can be greater than the width W1 of the first initialization gate line EB1L. For example, the width W2 of the first emitter line EM1L can be greater than the width W1 of the second emitter line EM2L.

[0109] In this document, for example, the width W2 of the second initialization gate line EB2L may be the same as the width W2 of the first emitter line EM1L. Alternatively, the width of the second initialization gate line EB2L may be different from the width of the first emitter line EM1L. For example, the width W1 of the first initialization gate line EB1L may be the same as the width W1 of the second emitter line EM2L. Alternatively, the width of the first initialization gate line EB1L may be different from the width of the second emitter line EM2L.

[0110] Figure 7C This illustrates applying the gate signal and the emit signal to... Figure 3C A conceptual diagram of the horizontal signal lines of a pixel.

[0111] Initialize the gate line EBL and the first emitter line EM1L and apply the bias voltage to Figure 3C The bias operation is related to the input electrode of the driving switching element T1 in the pixel, while the other horizontal signal lines are not related to the bias operation.

[0112] like Figure 7C As shown, the width W2 of the initialization gate line EBL and the first emitter line EM1L, which are related to the bias operation, can be greater than the width W1 of the horizontal signal line, which is not related to the bias operation.

[0113] For example, the width W2 of the initialization gate line EBL can be greater than the width W1 of the data write gate line GWL. For example, the width W2 of the first emitter line EM1L can be greater than the width W1 of the second emitter line EM2L.

[0114] like Figures 7A to 7C As shown, the width of the horizontal signal line associated with the bias operation can be made wide to prevent horizontal line defects.

[0115] Figure 8 This illustrates applying the gate signal and the emit signal to... Figure 3A A conceptual diagram of the horizontal signal lines of a pixel.

[0116] Reference Figure 8The horizontal signal lines that apply gate signals and transmit signals to the pixel may include a data write gate line GWL that applies a data write gate signal GW, a compensation gate line GCL that applies a compensation gate signal GC, a first initialization gate line EB1L that applies a first initialization gate signal EB1, a second initialization gate line EB2L that applies a second initialization gate signal EB2, a first transmit line EM1L that applies a first transmit signal EM1, and a second transmit line EM2L that applies a second transmit signal EM2.

[0117] The second initialization gate line EB2L applies a bias voltage to... Figure 3A The bias operation of the input electrode of the driving switching element T1 in the pixel is related to the bias operation, while other horizontal signal lines are not related to the bias operation. In this paper, the horizontal signal lines related to the bias operation may mean lines connected to the control electrode or input electrode of the eighth transistor T8.

[0118] like Figure 8 As shown, the width W1 of the second initialization gate line EB2L associated with the bias operation can be substantially the same as the width W1 of the horizontal signal line unrelated to the bias operation. In this embodiment, the resistance of the second initialization gate line EB2L associated with the bias operation can be less than the resistance of the horizontal signal line unrelated to the bias operation.

[0119] exist Figure 8 In this context, the resistance of the horizontal signal line related to the bias operation can be made low to prevent horizontal line defects.

[0120] Figure 9 It is shown Figure 1 A conceptual diagram of the layer structure of the display panel 100.

[0121] Reference Figure 9 The display panel 100 may include a substrate SB, a buffer layer BF disposed on the substrate SB, a first gate insulating layer GI1 disposed on the buffer layer BF, a first gate metal layer GM1 disposed on the first gate insulating layer GI1, a second gate insulating layer GI2 disposed on the first gate metal layer GM1, a second gate metal layer GM2 disposed on the second gate insulating layer GI2, a third gate insulating layer GI3 disposed on the second gate metal layer GM2, a third gate metal layer GM3 disposed on the third gate insulating layer GI3, a first interlayer insulating layer ILD1 disposed on the third metal layer GM3, a first source-drain metal layer SD1 disposed on the first interlayer insulating layer ILD1, a second interlayer insulating layer ILD2 disposed on the first source-drain metal layer SD1, and a second source-drain metal layer SD2 disposed on the second interlayer insulating layer ILD2.

[0122] For example, in Figure 3BIn the pixel structure, the first emitter line EM1L for applying the first emission signal EM1 can be arranged in the source-drain metal layers SD1 or SD2, and the second emitter line EM2L for applying the second emission signal EM2 can be arranged in the gate metal layers GM1, GM2, or GM3. The source-drain metal layers can have a lower resistance than the gate metal layer. Therefore, when the first emitter line EM1L for applying the first emission signal EM1 is arranged in the source-drain metal layers SD1 or SD2 and the second emitter line EM2L for applying the second emission signal EM2 is arranged in the gate metal layers GM1, GM2, or GM3, in Figure 9 In this context, the resistance of the horizontal signal line of the pixel related to the bias operation can be relatively low, thus preventing horizontal line defects.

[0123] Figure 10 It is shown Figure 1 Block diagram of the gate driver 300. Figure 11 It shows the arrangement of Figure 10 A conceptual diagram of the region of the gate driver 300. Figure 12 It is shown Figure 10 A conceptual diagram of the layer structure of the clock line of the gate driver 300.

[0124] Reference Figure 10 The gate driver 300 may include a general gate driver that generates a gate signal not applied to the bias switching element and a bias gate driver that generates a gate signal applied to the bias switching element.

[0125] For example, a general gate driver may include a data write gate driver GWD, a compensation gate driver GCD, and a first initialization gate driver EB1D. A bias gate driver may include a second initialization gate driver EB2D. The data write gate driver GWD may include stages GWST(1), GWST(2), GWST(3), ..., and GWST(N). The compensation gate driver GCD may include stages GCST(1), GCST(2), GCST(3), ..., and GCST(N). The first initialization gate driver EB1D may include stages EB1ST(1), EB1ST(2), EB1ST(3), ..., and EB1ST(N). The second initialization gate driver EB2D may include stages EB2ST(1), EB2ST(2), EB2ST(3), ..., and EB2ST(N).

[0126] like Figure 10 As shown, the width WE2 of the bias clock line CKE2L that applies the clock signal to the bias gate driver can be greater than the width WW of the ordinary clock line CKWL, the width WC of the ordinary clock line CKCL, and the width WE1 of the ordinary clock line CKE1L that applies the clock signal to the ordinary gate driver.

[0127] according to Figure 10 This reduces the load on the clock signal of the bias gate driver associated with bias operation, thus preventing horizontal line defects.

[0128] exist Figure 11 In this configuration, a standard gate driver may be disposed in a first region AR1, and a bias gate driver may be disposed in a second region AR2. The first region AR1 may be the region where a low supply voltage ELVSS is applied to the second source-drain metal layer SD2. The second region AR2 may be the region where a low supply voltage ELVSS is not applied to the second source-drain metal layer SD2, making the second source-drain metal layer SD2 of the second region AR2 a usable region.

[0129] Therefore, the ordinary gate driver arranged in the first region AR1 can receive the clock signal through the ordinary clock line arranged in the first source-drain metal layer SD1. The bias gate driver arranged in the second region AR2 can receive the clock signal through the bias clock line formed as a double layer CKE2L1 and CKE2L2 in the first source-drain metal layer SD1 and the second source-drain metal layer SD2.

[0130] according to Figure 11 and Figure 12 The load on the clock signal of the bias gate driver associated with bias operation can be reduced by using a bias clock line formed in a double layer, thereby preventing horizontal line defects.

[0131] Figure 13 It is shown Figure 1 A conceptual diagram of the 100 pixels and offset lines of the display panel.

[0132] Reference Figure 13 The bias line for applying the bias voltage VBIAS can extend in the second direction D2 and can be commonly connected to a plurality of pixels SP1, SP2 and SP3 arranged in the first direction D1. When there is insufficient space for the bias line in the effective area of ​​the display panel 100, the plurality of pixels SP1, SP2 and SP3 can share the bias line to increase space efficiency.

[0133] Figure 14 It is shown Figure 1 Examples of stages of a common gate driver in gate driver 300 and Figure 1 A conceptual diagram of an example of a bias gate driver stage in a gate driver 300. Figure 15 It is shown Figure 14 The output signal of the stage of the ordinary gate driver and Figure 14 The waveform of the output signal of the bias gate driver stage.

[0134] Reference Figure 14 and Figure 15 The stage GWST of the general gate driver can receive a first clock signal CK1, a gate high voltage VGH, and a gate low voltage VGL. The stage EB2ST of the bias gate driver, which is related to bias operation, can receive a second clock signal CK2, a gate high voltage VGH, and a gate low voltage VGL, which are different from the first clock signal CK1.

[0135] like Figure 15 As shown, the high level CK1(H) of the first clock signal can be substantially the same as the gate high voltage VGH, and the high level CK2(H) of the second clock signal can be greater than the gate high voltage VGH.

[0136] according to Figure 14 and Figure 15 This allows for increasing the high level CK2(H) of the second clock signal, thereby reducing the load on the clock signal of the bias gate driver associated with bias operation. Therefore, horizontal line defects can be prevented.

[0137] Figure 16 It is shown Figure 1 Examples of stages of a common gate driver in gate driver 300 and Figure 1 A conceptual diagram of an example of a bias gate driver stage in a gate driver 300.

[0138] Reference Figure 16 The stage GWST of the standard gate driver can receive clock signal CK, first gate high voltage VGH1, and first gate low voltage VGL1. The stage EB2ST of the bias gate driver can receive clock signal CK, second gate high voltage VGH2 (different from the first gate high voltage VGH1), and second gate low voltage VGL2 (different from the first gate low voltage VGL1).

[0139] according to Figure 16 The levels of the second gate high voltage VGH2 and the second gate low voltage VGL2 can be adjusted to reduce the load on the clock signal of the bias gate driver associated with bias operation. Therefore, horizontal line defects can be prevented.

[0140] Figure 17 It is shown Figure 1 Circuit diagram of an example of a display panel with 100 pixels. Figure 18 This indicates the application of [something] during the data writing period. Figure 17 A timing diagram of an instance of the input signal of a pixel. Figure 19 This shows the application during the self-scanning period. Figure 17 A timing diagram of an instance of the input signal of a pixel. Figure 20 This indicates the application of [something] during the data writing period. Figure 17 A timing diagram of an instance of the input signal of a pixel.

[0141] Figure 21 This shows the application during the self-scanning period. Figure 17 A timing diagram of an instance of the input signal of a pixel. Figure 22 This indicates the application of [something] during the data writing period. Figure 17 A timing diagram of an instance of the input signal of a pixel. Figure 23 This shows the application during the self-scanning period. Figure 17 A timing diagram of an instance of the input signal of a pixel.

[0142] Reference Figure 1 , Figure 2 , Figure 4 and Figures 17 to 23Each pixel may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a holding capacitor CHOLD, and a storage capacitor CST. The first transistor T1 includes a control electrode connected to a first node N1, an input electrode connected to a second node N2, and an output electrode connected to a third node N3. The second transistor T2 includes a control electrode for receiving a data write gate signal GW, an input electrode for receiving a data voltage VDATA, and an output electrode connected to a fourth node N4. The third transistor T3 includes a control electrode for receiving a compensation gate signal GC, an input electrode connected to a first node N1, and an output electrode connected to a third node N3. The fourth transistor T4 includes a control electrode for receiving a data initialization gate signal GI, an input electrode for receiving an initialization voltage VINT, and an output electrode connected to a first node N1. The fifth transistor T5 includes a control electrode for receiving the compensation gate signal GC and a reference voltage VINT. The transistors are: a sixth transistor T6, a seventh transistor T7, and a eighth transistor T8. The sixth transistor T6 includes a control electrode receiving the second emission signal EM2, an input electrode receiving the bias voltage VBIAS, and an output electrode connected to the anode of the light-emitting element EE. The seventh transistor T7 includes a control electrode receiving the first initialization gate signal EB1, an input electrode receiving the initialization voltage VINT, and an output electrode connected to the anode of the light-emitting element EE. The eighth transistor T8 includes a control electrode receiving the second initialization gate signal EB2, an input electrode receiving the bias voltage VBIAS, and an output electrode connected to the second node N2. The ninth transistor T9 includes a control electrode receiving the first emission signal EM1, an input electrode receiving the high supply voltage ELVDD, and an output electrode connected to the second node N2. The holding capacitor CHOLD includes a first electrode receiving the high supply voltage ELVDD and a second electrode connected to the fourth node N4. The storage capacitor CST includes a first electrode connected to the fourth node N4 and a second electrode connected to the first node N1. The light-emitting element EE may include an anode and a cathode receiving a low supply voltage ELVSS.

[0143] The driving switching element can be the first transistor T1. The bias switching element can be the eighth transistor T8.

[0144] Figure 18 This indicates the gate signal applied to the pixel during the DATA WRITING period, and Figure 19 This represents the gate signal applied to the pixel during the SELF SCAN period.

[0145] In this embodiment, the ONBIAS operation for adjusting the voltage of the input electrode of the first transistor T1 can be performed using the eighth transistor T8, and the OFFBIAS operation for adjusting the voltage of the output electrode of the first transistor T1 can be performed using the seventh transistor T7. During the OFFBIAS operation, both the seventh transistor T7 and the sixth transistor T6 are turned on.

[0146] The device can be enabled by a second initialization gate signal EB2 to perform an ON bias operation and disabled by a first initialization gate signal EB1 to perform an OFF bias operation. In this embodiment, the second initialization gate signal EB2 for the ON bias operation and the first initialization gate signal EB1 for the OFF bias operation are independent, so that the ON bias operation and the OFF bias operation can be finely adjusted, thereby preventing horizontal line defects.

[0147] exist Figure 20 and Figure 21 In the DATA WRITING period when the data voltage is written to the pixel, the length WF1 of the high-level duration of the first transmit signal EM1 can be less than the length WF2 of the high-level duration of the first transmit signal EM1 in the SELF SCAN period when the data voltage is not written to the pixel and the light-emitting element EE is turned on.

[0148] During the low-level duration of the first transmit signal EM1, the ninth transistor T9 can be turned on to perform bias operation BI using the high supply voltage ELVDD. The degree of bias operation BI using the high supply voltage ELVDD can be appropriately adjusted using the lengths WF1 and WF2 of the high-level duration of the first transmit signal EM1. As explained above, the bias operation BI using the high supply voltage ELVDD can be appropriately adjusted to effectively prevent horizontal line defects.

[0149] and Figure 18 and Figure 19 The implementation methods are different. Figure 22 and Figure 23 An embodiment is shown where the on-bias timing and off-bias timing are identical. Accordingly, in this embodiment, the on-bias operation is performed, while the off-bias operation may not be performed. In this case, the gate driver for the first initialization gate signal EB1 and the gate driver for the second initialization gate signal EB2 operate independently, thereby reducing the load on the gate driver during the on-bias operation. Therefore, horizontal line defects can be prevented.

[0150] According to this embodiment, during the self-scanning period of a display device supporting variable frequency, the biasing operation of applying a bias voltage to the input electrode of the driving transistor can be performed at a high frequency, thereby preventing flicker.

[0151] When biasing operations are performed at high frequencies during the self-scan period, horizontal line defects may occur due to the increased load on the gate drive signal. The width of the horizontal signal line of the pixel related to the bias operation can be made wide to prevent horizontal line defects. Furthermore, the horizontal signal line of the pixel related to the bias operation can be formed using a metal layer with low resistance to prevent horizontal line defects. Additionally, the horizontal signal line of the pixel related to the bias operation can be formed as a double layer of a first source-drain metal layer and a second source-drain metal layer to prevent horizontal line defects. Furthermore, the width of the gate drive signal line applied to the gate driver and related to the bias operation can be made wide to prevent horizontal line defects. Furthermore, the gate drive signal applied to the gate driver and related to the bias operation can be adjusted to prevent horizontal line defects.

[0152] Therefore, horizontal line defects can be prevented in display devices that support variable frequencies, thereby enhancing the display quality of the display device.

[0153] The display device according to this embodiment as explained above can enhance the display quality of the display panel.

[0154] The foregoing is illustrative of the concept of the invention and should not be construed as limiting it. While some exemplary embodiments of the concept of the invention have been described, those skilled in the art will readily appreciate that numerous modifications can be made in the exemplary embodiments without substantially departing from the novel teachings and advantages of the concept of the invention. Accordingly, all such modifications are intended to be included within the scope of the concept of the invention as defined by the claims. In the claims, any means plus function clause is intended to cover structures described herein as performing said functions.

Claims

1. A display device, comprising: A display panel, the display panel comprising pixels; A gate driver configured to provide a gate signal to the pixel; A data driver configured to provide a data voltage to the pixel; as well as A transmit driver configured to provide a transmit signal to the pixel. The pixels include: Light-emitting elements; A driving switching element, the driving switching element being configured to apply a driving current to the light-emitting element; and A bias switching element configured to provide a bias voltage to the input electrode of the drive switching element, and The frequency of the bias gate signal applied to the control electrode of the bias switching element is greater than the frequency of the data write gate signal applied to the pixel. The display panel is driven at a variable frequency. The first frame with the first frequency includes a first activation period and a first blanking period. The second frame, which has a second frequency different from the first frequency, includes a second activation period and a second blanking period. Wherein, the length of the first activation period is the same as the length of the second activation period, and The length of the first blanking period is different from the length of the second blanking period.

2. The display device according to claim 1, wherein The transmit driver is configured to output a first transmit signal and a second transmit signal to the pixel, and The bias voltage is the high level of the first transmitted signal.

3. The display device according to claim 1, wherein The pixels include: A first transistor, the first transistor including a control electrode connected to a first node, an input electrode connected to a second node, and an output electrode connected to a third node; The second transistor includes a control electrode configured to receive the data write gate signal, an input electrode configured to receive the data voltage, and an output electrode connected to the fourth node. The third transistor includes a control electrode configured to receive a compensation gate signal, an input electrode connected to the first node, and an output electrode connected to the third node; A fourth transistor, the fourth transistor including a control electrode configured to receive a first initialization gate signal, an input electrode configured to receive a reference voltage, and an output electrode connected to the fourth node; The fifth transistor includes a control electrode configured to receive a first transmitted signal, an input electrode configured to receive a power supply voltage, and an output electrode connected to the second node; A sixth transistor, the sixth transistor including a control electrode configured to receive a second transmission signal, an input electrode connected to the third node, and an output electrode connected to the anode of the light-emitting element; A seventh transistor, the seventh transistor including a control electrode configured to receive the first initialization gate signal, an input electrode configured to receive an initialization voltage, and an output electrode connected to the anode of the light-emitting element; The eighth transistor includes a control electrode configured to receive a second initialization gate signal, an input electrode configured to receive the bias voltage, and an output electrode connected to the second node; A storage capacitor, the storage capacitor including a first electrode configured to receive the power supply voltage and a second electrode connected to the first node; and A programming capacitor, the programming capacitor including a first electrode connected to the third node and a second electrode connected to the fourth node, and The driving switching element is the first transistor, and the bias switching element is the eighth transistor.

4. The display device according to claim 3, wherein The width of the second initialization gate line configured to apply the second initialization gate signal is greater than the width of the first initialization gate line configured to apply the first initialization gate signal.

5. The display device according to claim 3, wherein The resistance of the second initialization gate line configured to apply the second initialization gate signal is less than the resistance of the first initialization gate line configured to apply the first initialization gate signal.

6. The display device of claim 1, wherein, The pixels include: A first transistor, the first transistor including a control electrode connected to a first node, an input electrode connected to a second node, and an output electrode connected to a third node; The second transistor includes a control electrode configured to receive the data write gate signal, an input electrode configured to receive the data voltage, and an output electrode connected to the fourth node. The third transistor includes a control electrode configured to receive a compensation gate signal, an input electrode connected to the first node, and an output electrode connected to the third node; A fourth transistor, the fourth transistor including a control electrode configured to receive a first initialization gate signal, an input electrode configured to receive a reference voltage, and an output electrode connected to the fourth node; The fifth transistor includes a control electrode configured to receive a first transmitted signal, an input electrode configured to receive a power supply voltage, and an output electrode connected to the second node; A sixth transistor, the sixth transistor including a control electrode configured to receive a second transmission signal, an input electrode connected to the third node, and an output electrode connected to the anode of the light-emitting element; A seventh transistor, the seventh transistor including a control electrode configured to receive the first initialization gate signal, an input electrode configured to receive an initialization voltage, and an output electrode connected to the anode of the light-emitting element; The eighth transistor includes a control electrode configured to receive a second initialization gate signal, an input electrode configured to receive the first transmission signal, and an output electrode connected to the second node; A storage capacitor, the storage capacitor including a first electrode configured to receive the power supply voltage and a second electrode connected to the first node; and A programming capacitor, the programming capacitor including a first electrode connected to the third node and a second electrode connected to the fourth node, and The driving switching element is the first transistor, and the bias switching element is the eighth transistor.

7. The display device of claim 6, wherein, The width of the second initialization gate line configured to apply the second initialization gate signal is greater than the width of the first initialization gate line configured to apply the first initialization gate signal. Wherein, the width of the first transmission line configured to apply the first transmission signal is greater than the width of the second transmission line configured to apply the second transmission signal.

8. The display device of claim 6, wherein, A first transmit line configured to apply the first transmit signal is disposed in a source-drain metal layer, and The second transmitter line configured to apply the second transmission signal is arranged in the gate metal layer.

9. The display device according to claim 1, wherein The pixels include: A first transistor, the first transistor including a control electrode connected to a first node, an input electrode connected to a second node, and an output electrode connected to a third node; The second transistor includes a control electrode configured to receive the data write gate signal, an input electrode configured to receive the data voltage, and an output electrode connected to the fourth node. The third transistor includes a control electrode configured to receive a compensation gate signal, an input electrode connected to the first node, and an output electrode connected to the third node; The fourth transistor includes a control electrode configured to receive a data initialization gate signal, an input electrode configured to receive an initialization voltage, and an output electrode connected to the first node. The fifth transistor includes a control electrode configured to receive the compensation gate signal, an input electrode configured to receive a reference voltage, and an output electrode connected to the fourth node; A sixth transistor, the sixth transistor including a control electrode configured to receive a second transmission signal, an input electrode connected to the third node, and an output electrode connected to the anode of the light-emitting element; A seventh transistor includes a control electrode configured to receive an initialization gate signal, an input electrode configured to receive the initialization voltage, and an output electrode connected to the anode of the light-emitting element; The eighth transistor includes a control electrode configured to receive the initial gate signal, an input electrode configured to receive the first transmit signal, and an output electrode connected to the second node; The ninth transistor includes a control electrode configured to receive the first transmitted signal, an input electrode configured to receive a power supply voltage, and an output electrode connected to the second node; A holding capacitor, the holding capacitor including a first electrode configured to receive the power supply voltage and a second electrode connected to the fourth node; and A storage capacitor, the storage capacitor including a first electrode connected to the fourth node and a second electrode connected to the first node, and The driving switching element is the first transistor, and the bias switching element is the eighth transistor.

10. The display device of claim 9, wherein, The width of the initialization gate line configured to apply the initialization gate signal is greater than the width of the data write gate line configured to apply the data write gate signal, and Wherein, the width of the first transmission line configured to apply the first transmission signal is greater than the width of the second transmission line configured to apply the second transmission signal.

11. The display device according to claim 1, wherein The gate driver includes: A general-purpose gate driver, configured to generate a gate signal not applied to the bias switching element; and A bias gate driver configured to generate a gate signal applied to the bias switching element.

12. The display device of claim 11, wherein, The width of the bias clock line configured to apply a clock signal to the bias gate driver is greater than the width of the normal clock line configured to apply a clock signal to the normal gate driver.

13. The display device according to claim 11, wherein, The conventional gate driver disposed in the first region is configured to receive a clock signal via a conventional clock line disposed in the first source-drain metal layer, and The bias gate driver arranged in the second region is configured to receive a clock signal via a bias clock line formed as a double layer in the first source-drain metal layer and the second source-drain metal layer.

14. The display device according to claim 11, wherein, The conventional gate driver is configured to receive a first clock signal, a gate high voltage, and a gate low voltage. The bias gate driver is configured to receive a second clock signal different from the first clock signal, the gate high voltage, and the gate low voltage.

15. The display device according to claim 14, wherein, The high level of the first clock signal is the same as the high voltage of the gate, and Wherein, the high level of the second clock signal is greater than the high voltage of the gate.

16. The display device according to claim 11, wherein, The conventional gate driver is configured to receive a clock signal, a first gate high voltage, and a first gate low voltage. The bias gate driver is configured to receive the clock signal, a second gate high voltage different from the first gate high voltage, and a second gate low voltage different from the first gate low voltage.

17. The display device according to claim 1, wherein, The bias line configured to apply the bias voltage extends in the second direction and is commonly connected to a plurality of pixels arranged in the first direction.

18. The display device according to claim 1, wherein, The pixels include: A first transistor, the first transistor including a control electrode connected to a first node, an input electrode connected to a second node, and an output electrode connected to a third node; The second transistor includes a control electrode configured to receive the data write gate signal, an input electrode configured to receive the data voltage, and an output electrode connected to the fourth node. The third transistor includes a control electrode configured to receive a compensation gate signal, an input electrode connected to the first node, and an output electrode connected to the third node; The fourth transistor includes a control electrode configured to receive a data initialization gate signal, an input electrode configured to receive an initialization voltage, and an output electrode connected to the first node. The fifth transistor includes a control electrode configured to receive the compensation gate signal, an input electrode configured to receive a reference voltage, and an output electrode connected to the fourth node; A sixth transistor, the sixth transistor including a control electrode configured to receive a second transmission signal, an input electrode connected to the third node, and an output electrode connected to the anode of the light-emitting element; A seventh transistor includes a control electrode configured to receive a first initialization gate signal, an input electrode configured to receive the initialization voltage, and an output electrode connected to the anode of the light-emitting element; The eighth transistor includes a control electrode configured to receive a second initialization gate signal, an input electrode configured to receive the bias voltage, and an output electrode connected to the second node; The ninth transistor includes a control electrode configured to receive a first transmitted signal, an input electrode configured to receive a power supply voltage, and an output electrode connected to the second node; A holding capacitor, the holding capacitor including a first electrode configured to receive the power supply voltage and a second electrode connected to the fourth node; and A storage capacitor, the storage capacitor including a first electrode connected to the fourth node and a second electrode connected to the first node, and The driving switching element is the first transistor, and the bias switching element is the eighth transistor.

19. The display device according to claim 18, wherein, The duration of the high level of the first transmitted signal during the data writing period when the data voltage is written to the pixel is less than the duration of the high level of the first transmitted signal during the self-scanning period when the data voltage is not written to the pixel and the light-emitting element is turned on.

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