Storage controller and method of operation of a storage controller

Abstract

A storage controller and an operating method of the storage controller are provided. The storage controller includes: processing circuitry configured to read sub-stripe data from each of a plurality of non-volatile memory devices connected with a RAID (Redundant Array of Independent Disks), check error information of at least one of the sub-stripe data, and in response to the at least one of the sub-stripe data having an uncorrectable error, perform a RAID recovery operation; and a RAID memory storing a calculation result of the RAID recovery operation.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2021-0024815, filed with the Korean Intellectual Property Office on February 24, 2021, the contents of which are incorporated herein by reference. Technical Field

[0002] The present invention relates to systems including storage devices and RAID. Background Technology

[0003] Redundant Array of Inexpensive Disks (RAID) is a method primarily used for storage media containing critical data (such as servers). It allows for various configurations, such as simply distributing data across multiple storage media and immediately performing input / output, or copying and storing the same data across multiple media, or storing parity data on additional storage media even if errors occur in data stored on one or more of the media, enabling recovery of erroneous data. When such RAID is used, data loss is reduced or prevented, and data stability is enhanced. Furthermore, I / O operations can be balanced, and overall server performance can be improved.

[0004] On the other hand, in systems used to ensure data integrity, RAID level 5 or RAID level 6 systems, which distribute and store parity bits, are used in RAID configurations. RAID level 5 distributes and stores one parity bit per data chunk, while RAID level 6 distributes and stores two parity bits per data chunk. When using a level 5 or level 6 RAID system, RAID recovery is performed on the spare storage areas in the event of a failure by including one or two spare storage areas.

[0005] Since such RAID recovery processing involves accessing parity bits and data throughout the RAID system to generate the lost data, it has the disadvantage of increasing the time required for RAID recovery processing, and it also has a significant impact on the I / O performance of the entire RAID system due to the use of system resources during the reconstruction process. Summary of the Invention

[0006] Some exemplary embodiments of the present invention provide a storage controller and a method of operating the same, wherein, when an uncorrectable error occurs in a RAID system and recovery is performed, the storage controller can reduce the amount of time spent performing the recovery operation by using fewer resources.

[0007] Some exemplary embodiments of the present invention also provide a storage device in which, when an uncorrectable error occurs in a RAID system and recovery is performed, the storage device can reduce the amount of time spent performing the recovery operation by using fewer resources.

[0008] Some exemplary embodiments of the present invention also provide a RAID storage controller, wherein, when an uncorrectable error occurs and recovery is performed, the RAID storage controller can reduce the amount of time spent performing the recovery operation by using fewer resources.

[0009] According to some exemplary embodiments of the present invention, a storage device is provided, wherein when an uncorrectable error occurs and recovery is performed, the storage device can reduce the time required for the recovery operation by using fewer resources.

[0010] According to some exemplary embodiments of the present invention, a storage controller is provided, the storage controller comprising: a processing circuitry configured to: read sub-strip data from each of a plurality of non-volatile memory devices connected to a RAID (Redundant Array of Inexpensive Disks), check for error information in at least one of the sub-strip data, and perform a RAID recovery operation in response to said at least one sub-strip data having an uncorrectable error; and a RAID memory configured to store the calculation results of the RAID recovery operation.

[0011] According to some exemplary embodiments of the present invention, the operation method of the storage controller may include: reading sub-strip data from each of a plurality of non-volatile memory devices connected to a RAID (Redundant Array of Inexpensive Disks); checking the read sub-strip data for error information to check for the presence of uncorrectable errors; in response to the read sub-strip data having errors, incrementing a failure count and reading the next sub-strip data; and in response to the read sub-strip data not having errors, performing an XOR calculation on the read sub-strip data, wherein the error information is stored as a header or basic information of the sub-strip data.

[0012] According to some exemplary embodiments of the present invention, a storage controller is provided, the storage controller comprising: a DMA (Direct Memory Access) interface connected to a plurality of non-volatile memory devices, the DMA interface being configured to: send sub-strip data to each of the plurality of non-volatile memory devices and receive sub-strip data from each of the plurality of non-volatile memory devices; and a processing circuitry configured to: check for error information in the sub-strip data and perform an XOR calculation based on the sub-strip data without uncorrectable errors to extract recovered data, wherein the processing circuitry is configured to: not extract recovered data in response to the number of sub-strip data with uncorrectable errors exceeding the number of parity sub-strips.

[0013] However, the exemplary embodiments of the inventive concept are not limited to those described herein. The above and other exemplary embodiments of the inventive concept will become more apparent to those skilled in the art by referring to the specific implementation of the inventive concept given below. Attached Figure Description

[0014] Figure 1 This is a block diagram illustrating a RAID system according to some example embodiments.

[0015] Figure 2 This is shown as an example. Figure 1 The diagram shows a block diagram of the storage controller configuration.

[0016] Figure 3 This is an example block diagram illustrating a non-volatile memory device according to some example embodiments.

[0017] Figure 4 This is a diagram used to explain the recovery operation of a RAID controller according to some example embodiments.

[0018] Figure 5 and Figure 6 This is a conceptual diagram used to explain the operation of a storage controller according to some example embodiments.

[0019] Figure 7 This is a flowchart used to explain the operation method of a storage controller according to some example embodiments.

[0020] Figure 8 This is a flowchart used to explain the operation method of a storage controller according to some example embodiments.

[0021] Figure 9 This is a diagram illustrating a data center using storage devices according to some example embodiments. Detailed Implementation

[0022] In the following description, some exemplary embodiments based on the concept of the present invention will be described with reference to the accompanying drawings.

[0023] Figure 1 This is a block diagram illustrating a RAID system according to some example embodiments.

[0024] Reference Figure 1 The RAID system 10 includes a host 100 and a storage device 200.

[0025] Host 100 sends a read request to storage device 200 to read data. Storage device 200 reads the requested data Data from multiple non-volatile memory devices 300_1 to 300_n (i.e., NVM_1 to NVM_n) (for example, n can be an integer greater than 2) and sends the requested data Data. However, the reading of the multiple non-volatile memory devices 300_1 to 300_n by storage device 200 is not limited to this.

[0026] Furthermore, the storage device 200 can perform garbage collection and / or metadata reading as internally executable read operations. The inventive concept can also be applied to internal read operations on the non-volatile memory devices 300_1 to 300_n of the storage device 200 without external commands or control.

[0027] Host 100 writes data to storage device 200 and / or reads data stored in storage device 200. Host 100 may provide commands, addresses, and / or data to storage device 200. Host 100 may use commands and / or addresses to request to read data from storage device 200. As an example, host 100 may include at least one processor. Host 100 may be the processor itself and / or an electronic device and / or system including the processor.

[0028] Storage device 200 can access non-volatile memory devices 300_1 to 300_n in response to a command CMD provided by host 100, and / or perform various operations requested by host 100. Specifically, based on a command or address provided by host 100, storage device 200 can read data stored in buffer 220 and / or non-volatile memory devices 300_1 to 300_n. Furthermore, storage device 200 sends the read data (Data) to host 100. Storage device 200 may include storage controller 210 and / or multiple non-volatile memory devices 300_1 to 300_n.

[0029] Storage controller 210 provides an interfacing between host 100 and storage device 200. According to an example embodiment, storage controller 210 may also be referred to as a RAID controller.

[0030] Storage controller 210 reads data to determine whether errors in the data are correctable, and if an uncorrectable error (UCE) exists, storage controller 210 recovers the data that has been erroneous.

[0031] Data read according to some example embodiments includes a header. As one example, the header may include information about successful and / or failed data reading. As another example, the header may include information about successful (ECC success) and / or failed (ECC failure) error correction. As yet another example, the header may include information about the presence and / or absence of uncorrectable errors.

[0032] According to some example embodiments, the storage controller 210 may store basic information. Basic information may include, for example, data read success information and / or read failure information. As another example, basic information may include information about data error correction success (ECC success) and / or error correction failure (ECC failure). As yet another example, basic information may include information about the presence and / or absence of uncorrectable errors.

[0033] According to some example embodiments, when a header-based uncorrectable error is included in data (e.g., A1 data) read from any of a plurality of non-volatile memory devices, the storage controller 210 can recover the data (A1 data) based on data (e.g., A2, A3 to An-1, Pa) read from the remaining non-volatile memory devices belonging to the same stripe.

[0034] For example, when an uncorrectable error (Uncor or UCE) occurs in the first data, storage device 200 reads the remaining second data belonging to the same stripe, excluding the first data that has been erroneous, and performs a predetermined (or alternately, given) recovery calculation based on the read remaining second data to recover the first data. For example, storage controller 210 may store data in a RAID configuration across multiple non-volatile memory devices 300_1 to 300_n. Specifically, user data and parity data may be stored in each of the multiple non-volatile memory devices in units of sub-stripes. For example, if the user data consists of L sub-stripes and the parity data consists of M sub-stripes (L and M are natural numbers, and L is greater than M), the number of non-volatile memory devices connected in a RAID configuration can be (L+M).

[0035] To utilize the recovery types described above, storage controller 210 may include RAID engine 212 and / or ECC engine 214. When storage controller 210 connects to flash interface 217 (see...) Figure 2 ) Receives from non-volatile memory device 300 (one of non-volatile memory devices 300_1 to 300_n, or see Figure 3 When reading data, the storage controller 210 can perform flash recovery on the data read through the ECC engine 214.

[0036] Flash memory recovery can be techniques such as various read environment adjustments to blocks generated in one of the non-volatile memory devices 300, valley search, and / or ECC (error correction code).

[0037] Flash memory recovery may include, for example, hard decision decoding and / or soft decision decoding. Hard decision decoding and / or soft decision decoding are used. While hard decision decoding uses fewer resources and is therefore efficient, its error correction capability may be relatively degraded. On the other hand, soft decision decoding has higher error correction capability than hard decision decoding, but uses more resources. Therefore, according to some example embodiments, ECC engine 214 may first perform hard decision decoding and generate the decoding result as the header and / or base information of the data. ECC engine 214 may then perform soft decision decoding a second time under the control of RAID engine 212.

[0038] RAID engine 212 processes requested data to be accessed on a stripe-by-strip basis for storing data in RAID configuration across multiple non-volatile memory devices 300_1 to 300_n. For example, if an uncorrectable error (UCE) occurs in one or more sub-stripes included in a single stripe, storage controller 210 performs RAID recovery (RR) and can recover the single stripe. According to some example embodiments, RAID engine 212 may examine the header and / or basic information generated by ECC engine 214 and perform RAID recovery. In this case, the header may indicate information regarding whether an uncorrectable error (UCE) is included.

[0039] According to some example embodiments, even if the header indicates an uncorrectable error (UCE), the ECC engine 214 can be controlled to perform re-error decoding in cases where an error with a probability close to that of a correctable error becomes an uncorrectable error due to memory cell degradation. For example, although the ECC engine 214 initially performs hard decision decoding on the read data and determines an uncorrectable error (UCE), if soft decision decoding is performed a second time and the determination can be changed to a correctable error (CE), the RAID engine 212 controls the ECC engine 214 to update the decoding settings, and the ECC engine 214 can perform re-error decoding with the updated decoding settings, for example, in a soft decision decoding manner.

[0040] As in the example embodiment described above, since the inclusion of uncorrectable errors can be checked based on the header and / or basic information, the RAID engine 212 of the storage controller 210 can make its own determination to perform RAID recovery without the intervention of the CPU 211.

[0041] Figure 2 This is shown as an example. Figure 1 The block diagram shown illustrates the configuration of the storage controller 210.

[0042] Reference Figure 2 According to some example embodiments, the storage controller 210 includes a CPU 211, a RAID engine 212, a host interface 213, an ECC engine 214, a buffer memory 215, and / or a flash memory interface 217.

[0043] The CPU (Central Processing Unit) 211 will be used for non-volatile memory devices (see...). Figure 1 Various types of control information for read / write operations of the non-volatile memory devices 300_1 to 300_n are sent to the registers of the host interface 213 and the flash memory interface 217. The CPU 211 can operate according to the firmware provided for various control operations of the memory controller 210. For example, the CPU 211 can perform garbage collection for managing the non-volatile memory devices 300_1 to 300_n and / or perform address mapping and / or wear leveling, etc., of the flash translation layer (FTL).

[0044] According to some example embodiments, CPU 211 may include register 400. Register 400 may store computational data that requires fast access to generate control signals for CPU 211. According to some example embodiments, register 400 may store basic information. Basic information may include, for example, the presence and / or absence of error detection of data read from non-volatile memory device 300 and / or data requested to be written to non-volatile memory device 300, the number of error bits, the location of error bits, the presence or absence of error correction and / or the presence or absence of the impossibility of error correction, etc. CPU 211 may check the basic information to control the operation of RAID engine 212. Register 400 may be implemented as, for example, TCM (Tightly Coupled Memory) and / or may be implemented as SRAM (Static RAM), etc.

[0045] Although in the example embodiments described above, register 400 has been described as being included in CPU 211, in other example embodiments, register 400 may be implemented separately from CPU 211.

[0046] According to some example embodiments, RAID engine 212 divides the data provided by host 100 into stripes, and distributes and / or stores each stripe into each of non-volatile memory devices 300_1 to 300_n in units of sub-stripes. RAID engine 212 can generate parity data in units of stripes to generate data. The number and / or configuration type of sub-stripes corresponding to the parity data can be configured differently according to various example embodiments, depending on the RAID type. Each sub-strip may include at least one sub-strip capable of performing ECC decoding.

[0047] RAID can be of various levels. According to some example embodiments, RAID can be a RAID level (e.g., RAID 0+1, RAID 1+0, RAID 5+0, RAID 5+1, or RAID 0+1+5), wherein any one and / or at least two of the following RAID levels are combined: RAID level 0 (no parity data or striped stripes), RAID level 1 (no parity data or mirrored sets), RAID level 2 (Hamming code parity data), RAID level 3 (stripes with dedicated parity data, bit-interleaved parity data, or byte-level parity data), RAID level 4 (block-level parity data), RAID level 5 (stripes with distributed parity data or interleaved parity data), RAID level 6 (stripes with dual distributed parity data), RAID level 7, RAID level 10, and RAID level 53.

[0048] According to some example embodiments, the storage controller 210 may also include a RAID memory 219. The RAID memory 219 may be used as the working memory of the RAID engine 212 and may be implemented as various types of memory. For example, the RAID memory 219 may store intermediate values ​​and / or result values ​​of recovery calculations performed by the RAID engine 212. That is, the RAID memory 219 may store the XOR calculation results between sub-strip data. According to some example embodiments, the RAID memory 219 may be volatile memory and / or non-volatile memory. For example, the RAID memory 219 may be implemented as at least one of a cache, DRAM (Dynamic RAM), SRAM (Static RAM), PRAM (Phase Change RAM), MRAM (Magnetic RAM), RRAM (Resistive RAM), and / or flash memory device.

[0049] Host interface 213 can communicate with host 100. For example, host interface 213 provides a communication channel with host 100. Host interface 213 provides a physical connection between host 100 and storage device 200. That is, host interface 213 provides an interface connection with storage device 200 corresponding to the bus format of host 100. The bus format of host 100 can be configured to be at least one of USB (Universal Serial Bus), SCSI (Small Computer System Interface), PCI Express, ATA, PATA (Parallel ATA), SATA (Serial ATA), SAS (Serial Attached SCSI), and / or UFS (Universal Flash Memory).

[0050] According to some example embodiments, ECC engine 214 may perform encoding for error detection and correction on data to be written. According to some example embodiments, ECC engine 214 detects errors, including errors in data read from non-volatile memory device 300, and / or corrects detected errors.

[0051] The ECC engine 214 has a limit on the number of correctable bits. When an error exceeding this limit is detected, the ECC engine 214 can determine an uncorrectable error (UCE) and notify the CPU 211 of the occurrence of the uncorrectable error UCE. In some example embodiments, the ECC engine 214 can record whether the error is a correctable error (CE) or an uncorrectable error (UCE) as data header information H and / or basic information of register 400. In some example embodiments, the ECC engine 214 can also record the number of bits that have been erroneous as data header information H and / or basic information of register 400. According to some example embodiments, the recorded header and / or basic information can be one bit or multiple bits.

[0052] Predetermined (or alternately, given) information, programs, and / or commands regarding the operation or state of storage controller 210 may be stored in buffer memory 215. As an example, buffer memory 215 may temporarily store write data, read data, and / or global metadata. Global metadata may be, for example, various environmental information across the entire storage device.

[0053] According to some example embodiments, buffer memory 215 may include cache, ROM (read-only memory), PROM (programmable read-only memory), EPROM (erasable PROM), EEPROM (electrically erasable programmable read-only memory), PRAM (phase-change RAM), flash memory, SRAM (static RAM), and / or DRAM (dynamic RAM). While in some example embodiments buffer memory 215 may be implemented by being included in memory controller 210, in another example embodiment buffer memory 215 may also be implemented as... Figure 1 The storage controller 210 is an external non-volatile memory.

[0054] Flash interface 217 exchanges data with non-volatile memory devices 300_1 to 300_n. According to some example embodiments, flash interface 217 writes data sent from buffer memory 215 to non-volatile memory devices 300_1 to 300_n via corresponding memory channels CH1, CH2, ..., CHn. According to some example embodiments, flash interface 217 gathers read data from non-volatile memory devices 300_1 to 300_n provided via memory channels. The gathered data is then stored in buffer memory 215 and can be processed by CPU 211. As an example, each of the data to be written and the data before being gathered may also include a header, and RAID engine 212 may check from the header whether each piece of data includes errors, uncorrectable errors, or correctable errors. Optionally, as another example, each or one or more of the data to be written and the data before being gathered may be associated with basic information including error information, and RAID engine 212 may check from the basic information whether each or one or more pieces of data includes errors, uncorrectable errors, correctable errors, or the number of error bits.

[0055] According to some example embodiments, the flash memory interface 217 may include a DMA (Direct Memory Access) interface. Each of the non-volatile memory devices 300_1 to 300_n can be connected to the memory controller 210 via the DMA interface, without going through the host 100. The following will... Figure 7 The specific details are described in the text.

[0056] Furthermore, if an uncorrectable error (UCE) is detected in data read from non-volatile memory devices 300_1 to 300_n, the memory controller 210 can perform a recovery operation. By applying this type of recovery, the memory controller 210 of this invention can recover data at high speed when an uncorrectable error (UCE) occurs.

[0057] RAID engine 212 and ECC engine 214 may execute corresponding recovery algorithms for recovery operations according to some of the example embodiments described above. The recovery algorithm may be stored in ROM (not shown) and / or in non-volatile memory devices 300_1 to 300_n disposed in storage device 200. Furthermore, the algorithm is loaded into buffer memory 215 at startup and may be executed by RAID engine 212 and / or ECC engine 214.

[0058] Figure 3 This is an example block diagram illustrating a non-volatile memory device according to some example embodiments.

[0059] Reference Figure 3 The non-volatile memory device 300 includes control logic circuitry 320, a memory cell array 330, a page buffer unit 340, a voltage generator 350, and / or a line decoder 360. Although not explicitly stated... Figure 3 As shown, the non-volatile memory device 300 may also include a memory interface circuit 310, and may also include column logic, a pre-decoder, a temperature sensor, a command decoder and / or an address decoder, etc.

[0060] Control logic circuit 320 typically controls various operations within the non-volatile memory device 300. Control logic circuit 320 can output various control signals in response to commands CMD and / or addresses ADDR from memory interface circuit 310. For example, control logic circuit 320 can output voltage control signal CTRL_vol, row address X-ADDR, and / or column address Y-ADDR.

[0061] The memory cell array 330 may include multiple memory blocks BLK1 to BLKz (where z is a positive integer), and each of the multiple memory blocks BLK1 to BLKz may include multiple memory cells. The memory cell array 330 may be connected to the page buffer unit 340 via bit line BL, and may be connected to the line decoder 360 via word line WL, string select line SSL, and / or ground select line GSL.

[0062] In some example embodiments, the memory cell array 330 may include a three-dimensional memory cell array, and the three-dimensional memory cell array may include a plurality of NAND strings. Each NAND string may include memory cells connected to word lines vertically stacked on a substrate. U.S. Patent Publications Nos. 7,679,133, 8,553,466, 8,654,587, 8,559,235, and 2011 / 0233648 are incorporated herein by reference. In some example embodiments, the memory cell array 330 may include a two-dimensional memory cell array, and the two-dimensional memory cell array may include a plurality of NAND strings arranged along row and column directions.

[0063] Page buffer unit 340 may include multiple page buffers PB1 to PBn (n is an integer of three or greater), and the multiple page buffers PB1 to PBn may be connected to the memory cell via multiple bit lines BL. Page buffer unit 340 may select at least one bit line among the bit lines BL in response to column address Y-ADDR. Depending on the operating mode, page buffer unit 340 may operate as a write driver and / or a sense amplifier. For example, during a write operation, page buffer unit 340 may apply a bit line voltage corresponding to the data to be programmed to the selected bit line. During a read operation, page buffer unit 340 may sense the current and / or voltage of the selected bit line and sense the data stored in the memory cell.

[0064] Voltage generator 350 can generate various types of voltages for performing write, read, and / or erase operations based on the voltage control signal CTRL_vol. For example, voltage generator 350 can generate write (or programming) voltage, read voltage, programming verification voltage, and / or erase voltage as word line voltage VWL.

[0065] The row decoder 360 can select one of multiple word lines (WL) and / or one of multiple string select lines (SSL) in response to the row address X-ADDR. For example, the row decoder 360 can apply a programming voltage and / or a programming verification voltage to the selected word line during a write operation and can apply a read voltage to the selected word line during a read operation.

[0066] Figure 4 This is a diagram used to explain the recovery operation of a RAID controller according to some example embodiments.

[0067] Reference Figure 4The RAID engine 212 divides the data DATA requested to be written from the host 100 into multiple sub-stripes of data. The RAID engine 212 can distribute and store the divided sub-stripes of data (e.g., A1, A2, A3 to An-1) into various storage devices (e.g., non-volatile memory devices) (e.g., 3011, 3012, 3013, and / or 305). One or more parity sub-stripes Pa can be included in the divided sub-stripes of data. Here, the storage device can correspond to chips and / or dies, etc. Since the probability of simultaneous errors in multiple storage devices is almost very low, data reliability can be improved by the RAID engine 212.

[0068] Data DATA can be transmitted between host 100 and storage device 200 in stripes. Users of host 100 and / or storage device 200 can select the data size of the stripes. Data DATA may include one or more stripes. A stripe may include multiple sub-stripes (e.g., C1, C2, C3, ..., and / or Cn-1). Additionally, a stripe may include parity data (e.g., Pc) referenced to test for errors in the sub-stripes. Sub-stripes and parity data may be distributed and / or stored in multiple non-volatile memory devices (e.g., 3011, 3012, 3013, and / or 305). For ease of description herein, a stripe may consist of a total of N sub-stripes, and / or a stripe may include L user sub-stripes for storing user data and / or M parity sub-stripes for storing parity data (N = M + L).

[0069] For example, a sub-strip of data may have a data size corresponding to a read cell of a read operation performed in non-volatile memory devices 3011, 3012, 3013 and / or 305. Data stored in non-volatile memory devices 3011, 3012, 3013 and / or 305 may be read in units of read cells having the same data size as the sub-strip.

[0070] When such a RAID configuration is adopted, even if an error occurs in the data of a sub-strip stored in a storage device, the sub-strip data can be recovered by referring to the sub-strips containing parity data Pa, Pb, Pc, and / or Pd. For example, when an error occurs in the data of sub-strip C1 among sub-strips C1, C2, C3, ... and sub-strips formed by parity data Pc, the storage controller 210 can recover the erroneous C1 sub-strip data using the error-free sub-strips C2, C3, ... and the parity data Pc sub-strip. However, it is necessary to use error-free sub-strips and / or error-correctable sub-strips that are included due to error decoding performed by the ECC engine 214 to ensure data integrity so that the erroneous sub-strip can be recovered.

[0071] In some example embodiments, each of the non-volatile memory devices 3011, 3012, 3013, and / or 305 may be implemented as a single chip and / or die. Furthermore, each chip and / or die may be connected to an independently accessible channel via the memory controller 210.

[0072] Figure 5 and Figure 6 This is a conceptual diagram used to explain the operation of a storage controller according to some example embodiments.

[0073] Reference Figure 5 According to some example embodiments, the storage controller 210 includes a RAID engine 212 and / or a DMA (Direct Memory Access) interface 510 and / or 520.

[0074] According to some example embodiments, DMA interfaces 510 and / or 520 may be included. Figure 2 The flash memory interface 217 is included, and the DMA interfaces 510 and / or 520 can be connected to the non-volatile memory devices 301 and / or 305.

[0075] When DMA interfaces 510 and / or 520 receive sub-strip data from non-volatile memory device 301, DMA interfaces 510 and / or 520 may perform error decoding, append a header to the decoded data, and / or provide it to RAID engine 212. Specifically, according to some example embodiments, ECC engine 214 may include error decoders (e.g., ECC DEC) 512 and / or 522, and / or error encoders (not shown), and may perform error decoding and / or error encoding on data received and / or transmitted through DMA interfaces 510 and / or 520. For example, when ECC engine 214 performs error decoding on read sub-strip data, error decoders 512 and / or 522 generate header information H including error information based on the decoding result, and may add header information H to data (511). Alternatively, as another example, when the ECC engine 214 performs error decoding on the read sub-strip data, the error decoder 512 and / or 522 may generate basic information including error information based on the decoding result and store the basic information in register 400, and may associate the basic information with data (511).

[0076] Upon receiving header information / basic information and / or data 511, RAID engine 212 checks the header information / basic information and detects whether the data includes uncorrectable errors (UCEs). If no errors are present or only correctable errors are included, RAID engine 212 may include them as targets for XOR calculations. According to some example embodiments, RAID engine 212 may include an XOR machine 401 and / or an uncorrectable error detector 405.

[0077] As an example, the uncorrectable error detector 405 can examine the received header and detect whether the data includes an uncorrectable error (UCE). If the uncorrectable error UCE is not included, the XOR machine 401 can be made available. According to some example embodiments, the XOR machine 401 can process user data (e.g., multiple (e.g., L) sub-stripes (e.g., ... Figure 4 XOR calculations are performed on A1, A2, A3, ... to generate at least one (e.g., M) parity sub-stripes. Optionally, according to some example embodiments, if no uncorrectable error is detected based on the result of the uncorrectable error detector 405, the XOR machine 401 may perform XOR calculations on N sub-strip data 511 and / or M parity sub-strip data 521 based on user data to perform RAID recovery.

[0078] On the other hand, the RAID engine 212 may also include a counter 407. For example, the counter 407 may increment the execution count value i each time an XOR calculation is performed. Optionally, if error correction fails due to incorrect decoding, the counter 407 may increment the failure count value k.

[0079] The RAID 212 engine can determine whether a recovery is complete or has failed based on the counter value.

[0080] For example, suppose the data requested by the host is stored as L user data and M parity data in a total of N sub-stripes within the same stripe of multiple non-volatile memory devices. L and M are natural numbers, with L being a number greater than M. The L user data and M parity data can each be data from a sub-strip unit. Suppose that the first sub-strip data, including one of the L user data and M parity data, contains an uncorrectable error (UCE), and the remaining second sub-strip data, excluding the first sub-strip data, consists of the remaining user data and / or parity data excluding the uncorrectable error. For example, the first sub-strip data can be either user data or parity data. Similarly, the second sub-strip data can be either user data or parity data.

[0081] According to some example embodiments, RAID engine 212 performs an XOR calculation while increasing the execution count value i for the second sub-strip data, and performs the XOR calculation until the execution count value i becomes equal to the total number of sub-stripes N. When the failure count value k is within the number of parity sub-stripes M, RAID engine 212 determines that the first sub-strip data has been reliably recovered from the second sub-strip data, extracts the XOR calculation result as the first sub-strip data, and terminates the RAID recovery operation.

[0082] RAID engine 212 performs an XOR calculation on the second sub-strip data and increments the execution count value i. Subsequently, when the execution count value i reaches the total number of sub-stripes N, but the failure count value k exceeds the number of parity sub-stripes M (k>M), RAID engine 212 determines that there are many uncorrectable errors UCE and that the second sub-strip data used to recover the first sub-strip data is insufficient (or missing), and determines that RAID recovery has failed.

[0083] However, in this scenario, RAID engine 212 can perform enhanced ECC decoding before determining that RAID recovery has failed. Enhanced ECC decoding can be performed such that if error decoding is initially performed using, for example, hard-decision decoding, error decoding is performed in a soft-decision decoding manner (i.e., re-error decoding) during the second decoding. When an uncorrectable error UCE is determined during the first error decoding but a correctable error CE is determined during the second re-error decoding, the ECC engine can correct the data error to enhance the integrity of the second sub-strip data participating in the XOR calculation. Furthermore, when only one sub-strip data within the RAID contains an uncorrectable error, the aforementioned RAID engine 212 performs RAID recovery, and only when two or more sub-strip data contain uncorrectable errors, the RAID engine 212 updates the decoding settings and performs re-error decoding. Therefore, the number of additional reads of non-volatile memory devices for re-error decoding can be reduced.

[0084] According to some example embodiments, RAID engine 212 performs an XOR calculation on the second sub-strip data while incrementing the execution count value i. When the second sub-strip data includes uncorrectable errors (e.g., UECC (Uncorrectable Error Correction Code)), RAID engine 212 increments the failure count value k and reads the next second sub-strip data.

[0085] When all sub-stripes N have been read, if the failure count k is less than the number of parity sub-stripes M, it is determined that the RAID can be recovered using the sub-strip data read so far. The result of the XOR calculation (e.g., the result of the XOR calculation for all sub-strip data for which no errors were detected) is extracted as the first sub-strip data, and the RAID recovery operation is terminated. However, if the failure count k is greater than the number of parity sub-stripes M, it is determined that data recovery is difficult and RAID recovery fails.

[0086] Reference Figure 6 The storage controller 210 can be connected to multiple non-volatile memory devices 301 and / or 302 through multiple channels CH0, CH1, ... and each of the channels CH0, CH1, ... can include a write path and / or a read path.

[0087] The host 100 can send write requests and / or data to be written via the optical path (PG path), and can send read requests and receive read data via the read path (RD path).

[0088] According to some example embodiments, the write path for each channel may include write splitters 251W and / or 252W, which send the data to be written to the RAID engine 212. The read path for each channel may include read splitters 251R and / or 252R, which send the read data to the RAID engine 212. That is, the write splitters 251W and / or 252W and the read splitters 251R and / or 252R are connected between the front and back paths to send data, and can send the data to the RAID engine 212.

[0089] RAID engine 212 performs RAID recovery based on the header in which the decoding result of ECC engine 214 is reflected, and can notify host 100 of the result (S) of recovery completion or recovery failure.

[0090] Even if the decoding settings are updated and read again during RAID recovery processing, the RAID engine 212 can also notify the host 100 of basic information about the sub-strip data (e.g., address, operating environment information, and / or error-related information, etc.) when the sub-strip data read from at least one non-volatile memory device 300 includes uncorrectable errors (M).

[0091] According to some example embodiments, when the storage controller 210 receives a sequential read command through the file transfer layer, the storage controller 210 enables all non-volatile memory devices 300 connected in RAID mode and can read sub-strip data from each of them.

[0092] According to some example embodiments, when the storage controller 210 receives a random read command via the file transfer layer, it is not possible to read all non-volatile memory devices 300 connected in RAID configuration according to the random read command. Therefore, the storage controller 210 disconnects the RAID connection, enables all non-volatile memory devices 300 belonging to the same stripe of the requested data, and can read sub-strip data from each of them.

[0093] In the example above, because all sub-strip data belonging to the same stripe are read, even if at least one first sub-stripe data includes an uncorrectable error (UCE), the storage controller 210 can recover the erroneous first sub-stripe data based on the remaining second sub-stripe data read together, and can send the entire data to the host 100 based on the recovered first sub-stripe data and the remaining second sub-stripe data. Because the storage controller 210 can check whether an uncorrectable error is included based on the error information of each sub-stripe, the RAID engine 212 can make its own determination and perform RAID recovery without the intervention of the CPU 211.

[0094] RAID engine 212 performs an XOR calculation based on the read sub-strip data and stores the result. Storage controller 210 can compare the number M of parity sub-stripes with a failure count to extract the result of the stored XOR calculation as the recovered sub-strip data. The following will... Figure 7 and Figure 8 The text describes more specific operations.

[0095] Figure 7 This is a flowchart used to explain the operation method of the storage controller 210 according to some example embodiments.

[0096] Reference Figure 7 According to some example embodiments, the storage controller first resets the counter's count value (e.g., execution count value i and failure count value k) (S10). The storage controller reads sub-strip data (the i-th data) from each of the plurality of non-volatile memory devices connected to the RAID (S11) and checks the read sub-strip data for error information (ERR information) (S12). According to some example embodiments, the error information may be the header of the read sub-strip data (the i-th data), or the error information may be based on basic information stored in a register.

[0097] The storage controller checks for error information, and if the sub-strip data has an error (that is, if an error is detected) (S13), the storage controller increments the failure count value k and the execution count value i (S14), reads the next sub-strip data (the i++th data) (S11), and repeats steps S12 and S13. On the other hand, the storage controller checks for error information, and if the sub-strip data does not have an error (S13), the storage controller performs an XOR calculation using the read sub-strip data (the i-th data) (S15), and increments the execution count value i (S16).

[0098] The storage controller repeats steps S12 to S17 until the increased execution count value i becomes equal to the total number of sub-stripes N. If the increased execution count value i becomes equal to the total number of sub-stripes N (e.g., the total number of data sub-stripes and parity sub-stripes) (S17) (that is, all sub-stripes of the non-volatile memory device have been read), the storage controller compares the failure count value k with a predetermined (or alternately, given) value M (S18). At this point, the predetermined (or alternately, given) value M can be the number of parity sub-stripes in the multiple non-volatile memory devices connected to the RAID. For example, M can be 1 in the case of RAID5, and M can be 2 in the case of RAID6.

[0099] If the failure count value k is equal to or less than a predetermined (or alternately, given) value M (S18), the storage controller determines that it can be recovered in RAID mode and extracts the value subjected to XOR calculation in step S15 as the recovery data (S19). On the other hand, when the failure count value k is greater than the predetermined (or alternately, given) value M (S18), the storage controller can, according to... Figure 8 Make a decision.

[0100] Figure 8 This is a flowchart used to explain the operation method of a storage controller according to some example embodiments.

[0101] Reference Figure 7 and Figure 8 When the failure count value k is greater than a predetermined (or alternately, given) value, the storage controller executes steps S30 to S54. Steps S30 to S54 first read the sub-strip data again, attempt to perform error decoding, and check again whether the error cannot be recovered.

[0102] Specifically, the storage controller resets the count value again (S30) and reads sub-strip data from multiple non-volatile memories connected to the RAID (S31).

[0103] Set the read sub-strip data (i-th data) to the first error decoding mode (S32), and perform error decoding in the set mode (S33).

[0104] If the error is a correctable error as a result of the first error decoding (S34, pass), then an XOR calculation is performed using the sub-strip data (the i-th data) (S35), and the execution count value i is incremented to read the next sub-strip data (S36). Steps S31 to S36 are repeated until the execution count value i becomes equal to the total number of sub-stripes N (S37). When the execution count value i becomes equal to the total number of sub-stripes (S37) (that is, when all sub-stripes have been read), the failure count value k is compared with a predetermined (or alternately, given) value M. Figure 7 As shown, the predetermined (or alternately, given) value M is the number of parity sub-stripes.

[0105] If the failure count k is within a predetermined (or alternately, given) value (S38, Yes), it is determined that recovery can be performed using parity sub-strip data, and the XOR calculation result of S35 is extracted as the recovered data (S39). If the failure count k exceeds a predetermined (or alternately, given) value (S38, No), it is determined that recovery is not possible, recovery fails, and the recovery operation is terminated (S40).

[0106] If the error is an uncorrectable error (S34, failure) as a result of the first error decoding, the failure count value k is increased (S50), the setting is changed to the second error decoding mode (S51), the sub-strip data read in S31 is read again (S52), and error decoding is performed in the set mode (S53). For example, the first error decoding can be performed in a hard decision decoding mode, and / or the second error decoding can be performed in a soft decision decoding mode. Although an uncorrectable error UCE is determined during the first error decoding, if a correctable error CE is determined during the second error decoding, the storage controller can correct the data error to enhance the integrity of the second sub-strip data participating in the XOR calculation.

[0107] If the error, as a result of the second error decoding, is a correctable error (S54, pass), then steps S35 and thereafter are executed; and if the error is an uncorrectable error (S54, fail), then steps S36 and thereafter are executed. That is, in the case of an uncorrectable error, the next sub-strip data is read without further error decoding.

[0108] Therefore, according to some example embodiments, RAID recovery operations can be successfully performed even when the number of sub-stripes containing uncorrectable errors exceeds the number of parity sub-stripes. Furthermore, fewer resources are available for the recovery operation. Additionally, the amount of time spent performing the recovery operation can be reduced by using fewer resources.

[0109] Figure 9 This is a diagram illustrating a data center using storage devices according to some example embodiments.

[0110] Reference Figure 9 Data center 1000 is a facility that collects various types of data and provides services, and may be referred to as a data storage center. Data center 1000 may be a search engine and / or a system for database operations, and / or data center 1000 may be a computing system used by a company (such as a bank and / or a government agency). Data center 1000 may include application servers 1100 to 1100n and storage servers 1200 to 1200m. The number of application servers 1100 to 1100n and the number of storage servers 1200 to 1200m may be selected differently according to example embodiments, and the number of application servers 1100 to 1100n and the number of storage servers 1200 to 1200m may differ from each other.

[0111] Application server 1100 and / or storage server 1200 may include at least one of processors 1110 and 1210 and at least one of memories 1120 and 1220. Taking storage server 1200 as an example, processor 1210 may control the overall operation of storage server 1200 and access memory 1220 to execute command language and / or data loaded into memory 1220. Memory 1220 may be DDR SDRAM (Double Data Rate Synchronous DRAM), HBM (High Bandwidth Memory), HMC (Hybrid Memory Cube), DIMM (Dual In-line Memory Module), Optane DIMM, and / or NVM DIMM (Non-Volatile DIMM).

[0112] According to example embodiments, the number of processors 1210 and / or the number of memory 1220 included in storage server 1200 may be selected differently. In some example embodiments, processors 1210 and memory 1220 may provide processor-memory pairs. In some example embodiments, the number of processors 1210 and the number of memory 1220 may be different from each other. Processor 1210 may include a single-core processor or a multi-core processor. The above description of storage server 1200 can also be similarly applied to application server 1100. According to example embodiments, application server 1100 may not include storage device 1150. Storage server 1200 may include at least one or more storage devices 1250. The number of storage devices 1250 included in storage server 1200 may be selected differently according to example embodiments. According to example embodiments, when storage devices 1250 are non-volatile memory, they may also be implemented as Figures 1 to 8 The storage device in the middle.

[0113] Application servers 1100 to 1100n and storage servers 1200 to 1200m can communicate with each other via network 1300. Network 1300 can be implemented using FC (Fibre Channel) and / or Ethernet, etc. In this case, FC is the medium for relatively high-speed data transmission and can use optical switches that provide high performance / high availability. Depending on the access type of network 1300, storage servers 1200 to 1200m can be configured as file storage devices, block storage devices, and / or object storage devices.

[0114] In one example, network 1300 can be a storage-only network (such as a SAN (Storage Area Network)). For example, the SAN can be an FC-SAN implemented using an FC network and according to FCP (FC protocol). In another example embodiment, the SAN can be an IP-SAN implemented using a TCP / IP network and according to the iSCSI (SCSI over TCP / IP or Internet SCSI) protocol. In yet another example embodiment, network 1300 can be a general-purpose network (such as a TCP / IP network). For example, network 1300 can be implemented according to protocols such as FCoE (FC over Ethernet), NAS (Network Attached Storage), and / or NVMe-oF (NVMe over a network).

[0115] The following text will primarily describe application server 1100 and storage server 1200. The description of application server 1100 can also be applied to another application server 1100n, and the description of storage server 1200 can also be applied to another storage server 1200m.

[0116] Application server 1100 can store data requested by users or clients in one of storage servers 1200 to 1200m via network 1300. Furthermore, application server 1100 can retrieve data requested by users or clients from one of storage servers 1200 to 1200m via network 1300. For example, application server 1100 can be implemented using a web server and / or a DBMS (Database Management System).

[0117] Application server 1100 can access memory 1120n and / or storage device 1150n included in another application server 1100n via network 1300, or can access memory 1220 to 1220m and / or storage device 1250 to 1250m included in storage servers 1200 to 1200m via network 1300. Therefore, application server 1100 can perform various operations on data stored in application servers 1100 to 1100n and / or storage servers 1200 to 1200m. For example, application server 1100 can execute commands for moving and / or copying data between application servers 1100 to 1100n and / or storage servers 1200 to 1200m. At this time, data can be moved from storage devices 1250 to 1250m of storage servers 1200 to 1200m via storage devices 1220 to 1220m, or it can be directly moved to storage devices 1120 to 1120n of application servers 1100 to 1100n. Data moved via network 1300 can be encrypted for security and privacy.

[0118] Taking storage server 1200 as an example, interface (I / F) 1254 can provide a physical connection between processor 1210 and controller (CTRL) 1251, and / or a physical connection between network interface controller (NIC) 1240 and controller 1251. For example, interface 1254 can be implemented using the DAS (Direct Attached Storage) type, where storage device 1250 is directly connected to a dedicated cable. Furthermore, interface 1254 can be implemented using various interface types, such as ATA (Advanced Technology Attachment), SATA (Serial ATA), e-SATA (External SATA), SCSI (Small Computer Small Interface), SAS (Serial Attached SCSI), PCI (Peripheral Component Interconnect), PCIe (PCI Fast), NVMe (NVM Fast), IEEE 1394, USB (Universal Serial Bus), SD (Secure Digital) card, MMC (Multimedia Card), eMMC (Embedded Multimedia Card), UFS (Universal Flash Memory), eUFS (Embedded Universal Flash Memory), and / or CF (Compact Flash Memory) card interfaces.

[0119] Storage server 1200 may also include switch 1230 and / or NIC 1240. Under the control of processor 1210, switch 1230 may selectively connect processor 1210 and storage device 1250, or selectively connect NIC 1240 and storage device 1250. Application server 1100 may also include switch 1130 and NIC 1140. Under the control of processor 1110, switch 1130 may selectively connect processor 1110 and storage device 1150, or selectively connect NIC 1140 and storage device 1150.

[0120] In some example embodiments, NIC 1240 may include a network interface card and / or a network adapter, etc. NIC 1240 can connect to network 1300 via a wired interface, wireless interface, Bluetooth interface, and / or optical interface, etc. NIC 1240 may include internal memory, a DSP, and / or a host bus interface, etc., and can connect to processor 1210 and / or switch 1230, etc., via the host bus interface. The host bus interface may also be implemented as one of the examples of interface 1254 described above. In some example embodiments, NIC 1240 may also be integrated with at least one of processor 1210, switch 1230, and storage device 1250.

[0121] In storage servers 1200 to 1200m or application servers 1100 to 1100n, processors 1110 and 1210 can send commands to storage devices 1150 to 1150n and 1250 to 1250m or memories 1120 to 1120n and 1220 to 1220m to program and / or read data. In this case, the data may be data that has been corrected by an ECC (Error Correction Code) engine. The data is data that has undergone Data Bus Inversion (DBI) and / or Data Masking (DM) processing and may include CRC (Cyclic Redundancy Check) information. The data may be encrypted for security and privacy.

[0122] Storage devices 1150 to 1150m and / or 1250 to 1250m can send control signals and / or command / address signals to NAND flash memory devices 1252 to 1252m in response to a read command received from the processor. Therefore, when reading data from NAND flash memory devices 1252 to 1252m, the RE (Read Enable) signal is input as a data output control signal and can be used to output data to the Data Queue (DQ) bus. The RE signal can be used to generate a DQS (Data Strobe). Command and / or address signals can be latched into the page buffer based on the rising and / or falling edge of the WE (Write Enable) signal.

[0123] Controller 1251 typically controls the operation of storage device 1250. In some example embodiments, controller 1251 may include SRAM (Static Random Access Memory). Controller 1251 may write data to NAND flash memory device 1252 in response to a write command, and / or read data from NAND flash memory device 1252 in response to a read command. For example, write commands and / or read commands may be provided from processor 1210 in storage server 1200, processor 1210m in another storage server 1200m, and / or processor 1110 and / or 1110n in application servers 1100 and 1100n. DRAM 1253 may temporarily store (buffer) data to be written to NAND flash memory device 1252 and / or data to be read from NAND flash memory device 1252. Furthermore, DRAM 1253 may store metadata. Here, metadata is user data and / or data generated by controller 1251 to manage NAND flash memory device 1252. Storage device 1250 may include a security element (SE) for security and / or privacy.

[0124] One or more of the elements disclosed above may include one or more processing circuitry systems (such as hardware including logic circuitry, hardware / software combinations (such as a processor executing software), or combinations thereof), or be implemented as one or more processing circuitry systems (such as hardware including logic circuitry, hardware / software combinations (such as a processor executing software), or combinations thereof). For example, processing circuitry systems may more specifically include, but are not limited to: central processing unit (CPU), arithmetic logic unit (ALU), digital signal processor, microcomputer, field-programmable gate array (FPGA), system-on-a-chip (SoC), programmable logic unit, microprocessor, application-specific integrated circuit (ASIC), etc.

[0125] In concluding with the detailed description, those skilled in the art will understand that many variations and modifications can be made to the exemplary embodiments without substantially departing from the principles of the inventive concept. Therefore, the exemplary embodiments of the disclosed inventive concept are used only in a general and descriptive sense and not for limiting purposes.

Claims

1. A storage controller, comprising: The processing circuit system is configured as follows: Read sub-strip data from each of multiple non-volatile memory devices connected to a low-cost redundant disk array (RAID). Check for error messages in at least one of the sub-strip data, and In response to the error message indicating that at least one of the sub-strip data has an uncorrectable error, a RAID recovery operation is performed; and RAID memory, configured to store the calculation results of RAID recovery operations. The processing circuitry is further configured to: determine a failure count value based on the error information, and in response to the failure count value exceeding the number of parity sub-stripes, reset all count values ​​and reread the sub-strip data stored in each of the plurality of non-volatile memory devices.

2. The storage controller according to claim 1, wherein, The processing circuitry system is also configured as follows: Store the execution count value; The execution count is incremented each time sub-strip data is read; Store the failure count value; and In response to uncorrectable errors in the sub-strip data, the failure count is increased.

3. The storage controller according to claim 2, wherein, The processing circuitry is also configured as follows: Read the next sub-strip data; and RAID recovery operations are performed based on the error information until the execution count becomes equal to the total number of sub-stripes.

4. The storage controller according to claim 2, wherein, The processing circuitry is also configured to perform RAID recovery operations through the following processes: In response to a failure count value being less than the number of parity sub-stripes, an XOR operation is performed on all sub-strip data for which no errors were detected. The XOR operation result is stored in the RAID memory, and the stored result is retrieved as the recovered data.

5. The storage controller according to claim 2, wherein, The processing circuitry system is also configured as follows: In response to a failure count exceeding the number of parity sub-stripes, error decoding of the sub-strip data is performed by rereading it.

6. The storage controller according to claim 5, wherein, The processing circuitry is also configured as follows: Perform initial error decoding on sub-strip data using hard-decision error decoding; and In response to errors in the sub-strip data that are not corrected by the initial error decoding, a secondary error decoding is performed through soft decision error decoding.

7. The storage controller according to claim 6, wherein, The processing circuitry is also configured to terminate the RAID recovery operation in response to errors in the sub-strip data not being corrected through secondary error decoding.

8. The storage controller according to any one of claims 1 to 7, wherein, The processing circuitry is also configured to store the error information as a header or basic information of the sub-strip data.

9. A method of operating a storage controller, the method comprising: Read sub-strip data from each of multiple non-volatile memory devices connected to a low-cost redundant disk array (RAID); Check the error messages in the read sub-strip data to check for the presence of errors; If an error occurs in the sub-strip data being read, increment the failure count and read the next sub-strip data; as well as If the read sub-strip data is error-free, perform an XOR operation on the read sub-strip data. The error information is stored as the header or basic information of the sub-strip data, and The operation method further includes: in response to the failure count value exceeding the number of parity sub-stripes, resetting all count values ​​and rereading the sub-strip data stored in each of the plurality of non-volatile memory devices.

10. The method of operating the storage controller according to claim 9, further comprising: Once the storage controller has read all sub-strip data, in response to the number of parity sub-stripes whose failure count is less than or equal to the number of failure counts, it extracts the XOR calculation result as recovery data.

11. The method of operating the storage controller according to claim 9, further comprising: Perform the first error decoding on the reread sub-strip data, and Once all sub-strip data has been reread, in response to errors being corrected and the failure count being less than the number of parity sub-strips, the XOR calculation result is extracted as the recovery data.

12. The method of operating the storage controller according to claim 11, further comprising: In response to the failure to correct errors in the reread sub-strip data, the sub-strip data is read through a second error decoding, wherein the error correction capability of the second error decoding is higher than that of the first error decoding.

13. The method of operating the storage controller according to claim 12, further comprising: In response to an error not being corrected by the first error decoding, the failure count is increased.

14. The method of operating the storage controller according to claim 12, further comprising: In response to the reread sub-strip data, the error is corrected by a second error decoding, and an XOR calculation is performed with the reread sub-strip data.

15. The method of operating the storage controller according to claim 14, further comprising: In response to the error not being corrected by the second error decoding, the next sub-strip data is read.

16. The method of operating the storage controller according to claim 15, further comprising: The RAID recovery operation is terminated in response to the failure count exceeding the number of parity sub-stripes.

17. A storage controller, comprising: A direct memory access interface is connected to a plurality of non-volatile memory devices, and the direct memory access interface is configured to send sub-strip data to each of the plurality of non-volatile memory devices and receive sub-strip data from each of the plurality of non-volatile memory devices; as well as The processing circuit system is configured as follows: Examine the error messages in the sub-strip data to check for the presence of uncorrectable errors, and XOR computation is performed on sub-strip data that does not have uncorrectable errors to extract the recovered data, and The processing circuitry is further configured to: in response to the number of sub-strip data with uncorrectable errors exceeding the number of parity sub-strips, not extract recovery data, reset all count values, and reread the sub-strip data stored in each of the plurality of non-volatile memory devices.

18. The storage controller according to claim 17, wherein, The processing circuitry is also configured as follows: Perform first error decoding on the reread sub-strip data; and In response to the error being corrected, an XOR operation is performed based on the sub-strip data to extract the recovered data.

19. The storage controller according to claim 18, wherein, In response to the error not being corrected by the first error decoding, the processing circuitry is also configured to: Read the sub-strip data again; and A second error decoding is performed on the sub-strip data that is read again, wherein the error correction capability of the second error decoding is higher than that of the first error decoding.

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