Memory and its programming methods, memory systems

Abstract

This disclosure provides a memory and its programming method and system. The memory includes programmable memory cells with target states from state 1 to state L. The method includes: obtaining the number of initial verification pulses for the x-th state of the programmable memory cell whose target state is x-th; where x is a positive integer greater than 1 and less than or equal to L; and L is a positive integer greater than 1; when the sequence number i of the i-th programming operation is greater than or equal to 1 and less than a first preset value of the x-th state, the i-th programming operation is performed on the programmable memory cell whose target state is x-th; where i is a positive integer; when i is greater than or equal to the first preset value of the x-th state and less than the number of initial verification pulses for the x-th state, when performing the i-th programming operation, an i-th programming prohibition operation is performed on the programmable memory cell whose target state is x-th.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the semiconductor field, and particularly to a memory and its programming method, and a memory system. Background Technology

[0002] NAND flash memory, as a type of non-volatile memory, has advantages such as low cost, high capacity, and fast rewrite speed. NAND flash memory typically employs a one-pass or two-pass programming method. This means programming begins from the erase state and each programming state is verified sequentially until all programming states pass verification or the maximum programming pulse count is reached, at which point programming ends.

[0003] However, as memory cells are erased deeper, the threshold voltage distribution of the erase state becomes wider, affecting the read margin of each programming state and increasing the probability of memory read errors. Therefore, how to better program memory to increase the read margin of programming states and reduce the probability of memory read errors has become an urgent technical problem to be solved. Summary of the Invention

[0004] In view of the above, embodiments of the present disclosure provide a memory and a programming method thereof, as well as a memory system.

[0005] According to a first aspect of the present disclosure, a method for programming a memory is provided, the memory including programmable memory cells whose target states are from state 1 to state L, the method comprising:

[0006] Obtain the number of initial verification pulses for the x-th state of the programmable memory cell whose target state is x-th; where x is a positive integer greater than 1 and less than or equal to L; and L is a positive integer greater than 1.

[0007] When the sequence number i of the i-th programming operation is greater than or equal to 1 and less than the first preset value of the x-th state, the i-th programming operation is performed on the memory unit to be programmed with the target state being the x-th state; where i is a positive integer;

[0008] When i is greater than or equal to the first preset value of the x-th state and less than the number of initial verification pulses of the x-th state, when performing the i-th programming operation, the i-th programming prohibition operation is performed on the memory cell to be programmed with the target state being the x-th state.

[0009] According to a second aspect of the present disclosure, a memory is provided, comprising:

[0010] A memory cell array, the memory cell array comprising a plurality of programmable memory cells whose target states are from the first state to the Lth state;

[0011] Multiple word lines, each of which is coupled to a plurality of programmable memory cells;

[0012] A plurality of bit lines, each of which is coupled to a plurality of programmable memory cells; peripheral circuitry, coupled to the plurality of word lines and the plurality of bit lines and configured to perform the programming method described in the first aspect of the present disclosure on a selected memory cell among the plurality of programmable memory cells.

[0013] According to a third aspect of the present disclosure, a memory system is provided, comprising:

[0014] One or more memories as described in the second aspect of the embodiments of this disclosure;

[0015] A memory controller, coupled to the memory and configured to control the memory.

[0016] In this embodiment of the disclosure, by obtaining the number of initial verification pulses for each target state, and based on the relationship between the sequence number of the programming operation and the first preset value of each target state and the number of initial verification pulses for each target state, programming operations are performed on the memory units to be programmed for a portion of the target states, while programming prohibition operations are performed on the memory units to be programmed for another portion of different target states. This allows programming to continue on the memory units to be programmed for the portion of the target states, while prohibiting programming operations on the memory units to be programmed for the other portion of the target states, thereby increasing the read margin between the memory units to be programmed for the portion of the target states and the memory units to be programmed for the other portion of the target states.

[0017] Furthermore, by only programming some of the target states of the memory cells to be programmed, the charge loss of the memory cells to be programmed after reaching the programmed state is small, which can make the threshold voltage distribution of the memory cells to be programmed in the programmed state narrower. This is beneficial to increase the read margin of each target state in the memory, reduce the probability of memory misread, and thus improve the performance of the memory. Attached Figure Description

[0018] Figure 1a and Figure 1b This is a method for programming a memory according to an exemplary embodiment;

[0019] Figure 2 This is a flowchart illustrating a memory programming method according to an embodiment of the present disclosure;

[0020] Figure 3 This is a flowchart of a memory programming method according to an embodiment of the present disclosure. Figure 2 ;

[0021] Figures 4a to 4c This is a comparative diagram of the programming method of this disclosure embodiment and the programming method of the exemplary embodiment;

[0022] Figure 5 This is a flowchart of a memory programming method according to an embodiment of the present disclosure. Figure 3 ;

[0023] Figure 6 This is flowchart four illustrating a memory programming method according to an embodiment of the present disclosure;

[0024] Figure 7 This is a schematic diagram of a memory according to an embodiment of the present disclosure;

[0025] Figure 8 This is a cross-sectional view of a NAND flash memory string according to an embodiment of the present disclosure;

[0026] Figure 9 This is a block diagram of a memory including a memory cell array and peripheral circuitry, according to embodiments of the present disclosure.

[0027] Figure 10 This is a schematic diagram of a memory system according to an embodiment of the present disclosure;

[0028] Figure 11a This is a schematic diagram of a memory card according to an embodiment of the present disclosure;

[0029] Figure 11b This is a schematic diagram of a solid-state drive (SSD) according to an embodiment of the present disclosure. Detailed Implementation

[0030] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary implementations of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.

[0031] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0032] In the embodiments of this disclosure, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0033] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0034] In the development of NAND memory, early NAND memory chips mostly used single-level cells (SLC), meaning that one storage cell stores 1 bit of data. At this time, each storage cell has two states, specifically 0 and 1.

[0035] With the development of NAND memory, the storage cells of NAND memory chips have gradually evolved from single-level cells to multi-level cells (MLC), where one storage cell stores 2 bits of data. Then, triple-level cells (TLC) were introduced, where one storage cell stores 3 bits of data, and even quad-level cells (QLC), where one storage cell stores 4 bits of data. Correspondingly, the number of states of NAND memory chip storage cells has also increased from 2 to 4, 8, or even 16.

[0036] Taking TLC memory cell as an example, TLC memory cell has 1 erase state and 7 programming states. Its erase state is denoted as L0, and its programming states from the 1st state to the 7th state are denoted as L1, L2, L3, L4, L5, L6 and L7 respectively. It can be understood that the threshold voltage gradually increases from the L0 state to the L7 state.

[0037] Figure 1a and Figure 1b The method of programming a TLC using a one-step programming approach is shown. Specifically, for programming states L1 to L7, programming starts from the erase state L0, and each programming state is verified sequentially until all programming states are verified or the maximum programming pulse count is reached, at which point programming ends.

[0038] Table 1 shows the specific programming scheme. In the process of programming the TLC using the one-step programming method, multiple programming loops may be included. Each programming loop includes applying at least one programming pulse and applying a programming verification pulse (verify, V).

[0039] For example, in the first programming cycle, the L1 state memory cell to be programmed is verified. After the fifth programming cycle, the verification of the L1 state memory cell to be programmed ends. It can be understood that after the fifth programming cycle, that is, after the fifth programming verification pulse (V) is applied, the L1 state verification is successful and no further programming is required. L2 to L7 are similar and will not be described in detail.

[0040] Understandably, by executing multiple programming loop operations, the memory cells in the memory can be programmed from the L0 state to the L1, L2, L3, L4, L5, L6 and L7 states respectively.

[0041] Table 1

[0042]

[0043] The deeper the memory cell is erased, the smaller the threshold voltage of the L0 state, and the greater the difference between the threshold voltages of the L0 and L1 states. Using the above programming scheme, the memory cell to be programmed is programmed from the L0 state to the L1 to L7 states in one step. The data retention capability of the memory cells in the L1 to L7 states is poor, which leads to a wider distribution of the threshold voltage of the memory cells in the L1 to L7 states, and a worse read margin between two adjacent programming states.

[0044] The shallower the erase of the memory cell, the higher the threshold voltage of the L0 state. The threshold voltages of the L0 state and the L1 state are relatively close. Using the above programming scheme, the memory cell to be programmed is programmed from the L0 state to the L1 state to the L7 state in one step. The data retention capability of the memory cell from the L1 state to the L7 state is good. However, since the threshold voltages of the L0 state and the L1 state are relatively close, there may be overlap, which will lead to a deterioration in the read margin of the L0 state and the L1 state.

[0045] Furthermore, in the one-step programming scheme, programming pulses need to be applied to all unverified memory cells simultaneously each time. Only when a programmed memory cell is verified will a programming prohibition pulse be applied to the verified memory cell.

[0046] For example, in Table 1 above, in the first programming cycle, the first programming pulse is applied to the memory cells to be programmed in states L1 to L7 simultaneously. After the fifth programming cycle, the L1 state is verified. In the sixth programming cycle, the sixth programming pulse is applied to the memory cells to be programmed in states L2 to L7 simultaneously, and the memory cells in state L1 are disabled from programming.

[0047] Combining Table 1 and Figure 4a As shown, Figure 4a The solid black line to the right of L0 represents the threshold voltage distribution of the memory cell that is in L1 state after the first programming pulse is applied. When the second programming pulse is applied, a programming inhibit pulse is applied to the memory cell that is in L1 state. Figure 4a The black dashed line to the right of L0 represents the threshold voltage distribution of the memory cells to be programmed after the first programming pulse is applied, where the target state is L1 and has not yet reached L1, and the target states are L2 to L7. When the second programming pulse is applied, the memory cells to be programmed that have not reached L1 and the target states are L2 to L7 are programmed simultaneously.

[0048] It is understandable that, when the second programming pulse is applied, programming continues for the memory cells to be programmed that are in the L1 state but have not yet reached the L1 state, and those that are in the L2 to L7 states.

[0049] The problem with this programming scheme is that for memory cells that fail verification or have not yet undergone programming verification, programming pulses need to be applied continuously to program the memory cells to various programming states. This programming scheme results in a decrease in read margin between two adjacent programming states.

[0050] Furthermore, with this programming scheme, the memory cell to be programmed will experience a large fast charge loss after reaching the programming state, which leads to a wider threshold voltage distribution of the memory cell to be programmed in the programming state. In other words, the read margin of the memory cell to be programmed will be greatly reduced, which will further worsen the read margin between two adjacent programming states.

[0051] It should be noted that the above explanation uses TLC as an example, but it is not limited to this. For example, when programming QLC, the number of programming states increases to 15. As the number of programming states in the memory cell further increases, the read margin of the programming states in the memory further deteriorates.

[0052] In view of this, embodiments of the present disclosure provide a method for programming a memory. Figure 2 This is a flowchart illustrating a memory programming method according to an embodiment of the present disclosure. The memory includes programmable memory cells whose target states are state 1 to state L, as shown below. Figure 2 As shown, the programming method includes the following steps:

[0053] S110: Obtain the number of initial verification pulses for the x-th state of the programmable memory cell whose target state is x-th state; where x is a positive integer greater than 1 and less than or equal to L; L is a positive integer greater than 1.

[0054] S120: When the sequence number i of the i-th programming operation is greater than or equal to 1 and less than the first preset value of the x-th state, the i-th programming operation is performed on the memory unit to be programmed with the target state being the x-th state; where i is a positive integer;

[0055] S130: When i is greater than or equal to the first preset value of the x-th state and less than the number of initial verification pulses of the x-th state, when performing the i-th programming operation, the i-th programming prohibition operation is performed on the memory cell to be programmed with the target state being the x-th state.

[0056] For example, the memory may include a memory array composed of multiple memory cells. A memory cell may include a single-level cell storing 1 bit of data, a multi-level cell storing 2 bits of data, a three-level cell storing 3 bits of data, a four-level cell storing 4 bits of data, or a memory cell storing more than 10 bits of data. Taking TLC as an example, the highest programming state of the memory is the 7th state; therefore, the value of L is 7. Taking QLC as an example, the highest programming state of the memory is the 15th state; therefore, the value of L is 15.

[0057] In step S110, the number of initial verification pulses for the x-th state of the target programmable memory cell (target state x) can be obtained based on the information stored in the data register in the memory. It should be noted that the number of initial verification pulses for the x-th state and the number of initial verification pulses for the (x+1)-th state can be the same or different. Preferably, the number of initial verification pulses for the x-th state is less than the number of initial verification pulses for the (x+1)-th state, where x+1 is a positive integer less than or equal to L.

[0058] For example, taking TLC as an example, as shown in Table 1 above, the number of initial verification pulses for L2 state is 3, for L3 state it is 5, for L4 state it is 6, for L5 state it is 8, for L6 state it is 10, and for L7 state it is 13. This is merely an example to convey the present disclosure to those skilled in the art; however, the present disclosure is not limited thereto. The number of initial verification pulses for each target state in the memory can be determined according to the step size of the programming pulses, and the present disclosure does not impose any limitations here.

[0059] In S120 and S130, before verifying the x-th state, it can be determined whether to perform a programming operation or a programming prohibition operation on the memory cell whose target state is the x-th state, based on the relationship between the sequence number i of the i-th programming operation and the first preset value of the x-th state and the number of the x-th state's initial verification pulses.

[0060] Here, the first preset value of the x-th state can be the programming pulse number corresponding to the start of the programming prohibition operation on the x-th state's programmable memory unit before the initial verification of the x-th state's programmable memory unit.

[0061] Specifically, when the sequence number i of the current programming operation is less than the first preset value of the x-th state, a programming operation is performed on the memory cell to be programmed when the target state is the x-th state. When the sequence number i of the current programming operation is greater than or equal to the first preset value of the x-th state, and less than the number of initial verification pulses of the x-th state, a programming prohibition operation is performed on the memory cell to be programmed when the target state is the x-th state.

[0062] It should be noted that the first preset value of the x-th state and the first preset value of the (x+1)-th state may be the same or different.

[0063] Performing a programming operation on the memory cell to be programmed, whose target state is the x-th state, includes: turning on the upper select transistor of the selected memory string, turning off the lower select transistor of the selected memory string, applying a bit line programming voltage to the bit lines coupled to the selected memory string, and applying a word line programming voltage to the word lines coupled to the memory cell to be programmed, whose target state is the x-th state. Here, the selected memory string includes the memory cell to be programmed, whose target state is the x-th state.

[0064] Perform a programming disable operation on the programmable memory cell whose target state is the x-th state, including: turning off the upper select transistor of the unselected memory string, turning off the lower select transistor of the unselected memory string, and applying a bit line programming disable voltage (greater than the bit line programming voltage) to the bit line coupled to the unselected memory string. Here, the unselected memory string includes the programmable memory cell whose target state is the x-th state.

[0065] In this embodiment of the disclosure, by obtaining the number of initial verification pulses for each target state, and based on the relationship between the sequence number of the programming operation and the first preset value of each target state and the number of initial verification pulses for each target state, programming operations are performed on the memory units to be programmed for a portion of the target states, while programming prohibition operations are performed on the memory units to be programmed for another portion of the target states. This allows programming operations to continue on the memory units to be programmed for the portion of the target states, while programming operations on the memory units to be programmed for the other portion of the target states are prohibited, thereby increasing the read margin between the memory units to be programmed for the portion of the target states and the memory units to be programmed for the other portion of the target states.

[0066] Furthermore, by only programming some of the target states of the memory cells to be programmed, the charge loss of the memory cells to be programmed after reaching the programmed state is small, which can make the threshold voltage distribution of the memory cells to be programmed in the programmed state narrower. This is beneficial to increase the read margin of each target state in the memory, reduce the probability of memory misread, and thus improve the performance of the memory.

[0067] In some embodiments, the first preset value corresponding to each target state is 2. The following will use TLC as an example, combined with... Figure 3 Please refer to Table 2 for further explanation.

[0068] For example, the number of L2 state initial verification pulses n for the target L2 state of the memory cell to be programmed is 3. When performing the second programming operation, the second programming prohibition operation is performed on the target L2 state of the memory cell to be programmed.

[0069] For example, if the number of L3 state initial verification pulses n for the target L3 state of the memory cell to be programmed is 5, a programming prohibition operation is performed on the target L3 state of the memory cell during the execution of the second programming operation to the fourth programming operation. For example, when performing the fourth programming operation, a fourth programming prohibition operation is performed on the target L3 state of the memory cell to be programmed.

[0070] For example, if the number of L4 state initial verification pulses n for the target L4 state of the memory cell to be programmed is 6, a programming prohibition operation is performed on the target L4 state of the memory cell during the execution of the second programming operation to the fifth programming operation. For example, when performing the fifth programming operation, a fifth programming prohibition operation is performed on the target L4 state of the memory cell to be programmed.

[0071] For example, if the number of L5 state initial verification pulses n for the target L5 state of the memory cell to be programmed is 8, then during the execution of the second to the seventh programming operations, a programming prohibition operation is performed on the target L5 state of the memory cell to be programmed. For example, during the execution of the seventh programming operation, a seventh programming prohibition operation is performed on the target L5 state of the memory cell to be programmed.

[0072] For example, the number of L6 state start verification pulses n for the target L6 state of the memory cell to be programmed is 10. During the execution of the second programming operation to the ninth programming operation, a programming prohibition operation is performed on the target L6 state of the memory cell to be programmed. For example, when performing the ninth programming operation, a ninth programming prohibition operation is performed on the target L6 state of the memory cell to be programmed.

[0073] For example, if the number of L7 state initial verification pulses n for the target L7 state of the memory cell to be programmed is 13, a programming prohibition operation is performed on the target L7 state of the memory cell during the execution of the second programming operation to the twelfth programming operation. For example, when performing the twelfth programming operation, a twelfth programming prohibition operation is performed on the target L7 state of the memory cell to be programmed.

[0074] In some embodiments, S120 includes: when i equals 1, performing a first programming operation on the memory cell to be programmed with the target state being the first state; the method further includes: performing a first programming operation on the memory cell to be programmed with the target state being the second state to the Lth state.

[0075] It should be noted that when i equals 1, i.e., when the first programming pulse is applied, since the signal value of the first programming pulse is usually small, it will not overprogram the memory. Therefore, the first programming pulse can program all memory cells in states L1 to L7 without affecting the read margin. After applying the first programming pulse, the first programming verification pulse (i.e., verifying L1) is applied to the memory cells in state L1.

[0076] Table 2

[0077]

[0078] Combine Table 2 and Figure 4b As shown, Figure 4b The solid black line to the right of L0 represents the threshold voltage distribution of the memory cells that are in the L1 state after the first programming pulse is applied. When the second programming pulse is applied, programming prohibition pulses are applied to the memory cells that are in the L1 state and have reached the L1 state, as well as the memory cells that are in the L2 to L7 states. Figure 4bThe black dashed line to the right of L0 represents the threshold voltage distribution of the memory cell to be programmed after the first programming pulse is applied, where the target state is L1 and the L1 state has not yet been reached. When the second programming pulse is applied, the memory cell to be programmed is programmed while the target state is L1 and the L1 state has not yet been reached.

[0079] It is understandable that when the second programming pulse is applied, programming is performed on the memory cells whose target state is L1 and have not yet reached L1, while programming is disabled on the memory cells whose target states are L2 to L7. This avoids programming all memory cells whose target state is L1 and have not yet reached L1, as well as those whose target states are L2 to L7. This helps to reduce the distribution width of the threshold voltage of the memory cells whose target state is L1, thereby increasing the read margin between L1 and L2 states.

[0080] Furthermore, programming is only performed on memory cells whose target state is L1 and which have not yet reached L1 state. After reaching L1 state, the charge loss of the memory cells to be programmed is small, and the threshold voltage distribution of memory cells in L1 state is narrow, which is beneficial to increase the read margin between L0 state and L1 state as well as the read margin between L1 state and L2 state.

[0081] Combine Table 2 and Figure 4c As shown, Figure 4c The solid black line to the right of L0 represents the threshold voltage distribution of memory cells that reach the L1 state and memory cells that reach the L2 state after the application of the 6th programming pulse. When the 7th programming pulse is applied, a programming inhibit pulse is applied to the memory cells that reach the L1 state, the memory cells that reach the L2 state, and the memory cells that are to be programmed and whose target states are L5 to L7. Figure 4b The black dashed line to the right of L0 represents the threshold voltage distribution of the memory cells to be programmed after the application of the 6th programming pulse, which are in the L2 state but have not reached the L2 state, as well as the L3 and L4 states. When the 7th programming pulse is applied, the memory cells to be programmed are programmed in the L2 state but have not reached the L2 state, as well as the L3 and L4 states.

[0082] It is understandable that when the 7th programming pulse is applied, programming is performed on the memory cells that have not reached the L2 state, while programming is prohibited on the memory cells that are in the L5 to L7 states. This avoids programming the memory cells that are in the L2 state and have not reached the L2 state, as well as the memory cells that are in the L5 to L7 states. This helps to narrow the threshold voltage distribution width of the memory cells that are in the L2 state, thereby increasing the read margin between the L1 and L2 states and the read margin between the L2 and L3 states.

[0083] It needs to be emphasized that, Figures 4a to 4c The solid line below L0 represents the voltage distribution of the memory cells to be programmed in the erase state (i.e., L0) for target states L1 to L7, which will not be described further hereafter. In this embodiment, by setting the first preset value of each target state (Lx) to 2, that is, from the second programming pulse until the number of initial verification pulses for each target state is reached, a programming prohibition pulse is applied to the memory cell to be programmed in that target state. In this way, the number of target states involved in each programming can be reduced, which is beneficial to narrowing the threshold voltage distribution width of each target state in the memory, thereby reducing the read margin of each target state in the memory.

[0084] In some embodiments, the first preset value corresponding to each target state is different, and the above method further includes: obtaining the x-th difference between the x-th initial verification pulse number and the second preset value; wherein, the second preset value is a positive integer; when the x-th difference is less than or equal to 1, the first preset value of the x-th state is determined to be equal to 2; when the x-th difference is greater than 1, the value of the x-th difference is determined to be equal to the first preset value of the x-th state.

[0085] The following will use TLC, where k takes the value of 4, and combine it with... Figure 5 Please refer to Table 3 for further explanation. Figure 5 In this context, k represents the second preset value. It should be understood that k can also be any other positive integer.

[0086] For example, when the number of L2 state initial verification pulses n of the target state L2 state to be programmed memory cell is 3, nk equals -1, that is, the second difference is -1, and the first preset value of the target state L2 state to be programmed memory cell is determined to be equal to 2. When performing the second programming operation, the second programming prohibition operation is performed on the target state L2 state to be programmed memory cell.

[0087] For example, when the number of L3 state initial verification pulses n for the target L3 state of the programmable memory cell is 5, nk equals 1, that is, the third difference is 1. The first preset value for determining that the target L3 state of the programmable memory cell is equal to 2 is then applied. During the execution of the second to fourth programming operations, a programming prohibition operation is performed on the target L3 state of the programmable memory cell. For example, during the execution of the fourth programming operation, a fourth programming prohibition operation is performed on the target L3 state of the programmable memory cell.

[0088] For example, when the number of L4 state initial verification pulses n for the target L4 state of the programmable memory cell is 6, nk equals 2, that is, the fourth difference is 2. The first preset value for determining that the target L4 state of the programmable memory cell is equal to 2 is then applied. During the execution of the second to fifth programming operations, a programming prohibition operation is performed on the target L4 state of the programmable memory cell. For example, during the execution of the fifth programming operation, a fifth programming prohibition operation is performed on the target L4 state of the programmable memory cell.

[0089] For example, when the number of L5 state initial verification pulses n for the target L5 state of the programmable memory cell is 8, nk equals 4, that is, the fifth difference is 4. The first preset value for determining the target L5 state of the programmable memory cell is equal to 4. The second and third programming operations are performed on the target L5 state of the programmable memory cell. During the execution of the fourth to seventh programming operations, a programming prohibition operation is performed on the target L5 state of the programmable memory cell. For example, during the execution of the seventh programming operation, a seventh programming prohibition operation is performed on the target L5 state of the programmable memory cell.

[0090] For example, when the number of L6 state initial verification pulses n for the target L6 state of the programmable memory cell is 10, nk equals 6, that is, the 6th difference is 6. The first preset value for the target L6 state of the programmable memory cell is determined to be equal to 6. The second to fifth programming operations are performed on the target L6 state of the programmable memory cell. During the execution of the sixth to ninth programming operations, a programming prohibition operation is performed on the target L6 state of the programmable memory cell. For example, during the execution of the ninth programming operation, a ninth programming prohibition operation is performed on the target L6 state of the programmable memory cell.

[0091] For example, when the number of L7 state initial verification pulses n for the target L7 state of the programmable memory cell is 13, nk equals 9, that is, the 7th difference is 9. The first preset value for the target L7 state of the programmable memory cell is determined to be equal to 9. The second to eighth programming operations are performed on the target L7 state of the programmable memory cell. During the execution of the ninth to twelfth programming operations, a programming prohibition operation is performed on the target L7 state of the programmable memory cell. For example, during the execution of the twelfth programming operation, a twelfth programming prohibition operation is performed on the target L7 state of the programmable memory cell.

[0092] It should be noted that when i equals 1, i.e., when the first programming pulse is applied, since the signal value of the first programming pulse is usually small, it will not overprogram the memory. Therefore, the first programming pulse can program all memory cells in states L1 to L7 without affecting the read margin. After applying the first programming pulse, the first programming verification pulse (i.e., verifying L1) is applied to the memory cells in state L1.

[0093] In some embodiments, the second preset value is greater than or equal to 1 and less than or equal to 5. The second preset value can be any positive integer from 1 to 5. In practical applications, the second preset value can be selected according to the actual read margin requirements and memory performance, and this disclosure does not impose any limitations on it.

[0094] Table 3

[0095]

[0096] In this embodiment of the disclosure, when the value of the first preset value corresponding to each target state is different, after obtaining the number of initial verification pulses for each target state, if the difference between the number of initial verification pulses for each target state and the current programming pulse number is greater than a second preset value (i.e., k), a programming operation can be performed on the memory unit to be programmed for that target state; if the difference between the number of initial verification pulses for each target state and the current programming pulse number is less than or equal to the second preset value, a programming prohibition operation can be performed on the memory unit to be programmed for that target state. It is understood that in this embodiment of the disclosure, the first preset value of the memory unit to be programmed for each target state can be determined according to the number of initial verification pulses for each target state and the second preset value, which can improve the flexibility of the programming method.

[0097] Furthermore, for storage cells with the same target state (e.g., the xth state), in this embodiment of the present disclosure, when i is greater than or equal to 1 and less than a first preset value of the xth state, the i-th programming operation is performed on the storage cell to be programmed with the target state being the xth state, while when i is greater than or equal to the first preset value of the xth state, the storage cell to be programmed with the target state being the xth state is not programmed. This can reduce programming interference and program the storage cells in advance, thereby improving programming efficiency.

[0098] In some embodiments, the method further includes: obtaining the xj-th initial verification pulse number for verifying the programmable memory cell whose target state is the xj-th state; wherein xj is greater than 1 and less than L, and j is a positive integer; and determining that the value of the xj-th initial verification pulse number is equal to a first preset value of the x-th state.

[0099] The following will use TLC, where j takes the value of 2, and combine it with... Figure 6 Please refer to Table 4 for further explanation. Figure 6 In this context, m represents the number of initial verification pulses for the xj-th state of the target memory cell to be verified. It should be understood that the value of j can also be other positive integers.

[0100] For example, when the number of L4 state initial verification pulses n for the target L4 state programmable memory cell is 6, xj equals 2. The number of L2 state initial verification pulses m for the target L2 state programmable memory cell is obtained as 3. The first preset value for the target L4 state programmable memory cell is determined to be 3. During the execution of the first and second programming operations, the first and second programming operations are performed on the target L4 state programmable memory cell, respectively. During the execution of the third to fifth programming operations, a programming prohibition operation is performed on the target L4 state programmable memory cell. For example, during the execution of the fifth programming operation, a fifth programming prohibition operation is performed on the target L4 state programmable memory cell.

[0101] When the number of L5-state initial verification pulses n for the target L5-state programmable memory cell is 8, xj equals 3. The number of L3-state initial verification pulses m for the target L3-state programmable memory cell is obtained as 5. The first preset value for the target L5-state programmable memory cell is determined to be 5. During the execution of the second to fourth programming operations, the second, third, and fourth programming operations are performed on the target L5-state programmable memory cell, respectively. During the execution of the fifth to seventh programming operations, a programming prohibition operation is performed on the target L5-state programmable memory cell. For example, during the execution of the seventh programming operation, a seventh programming prohibition operation is performed on the target L5-state programmable memory cell.

[0102] For example, when the number of L6-state initial verification pulses n for the target L6-state programmable memory cell is 10, xj equals 4. The number of L4-state initial verification pulses m for the target L4-state programmable memory cell is obtained as 6. The first preset value for the target L6-state programmable memory cell is determined to be 6. During the execution of the second to fifth programming operations, the second, third, fourth, and fifth programming operations are performed on the target L6-state programmable memory cell, respectively. During the execution of the sixth to ninth programming operations, a programming prohibition operation is performed on the target L6-state programmable memory cell. For example, during the execution of the ninth programming operation, a ninth programming prohibition operation is performed on the target L6-state programmable memory cell.

[0103] For example, when the number of L7 state initial verification pulses n for the target L7 state programmable memory cell is 13, xj equals 5. The number of L5 state initial verification pulses m for the target L5 state programmable memory cell is obtained as 8. The first preset value for the target L7 state programmable memory cell is determined to be 8. During the execution of the second to seventh programming operations, the second, third, fourth, fifth, sixth, and seventh programming operations are performed on the target L7 state programmable memory cell, respectively. During the execution of the eighth to twelfth programming operations, a programming prohibition operation is performed on the target L7 state programmable memory cell. For example, during the execution of the twelfth programming operation, a twelfth programming prohibition operation is performed on the target L7 state programmable memory cell.

[0104] It should be noted that when i equals 1, i.e., when the first programming pulse is applied, since the signal value of the first programming pulse is usually small, it will not overprogram the memory. Therefore, the first programming pulse can program all memory cells in states L1 to L7 without affecting the read margin. After applying the first programming pulse, the first programming verification pulse (i.e., verifying L1) is applied to the memory cells in state L1.

[0105] Table 4

[0106]

[0107] The following will use TLC, where j takes the value of 3, and combine it with... Figure 6 Please refer to Table 5 for further explanation. Figure 6 In this context, m represents the number of initial verification pulses for the xj-th state of the target memory cell to be verified. It should be understood that the value of j can also be other positive integers.

[0108] For example, when the number of initial verification pulses n for the target L4 state of the programmable memory cell is 6, xj equals 1. The number of initial verification pulses m for the target L1 state of the programmable memory cell is obtained as 1. The first preset value for the target L4 state of the programmable memory cell is determined to be equal to 1. During the execution of the second to fifth programming operations, a programming prohibition operation is performed on the target L4 state of the programmable memory cell. For example, during the execution of the fifth programming operation, a fifth programming prohibition operation is performed on the target L4 state of the programmable memory cell.

[0109] For example, when the number of L5 state initial verification pulses n for the target L5 state programmable memory cell is 8, xj equals 2. The number of L2 state initial verification pulses m for the target L2 state programmable memory cell is obtained as 3. The first preset value for the target L5 state programmable memory cell is determined to be 3. A second programming operation is performed on the target L5 state programmable memory cell. During the execution of the third to seventh programming operations, a programming prohibition operation is performed on the target L5 state programmable memory cell. For example, during the execution of the seventh programming operation, a seventh programming prohibition operation is performed on the target L5 state programmable memory cell.

[0110] For example, when the number of L6-state initial verification pulses n for the target L6-state programmable memory cell is 10, xj equals 3. The number of L3-state initial verification pulses m for the target L3-state programmable memory cell is obtained as 5. The first preset value for the target L6-state programmable memory cell is determined to be 5. During the execution of the second to fourth programming operations, the second, third, and fourth programming operations are performed on the target L6-state programmable memory cell, respectively. During the execution of the fifth to ninth programming operations, a programming prohibition operation is performed on the target L6-state programmable memory cell. For example, during the ninth programming operation, a ninth programming prohibition operation is performed on the target L6-state programmable memory cell.

[0111] For example, when the number of L7 state initial verification pulses n for the target L7 state programmable memory cell is 13, xj equals 4. The number of L4 state initial verification pulses m for the target L4 state programmable memory cell is obtained as 6. The first preset value for the target L7 state programmable memory cell is determined to be 6. During the execution of the second to fifth programming operations, the second, third, fourth, and fifth programming operations are performed on the target L7 state programmable memory cell, respectively. During the execution of the sixth to twelfth programming operations, a programming prohibition operation is performed on the target L7 state programmable memory cell. For example, during the execution of the twelfth programming operation, a twelfth programming prohibition operation is performed on the target L7 state programmable memory cell.

[0112] It should be noted that when i equals 1, i.e., when the first programming pulse is applied, since the signal value of the first programming pulse is usually small, it will not overprogram the memory. Therefore, the first programming pulse can program all memory cells in states L1 to L7 without affecting the read margin. After applying the first programming pulse, the first programming verification pulse (i.e., verifying L1) is applied to the memory cells in state L1.

[0113] In some embodiments, the value of j is determined based on the number of target states in the memory. For example, for TLC, the number of target states is 7 (i.e., L = 7), and the value of j is any positive integer from 1 to 5. For QLC, the number of target states is 15 (i.e., L = 15), and the value of j is any positive integer from 1 to 10. In practical applications, the value of j can be selected according to the actual read margin requirements and memory performance, and this disclosure does not impose any limitations.

[0114] Table 5

[0115]

[0116] It is understood that in this embodiment of the present disclosure, by obtaining the number of initial verification pulses of the target low-state programmable memory cell and using the number of initial verification pulses of the target low-state programmable memory cell as the first preset value of the high state, when the programming verification operation is started on the target low-state programmable memory cell, the programming prohibition operation is started on the high-state programmable memory cell. In this way, the low-state programmable memory cell and the high-state programmable memory cell can be programmed separately, so that the threshold voltage distribution of each target state memory cell in the memory is narrower, and the read margin of each target state in the memory is increased.

[0117] In some embodiments, the above method further includes:

[0118] When i is greater than or equal to the number of initial verification pulses in the x-th state, the i-th programming operation is performed on the memory cell to be programmed when the target state is the x-th state;

[0119] After performing the i-th programming operation, perform the i-th programming verification operation to obtain the i-th verification result;

[0120] For the i-th verification result indicating that programming has passed and the target state is the x-th state, perform the (i+1)-th programming prohibition operation on the memory cell to be programmed;

[0121] The i-th verification result indicates that the programming failed and the target state is the x-th state of the memory cell to be programmed, the i+1-th programming operation is performed.

[0122] It is understandable that, based on the i-th verification result, it can be determined whether to perform the (i+1)-th programming prohibition operation or the (i+1)-th programming operation on the memory cell to be programmed, whose target state is the X-th state. It is also understandable that, when the i-th verification result indicates that programming has passed, the memory cell to be programmed, whose target state is the X-th state, has reached the X-th state after the i-th programming operation.

[0123] For example, when the i-th verification result indicates that the programming of the memory cell to be programmed is in the x-th state, during the i+1-th programming operation, the i+1-th programming prohibition operation is performed on these memory cells that have reached the x-th state after the i-th programming operation and whose target state is the x-th state, to prevent over-programming. When the i-th verification result indicates that the programming of the memory cell to be programmed is in the x-th state is unsuccessful, programming needs to continue for these memory cells that have not reached the x-th state after the i-th programming operation and whose target state is the x-th state, that is, the i+1-th programming operation is performed on these memory cells that have not reached the x-th state after the i-th programming operation and whose target state is the x-th state.

[0124] The i-th verification result is used to represent the programming result of the memory cell to be programmed after performing the i-th programming operation. The i-th verification result may include at least one of the following: a first type of indication information indicating whether each verified memory cell has been successfully programmed; a second type of indication information indicating whether each verified memory cell has failed to be programmed; or a third type of indication information indicating the number of memory cells that have reached the target programming state.

[0125] The i-th verification result includes at least a verification sub-result of programming verification of the x-th state. Here, the verification sub-result of programming verification of the x-th state is used to represent the result obtained by programming verification of the memory cell whose target state is x-th during the i-th programming verification operation. The verification sub-result of the x-th state may include at least one of the following: a first type of indication information indicating whether each memory cell whose target state is x-th has been successfully programmed; a second type of indication information indicating whether each memory cell whose target state is x-th has failed to be programmed; and a third type of indication information indicating the number of memory cells that have reached the target state x-th.

[0126] For example, binary encoding can be used to indicate whether the memory cell has been successfully programmed. For instance, 0 can represent successful programming and 1 can represent unsuccessful programming; conversely, 1 can represent successful programming and 0 can represent unsuccessful programming. In implementation, those skilled in the art can choose an appropriate method to represent whether the memory cell has been successfully programmed based on the actual situation, and this disclosure does not limit this approach.

[0127] In some embodiments, performing the i-th programming operation on a programmable memory cell whose target state is the x-th state includes: applying the i-th bit line programming voltage to the bit line coupled to the programmable memory cell whose target state is the x-th state;

[0128] Performing an (i+1)th programming disable operation on the memory cell to be programmed, whose i-th verification result indicates that programming has passed and whose target state is the x-th state, includes: applying an (i+1)th bit-line programming disable voltage to the bit line coupled to the memory cell to be programmed, whose i-th verification result indicates that programming has passed and whose target state is the x-th state; wherein the (i+1)th bit-line programming disable voltage is greater than the i-th bit-line programming voltage;

[0129] Performing the (i+1)th programming operation on the memory cell to be programmed, whose programming failed as indicated by the i-th verification result and whose target state is the x-th state, includes: applying the (i+1)th bit line programming voltage to the bit line coupled to the memory cell to be programmed, whose programming failed as indicated by the i-th verification result and whose target state is the x-th state; wherein the (i+1)th bit line programming voltage is greater than or equal to the i-th bit line programming voltage; and the (i+1)th bit line programming voltage is less than the (i+1)th bit line programming disable voltage.

[0130] For example, the i-th bit line programming voltage is applied to the bit line of the memory cell to be programmed when the target state is the x-th state, so as to program the memory cell to be programmed when the target state is the X-th state.

[0131] The (i+1)th bit line programming disable voltage is applied to the bit line of the memory cell to be programmed, where the i-th verification result indicates that programming has passed and the target state is the x-th state, so as to disable programming of the memory cell to be programmed, where the i-th verification result indicates that programming has passed and the target state is the x-th state.

[0132] For example, referring to Table 6, when i equals 5, i.e., equal to the number of L3-state initial verification pulses of the target L3-state memory cell to be programmed, a fifth bit-line programming voltage is applied to the bit line coupled to the target L3-state memory cell to be programmed. When the fifth verification result indicates that programming of the target L3-state memory cell to be programmed has failed, a sixth bit-line programming voltage is applied to the bit line coupled to the target L3-state memory cell to be programmed, and the sixth bit-line programming voltage is greater than or equal to the fifth bit-line programming voltage. In Table 6, Vdd represents the bit-line programming disable voltage applied at a high level to the bit line coupled to the target L3-state memory cell to be programmed.

[0133] For example, referring to Table 6, when the 8th verification result indicates that programming of the target memory cell in the L3 state has passed, when performing the 9th programming operation to program the memory cell in the higher target state, a programming inhibit voltage (Vdd) may be applied to the bit line of the memory cell coupled to the L3 state to prevent overprogramming of the memory cell already programmed to the L3 state.

[0134] Table 6

[0135]

[0136] It is understood that, in the embodiments of this disclosure, after the initial verification pulse count of the target state is reached, a programming operation or a soft programming operation can be performed on the memory cell of the target state, that is, different levels are applied to the bit line of the memory cell to be programmed coupled to the target state. Specifically, the level applied to the bit line next time can be determined according to the previous verification result.

[0137] For example, when the verification result indicates a voltage close to the threshold voltage of the target state, a level greater than 0V and less than Vdd can be applied to the bit line of the memory cell to be programmed, coupled to the target state, to perform a soft programming operation on the memory cell of the target state. When the verification result indicates a voltage much lower than the threshold voltage of the target state, a level of 0V can be applied to the bit line of the memory cell to be programmed, coupled to the target state, to perform a programming operation on the memory cell of the target state.

[0138] This reduces the distribution width of the threshold voltage for each target state, which is beneficial for increasing the read margin of each target state in the memory.

[0139] In some embodiments, when the sequence number i of the i-th programming operation is greater than or equal to 1 and less than a first preset value of the x-th state, the i-th programming operation is performed on the memory cell to be programmed with the target state being the x-th state, including: applying the i-th bit line programming voltage to the bit line coupled to the memory cell to be programmed with the target state being the x-th state;

[0140] When i is greater than or equal to the first preset value of the x-th state and less than the number of initial verification pulses of the x-th state, when performing the i-th programming operation, the i-th programming prohibition operation is performed on the memory cell to be programmed with the target state being the x-th state, including: applying the i-th bit line programming prohibition voltage to the bit line coupled to the memory cell to be programmed with the target state being the x-th state; wherein the i-th bit line programming voltage is less than the i-th bit line programming prohibition voltage.

[0141] For example, referring to Table 3, when performing the second programming operation, a second bit line programming voltage, i.e. 0V, is applied to the bit lines of the memory cells to be programmed that are coupled to the target states L1, L5 to L7, and a second bit line programming disable voltage, i.e. Vdd, is applied to the bit lines of the memory cells to be programmed that are coupled to the target states L2 to L4, where Vdd is greater than 0V.

[0142] Figure 7 This is a schematic diagram illustrating a memory 100 according to an embodiment of the present disclosure. (Refer to...) Figure 7 As shown, the memory 100 includes:

[0143] The storage cell array 101 includes a plurality of programmable storage cells 106 whose target states are from the first state to the Lth state;

[0144] Multiple word lines 118 are coupled to multiple programmable memory units 106 respectively;

[0145] Multiple bit lines 116 are coupled to multiple programmable memory cells 106 respectively;

[0146] The peripheral circuit 102 is coupled to a plurality of word lines 118 and a plurality of bit lines 116 and is configured to perform the programming method of any of the above embodiments on a selected row of memory cells among a plurality of memory cells to be programmed 106.

[0147] The memory cell array 101 may be a NAND flash memory cell array, wherein the memory cell array 101 is provided in the form of an array of NAND memory strings 108, each NAND memory string 108 extending vertically. In some embodiments, each NAND memory string 108 includes a plurality of memory cells 106 coupled in series and stacked vertically. Each memory cell 106 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 106. Each memory cell 106 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0148] In some implementations, each storage cell 106 is a single-level cell having two possible storage states and thus being able to store one bit of data. For example, a first storage state "0" may correspond to a first voltage range, and a second storage state "1" may correspond to a second voltage range.

[0149] In some implementations, each storage cell 106 is a cell capable of storing more than a single bit of data in more than four storage states. For example, it may store two bits per cell (also known as a multi-level cell), three bits per cell (also known as a three-level cell), or four bits per cell (also known as a four-level cell). Each multi-level cell may be programmed to take a range of possible nominal storage values. In one example, if each multi-level cell stores two bits of data, the multi-level cell may be programmed to take one of three possible programming levels from the erase state by writing one of the three possible nominal storage values ​​to the cell. A fourth nominal storage value may be used for the erase state.

[0150] like Figure 7 As shown, each NAND memory string 108 may include a source select transistor (SST) 110 at its source end and a drain select transistor (DST) 112 at its drain end. The source select transistor 110 and the drain select transistor 112 may be configured to activate the selected NAND memory string 108 (column of the array) during read and program operations.

[0151] In some implementations, the sources of NAND memory strings 108 in the same block 104 are coupled through the same source line (SL) 114 (e.g., common SL). In other words, according to some implementations, all NAND memory strings 108 in the same block 104 have an array common source (ACS).

[0152] According to some implementations, the drain select transistor 112 of each NAND memory string 108 is coupled to a corresponding bit line 116, and data can be read from or written to the bit line 116 via an output bus (not shown).

[0153] In some embodiments, each NAND flash memory string 108 is configured to apply a select voltage (e.g., higher than the threshold voltage of the drain select transistor 112) or a deselect voltage (e.g., 0V) to the corresponding drain select gate via one or more drain select gate lines 111, where the select voltage is used to turn on the drain select transistor 112 and the deselect voltage is used to turn off the drain select transistor 112. And / or, in some embodiments, each NAND flash memory string 108 is configured to apply a select voltage (e.g., higher than the threshold voltage of the source select transistor 110) or a deselect voltage (e.g., 0V) to the corresponding source select gate via one or more source select gate lines 115, where the select voltage is used to turn on the source select transistor 110 and the deselect voltage is used to turn off the source select transistor 110.

[0154] like Figure 7 As shown, the NAND storage string 108 can be organized into multiple blocks 104, each of which can have a common source line 114 (e.g., coupled to ground). In some implementations, each block 104 is the basic data unit for an erase operation, i.e., all storage cells 106 on the same block 104 are erased simultaneously.

[0155] It should be understood that, in some examples, erasure operations can be performed at the half-block level, at the quarter-block level, or at any level with any suitable number of blocks or any suitable fraction of blocks. Memory cells 106 of adjacent NAND memory strings 108 can be coupled via word lines 118, which select which row of memory cells 106 is affected by read and program operations.

[0156] In some implementations, each word line 118 may correspond to a memory page 120. The size of a memory page 120, measured in bits, may be related to the number of NAND memory strings 108 coupled by word lines 118 in a block 104. Each word line 118 may include multiple control gates (gate electrodes) and gate lines coupling the control gates at each memory cell 106 in the corresponding memory page 120. It is understood that a memory cell row is a plurality of memory cells 106 located in the same memory page 120.

[0157] Figure 8 This is a cross-sectional view of a NAND storage string 108 according to an embodiment of the present disclosure. Figure 8 As shown, the NAND memory string 108 can extend vertically through the memory stack layer 204 above the substrate 202. The substrate 202 can include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0158] The memory stack layer 204 may include alternating gate conductive layers 206 and gate dielectric layers 208. The number of pairs of gate conductive layers 206 and gate dielectric layers 208 in the memory stack layer 204 determines the number of memory cells 106 in the memory cell array 101.

[0159] The gate conductive layer 206 may include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer 206 may include a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 206 may include a doped polysilicon layer. Each gate conductive layer 206 may include a control gate surrounding the memory cell 106 and may extend laterally at the top of the memory stack 204 as a drain select gate line 111, at the bottom of the memory stack 204 as a source select gate line 115, or between the drain select gate line 111 and the source select gate line 115 as a word line 118.

[0160] It should be understood that, despite Figure 8 Additional components, not shown, but which may form the memory cell array 101, include, but are not limited to, gate line gaps / source contacts, local contacts, interconnect layers, etc.

[0161] Return to reference Figure 7The peripheral circuitry 102 can be coupled to the memory cell array 101 via bit line 116, word line 118, source line 114, source select gate line 115, and drain select gate line 111. The peripheral circuitry 102 can include any suitable analog, digital, and mixed-signal circuitry to facilitate the operation of the memory cell array 101 by applying voltage and / or current signals to each target memory cell 106 and sensing voltage and / or current signals from each target memory cell 106 via bit line 116, word line 118, source line 114, source select gate line 115, and drain select gate line 111.

[0162] The peripheral circuit 102 may include various peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 9 An exemplary peripheral circuit 102 is shown, which includes a page buffer / sensor amplifier 304, a column decoder / bit line (BL) driver 306, a row decoder / word line (WL) driver 308, a voltage generator 310, a control logic unit 312, a register 314, an interface 316, and a data bus 318. It should be understood that in some examples, additional components may be included. Figure 9 Additional peripheral circuitry not shown.

[0163] Page buffer / sensor amplifier 304 can be configured to read data from and program (write) data to memory cell array 101 according to control signals from control logic unit 312. In one example, page buffer / sensor amplifier 304 can store a page of programming data (write data) to be programmed into a memory page 120 of memory cell array 101. In another example, page buffer / sensor amplifier 304 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 106 coupled to selected word line 118. In yet another example, page buffer / sensor amplifier 304 can also sense a low-power signal from bit line 116 representing a data bit stored in memory cell 106 and amplify a small voltage swing to a recognizable logic level during read operations. Column decoder / bit line driver 306 can be configured to be controlled by control logic unit 312 and select one or more NAND memory strings 108 by applying a bit line voltage generated from voltage generator 310.

[0164] The line decoder / word line driver 308 can be configured to be controlled by the control logic unit 312 and to select / deselect word lines 118 of the selection block 104. The line decoder / word line driver 308 can also be configured to use word line voltages (V) generated from the voltage generator 310. WLThe line decoder / word line driver 308 can also select / deselect and drive the source select gate 115 and the drain select gate 111. As described in detail below, the line decoder / word line driver 308 is configured to perform an erase operation on memory cells 106 coupled to one or more selected word lines 118. The voltage generator 310 can be configured to be controlled by the control logic unit 312 and generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 101.

[0165] Control logic unit 312 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 314 can be coupled to control logic unit 312 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 316 can be coupled to control logic unit 312 and acts as a control buffer to buffer control commands received from the host (not shown) and relay them to control logic unit 312, as well as to buffer status information received from control logic unit 312 and relay it to the host. Interface 316 can also be coupled to column decoder / bit line driver 306 via data bus 318 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory cell array 101.

[0166] It should be emphasized that the peripheral circuit 102 is configured to perform the programming operations provided in the embodiments of this disclosure on a selected memory cell row among a plurality of memory cell rows.

[0167] Figure 10 This is a schematic diagram illustrating a memory system 400 according to an embodiment of the present disclosure. (Refer to...) Figure 10 As shown, the memory system 400 includes:

[0168] One or more memory 100 as described in the above embodiments;

[0169] Memory controller 406 is coupled to memory 100 and configured to control memory 100.

[0170] System 400 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein.

[0171] like Figure 10 As shown, system 400 may include a host 408 and a storage subsystem 402, the storage subsystem 402 having one or more memories 100, and the storage subsystem also including a memory controller 406. The host 408 may be a processor of an electronic device (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host 408 may be configured to send data to the memory 100. Alternatively, the host 408 may be configured to receive data from the memory 100.

[0172] Memory 100 can be any memory device disclosed in this disclosure. Memory 100 (e.g., a NAND flash memory device (e.g., a three-dimensional (3D) NAND flash memory device)) can have reduced leakage current from drive transistors (e.g., string drivers) coupled to unselected word lines during erase operations, which allows for further reduction in the size of the drive transistors.

[0173] According to some implementations, the memory controller 406 is also coupled to the host 408. The memory controller 406 can manage data stored in the memory 100 and communicate with the host 408.

[0174] In some implementations, the memory controller 406 is designed to operate in low duty cycle environments, such as secure digital (SD) cards, compact flash (CF) cards, universal serial bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc.

[0175] In some implementations, the memory controller 406 is designed to operate in a high duty cycle environment solid-state drive (SSD) or embedded multimedia card (eMMC), which serves as data storage for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays.

[0176] The memory controller 406 can be configured to control operations of the memory 100, such as read, erase, and program operations. The memory controller 406 can also be configured to manage various functions relating to data stored or to be stored in the memory 100, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 406 is also configured to process error correction codes (ECC) relating to data read from or written to the memory 100.

[0177] The memory controller 406 can also perform any other suitable function, such as formatting the memory 100. The memory controller 406 can communicate with external devices (e.g., the host 408) according to a specific communication protocol. For example, the memory controller 406 can communicate with external devices through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, etc.

[0178] The memory controller 406 and one or more memories 100 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 400 can be implemented and packaged into different types of end electronic products.

[0179] In such Figure 11a In one example shown, the memory controller 406 and a single memory 100 can be integrated into a memory card 502. The memory card 502 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 502 can also include a connector for connecting the memory card 502 to a host computer (e.g., ...). Figure 10 The memory card connector 504 is coupled to the host 408.

[0180] In such Figure 11b In another example shown, the memory controller 406 and multiple memories 100 may be integrated into a solid-state drive (SSD) 506. The solid-state drive 506 may also include a connection between the solid-state drive 506 and a host (e.g., Figure 10 The solid-state drive connector 508 is coupled to the host 408 in the memory card 502. In some embodiments, the storage capacity and / or operating speed of the solid-state drive 506 is greater than the storage capacity and / or operating speed of the memory card 502.

[0181] It is understood that the memory controller 406 may perform the programming methods provided in any embodiment of this disclosure.

[0182] It should be understood that the phrase "some embodiments" mentioned throughout the specification means that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this disclosure. Therefore, "in some embodiments" or "in other embodiments" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0183] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0184] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed may be through some interfaces, and the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0185] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units. They may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0186] In addition, each functional unit in the various embodiments of this disclosure can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be implemented in hardware or in the form of hardware plus software functional units.

[0187] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method for programming a memory, characterized in that, The memory includes programmable memory cells with target states ranging from state 1 to state L. The programming method includes multiple programming operations, and the programming method includes: Obtain the number of initial verification pulses for the x-th state of the target memory cell to be programmed, where the x-th state is the sequence number of the first programming operation verification performed on the target memory cell; where x is a positive integer greater than 1 and less than or equal to L; and L is a positive integer greater than 1. When the sequence number i of the i-th programming operation in the plurality of programming operations is greater than or equal to 1 and less than the first preset value of the x-th state, the i-th programming operation is performed on the memory unit to be programmed with the target state being the x-th state; where i is a positive integer; When i is greater than or equal to the first preset value of the x-th state and less than the number of initial verification pulses of the x-th state, when performing the i-th programming operation, the i-th programming prohibition operation is performed on the memory cell to be programmed with the target state being the x-th state.

2. The method according to claim 1, characterized in that, The first preset value corresponding to each target state is 2.

3. The method according to claim 1, characterized in that, The first preset value is different for each of the target states, and the method further includes: Obtain the x-th difference between the x-th state initial verification pulse number and the second preset value; wherein the second preset value is a positive integer; When the x-th difference is less than or equal to 1, the first preset value of the x-th state is determined to be equal to 2; When the x-th difference is greater than 1, the first preset value of the x-th state is determined to be equal to the value of the x-th difference.

4. The method according to claim 3, characterized in that, The second preset value is greater than or equal to 1 and less than or equal to 5.

5. The method according to claim 1, characterized in that, The method further includes: Obtain the initial verification pulse number for the xj-th state of the programmable memory cell whose target state is xj-th; where xj is greater than 1 and less than L, and j is a positive integer; The first preset value of the x-th state is determined to be equal to the value of the starting verification pulse number of the xj-th state.

6. The method according to claim 5, characterized in that, The value of j is determined based on the number of target states in the memory.

7. The method according to claim 1, characterized in that, When the sequence number i of the i-th programming operation is greater than or equal to 1 and less than the first preset value of the x-th state, the i-th programming operation is performed on the memory unit to be programmed with the target state being the x-th state, including: When i equals 1, perform the first programming operation on the memory cell to be programmed with the target state being the first state; The method further includes performing the first programming operation on the memory cell to be programmed whose target state is from the second state to the Lth state.

8. The method according to claim 1, characterized in that, The method further includes: When i is greater than or equal to the number of initial verification pulses of the x-th state, the i-th programming operation is performed on the programmable memory cell whose target state is the x-th state; After performing the i-th programming operation, perform the i-th programming verification operation to obtain the i-th verification result; For the memory cell to be programmed that the i-th verification result indicates that programming has passed and the target state is the x-th state, perform the (i+1)-th programming prohibition operation; For the memory cell to be programmed that the i-th verification result indicates that programming has failed and the target state is the x-th state, perform the (i+1)-th programming operation.

9. The method according to claim 8, characterized in that, The step of performing the i-th programming operation on the memory cell to be programmed, whose target state is the x-th state, includes: Apply the i-th bit line programming voltage to the bit line of the memory cell to be programmed, which is coupled to the target state x-th state; For the memory cell to be programmed, whose programming has passed as indicated by the i-th verification result and whose target state is the x-th state, the (i+1)-th programming prohibition operation is performed, including: An (i+1)th bit-line programming disable voltage is applied to the bit line of the memory cell to be programmed, which is coupled to the i-th verification result indicating that programming has passed and the target state is the x-th state; wherein, the (i+1)th bit-line programming disable voltage is greater than the i-th bit-line programming voltage; For the memory cells to be programmed where the i-th verification result indicates programming failure and the target state is the x-th state, the (i+1)-th programming operation is performed, including: An (i+1)th bitline programming voltage is applied to the bitline of the memory cell to be programmed, which is coupled to the i-th verification result indicating that programming has failed and the other part of the target state is the x-th state; wherein the (i+1)th bitline programming voltage is greater than or equal to the i-th bitline programming voltage; and the (i+1)th bitline programming voltage is less than the (i+1)th bitline programming disable voltage.

10. The method according to claim 1, characterized in that, When the sequence number i of the i-th programming operation is greater than or equal to 1 and less than the first preset value of the x-th state, the i-th programming operation is performed on the memory unit to be programmed with the target state being the x-th state, including: Apply the i-th bit line programming voltage to the bit line of the memory cell to be programmed, which is coupled to the target state x-th state; When i is greater than or equal to the first preset value of the x-th state and less than the number of initial verification pulses of the x-th state, during the execution of the i-th programming operation, the i-th programming prohibition operation is performed on the memory unit to be programmed with the target state being the x-th state, including: An i-th bit-line programming disable voltage is applied to the bit line coupled to the memory cell to be programmed in the target state x-th state; wherein the i-th bit-line programming voltage is less than the i-th bit-line programming disable voltage.

11. A memory, characterized in that, include: A memory cell array, the memory cell array comprising a plurality of programmable memory cells whose target states are from the first state to the Lth state; Multiple word lines, each of which is coupled to a plurality of programmable memory cells; Multiple bit lines, each bit line being coupled to the multiple programmable memory cells; Peripheral circuitry, coupled to the plurality of word lines and the plurality of bit lines, and configured to perform the programming method as described in any one of the plurality of programmable memory cells on a selected memory cell.

12. A memory system, characterized in that, include: One or more memories as described in claim 11; A memory controller, coupled to the memory and configured to control the memory.

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