Multilayer ceramic electronic component

Abstract

The present disclosure provides a multilayer ceramic electronic component including a ceramic main body, a first external electrode, and a second external electrode, the ceramic main body including a capacitance forming portion, a first edge portion, and a second edge portion, the capacitance forming portion including dielectric layers and first and second internal electrodes, and the dielectric layers being interposed between the first and second internal electrodes, the first edge portion being provided on one surface of the capacitance forming portion, and the second edge portion being provided on the other surface of the capacitance forming portion. -0.1 ≤ (Tm - Ta) / Ta is satisfied, where Tm is an average height of a central region in a second direction of at least one of the first and second edge portions, and Ta is an average height of an outer region in the second direction of the capacitance forming portion.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2021-0024912, filed on February 24, 2021, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure relates to a multilayer ceramic electronic component. Background Technology

[0003] Typically, electronic components using ceramic materials (such as capacitors, inductors, piezoelectric elements, varistors, or thermistors) consist of a ceramic body made of ceramic material, an internal electrode formed inside the ceramic body, and an external electrode mounted on the surface of the ceramic body to connect to the internal electrode.

[0004] In recent years, as electronic products have become smaller and more multifunctional, chip components have also become smaller and more highly functional. Therefore, multilayer ceramic electronic components also need to have small size and high capacitance.

[0005] Multilayer ceramic electronic components comprise dielectric layers, internal electrodes, and external electrodes, and are typically manufactured by simultaneous sintering. However, when manufacturing multilayer ceramic electronic components by simultaneous sintering, the ceramic composition of the dielectric layer and the metallic composition of the internal electrodes exhibit different behaviors during the sintering process. Specifically, the ceramic and metallic compositions have different shrinkage initiation temperatures during sintering, and their shrinkage rates are typically different.

[0006] Differences in firing shrinkage cause shape deformation of electronic components, which can lead to defects such as short circuits and edge defects (e.g., floating edges) and may affect the grains and grain boundaries of the dielectric layer that forms capacitors, potentially degrading the electrical properties of ceramic electronic components. This problem becomes even more pronounced as the size of multilayer ceramic electronic components decreases, resulting in issues with reliability, quality, and yield degradation. Summary of the Invention

[0007] One of the various objectives of this disclosure is to suppress structural deformation of multilayer ceramic electronic components.

[0008] One of the various objectives of this disclosure is to reduce the short-circuit rate of multilayer ceramic electronic components.

[0009] One of the various objectives of this disclosure is to provide a multilayer ceramic electronic component with improved withstand voltage characteristics.

[0010] One of the various objectives of this disclosure is to provide a multilayer ceramic electronic component with excellent reliability.

[0011] According to one aspect of this disclosure, a multilayer ceramic electronic component includes: a ceramic body comprising a capacitor forming portion, a first edge portion, and a second edge portion; the capacitor forming portion having a first surface and a second surface opposite to each other in a first direction, a third surface and a fourth surface opposite to each other in a second direction, and a fifth surface and a sixth surface opposite to each other in a third direction; the capacitor forming portion including a first inner electrode and a second inner electrode stacked in a third direction, and a dielectric layer therebetween the first inner electrode and the second inner electrode; the first edge portion being disposed on the third surface of the capacitor forming portion; and the second edge portion being disposed on the fourth surface of the capacitor forming portion; a first outer electrode connected to the first inner electrode; and a second outer electrode connected to the second inner electrode, wherein, satisfying...

[0012] -0.1≤(Tm-Ta) / Ta

[0013] Wherein, Tm is the average height of at least one of the first edge portion and the second edge portion in the central region in the second direction, and Ta is the average height of the capacitor forming portion in the outer region in the second direction. Attached Figure Description

[0014] The above and other aspects, features and advantages of this disclosure will be more clearly understood by taking into account the accompanying drawings and the following detailed description, in which:

[0015] Figure 1 This is a schematic perspective view of a multilayer ceramic electronic assembly according to an embodiment of the present disclosure;

[0016] Figure 2 It is shown schematically. Figure 1 A three-dimensional view of the ceramic body;

[0017] Figure 3 It is along Figure 1 A cross-sectional view taken from line I-I';

[0018] Figure 4 It is along Figure 1 A cross-sectional view taken from line II-II';

[0019] Figure 5 yes Figure 4 A magnified view of region A;

[0020] Figure 6 This is a graph showing the relationship between the variation of (Tm-Ta) / Ta in a multilayer ceramic electronic component according to an embodiment of the present disclosure and the average grain size of the dielectric layer in the outer region of the capacitor forming portion in the second direction; and

[0021] Figure 7 It is a graph showing the relationship between the variation of (Tm-Ta) / Ta and the withstand voltage of a multilayer ceramic electronic component according to an embodiment of the present disclosure. Detailed Implementation

[0022] In the following description, embodiments of the present disclosure will be described with reference to the accompanying drawings. It is not intended to limit the technology described herein to the specific embodiments, and the scope of this disclosure should be understood to include various modifications, equivalents, and / or alternatives to the embodiments of the present disclosure. Similar reference numerals may be used for similar components in conjunction with the description of the accompanying drawings.

[0023] In the accompanying drawings, for clarity, parts irrelevant to the description may be omitted, and the thickness of elements may be enlarged to clearly indicate layers and regions. The same reference numerals may be used to describe components having the same function within the scope of the same concept.

[0024] In this specification, expressions such as “have,” “may have,” “include,” or “may include” may indicate the presence of a corresponding feature (e.g., a value, function, operation, component) and may not exclude the presence of additional features.

[0025] In this specification, expressions such as “A and / or B”, “at least one of A and B”, or “one or more of A and B” may include all possible combinations of the items listed together. For example, “A and / or B”, “at least one of A and B”, or “one or more of A and B” may include: (1) only A; (2) only B; or (3) both A and B.

[0026] In the accompanying drawings, the X direction can be defined as a first direction, the L direction, or the length direction; the Y direction can be defined as a second direction, the W direction, or the width direction; and the Z direction can be defined as a third direction, the T direction, or the thickness direction.

[0027] This disclosure relates to a multilayer ceramic electronic component 100. Figures 1 to 5 This is a schematic diagram illustrating a multilayer ceramic electronic assembly 100 according to an embodiment of the present disclosure. (Refer to...) Figures 1 to 5According to embodiments of the present disclosure, a multilayer ceramic electronic component 100 may include: a ceramic body 110, the ceramic body 110 including a capacitor forming portion 120, a first edge portion 113 and a second edge portion 112, the capacitor forming portion 120 having a first surface and a second surface opposite to each other in a first direction, a third surface and a fourth surface opposite to each other in a second direction, and a fifth surface and a sixth surface opposite to each other in a third direction, and the capacitor forming portion 120 including a first inner electrode 121 and a second inner electrode 122 stacked in a third direction and a dielectric layer 111, the dielectric layer 111 being between the first inner electrode 121 and the second inner electrode 122, the first edge portion 113 being disposed on the third surface of the capacitor forming portion 120, and the second edge portion 112 being disposed on the fourth surface of the capacitor forming portion 120; a first outer electrode 131 connected to the first inner electrode 121; and a second outer electrode 132 connected to the second inner electrode 122.

[0028] In this case, the multilayer ceramic electronic component 100 can satisfy the following equation 1.

[0029] [Formula 1]

[0030] -0.1≤(Tm-Ta) / Ta

[0031] In Equation 1, Tm is the average height of the central region of the edge portion, and Ta is the average height of the outer region of the capacitor forming portion in the second direction.

[0032] In this specification, the term "central region" of an edge portion may refer to the central region of the edge portion in a second direction, and may also refer to the region extending inward from the outer surface of the edge portion into the region equal to 1 / 2 of the average thickness of the edge portion. Figure 4 It is along Figure 1 The cross-sectional view taken from line II-II', and Figure 5 yes Figure 4 A magnified view of region A. (Refer to...) Figure 4 and Figure 5 If the average thickness of edges 113 and 112 is 2×W, ​​then the region corresponding to the virtual line passing through a point m at a distance W from the outer surface of edges 113 and 112 can be called the central region of the edges. The central region of the edges is defined by the virtual line C passing through the center of the ceramic body along the Y direction. Y The point of intersection can be called the center point M of the edge. C Additionally, in this specification, the "external region" of the capacitor forming section may refer to the region of the capacitor forming section that has a slope on both sides facing the capacitor forming section in the second direction, and may also refer to the region between the virtual line passing through point a and the corresponding surface of the capacitor forming section in the second direction, where point a is a distance W from the corresponding surface of the capacitor forming section in the second direction. (See reference...) Figure 5The region between the virtual line connecting the ends of the first inner electrode 121 and the second inner electrode 122 of the capacitor forming part and a virtual line at a distance W from the virtual line can be called the outer region of the capacitor forming part.

[0033] In this specification, the height of the central region of edges 113 and 112 can be a value measured in the third direction (Z direction) for the central region of edges 113 and 112, and can represent the shortest vertical distance from one side to the other in the third direction (Z direction) for the central region of edges 113 and 112. Furthermore, the average height of the central region can be the arithmetic mean of values ​​measured at 10 equally spaced locations in the X direction for the cutting surface (perpendicular to the Y direction) passing through the central region of edges 113 and 112. More specifically, to reduce error, values ​​can be measured at 10 locations other than the regions corresponding to the two surfaces of the central region of edges 113 and 112 in the X direction, and averaged to obtain the arithmetic mean. In this case, after dividing the cutting surface into 12 equal parts in the X direction, the average height can then be obtained by averaging the measured values. Furthermore, the average height of the outer region of the capacitor forming portion 120 in the second direction can be a value measured in the same manner as the central regions of the edge portions 113 and 112, and can be the arithmetic mean of values ​​measured at 10 equally spaced locations in the X direction for a cut surface (perpendicular to the Y direction) passing through the outer region of the capacitor forming portion 120 in the second direction. In the multilayer ceramic electronic assembly 100 according to this disclosure, the average height of the central regions of the edge portions 113 and 112 and the average height of the outer region of the capacitor forming portion 120 in the second direction satisfy Equation 1, such that structural deformation due to the difference in firing shrinkage between the capacitor forming portion 120 and the edge portions 113 and 112 can be minimized. For example, it can be measured by an optical microscope or a scanning electron microscope (SEM). However, this disclosure is not limited thereto. Other methods and / or tools understood by those skilled in the art can be used even if not described in this disclosure.

[0034] In one example, the upper limit of (Tm-Ta) / Ta in Equation 1 can be 0 or less, but is not limited thereto. For example, (Tm-Ta) / Ta in Equation 1 can be 0 or less, -0.01 or less, -0.015 or less, or -0.02 or less, but is not limited thereto. By making the ratio of (Tm-Ta) / Ta in Equation 1 satisfy the above range, compressive stress can be locally formed on the outer region of the capacitor forming portion 120, and the size of the dielectric grains in the outer region of the capacitor forming portion 120 can be reduced (e.g., Figure 6 As shown in the figure. This increases the proportion of grain boundaries with relatively high resistance and improves withstand voltage characteristics (e.g., Figure 7(As shown). For example, as Figure 6 and Figure 7 As shown, when (Tm-Ta) / Ta in Formula 1 is about -0.03 or less, the average grain size Gm of the outer region of the capacitor forming part in the second direction can be about 400 nm or less, and the withstand voltage can be 47 V or more.

[0035] In embodiments of this disclosure, the ceramic body 110 of the multilayer ceramic electronic component 100 may include a capacitor forming portion 120, a first edge portion 113, and a second edge portion 112.

[0036] There are no particular restrictions on the specific shape of the ceramic body 110, but as Figure 2 As shown, the ceramic body 110 may have a hexahedral shape or a similar shape. Due to the shrinkage of the ceramic powder contained in the ceramic body 110 during the sintering process, the ceramic body 110 may have a substantially hexahedral shape, although not a hexahedral shape with perfectly straight lines. If desired, the ceramic body 110 may be rounded so that the corners are not angled. The rounding process may use, for example, tumble polishing, but is not limited to this.

[0037] In the capacitor forming section 120 of the multilayer ceramic electronic assembly 100 according to the present disclosure, dielectric layers 111, first internal electrodes 121, and second internal electrodes 122 may be stacked alternately. Dielectric layers 111, first internal electrodes 121, and second internal electrodes 122 may be stacked in a third direction (Z direction). Multiple dielectric layers 111 are in a sintered state, and the boundaries between adjacent dielectric layers 111 may be integrated to a degree that is difficult to determine without using a scanning electron microscope (SEM).

[0038] According to embodiments of this disclosure, the raw materials used to form the dielectric layer 111 are not particularly limited, as long as sufficient capacitance can be obtained. For example, barium titanate-based materials, lead-based perovskite composite materials, strontium titanate-based materials, etc., can be used, or materials composed of (Ba... 1-x Ca x (Ti) 1-y (Zr, Sn, Hf) y The composition is represented by O3 (where 0≤x≤1, 0≤y≤0.5). Furthermore, for the purposes of this disclosure, various ceramic additives, organic solvents, plasticizers, binders, dispersants, etc., can be added to powders such as barium titanate (BaTiO3) as materials for forming the dielectric layer 111.

[0039] The dielectric layer 111 of the capacitor forming portion 120 may include dielectric grains. Additionally, the dielectric layer 111 may include grain boundaries disposed between two or more grains. Grains can be distinguished by grain boundaries.

[0040] In one example of this disclosure, the ratio (Gm / Gc) of the average grain size Gm of the dielectric layer 111 in the outer region of the capacitor forming portion 120 of the multilayer ceramic electronic assembly 100 in the second direction to the average grain size (Gc) of the dielectric layer 111 in the central region of the capacitor forming portion 120 may exceed 0.9. The central region of the capacitor forming portion 120 may represent the region near the center of the multilayer ceramic electronic assembly 100, and may include the region where the center of the capacitor forming portion 120 in the X direction, the center of the capacitor forming portion 120 in the Y direction, and the center of the capacitor forming portion 120 in the Z direction intersect each other.

[0041] Furthermore, the ratio (Gm / Gc) of the average grain size Gm of the dielectric layer 111 in the outer region of the capacitor forming portion in the second direction to the average grain size (Gc) of the dielectric layer 111 in the central region of the capacitor forming portion may be less than 1.3. When the ratio (Gm / Gc) of the average grain size Gm of the dielectric layer 111 in the outer region of the capacitor forming portion 120 in the second direction to the average grain size (Gc) of the dielectric layer 111 in the central region of the capacitor forming portion 120 is outside the above range, the stress between the central region of the capacitor forming portion 120 and the outer region of the capacitor forming portion 120 in the second direction may increase, leading to shape changes and potentially causing a short circuit.

[0042] In this specification, the “average grain size” of a grain can be the arithmetic mean of the grain size measured at 10 locations in the XZ section of the capacitor forming portion 120. These 10 locations can be the arithmetic mean of values ​​measured at 10 equally spaced locations in the X direction along a cut surface perpendicular to the Y direction of the multilayer ceramic electronic assembly 100 and passing through a corresponding region of the multilayer ceramic electronic assembly 100. The grain size can be represented as the length of the grain in the longitudinal direction calculated by an image analysis program (MediaCybernetics’ ImageProPlus, version 4.5) after an image of a slice of the electronic assembly is captured using an optical device such as a scanning electron microscope (SEM, Jeol's JSM-7400F).

[0043] In one example, the average thickness of dielectric layer 111 may be 0.5 μm or less. The average thickness of dielectric layer 111 may be the average of values ​​measured at five different locations on the sintered dielectric layer 111. There is no particular lower limit to the average thickness of dielectric layer 111; for example, the average thickness of dielectric layer 111 may be 0.01 μm or greater. The thickness can be measured by, for example, optical microscopy or scanning electron microscopy (SEM).

[0044] The dielectric layer 111 can be formed by adding additives to a slurry containing the above-described materials, coating it onto a carrier film, and drying it to prepare multiple ceramic sheets. The ceramic sheets can be formed by using a doctor blade to shape the slurry into sheet shapes with a thickness of a few micrometers, but are not limited thereto.

[0045] In the examples of this disclosure, the first internal electrode 121 of the multilayer ceramic electronic assembly 100 may be led to the first, third, and fourth surfaces of the capacitor forming portion 120. The first internal electrode 121 led to the first surface of the capacitor forming portion 120 may be connected to the first external electrode 131, which will be described later, and the first internal electrode 121 may not be led to the second surface of the capacitor forming portion 120. Additionally, the second internal electrode 122 of the multilayer ceramic electronic assembly 100 may be led to the second, third, and fourth surfaces of the capacitor forming portion 120. The second internal electrode 122 led to the second surface of the capacitor forming portion 120 may be connected to the second external electrode 132, which will be described later, and the first internal electrode 121 may not be led to the first surface of the capacitor forming portion 120.

[0046] In one example, the average thickness of the first inner electrode 121 and the second inner electrode 122 may be 0.5 μm or less. The average thickness of the first inner electrode 121 and the second inner electrode 122 may be the average of values ​​measured at five different locations on the sintered inner electrode. There is no particular limitation on the lower limit of the average thickness of the first inner electrode 121 and the second inner electrode 122; for example, the average thickness of the first inner electrode 121 and the second inner electrode 122 may be 0.01 μm or greater.

[0047] The materials of the first internal electrode 121 and the second internal electrode 122 are not limited to any particular material, and can be formed using a conductive paste of one or more conductive metals selected from silver (Ag), palladium (Pd), gold (Au), platinum (Pt), nickel (Ni), copper (Cu), tin (Sn), tungsten (W), titanium (Ti) and alloys thereof.

[0048] The ceramic body 110 can be formed by alternately stacking ceramic green sheets on which a first internal electrode 121 is printed and ceramic green sheets on which a second internal electrode 122 is printed in a third direction (Z direction). As a method for printing the first internal electrode 121 and the second internal electrode 122, screen printing, gravure printing, etc. can be used, but the printing method is not limited to these.

[0049] In embodiments of this disclosure, a first edge portion 113 may be disposed on a third surface of a capacitor forming portion 120 of a multilayer ceramic electronic component 100 of this disclosure, and a second edge portion 112 may be disposed on a fourth surface of the capacitor forming portion 120. The first edge portion 113 and the second edge portion 112 may comprise ceramic materials, and may comprise barium (Ba) and titanium (Ti), such as barium titanate (BaTiO3) based ceramic materials.

[0050] In examples of this disclosure, the first edge portion 113 and the second edge portion 112 of the multilayer ceramic electronic assembly 100 according to this disclosure may include a ceramic material having a composition similar to that of the ceramic material of the dielectric layer 111 of the capacitor forming portion 120 as the main component. In this specification, the term "main component" may refer to a component that occupies a relatively large weight percentage compared to other components, and may refer to a component that, based on the weight of the entire composition or the entire dielectric layer, is greater than or equal to 50% (by weight). Conversely, the term "sub-component" may refer to a component that occupies a relatively small weight percentage compared to other components, and may refer to a component that, based on the weight of the entire composition or the entire dielectric layer, is less than 50% (by weight).

[0051] The principal component can be composed of (Ba 1-x Ca x (Ti) 1-y (Zr, Sn, Hf) y The composition is represented by BaTiO3 (where 0 ≤ x ≤ 1, 0 ≤ y ≤ 0.5). The main component can be, for example, a chemical in which Ca, Zr, Sn, and / or Hf are partially dissolved in BaTiO3. In the above composition formula, x can be greater than or equal to 0 and less than or equal to 1, and y can be greater than or equal to 0 and less than or equal to 0.5, but is not limited thereto. For example, when x is 0 and y is 0 in the above composition formula, the main component can be BaTiO3.

[0052] In embodiments of this disclosure, the ratio of barium (Ba) to titanium (Ti) in the dielectric layer 111 of the capacitor forming portion 120 of the multilayer ceramic electronic assembly 100 may differ from the ratio of barium (Ba) to titanium (Ti) in the edge portions 112 and 113. When the value of the barium (Ba) to titanium (Ti) ratio (Ba / Ti) in the dielectric layer 111 of the capacitor forming portion 120 differs from the value of the barium (Ba) to titanium (Ti) ratio (Ba / Ti) in the edge portions 113 and 112, the difference between the firing shrinkage of the capacitor forming portion 120 including the inner electrode and the firing shrinkage of the edge portions 113 and 112 excluding the inner electrode can be offset, thereby suppressing structural deformation of the multilayer ceramic electronic assembly 100. Here, the barium (Ba) to titanium (Ti) ratio refers to the ratio of the barium (Ba) content to the titanium (Ti) content. For example, the barium (Ba) to titanium (Ti) ratio in the dielectric layer 111 of the capacitor forming portion 120 refers to the ratio of the molar content of barium (Ba) to the molar content of titanium (Ti) in the dielectric layer 111 of the capacitor forming portion 120. As an example, the barium (Ba) to titanium (Ti) ratio in the dielectric layer 111 of the capacitor forming portion 120 of the multilayer ceramic electronic assembly 100 according to this disclosure may be less than the barium (Ba) to titanium (Ti) ratio in the second edge portion 112 and the first edge portion 113, respectively, but is not limited thereto. The barium (Ba) to titanium (Ti) ratio in the dielectric layer 111 of the capacitor forming portion 120 of the multilayer ceramic electronic assembly 100 according to this disclosure may be less than the barium (Ba) to titanium (Ti) ratio in the second edge portion 112 and the first edge portion 113.

[0053] In one example, the barium (Ba) to titanium (Ti) ratio (Ba / Ti) of the edges 113 and 112 may exceed 1. This ratio can affect the shrinkage initiation temperature during sintering. When the ratio is 1 or less, sintering shrinkage may begin at a low temperature, and therefore, sintering may be completed at a low temperature. In this case, the stress due to the difference in sintering shrinkage between the capacitor forming portion 120 and the edges 113 and 112 may increase, and the short-circuit rate may increase. There is no particular upper limit to the ratio of barium (Ba) to titanium (Ti) of the edges 113 and 112; for example, it may be 1.5 or less, but is not limited to this.

[0054] The first edge portion 113 and the second edge portion 112 can be formed by stacking a single dielectric layer or two or more dielectric layers respectively, and are essentially used to prevent damage to the inner electrode due to physical or chemical stress.

[0055] The method for forming the edge portions 113 and 112 of the multilayer ceramic electronic component 100 according to this disclosure is not particularly limited, and can be formed, for example, by attaching ceramic sheets for forming the first edge portion 113 and ceramic sheets for forming the second edge portion 112. The first edge portion 113 and the second edge portion 112 can be formed by fixing the capacitor forming portion 120 to a fixture or the like and then transferring the ceramic sheet, but is not limited thereto.

[0056] In the multilayer ceramic electronic assembly 100 according to the example of this disclosure, a first external electrode 131 and a second external electrode 132 may be disposed on the outer surface of the ceramic body 110. The first external electrode 131 may be connected to a first internal electrode 121, and the second external electrode 132 may be connected to a second internal electrode 122. In this case, the first external electrode 131 may be disposed on the first surface of the capacitor forming portion 120 of the multilayer ceramic electronic assembly 100 according to this disclosure, and the second external electrode 132 may be disposed on the second surface of the capacitor forming portion 120.

[0057] In one example, at least a portion of the first external electrode 131 may be configured to extend onto the third, fourth, fifth, and sixth surfaces of the capacitor forming portion 120. Additionally, at least a portion of the second external electrode 132 may be configured to extend onto the third, fourth, fifth, and sixth surfaces of the capacitor forming portion 120. In this case, the first external electrode 131 and the second external electrode 132 may be spaced apart from each other. When the extension is provided, the extension can serve as a so-called strip and can improve the mounting strength of the multilayer ceramic electronic assembly 100 and prevent moisture penetration.

[0058] The first external electrode 131 and the second external electrode 132 can be sintered electrodes comprising a conductive metal and glass. The glass can be a composition in which oxides are mixed; the oxides are not particularly limited and can be one or more selected from the group consisting of silicon oxide, boron oxide, aluminum oxide, transition metal oxides, alkali metal oxides, and alkaline earth metal oxides. The transition metals can be one or more selected from the group consisting of zinc (Zn), titanium (Ti), copper (Cu), vanadium (V), manganese (Mn), iron (Fe), and nickel (Ni); the alkali metals can be one or more selected from the group consisting of lithium (Li), sodium (Na), and potassium (K); and the alkaline earth metals can be one or more selected from the group consisting of magnesium (Mg), calcium (Ca), strontium (Sr), and barium (Ba).

[0059] As an example of a method for forming the first external electrode 131 and the second external electrode 132, the first external electrode 131 and the second external electrode 132 can be formed by immersing a ceramic body 110 in a conductive paste containing a conductive metal and then sintering the resulting structure, or by printing the conductive paste onto the surface of the ceramic body 110 using screen printing or gravure printing and then sintering the resulting structure. Alternatively, the first external electrode 131 and the second external electrode 132 can be formed by coating the surface of the ceramic body with conductive paste and then sintering the resulting structure, or by transferring a dry film obtained by drying the conductive paste onto the ceramic body and then sintering the resulting structure, but are not limited to these methods. For example, the first external electrode 131 and the second external electrode 132 can be formed by forming conductive paste on the ceramic body 110 and then sintering the resulting structure using various methods other than those described above.

[0060] In one example, the multilayer ceramic electronic component according to this disclosure may further include plating layers respectively disposed on the first external electrode 131 and the second external electrode 132. The plating layers may include one or more of copper (Cu), nickel (Ni), tin (Sn), palladium (Pd), platinum (Pt), iron (Fe), gold (Au), silver (Ag), tungsten (W), titanium (Ti), lead (Pb), and alloys thereof. The plating layers may be formed as a single layer or multiple layers, and may be formed by sputtering or electroplating, but are not limited thereto.

[0061] As described above, as one of the various effects of this disclosure, structural deformation of multilayer ceramic electronic components can be suppressed.

[0062] As one of the various effects of this disclosure, it can reduce the short-circuit rate of multilayer ceramic electronic components.

[0063] As one of the various effects of this disclosure, a multilayer ceramic electronic component with improved withstand voltage characteristics can be provided.

[0064] As one of the various effects of this disclosure, it can improve the reliability of multilayer ceramic electronic components.

[0065] However, the various advantages and effects of this disclosure are not limited to those described above, and will be more readily understood in the process of describing specific embodiments of this disclosure.

[0066] While embodiments have been shown and described above, it will be readily understood by those skilled in the art that modifications and variations may be made without departing from the scope of this disclosure as defined by the appended claims.

Claims

1. A multilayer ceramic electronic component, comprising: A ceramic body includes a capacitor forming portion, a first edge portion, and a second edge portion. The capacitor forming portion has a first surface and a second surface opposite to each other in a first direction, a third surface and a fourth surface opposite to each other in a second direction, and a fifth surface and a sixth surface opposite to each other in a third direction. The capacitor forming portion includes a first inner electrode and a second inner electrode stacked in a third direction, and a dielectric layer, wherein the dielectric layer is located between the first inner electrode and the second inner electrode. The first edge portion is disposed on the third surface of the capacitor forming portion, and the second edge portion is disposed on the fourth surface of the capacitor forming portion. The first external electrode is connected to the first internal electrode; as well as The second external electrode is connected to the second internal electrode. Wherein, the following conditions are met: Tm and Ta are not equal, and -0.1≤(Tm-Ta) / Ta, Wherein, Tm is the average height of the central region of at least one of the first edge portion and the second edge portion in the second direction in the third direction, and Ta is the average height of the outer region of the capacitor forming portion in the second direction in the third direction.

2. The multilayer ceramic electronic component according to claim 1, wherein, (Tm-Ta) / Ta is less than 0.

3. The multilayer ceramic electronic component according to claim 1, wherein, The dielectric layer of the capacitor forming portion includes dielectric grains, and Gm / Gc exceeds 0.9, where Gm is the average grain size of the dielectric grains of the dielectric layer in the outer region of the capacitor forming portion in the second direction, and Gc is the average grain size of the dielectric grains of the dielectric layer in the central region of the capacitor forming portion.

4. The multilayer ceramic electronic component according to claim 3, wherein, Gm / Gc is less than 1.

3.

5. The multilayer ceramic electronic component according to claim 1, wherein, The dielectric layer, as well as the first and second edge portions, comprises barium and titanium, and The barium to titanium ratio of the dielectric layer in the capacitor forming portion is different from the barium to titanium ratio in the first edge portion and the second edge portion.

6. The multilayer ceramic electronic component according to claim 5, wherein, The ratio of barium to titanium in the first edge portion and the second edge portion exceeds 1.

7. The multilayer ceramic electronic component according to claim 1, wherein, The average thickness of the dielectric layer in the capacitor forming portion is 0.5 μm or less.

8. The multilayer ceramic electronic component according to claim 1, wherein, The first internal electrode is led out to the first surface, the third surface, and the fourth surface of the capacitor forming portion. The second internal electrode is led out to the second surface, the third surface, and the fourth surface of the capacitor forming portion.

9. The multilayer ceramic electronic component according to claim 1, wherein, The first inner electrode and the second inner electrode have an average thickness of 0.5 μm or less.

10. The multilayer ceramic electronic component according to claim 1 or 9, wherein, The first inner electrode and the second inner electrode have an average thickness of 0.01 μm or greater.

11. The multilayer ceramic electronic component according to any one of claims 1-9, wherein, The first external electrode is disposed on the first surface of the capacitor forming portion. The second external electrode is disposed on the second surface of the capacitor forming portion.

12. The multilayer ceramic electronic component according to claim 11, wherein, At least a portion of the first external electrode is configured to extend onto the third, fourth, fifth, and sixth surfaces of the capacitor forming portion. Wherein, at least a portion of the second external electrode is configured to extend onto the third, fourth, fifth, and sixth surfaces of the capacitor forming portion.

13. The multilayer ceramic electronic component according to claim 5, wherein, The ratio of barium to titanium in the dielectric layer of the capacitor forming portion is smaller than the ratio of barium to titanium in the first edge portion and the ratio of barium to titanium in the second edge portion, respectively.

14. The multilayer ceramic electronic component according to claim 5, wherein, The ratio of barium to titanium in the dielectric layer of the capacitor forming portion is less than the ratio of barium to titanium in the first edge portion and the second edge portion.

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