Methods for manufacturing semiconductor devices

Abstract

This invention relates to a method for manufacturing a semiconductor device capable of forming fine patterns. The method for manufacturing a semiconductor device according to the invention may include: forming an etching mask layer on an etching target layer; forming a spacer structure on the etching mask layer, wherein first spacers and second spacers are alternately disposed and spaced apart from each other; forming first spacer lines by selectively etching the first spacers; forming second spacer lines by selectively etching the second spacers; and etching the etching target layer using the first and second spacer lines to form a plurality of fine line patterns.

Description

[0001] Cross-reference of related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0023612, filed on February 22, 2021, which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to a semiconductor device, and more specifically, to a method for manufacturing a semiconductor device including fine patterns. Background Technology

[0004] Various patterns are formed during semiconductor device manufacturing. Minimizing the critical size of these patterns using conventional photolithography has limitations. Therefore, a technique is needed to achieve critical sizes exceeding the critical resolution of photolithography. Summary of the Invention

[0005] Various embodiments of this disclosure provide a method for manufacturing a semiconductor device capable of forming fine patterns.

[0006] According to one embodiment of the present invention, a method of manufacturing a semiconductor device includes: forming an etching mask layer on an etching target layer; forming a spacer structure on the etching mask layer, wherein a first spacer and a second spacer are alternately disposed and spaced apart from each other in the spacer structure; forming a first spacer line by selectively etching the first spacer; forming a second spacer line by selectively etching the second spacer; and etching the etching target layer using the first spacer line and the second spacer line to form a plurality of fine line patterns.

[0007] According to one embodiment of the present invention, a method of manufacturing a semiconductor device includes: forming a spacer structure on a bit line conductive layer, wherein a first spacer and a second spacer extending in a first direction are spaced apart from each other and alternately disposed along a second direction; forming a first spacer line having an end aligned with a third direction, the third direction intersecting the first direction, by selectively etching the first spacer; forming a second spacer line having an end aligned with a fourth direction, the fourth direction being parallel to the third direction, by selectively etching the second spacer; and etching the bit line conductive layer using the first spacer line and the second spacer line to form an even number of bit lines having an end aligned with the third direction and an odd number of bit lines having an end aligned with the fourth direction.

[0008] According to an embodiment of the present invention, a method of manufacturing a semiconductor device includes: forming an etching mask layer on an etching target layer; forming a first spacer and a second spacer, each extending in a first direction, the first spacer and the second spacer being alternately arranged on the etching mask layer along a second direction to be spaced apart from each other; forming a first spacer line by selectively etching the first spacer; forming a second spacer line by selectively etching the second spacer; and etching the etching target layer using the first spacer line and the second spacer line to form a plurality of fine line patterns, wherein the first spacer line and the second spacer line form a zig-zag pattern along the second direction, wherein a first end of the first spacer line is aligned along the second direction on a first line, wherein a first end of the second spacer line is aligned along the second direction on a second line parallel to the first line, and wherein the first line and the second line are parallel to the second direction.

[0009] In this invention, two cutting mask layers are used to cut spacer lines formed of different materials, and the length of the line pattern can be adjusted by using the misalignment between the two cutting mask layers and the difference in the etching rate of the spacer lines.

[0010] The purpose of this invention is to improve the contact margin of the contact plug connected to the end of the wire by arranging the end of the wire in a zigzag pattern through selective adjustment of the wire length.

[0011] These and other features and objectives of this disclosure will become apparent to those skilled in the art from the accompanying drawings and the detailed description of various embodiments of the invention. Attached Figure Description

[0012] Figures 1A to 12B This is a plan view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0013] Figure 13 This is a view illustrating a semiconductor device according to an embodiment of the present invention. Detailed Implementation

[0014] The various embodiments described herein will be illustrated with reference to cross-sectional views, plan views, and block diagrams, which are ideal schematic representations of the invention. Therefore, the structure of the drawings can be modified by manufacturing techniques and / or tolerances. Embodiments of the invention are not limited to the specific structures shown in the drawings, but include any variations in structure that may result from manufacturing processes. Furthermore, any regions and their shapes shown in the schematic drawings are intended to illustrate specific examples of the regional structures of various elements and are not intended to limit the scope of the invention.

[0015] First, in order to better understand the present invention, related technologies will be explained before describing the present invention.

[0016] Dual patterning (DPT) techniques have been developed to achieve fine patterns with resolutions exceeding those of photolithography. An example of DPT is spacer patterning (SPT). In spacer patterning, a sacrificial pattern is formed, and spacers are formed on the sidewalls of the sacrificial pattern. The sacrificial pattern is then removed, and the remaining spacers are used as an etching mask. Spacer patterning is suitable for forming repeating patterns, i.e., identical patterns repeatedly spaced apart from each other at constant intervals.

[0017] Figures 1A to 12B This is a plan view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0018] according to Figures 1A to 1C The etching target layer 102 can be formed on the substrate 101. The substrate 101 can be a single-layer or multi-layer structure. The substrate 101 can include an insulating layer, a conductive layer, a semiconductor layer, or a combination thereof. The substrate 101 can include a silicon substrate. The substrate 101 can include a silicon substrate in which shallow trench isolation (STI) is formed. The etching target layer 102 can be a single-layer or multi-layer structure. The etching target layer 102 can include an insulating layer, a conductive layer, a semiconductor layer, or a combination thereof. The etching target layer 102 can include a metal layer. The etching target layer 102 can be a stacked layer of metal layers and insulating layers. In another embodiment, the etching target layer 102 can be a material used to form a bit line structure. For example, the etching target layer 102 can be a stacked layer in which a barrier layer, a bit line layer, and a hard mask layer are stacked sequentially in the aforementioned order. The barrier layer can include TiN, TiSiN, WN, WSiN, and combinations thereof. The bit line layer can include a metal layer. The bit line layer can include a tungsten layer. Hard mask layers may include nitrides, oxides, carbon, polysilicon, spin-on carbon (SOC), or combinations thereof.

[0019] A hard mask layer may be formed on the etch target layer 102. The hard mask layer may be a single layer or multiple layers. For example, a multi-layered hard mask layer may include a stack of a first hard mask layer 103 and a second hard mask layer 104. The first hard mask layer 103 may include a material with etching selectivity relative to the etch target layer 102. The first hard mask layer 103 may include nitrides, oxides, amorphous carbon, anti-reflective coating (ARC), polysilicon, spin-on carbon (SOC), or combinations thereof. A second hard mask layer 104 may be formed on the first hard mask layer 103. The second hard mask layer 104 may include a material with etching selectivity relative to the first hard mask layer 103. The second hard mask layer 104 may include nitrides, oxides, amorphous carbon, ARC, polysilicon, SOC, or combinations thereof. The first hard mask layer 103 and the second hard mask layer 104 may be made of different materials. In another embodiment, the first hard mask layer 103 may be omitted and only the second hard mask layer 104 may be formed.

[0020] A patterned mask layer 105 may be formed on a second hard mask layer 104. The patterned mask layer 105 may include a photoresist. The patterned mask layer 105 may be formed, for example, by photolithography.

[0021] The first spacer layer 106A can be formed on the patterned mask layer 105 (see reference). Figure 1A The first spacer layer 106A may be formed to cover any exposed portions of the top surface of the patterned mask layer 105 and the second hard mask layer 104 that are not covered by the patterned mask layer 105. The first spacer layer 106A may be formed, for example, by atomic layer deposition (ALD) or chemical vapor deposition (CVD). The first spacer layer 106A may include a material that is etch-selective relative to the second hard mask layer 104. For example, in one embodiment, the second hard mask layer 104 may be formed of or comprise polysilicon, and the first spacer layer 106A may be formed of or comprise silicon oxide or silicon nitride.

[0022] The first sacrificial spacer 106 can be formed on the sidewall of the patterned mask layer 105 (see reference). Figure 1B The first sacrificial spacer 106 may have a shape that covers the sidewalls of the patterned mask layer 105. In top view, the first sacrificial spacer 106 may have a closed-loop shape. For example, the closed-loop shape may include a quadrilateral shape such as a rectangle or a curved shape such as a ring.

[0023] Can be used for ( Figure 1AAn etching process is performed on the first spacer layer 106A to form the first sacrificial spacer 106. The etching process of the first spacer layer 106A may include dry etching. The first sacrificial spacer 106 may include a material having etch selectivity relative to the second hard mask layer 104. The first sacrificial spacer 106 may include silicon oxide.

[0024] Figure 1C It is along Figure 1B A planar view taken along the AA′ direction. The patterned mask layer 105 can have a linear shape extending in any direction (i.e., in the first direction D1). The first sacrificial spacer 106 can have a closed-loop shape covering the sidewalls of the patterned mask layer 105. Adjacent patterned mask layers 105 can be parallel to each other along the second direction D2. The first direction D1 and the second direction D2 can intersect perpendicularly.

[0025] like Figure 2A and Figure 2B As shown, the patterned mask layer 105 can be removed. Therefore, the first sacrificial spacer 106 can remain on the second hard mask layer 104. Figure 2B It is along Figure 2A A planar view taken along the AA′ direction. The second hard mask layer 104 can be partially exposed in the lower inner and lower outer portions of the first sacrificial spacer 106.

[0026] like Figure 3A and Figure 3B As shown, the second hard mask layer 104 can be etched by using the first sacrificial spacer 106 as an etch stop layer. Therefore, the first spacer 104S can be formed on the first hard mask layer 103. The first spacer 104S can have the same shape as the first sacrificial spacer 106. Figure 3B It is along Figure 3A A planar view taken along the AA′ direction. The first spacer 104S may be a spacer with a closed-loop shape. The first hard mask layer 103 may be partially exposed in the lower inner and lower outer portions of the first spacer 104S.

[0027] like Figures 4A to 4C As shown, after removing the first sacrificial spacer 106, a second sacrificial spacer 107 can be formed on the sidewall of the first spacer 104S. The second sacrificial spacer 107 can have a shape that covers the sidewall of the first spacer 104S. The second sacrificial spacer 107 can have a closed-loop shape. (This can be performed...) Figure 4A The deposition and etching process of the second spacer layer 107′ is used to form the second sacrificial spacer 107. The second sacrificial spacer 107 may include a material having etching selectivity relative to the first hard mask layer 103. The second sacrificial spacer 107 may include silicon oxide.

[0028] Figure 4C It is along Figure 4B The plan view is taken along the AA′ direction, and the second sacrificial spacer 107 can be formed on the inner and outer sidewalls of the first spacer 104S. For example, the second sacrificial spacer 107 can include an inner second spacer 107A and an outer second spacer 107B. The inner second spacer 107A can be formed on the inner sidewall of the first spacer 104S, while the outer second spacer 107B can be formed on the outer sidewall of the first spacer 104S. Each of the inner second spacer 107A and the outer second spacer 107B can have a closed-loop shape.

[0029] Figure 5B It is along Figure 5A The planar view intercepted along the AA′ direction. For example... Figure 5A and Figure 5B As shown, a second spacer 108 can be formed. For example, a third spacer layer (not shown) can be formed on... Figure 4A and Figure 4B The second spacer 108 can be formed on top of the structure and an etching or planarization process of the third spacer layer can be performed. The second spacer 108 can fill the space inside the inner second spacer 107A and can be formed on the outer sidewall of the outer second spacer 107B. The space between adjacent outer second spacers 107B can be filled with the second spacer 108.

[0030] The first spacer 104S and the second spacer 108 can be made of different materials. The first spacer 104S and the second spacer 108 can have different etching rates.

[0031] The series of processes described above for forming spacers is referred to as the spacer-on-spacer (SOS) process. According to an embodiment of the present invention, the SOS process includes the following steps: forming a first spacer 104S using a first sacrificial spacer 106 as an etching barrier layer; forming a second sacrificial spacer 107 on the first spacer 104S; and forming a second spacer 108 on the second sacrificial spacer. When the SOS process is applied, a fine pitch pattern can be easily formed.

[0032] like Figure 6A and Figure 6B As shown, the second sacrificial spacer 107, namely the inner second spacer 107A and the outer second spacer 107B, can be removed. Therefore, the opening 108S can be defined between the first spacer 104S and the second spacer 108. Figure 6B It is along Figure 6AA planar view taken along the AA′ direction. Each opening 108S is a space in which the second sacrificial spacer 107 has been removed and can have a closed-loop shape. The surface of the first hard mask layer 103 can be partially exposed through the opening 108S.

[0033] The first spacer 104S and the second spacer 108 remaining after the removal of the second sacrificial spacer 107 are referred to as the spacer structure. The first spacer 104S and the second spacer 108 may be arranged alternately and spaced apart from each other at a constant interval along the second direction D2. Each of the first spacer 104S and the second spacer 108 may have a closed-loop shape.

[0034] like Figure 7A and Figure 7B As shown, the first cutting mask layer CM1 can be formed on Figure 6A and Figure 6B In terms of structure. Figure 7B It is along Figure 7A A planar view taken along the AA′ direction. The first dicing mask layer CM1 may include a material with etching selectivity relative to the first spacer 104S or the second spacer 108. In one embodiment, the first dicing mask layer CM1 may include a photoresist. The first dicing mask layer CM1 may have a flat plate shape that partially blocks the first spacer 104S and the second spacer 108. The first dicing mask layer CM1 may have an elongated rectangular shape extending in a second direction D2 perpendicular to a first direction D1, which is the direction in which the first spacer 104S and the second spacer 108 extend along their longitudinal direction. The first dicing mask layer CM1 may block the middle portion of the first spacer 104S and the second spacer 108 while exposing a first end E1 and a second end E2 on either side of the middle portion of the first spacer 104S and the second spacer 108. The first dicing mask layer CM1 may asymmetrically expose the ends E1 and E2 of the first spacer 104S and the second spacer 108. In other words, the first end E1 of the second spacer 108 and the first spacer 104S can have a smaller exposed area than the exposed area of ​​the second end E2 of the second spacer 108 and the first spacer 104S. The first end E1 and the second end E2 refer to the portions that can be removed by an etching process using the first cutting mask layer CM1.

[0035] In this embodiment, the first dicing mask layer CM1 may be an etching barrier layer used to etch the first end E1 and the second end E2 of the second spacer 108. The first dicing mask layer CM1 may be referred to as a sealing mask layer or a barrier mask layer.

[0036] like Figure 8A and Figure 8BAs shown, the first cutting mask layer CM1 can be used as an etching barrier layer to etch the first end E1 and the second end E2 of the second spacer 108 to form the second spacer line 108L. Figure 8B It is along Figure 8A A planar view intercepted along the AA′ direction. The second spacer 108L can have a plane in any direction (e.g., in the case of...). Figure 8B The linear shape extends in the direction D1 shown. The first spacer 104S can be disposed between adjacent second spacer lines 108L. More specifically, the first spacer 104S can be formed as a rectangular ring surrounding every other second spacer line 108L disposed along the second direction D2. The first spacer 104S may not contact the second spacer lines 108L. Therefore, referring to... Figure 8B A plurality of second spacer lines 108L can be formed to be spaced apart from each other at a constant interval along a second direction D2, and each second spacer line 108L extends along its long axis in a first direction D1. Furthermore, a plurality of rectangular annular first spacers 104S can be formed to be spaced apart from each other and from the second spacer lines 108L, while surrounding every other second spacer line 108L. During etching of the first end E1 and the second end E2 of the second spacer 108, each exposed portion of the first spacer 104S may not be etched. That is, the etching process can be performed by using chemically selective etching on the ends of the second spacer 108, which is one of the ends of the first spacer 104S and the second spacer 108.

[0037] Subsequently, the first cutting mask layer CM1 can be removed.

[0038] like Figure 9A and Figure 9B As shown, a second dicing mask layer CM2 can be formed to cover a portion of the first spacer 104S and the second spacer line 108L. The second dicing mask layer CM2 may include a material with etching selectivity relative to the first spacer 104S or the second spacer line 108L. In this embodiment, the second dicing mask layer CM2 may include a photoresist. Figure 9B It is along Figure 9AThe second dicing mask layer CM2 is a planar view taken along the AA′ direction, and may have a flat plate shape that partially blocks the first spacer 104S. The second dicing mask layer CM2 may extend in a direction intersecting the first spacer 104S. The second dicing mask layer CM2 may block the middle portion of the first spacer 104S while exposing the two ends E11 and E12 of the first spacer 104S on either side of the middle portion. The second dicing mask layer CM2 may expose the ends E11 and E12 of the first spacer 104S asymmetrically. In other words, the first end E11 of the first spacer 104S may have a smaller exposure area than the second end E12 of the first spacer 104S. The first end E11 and the second end E12 may refer to portions that can be removed by an etching process using the second dicing mask layer CM2.

[0039] In this embodiment, the second dicing mask layer CM2 may be an etching barrier layer for etching the first end E11 and the second end E12 of the first spacer 104S. The second dicing mask layer CM2 may also be referred to as a sealing mask layer or a barrier mask layer.

[0040] The second cutting mask layer CM2 can partially block the second spacer line 108L. The end of the second spacer line 108L adjacent to the first end E11 of the first spacer 104S can be selectively exposed by the second cutting mask layer CM2.

[0041] like Figure 10A and Figure 10B As shown, the second cutting mask layer CM2 can be used as an etching barrier layer to etch the first end E11 and the second end E12 of the first spacer 104S. Therefore, the first spacer line 104L can be formed. Figure 10B It is along Figure 10A The plan view intercepted in the AA′ direction, and the first spacer 104L can have in any direction (e.g., in Figure 10B The linear shape extends along the first direction D1. The second spacer line 108L can be disposed between adjacent first spacers line 104L. The first spacers line 104L and the second spacers line 108L can be disposed alternately along the second direction D2.

[0042] When etching the first end E11 and the second end E12 of the first spacer 104S, the exposed portion of the second spacer line 108L may not be etched. That is, etching can be performed by chemically selective etching of the end of the first spacer 104S, which is one end of the first spacer 104S and the second spacer line 108L.

[0043] Subsequently, the second cutting mask layer CM2 can be removed.

[0044] The first spacer 104L and the second spacer 108L may have the same length. Each of the first spacers 104L may include a first end 104E1 and a second end 104E2. Each of the second spacers 108L may include a first end 108E1 and a second end 108E2. The first ends 104E1 of the first spacers 104L and the first ends 108E1 of the second spacers 108L may be arranged in a zigzag pattern. Therefore, the first ends 104E1 of the first spacers 104L and the first ends 108E1 of the second spacers 108L may not be aligned. The second ends 104E2 of the first spacers 104L and the second ends 108E2 of the second spacers 108L may be arranged in a zigzag pattern, and therefore, the second ends 104E2 of the first spacers 104L and the second ends 108E2 of the second spacers 108L may not be aligned.

[0045] The first spacer 104L and the second spacer 108L can be parallel to each other along the second direction D2, and can each have a shape extending in the first direction D1.

[0046] The first end 104E1 of the first spacer 104L can be arranged to be aligned with the second direction D2. The second end 104E2 of the first spacer 104L can be arranged to be aligned with the second direction D2. The first end 104E1 of the first spacer 104L can be aligned with the second direction D2, and the second end 104E2 of the first spacer 104L can be aligned with the second direction D2.

[0047] The first end 108E1 of the second spacer 108L can be arranged to be aligned with the second direction D2. The second end 108E2 of the second spacer 108L can be arranged to be aligned with the second direction D2. The first end 108E1 of the second spacer 108L can be arranged on the same straight line along the second direction D2, and the second end 108E2 of the second spacer 108L can be arranged on the same straight line along the second direction D2.

[0048] The second direction D2 may include a third direction D21 and a fourth direction D22 that are parallel to each other, and the third direction D21 and the fourth direction D22 may intersect the first direction D1 perpendicularly. For example, the first end 104E1 of the first spacer 104L may be arranged to be aligned along the same line parallel to the third direction D21. The first end 108E1 of the second spacer 108L may be arranged to be aligned along the same line parallel to the fourth direction D22. The first end 104E1 of the first spacer 104L and the first end 108E1 of the second spacer 108L may be arranged to be aligned along the same line parallel to the fifth direction D3, which obliquely intersects the third direction D21 and the fourth direction D22. The second end 104E2 of the first spacer 104L may be arranged to be aligned along the same line parallel to the third direction D21. The second end 108E2 of the second spacer 108L may be arranged to be aligned along the same line parallel to the fourth direction D22. The second end 104E2 of the first spacer 104L and the second end 108E2 of the second spacer 108L can be arranged to be aligned along the same line parallel to the fifth direction D3, which intersects the third direction D21 and the fourth direction D22 at an angle.

[0049] Since the adjacent ends are set at the angles described above, the first end 104E1 and the second end 104E2 of the first spacer 104L can be not set on the same straight line as the first end 108E1 and the second end 108E2 of the second spacer 108L, respectively.

[0050] A sufficiently large distance between the first end 104E1 of the first spacer 104L and the first end 108E1 of the second spacer 108L can be ensured by the zigzag arrangement of the first ends 104E1 and 108E1 as described above. Furthermore, by arranging the second ends 104E2 and 108E2 in a zigzag manner, a sufficiently large distance can be ensured between the second end 104E2 of the first spacer 104L and the second end 108E2 of the second spacer 108L.

[0051] like Figure 11A and Figure 11B As shown, the first spacer line 104L and the second spacer line 108L can be used as etch stop layers to etch the first hard mask layer 103. Therefore, the first hard mask layer line 103L can be formed on the etch target layer 102. When the first hard mask layer 103 is omitted, the first spacer line 104L and the second spacer line 108L can be used as etch stop layers to etch the etch target layer 102.

[0052] Figure 11B It is along Figure 11AThe first hard mask layer line 103L is a planar view taken along the AA′ direction, and the first hard mask layer line 103L can have a linear shape extending in any direction (e.g., the first direction D1). Hereinafter, the first hard mask layer line 103L is abbreviated as etching mask line 103L. Etching mask line 103L can include a first line portion 103L1 and a second line portion 103L2. The first line portion 103L1 and the second line portion 103L2 can be arranged alternately. The first line portion 103L1 can have the same shape as the first spacer line 104L, and the second line portion 103L2 can have the same shape as the second spacer line 108L.

[0053] Each of the first line portions 103L1 may include a first end E21 and a second end E22. Each of the second line portions 103L2 may include a first end E31 and a second end E32. The first end E21 of the first line portion 103L1 and the first end E31 of the second line portion 103L2 may be arranged in a zigzag pattern. Therefore, the first end E21 of the first line portion 103L1 and the first end E31 of the second line portion 103L2 may not be arranged on the same straight line. The second end E22 of the first line portion 103L1 and the second end E32 of the second line portion 103L2 may be arranged in a zigzag pattern. Therefore, the second end E22 of the first line portion 103L1 and the second end E32 of the second line portion 103L2 may not be arranged on the same straight line.

[0054] The first line portion 103L1 and the second line portion 103L2 may be parallel to each other along the second direction D2, and may each have a shape extending in the first direction D1.

[0055] The first end E21 of the first line portion 103L1 can be arranged to be aligned with the second direction D2. The second end E22 of the first line portion 103L1 can be arranged to be aligned with the second direction D2. The first end E21 of the first line portion 103L1 can be arranged on the same straight line along the second direction D2, and the second end E22 of the first line portion 103L1 can be arranged on the same straight line along the second direction D2.

[0056] The first end E31 of the second line portion 103L2 can be aligned with the second direction D2. The second end E32 of the second line portion 103L2 can be aligned with the second direction D2. The first end E31 of the second line portion 103L2 can be aligned with the second direction D2, and the second end E32 of the second line portion 103L2 can be aligned with the second direction D2.

[0057] The second direction D2 may include a third direction D21 and a fourth direction D22 that are parallel to each other, and the third direction D21 and the fourth direction D22 may intersect the first direction D1 perpendicularly. For example, the first end E21 of the first line portion 103L1 may be arranged to be aligned along the same line parallel to the third direction D21. The first end E31 of the second line portion 103L2 may be arranged to be aligned along the same line parallel to the fourth direction D22. The first end E21 of the first line portion 103L1 and the first end E31 of the second line portion 103L2 may be arranged to be aligned along the same line parallel to the fifth direction D3, which obliquely intersects the third direction D21 and the fourth direction D22. The second end E22 of the first line portion 103L1 may be arranged to be aligned along the same line parallel to the third direction D21. The second end E32 of the second line portion 103L2 may be arranged to be aligned along the same line parallel to the fourth direction D22. The second end E22 of the first line portion 103L1 and the second end E32 of the second line portion 103L2 can be arranged to be aligned along the same line parallel to the fifth direction D3, which intersects the third direction D21 and the fourth direction D22 at an angle.

[0058] Since the adjacent ends are arranged at the angles described above, the first end E21 of the first line portion 103L1 and the first end E31 of the second line portion 103L2 do not need to be on the same straight line. The second end E22 of the first line portion 103L1 and the second end E32 of the second line portion 103L2 do not need to be on the same straight line.

[0059] By arranging the first ends E21 and E31 in a zigzag pattern as described above, a sufficiently large distance can be ensured between the first end E21 of the first line portion 103L1 and the first end of the second line portion 103L2. Furthermore, by arranging the second ends E22 and E32 in a zigzag pattern, a sufficiently large distance can be ensured between the second end E22 of the first line portion 103L1 and the second end E32 of the second line portion 103L2.

[0060] like Figure 12A and Figure 12BAs shown, after removing the first spacer line 104L and the second spacer line 108L, the etching mask line 103L can be used as an etching barrier layer to etch the target layer 102. Therefore, a plurality of fine line patterns 102L can be formed on the upper part of the substrate 101. In another embodiment, the first spacer line 104L, the second spacer line 108L, and the etching mask line 103L can be used as etching barriers layers to etch the target layer 102. In this case, the first spacer line 104L and the second spacer line 108L can be removed when the etching process for forming the fine line pattern 102L is completed.

[0061] The fine line pattern 102L may include a first pattern 102L1 and a second pattern 102L2. The first pattern 102L1 and the second pattern 102L2 may be arranged alternately along a second direction D2. The first pattern 102L1 may have the following characteristics: Figure 11B The first line portion 103L1 shown has the same shape, and the second pattern 102L2 can be with the same shape as shown. Figure 11B The second line portion 103L2 shown has the same shape. The first pattern 102L1 can be an even pattern, while the second pattern 102L2 can be an odd pattern.

[0062] Each of the first patterns 102L1 may include a first end E41 and a second end E42. Each of the second patterns 102L2 may include a first end E51 and a second end E52. The first end E41 of the first pattern 102L1 and the first end E51 of the second pattern 102L2 may be arranged in a zigzag pattern. Therefore, the first end E41 of the first pattern 102L1 and the first end E51 of the second pattern 102L2 may not be aligned on the same straight line. The second end E42 of the first pattern 102L1 and the second end E52 of the second pattern 102L2 may be arranged in a zigzag pattern. Therefore, the second end E42 of the first pattern 102L1 and the second end E52 of the second pattern 102L2 may not be aligned on the same straight line.

[0063] The first pattern 102L1 and the second pattern 102L2 can be parallel to each other along the second direction D2, and each can have a shape extending in the first direction D1.

[0064] The first end E41 of the first pattern 102L1 can be aligned in the second direction D2. The second end E42 of the first pattern 102L1 can be aligned in the second direction D2. The first end E41 of the first pattern 102L1 can be aligned along the same straight line along the second direction D2, and the second end E42 of the first pattern 102L1 can be aligned along the same straight line along the second direction D2.

[0065] The first end E51 of the second pattern 102L2 can be arranged on the same straight line along the second direction D2, and the second end E52 of the second pattern 102L2 can be arranged on the same straight line along the second direction D2.

[0066] The second direction D2 may include a third direction D21 and a fourth direction D22 that are parallel to each other, and the third direction D21 and the fourth direction D22 may intersect the first direction D1 perpendicularly. For example, the first end E41 of the first pattern 102L1 may be arranged to be aligned along the same line parallel to the third direction D21. The first end E51 of the second pattern 102L2 may be arranged to be aligned along the same line parallel to the fourth direction D22. The first end E41 of the first pattern 102L1 and the first end E51 of the second pattern 102L2 may be arranged to be aligned along the same line parallel to the fifth direction D3, which obliquely intersects the third direction D21 and the fourth direction D22. The second end E42 of the first pattern 102L1 may be arranged to be aligned along the same line parallel to the third direction D21. The second end E52 of the second pattern 102L2 may be arranged to be aligned along the same line parallel to the fourth direction D22. The second end E42 of the first pattern 102L1 and the second end E52 of the second pattern 102L2 can be arranged to be aligned along the same line parallel to the fifth direction D3, which intersects the third direction D21 and the fourth direction D22 at an angle.

[0067] Since the adjacent ends are arranged at the angles described above, the first end E41 of the first pattern 102L1 and the first end E51 of the second pattern 102L2 do not need to be on the same straight line. The second end E42 of the first pattern 102L1 and the second end E52 of the second pattern 102L2 do not need to be on the same straight line.

[0068] By arranging the first ends E41 and E51 in a zigzag pattern as described above, a sufficiently large distance can be ensured between the first end E41 of the first pattern 102L1 and the first end E51 of the second pattern 102L2. Furthermore, by arranging the second ends E42 and E52 in a zigzag pattern, a sufficiently large distance can be ensured between the second end E42 of the first pattern 102L1 and the second end E52 of the second pattern 102L2.

[0069] Figure 13 This is a view illustrating a semiconductor device according to an embodiment of the present invention.

[0070] refer to Figure 13 The semiconductor device 200 may include a plurality of wires 201, and contact plugs 202A and 202B may be connected to the ends of the wires 201. Each of the wires 201 may include a word line, a bit line, or a metal wiring. The wires 201 may include polysilicon, titanium nitride, tungsten, or stacks thereof.

[0071] The conductor 201 may include a first conductor L1 and a second conductor L2. The first conductor L1 and the second conductor L2 may be arranged alternately. The first conductor L1 and the second conductor L2 may extend parallel to each other. The first conductor L1 and the second conductor L2 may have the same width and length. The first conductor L1 and the second conductor L2 may respectively correspond to... Figure 12B The first pattern 102L1 and the second pattern 102L2. (Refer to...) Figures 1A to 12B Describe the method for forming a first conductor L1 and a second conductor L2. The first conductor L1 can be an even number of conductors, while the second conductor L2 can be an odd number of conductors.

[0072] Each of the first conductors L1 may include a first end P1 and a second end P2. Each of the second conductors L2 may include a first end P11 and a second end P12. The first end P1 of the first conductor L1 and the first end P11 of the second conductor L2 may be arranged in a zigzag pattern. Therefore, the first end P1 of the first conductor L1 and the first end P11 of the second conductor L2 may not be on the same straight line. The second end P2 of the first conductor L1 and the second end P12 of the second conductor L2 may be arranged in a zigzag pattern. Therefore, the second end P2 of the first conductor L1 and the second end P12 of the second conductor L2 may not be on the same straight line.

[0073] Contact plug 202A can be connected to the second end P2 of the first wire L1, and contact plug 202B can be connected to the first end P11 of the second wire L2. Contact plugs 202A and 202B may not be connected to the first end P1 of the first wire L1, and contact plugs 202A and 202B may not be connected to the second end P12 of the second wire L2.

[0074] There may be no conductive material between the contact plugs 202A connected to the second end P2 of the first conductor L1 (refer to 'D11'). Therefore, the parasitic capacitance between the contact plugs 202A can be reduced, and bridging between the second end P12 of the second conductor L2 and the contact plugs 202A can be prevented.

[0075] There may be no conductive material between the contact plugs 202B connected to the first end P1 of the second conductor L2 (refer to 'D12'). Therefore, the parasitic capacitance between the contact plugs 202B can be reduced, and bridging between the first end P1 of the first conductor L1 and the contact plugs 202B can be prevented.

[0076] according to Figures 1A to 13 Line patterns can be formed using dual-space patterning. The line length of the line pattern can be selectively adjusted by using a first cutting mask layer CM1 and a second cutting mask layer CM2, thereby improving the contact margin of even-numbered and odd-numbered line patterns.

[0077] In this disclosure, two dicing mask layers are used to cut spacer lines formed of different materials, but the length of the line pattern can be adjusted by utilizing the misalignment between the two dicing mask layers and the difference in etching rate of the spacer lines.

[0078] Although this disclosure has been shown and described with reference to specific embodiments thereof, the invention is not limited thereto. Those skilled in the art will readily understand that various substitutions, changes, or modifications can be made therein without departing from the scope of this disclosure.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: An etching mask layer is formed on the target etching layer; A spacer structure is formed on the etched mask layer, wherein a first spacer and a second spacer are alternately arranged and spaced apart from each other in the spacer structure; The first spacer line is formed by selectively etching the first spacer; The second spacer line is formed by selectively etching the second spacer; as well as The target layer is etched using the first spacer line and the second spacer line to form multiple fine line patterns. Each of the first spacer and the second spacer has a closed-loop shape. The step of forming the first spacer line includes: A first cutting mask layer is formed on the spacer structure, the first cutting mask layer selectively exposing the ends of the first spacer and the ends of the second spacer; and The first cutting mask layer is used as an etching barrier layer to etch the exposed area at the end of the first spacer; The step of forming the second spacer line includes: A second cutting mask layer is formed, which selectively exposes the ends of the first spacer line and the ends of the second spacer; and The exposed area at the end of the second spacer is etched using the second cutting mask layer as an etching barrier layer. The ends of the first spacer and the second spacer are arranged in a sawtooth shape.

2. The method according to claim 1, wherein, The first spacer and the second spacer are formed of materials with different etching rates.

3. The method according to claim 1, wherein, The step of etching the exposed area of ​​the end of the first spacer using the first cutting mask layer as an etching barrier layer uses a chemical product to selectively etch the end of the first spacer, which is one of the ends of the first spacer and the ends of the second spacer.

4. The method according to claim 1, wherein, The step of etching the exposed area of ​​the end of the second spacer using the second cutting mask layer as an etching barrier layer uses a chemical agent to selectively etch the end of the second spacer, which is one of the ends of the first spacer line and the end of the second spacer.

5. The method according to claim 1, wherein, The step of forming the spacer structure includes: A hard mask layer is formed on the etched mask layer; A sacrificial pattern is formed on the hard mask layer; A first sacrificial spacer is formed on the sidewall of the sacrificial pattern; Remove the sacrifice pattern; The hard mask layer is etched using the first sacrificial spacer as an etch barrier layer to form the first spacer; Remove the first sacrificial spacer; A second sacrificial spacer is formed on both the inner and outer sidewalls of the first spacer; Form the second spacer on the second sacrificial spacer; and Remove the second sacrificial spacer.

6. The method according to claim 1, wherein, The etched target layer includes an insulating layer, a semiconductor material, a metal layer, a metal nitride, or a combination thereof.

7. The method according to claim 1, wherein, The fine line pattern includes bit lines or word lines.

8. The method according to claim 1, wherein The end of the first spacer is arranged to be aligned with the first direction. The end of the second spacer is arranged to be aligned with a second direction, which is parallel to the first direction.

9. The method according to claim 1, wherein, The first cutting mask layer and the second cutting mask layer are not aligned with each other.

10. A method for manufacturing a semiconductor device, the method comprising: A spacer structure is formed on the bit line conductive layer, wherein a first spacer and a second spacer extending in a first direction are spaced apart from each other and are alternately arranged along a second direction; The first spacer is selectively etched by using a first cutting mask layer as an etching barrier layer to form a first spacer line having an end aligned with a third direction, the third direction intersecting the first direction; The second spacer is selectively etched by using a second dicing mask layer as an etching barrier layer to form a second spacer line having an end aligned with a fourth direction, the fourth direction being parallel to the third direction; as well as The bit line conductive layer is etched using the first spacer line and the second spacer line to form an even number of bit lines having ends aligned with the third direction and an odd number of bit lines having ends aligned with the fourth direction. Each of the first spacer and the second spacer has a closed-loop shape. The ends of the even-numbered bit lines and the ends of the odd-numbered bit lines are arranged in a zigzag pattern.

11. The method of claim 10, wherein The ends of the even-numbered bit lines and the ends of the odd-numbered bit lines include a first end and a second end, the first end and the second end facing each other along the first direction. The first ends of the even-numbered bit lines and the first ends of the odd-numbered bit lines are adjacent to each other in a zigzag pattern, and The second ends of the even-numbered bit lines are adjacent to the second ends of the odd-numbered bit lines in a zigzag pattern.

12. The method according to claim 11, further comprising, after etching the bit line conductive layer: A first contact plug is formed, the first contact plug being connected to the first end of the even-numbered bit line and being arranged to be aligned with the third direction; as well as A second contact plug is formed, which is connected to the second end of the odd-numbered bit line and is arranged to be aligned with the fourth direction.

13. The method according to claim 10, wherein, The first spacer and the second spacer are formed of materials with different etching rates.

14. The method of claim 10, wherein, The steps of forming the first spacer line include: A first cutting mask layer is formed on the spacer structure, the first cutting mask layer selectively exposing the ends of the first spacer and the ends of the second spacer; and The first cutting mask layer is used as an etching barrier layer to etch the exposed area at the end of the first spacer.

15. The method according to claim 14, wherein, The step of etching the exposed area of ​​the end of the first spacer using the first cutting mask layer as an etching barrier layer includes using a chemical agent to selectively etch the end of the first spacer, which is one of the ends of the first spacer and the ends of the second spacer.

16. The method of claim 10, wherein, The steps of forming the second spacer line include: Forming a second cutting mask layer, the second cutting mask layer selectively exposing the ends of the first spacer line and the ends of the second spacer; and The second cutting mask layer is used as an etching barrier layer to etch the exposed area at the end of the second spacer.

17. The method according to claim 16, wherein, The step of etching the exposed area of ​​the end of the second spacer using the second cutting mask layer as an etching barrier layer includes using a chemical agent to selectively etch the end of the second spacer, which is one of the ends of the first spacer line and the ends of the second spacer.

18. The method according to claim 10, wherein, The step of forming the spacer structure includes: A hard mask layer is formed on the bit line conductive layer; A sacrificial pattern is formed on the hard mask layer; A first sacrificial spacer is formed on the sidewall of the sacrificial pattern; Remove the sacrifice pattern; The hard mask layer is etched using the first sacrificial spacer as an etch barrier layer to form the first spacer; Remove the first sacrificial spacer; A second sacrificial spacer is formed on both the inner and outer sidewalls of the first spacer; Form the second spacer on the second sacrificial spacer; and Remove the second sacrificial spacer.

19. The method according to claim 10, wherein, The first cutting mask layer and the second cutting mask layer are not aligned with each other.

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