Semiconductor Devices and Their Fabrication Methods

Abstract

Semiconductor devices and their fabrication methods relate to forming trenches on the fins of a semiconductor device (such as the fins of a finned field-effect transistor device) and forming a multilayer dielectric structure within the trenches. Depending on the application, the profile of the multilayer dielectric structure can be controlled to reduce shading effects and the risk of dicing failures, and offers other potential advantages. The multilayer dielectric structure may comprise two, three, or any number of layers and may have a stepped profile, a linear profile, or any other type of profile.

Description

Technical Field

[0001] The embodiments of the present invention generally relate to semiconductor devices and methods of fabrication thereof, and more particularly to forming an insulating layer in a semiconductor device to provide electrical isolation. Background Technology

[0002] This invention generally relates to semiconductor devices and methods of fabrication thereof, and more particularly to forming an insulating layer in a semiconductor device to provide electrical isolation. As the structural dimensions in semiconductor devices continue to shrink, forming thin insulating layers at critical locations within the device presents significant challenges. These challenges can lead to undesirable effects, such as reduced semiconductor device yield. Semiconductor devices are used in a variety of electronic devices, and improving their throughput and performance is often a key consideration. Summary of the Invention

[0003] One embodiment of the present invention relates to a semiconductor device. The semiconductor device includes an isolation structure; a fin extending above the isolation structure; a dielectric structure formed on the fin; and a gate formed on the isolation structure and the fin and adjacent to the dielectric structure. The dielectric structure includes a first dielectric layer and a second dielectric layer.

[0004] Another embodiment of the present invention relates to a method for fabricating a semiconductor device. The method includes forming a trench on a fin of the semiconductor device; forming a first dielectric layer in the trench and forming a second dielectric layer in the trench to form a dielectric structure in the trench; and removing a portion of the first dielectric layer to control the profile of the dielectric structure.

[0005] Another embodiment of the present invention relates to a method for fabricating a semiconductor device. The method includes forming a trench on a fin of the semiconductor device; forming a first dielectric layer in the trench, forming a second dielectric layer in the trench, and forming a third dielectric layer in the trench to form a dielectric structure in the trench; and removing a portion of the first dielectric layer to control the contour of the dielectric structure. Attached Figure Description

[0006] Figure 1 These are perspective views of a semiconductor device in some embodiments.

[0007] Figure 2 In some embodiments, Figure 1 A cross-sectional view of a semiconductor device along the gate region.

[0008] Figures 3A to 3D In some embodiments, Figure 1 The attached diagram shows various multilayer dielectric structures that can be formed in semiconductor devices.

[0009] Figure 4A In some embodiments, forming Figure 3AA flowchart of the process used to construct the multilayer dielectric structure.

[0010] Figures 4B to 4F In some embodiments, Figure 1 Semiconductor devices in Figure 4A Cross-sectional views of various process steps.

[0011] Figure 5A In some embodiments, forming Figure 3B A flowchart of the process used to construct the multilayer dielectric structure.

[0012] Figures 5B to 5F In some embodiments, Figure 1 Semiconductor devices in Figure 5A Cross-sectional views of various process steps.

[0013] Figure 6A In some embodiments, forming Figure 3C A flowchart of the process used to construct the multilayer dielectric structure.

[0014] Figures 6B to 6I In some embodiments, Figure 1 Semiconductor devices in Figure 6A Cross-sectional views of various process steps.

[0015] Explanation of reference numerals in the attached figures:

[0016] H D H1, H2: Height

[0017] W D W T W1, W2, W3: Width

[0018] 100: Semiconductor devices

[0019] 112, 114: Gate

[0020] 122, 124: Source / Drain Regions

[0021] 132, 134, 136: Active fins

[0022] 142: Virtual fin

[0023] 152: Isolation Structure

[0024] 162, 164: Insulation layer

[0025] 172: Dielectric layer

[0026] 174: Dielectric Structure

[0027] 180: Section

[0028] 210: Trench

[0029] 220: Dummy Gate

[0030] 230: Mask layer

[0031] 240: Dummy gate dielectric layer

[0032] 311: First dielectric layer

[0033] 312: Second dielectric layer

[0034] 313: Third dielectric layer

[0035] 400, 500, 600: Process

[0036] 401, 402, 403, 404, 405, 501, 502, 503, 504, 505, 601, 602, 603, 604, 605, 606, 607, 608: Steps Detailed Implementation

[0037] The following detailed description is illustrated with accompanying drawings to aid in understanding various aspects of the invention. It is worth noting that the various structures are for illustrative purposes only and are not drawn to scale, as is customary in the art. In practice, the dimensions of various structures may be increased or decreased arbitrarily for clarity.

[0038] The different embodiments or examples provided below can implement different structures of the present invention. The specific components and arrangements described below are used to simplify the content of the present invention and are not intended to limit the present invention. For example, the description of forming a first component on a second component includes embodiments in which the two are in direct contact, or embodiments in which the two are separated by other additional components and are not in direct contact. Furthermore, multiple embodiments of the present invention may use the same reference numerals repeatedly for brevity, but elements with the same reference numerals in various embodiments and / or arrangements do not necessarily have the same correspondence.

[0039] In addition, spatial relative terms such as “below,” “below,” “lower,” “above,” “higher,” or similar terms are used to describe the relationship between some elements or structures in the accompanying drawings and other elements or structures. These spatial relative terms include different orientations of the device in use or operation, as well as the orientations described in the accompanying drawings. When the device is turned in a different orientation (rotated 90 degrees or other orientations), the spatial relative adjectives used will also be interpreted according to the orientation after the turn.

[0040] This invention provides various embodiments of semiconductor devices and their formation methods, relating to the use of multilayer dielectric layers for contour control in semiconductor devices. Multilayer dielectric layers can be used during fabrication processes to more completely fill trenches, avoiding the formation of air gaps and shadowing effects. Furthermore, multilayer dielectric layers can be used to illustrate variations in removal processes, such as the removal of polysilicon prior to the formation of a metal gate structure. The multilayer dielectric structures described herein can improve the yield and performance of semiconductor devices.

[0041] Figure 1 These are perspective views of a semiconductor device 100 in some embodiments. The semiconductor device 100 is typically a fin field-effect transistor (FET) structure. However, the embodiments described herein can also be implemented in other transistor structures, such as nanosheet FET structures, fully wound gate FET structures, or other similar types of transistor structures. The semiconductor device 100 in the figures includes a gate 112, a gate 114, source / drain regions 122 and 124, active fins 132, 134, and 136, dummy fins 142, an isolation structure 152, an insulating layer 162 and 164, a dielectric layer 172, and a dielectric structure. Figure 1 As shown, section 180 cuts through gate 114. Semiconductor device 100 can typically be implemented in an integrated circuit.

[0042] Both gates 112 and 114 can be metal gate structures, such as a high-dielectric-constant gate dielectric layer and a metal gate structure. In these embodiments, the stack comprises a conductive metal material and a high-dielectric-constant dielectric material. The stack may also include a work function layer, a capping layer, and / or other layers to form a high-dielectric-constant gate dielectric layer and a metal gate structure suitable for the intended application. The high-dielectric-constant gate dielectric layer and metal gate structure can be formed using various suitable processes, such as gate-first or gate-post-processing. Gates 112 and 114 are generally parallel and can be parallel gate stacks (which may include additional similar gate structures, not shown). Figure 1 In some applications, high-dielectric-constant gate dielectric layers and metal gate structures can reduce leakage charge and improve performance compared to polysilicon gates. However, it should be understood that the techniques described herein can also be used in semiconductor devices having polysilicon gate structures or other types of gate structures. In some embodiments, during the fabrication of semiconductor device 100 to facilitate the formation of spacer layers and / or other insulating layers in semiconductor device 100, dummy gate structures (such as dummy gate 220, detailed below) may be formed. Once the fabrication process of semiconductor device 100 is completed, it should be understood that in some embodiments, gates 112 and 114 are adjacent to the spacer layer to provide electrical isolation between gates 112 and 114.

[0043] Both source / drain regions 122 and 124 can be epitaxial materials formed by epitaxial growth processes. For example, portions of active fins 132, 134, 136, and dummy fins 142 can be removed to expose the epitaxial regions used to form source / drain regions 122. Then, epitaxial growth processes such as chemical vapor deposition, vapor phase epitaxy, molecular beam epitaxy, liquid phase epitaxy, other suitable processes, or combinations thereof can be used to form the epitaxial material used for source / drain regions 122 in the epitaxial regions. Similarly, portions of active fins 132, 134, 136, and dummy fins 142 can be removed to expose the epitaxial regions used to form source / drain regions 124. Then, a suitable epitaxial growth process is used to form the epitaxial material used for source / drain regions 124 in the epitaxial regions. The source / drain regions 122 and 124 can be doped with appropriate dopants, and the dopants can include n-type or p-type dopants such as arsenic, phosphorus, diborane, other suitable dopants, or combinations thereof.

[0044] Active fins 132, 134, and 136 are typically made of conductive materials and provide current paths. The materials used for active fins 132, 134, and 136 may be silicon, silicon-germanium, other suitable conductive materials, or combinations thereof. In some embodiments, the semiconductor device 100 is a fin field-effect transistor device, and the active fins 132, 134, and 136 are active fins of the fin field-effect transistor device. Active fins 132, 134, and 136 typically extend above the isolation structure 152 and are typically parallel to the dummy fin 142.

[0045] The dummy fin 142 is generally composed of a dielectric insulating material and does not provide current paths, similar to active fins 132, 134, and 136. The dummy fin 142 has a similar structure to the active fins 132, 134, and 136 in the active region of the semiconductor device 100, in order to reduce stress on the substrate of the semiconductor device 100. Figure 1As shown, active fins 132, 134, and 136 are located on both sides of the dummy fin 142 and are parallel to the dummy fin 142. The inclusion of the dummy fin 142 can further provide critical dimensional consistency in the semiconductor device 100, thereby improving the efficiency and ease of fabrication of the semiconductor device 100 and improving the performance of the semiconductor device 100. In some embodiments, the size and shape of the dummy fin 142 are the same as or substantially the same as the size and shape of the active fins 132, 134, and 136. However, compared to the active fins 132, 134, and 136, the dummy fin 142 may be larger, smaller, thicker, thinner, higher, or lower. In some embodiments, the semiconductor device 100 is a fin field-effect transistor device, and the dummy fin 142 is a non-active fin of the fin field-effect transistor device. The dummy fin 142 can be a single membrane or a composite membrane, and its constituent materials can be silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride, silicon carbonitride, hafnium oxide, tantalum nitride, other suitable materials, or combinations thereof.

[0046] The isolation structure 152 typically prevents leakage current between components of the semiconductor device 100. For example, the isolation structure 152 may be a shallow trench isolation structure. The isolation structure 152 may be formed by creating trenches in the substrate (such as a substrate silicon substrate) of the semiconductor device 100, filling the trenches with an insulating material (such as a dielectric material, such as silicon oxide), and removing excess insulating material using processes such as chemical mechanical polishing. The isolation structure 152 typically provides a substrate for forming other components of the semiconductor device 100 (such as active fins 132, 134, 136, dummy fins 142, gate 114, and source / drain regions 122) thereon.

[0047] Insulating layers 162 and 164 can be made of various materials. For example, insulating layers 162 and 164 can be interlayer dielectric layers and / or contact etch stop layers. In embodiments where insulating layers 162 and / or 164 are interlayer dielectric layers, the composition of insulating layers 162 and / or 164 can be a dielectric material with a low dielectric constant, such as doped silicon oxide, porous silicon oxide, other suitable materials, or combinations thereof.

[0048] Dielectric layer 172 and dielectric structure are typically located on dummy fin 142. Dielectric layer 172 provides electrical isolation for gate 112, and dielectric structure provides electrical isolation for gate 114. Dielectric layer 172 and dielectric structure may be located on dummy fin 142 in a specific region of semiconductor device 100 to provide electrical isolation for structures such as gate 112, gate 114, and other similar structures. The dielectric layer 172 and dielectric structure may be composed of a high dielectric constant dielectric material, a low dielectric constant dielectric material, or a combination thereof, such as silicon oxide, silicon oxynitride, silicon carbonitride, silicon carbonitride, hafnium oxide, tantalum nitride, other suitable materials, or a combination thereof.

[0049] like Figure 2 In some embodiments shown, the cross-sectional view of the semiconductor device 100 is along... Figure 1 The cross-section 180 shown (e.g., cutting through gate 114) should be understood. Figure 2 The cross-sectional view of the semiconductor device 100 shown represents a point in time before the fabrication process is completed. Specifically, Figure 2 The cross-sectional view shows the semiconductor device 100 at a time point related to the formation of the dielectric structure. To avoid excessive shading caused by the formation of the gate 114, a multilayer approach can be used to form the dielectric structure, thereby controlling the profile of the dielectric structure (because the dielectric structure can be thinner, or the profile of the dielectric structure can be controlled to reduce the shading effect). By controlling the profile of the dielectric structure, the gate 114 (and associated work function layers, spacer layers, or similar layers) can contact the dielectric structure in various ways to reduce the shading effect, depending on the intended application. For example, the gate 114 (and associated layers) can contact one or more dielectric layers such as the first dielectric layer 311, the second dielectric layer 312, and the third dielectric layer 313 (see...). Figures 3A to 3D (4A to 4F, 5B to 5F, and 6B to 6I). Gate 114 may contact the upper surface and / or side surface of the first dielectric layer 311, the second dielectric layer 312, and the third dielectric layer 313.

[0050] exist Figure 2In the cross-sectional view, a dummy gate dielectric layer 240 is formed over active fins 132, 134, 136, dummy fins 142, and isolation structure 152. Furthermore, a dummy gate 220 is formed over the dummy gate dielectric layer 240, and a masking layer 230 is formed over the dummy gate 220. Using the dummy gate 220, dummy gate dielectric layer 240, and masking layer 230 improves the method of forming the spacer layer, and the spacer layer ultimately provides the electrical isolation required for the gate 114. The dummy gate 220, masking layer 230, and dummy gate dielectric layer 240 can be at least partially removed before the semiconductor device 100 is fabricated. For example, a post-gate fabrication process can be used to replace the dummy gate 220 with an active gate (such as the gate 114 described above). Because the profile of the dielectric structure can be controlled using a multi-layer scheme, unwanted effects (such as poor metal filling and residual anti-reflective coating) can be avoided or reduced when forming the gate 114.

[0051] In some embodiments, the dummy gate 220 may be composed of polysilicon. However, other suitable materials, such as conductive and insulating materials, or combinations thereof, may also be used to form the dummy gate 220. In summary, the removal method for the dummy gate 220 may employ various suitable processes, including wet etching, dry etching, plasma etching, reactive ion etching, other charging processes, or combinations thereof. Figure 2 As shown in the cross-sectional view, a portion of the dummy gate 220 and a portion of the masking layer 230 in a region on the dummy fin 142 can be removed to form a trench 210. Essentially, the dummy gate 220 and the masking layer 230 are cut to form the trench 210. After forming the trench 210, a dielectric structure is then formed within the trench 210 and on the dummy fin 142.

[0052] The mask layer 230 can be composed of various materials containing metals and metal compounds, such as titanium, tantalum, titanium nitride, tantalum nitride, other suitable materials, or combinations thereof. In some embodiments, the mask layer 230 is a hard mask layer, which facilitates the removal of the polysilicon material used for the underlying dummy gate 220. For example, a hard mask is more suitable for plasma etching processes than a softer mask such as a polymer mask, because the etching intensity needs to be sufficient to remove the underlying polysilicon material. Finally, the mask layer 230 can be removed from the semiconductor device 100 using chemical mechanical polishing, other suitable processes, or combinations thereof.

[0053] The dummy gate dielectric layer 240 can be composed of various materials, such as silicon oxide, silicon nitride, other suitable materials, or combinations thereof. In some embodiments, the dummy gate dielectric layer can serve as an etch stop layer to protect underlying structures such as active fins 132, 134, 136, dummy fins 142, and isolation structure 152 when the dummy gate 220 is removed. Once the dummy gate dielectric layer 240 is removed, the active fins 132, 134, and 136 are exposed, allowing the gate 114 to be formed on the active fins 132, 134, and 136. The dummy gate dielectric layer 240 may be partially removed to expose the active fins 132, 134, and 136, but the dummy gate dielectric layer 240 may still cover a portion of the upper surface of the isolation structure 152 and the dummy fins 142. In some embodiments, the dummy gate dielectric layer 240 is removed to expose the dummy fins 142, and a portion of the dummy fins 142 is also removed.

[0054] like Figure 2 As shown, the height of the dummy fin 142 measured on the upper surface of the self-isolating structure 152 is height H. D Furthermore, the dummy fin 142 has a width W D In some embodiments, height H D Between to However, other heights outside this range can also be implemented. Height H D It can be equal to the height of active fins 132, 134, and 136 (measured on the upper surface of the self-isolating structure 152), or height H. D The width W can be greater than or less than the height (measured on the upper surface of the self-isolating structure 152) of active fins 132, 134, and 136. In some embodiments, the width W D Between to However, other widths outside this range can also be used. Width W D This can be considered a key dimension of the dummy fin 142, which is typically the minimum structural dimension of the dummy fin 142.

[0055] like Figures 3A to 3D Some embodiments shown employ a multilayer approach to form the dielectric structure. By forming the dielectric structure using a multilayer approach, the profile of the dielectric structure can be controlled. For example, a dielectric structure formed using a multilayer approach can have a linear profile and be relatively thin. Furthermore, a dielectric structure formed using a multilayer approach can have a stepped profile.

[0056] exist Figure 3AIn this structure, the dielectric structure includes a first dielectric layer 311 and a second dielectric layer 312. Both the first dielectric layer 311 and the second dielectric layer 312 are located above the dummy fin 142 and the dummy fin dielectric layer 240, and within the trench 210. For example... Figure 3A As shown, the first dielectric layer 311 has a width W1, while the second dielectric layer 312 has a width W2. Figure 3A In the illustrated embodiment, width W1 is greater than width W2, giving the dielectric structure a stepped profile. Fabrication Figure 3A The process of the structure shown is described below in conjunction with process 400. Figure 3A The embodiments shown are beneficial to the yield and performance of semiconductor devices, depending on the intended application.

[0057] exist Figure 3B In this structure, the dielectric structure includes a first dielectric layer 311 and a second dielectric layer 312. Both the first dielectric layer 311 and the second dielectric layer 312 are located above the dummy fin 142 and the dummy fin dielectric layer 240, and within the trench 210. For example... Figure 3B As shown, the first dielectric layer 311 has a width W1, while the second dielectric layer 312 has a width W2. Figure 3B In the illustrated embodiment, width W1 is equal to or approximately equal to width W2 (e.g., the difference is within 10%), giving the dielectric structure a linear profile. However, as fabricated... Figure 3B The structure shown uses process 500, which, by employing a first dielectric layer 311 and a second dielectric layer 312, facilitates the formation of a thinner overall dielectric structure. In summary, widths W1 and W2 are comparable to width W... D Thin. A thinner dielectric structure increases the process tolerance for forming the gate 114, thereby improving the method for forming the gate 114. Figure 3A The embodiments shown are beneficial to the yield and performance of semiconductor devices, depending on the intended application.

[0058] exist Figure 3C In this structure, the dielectric structure includes a first dielectric layer 311, a second dielectric layer 312, and a third dielectric layer 313. The first dielectric layer 311, the second dielectric layer 312, and the third dielectric layer 313 are all located above the dummy fin 142 and the dummy fin dielectric layer 240, and within the trench 210. For example... Figure 3C As shown, the first dielectric layer 311 and the second dielectric layer 312 have a width W1 (the same or substantially the same), while the third dielectric layer 313 has a width W2. Figure 3C In the embodiment, the width W1 is greater than the width W2, giving the dielectric structure a stepped profile that is consistent with... Figure 3A The structures shown are similar. However Figure 3C and Figure 3A Their structures are different. Figure 3CThe structure contains a third dielectric layer, making the overall dielectric structure relatively thin. Therefore Figure 3C The width W1 in the middle is less than Figure 3A The width W1 in the middle, and Figure 3C The width W2 in the middle is less than Figure 3A The width W2 in the middle. (Creation) Figure 3C The process example shown will be explained in conjunction with process 600 as follows. Figure 3C The embodiments shown are beneficial to the yield and performance of semiconductor devices, depending on the intended application.

[0059] exist Figure 3D In this structure, the dielectric structure also includes a first dielectric layer 311, a second dielectric layer 312, and a third dielectric layer 313. The first dielectric layer 311, the second dielectric layer 312, and the third dielectric layer 313 are all located above the dummy fin 142 and the dummy fin dielectric layer 240, and within the trench 210. For example... Figure 3D As shown, the first dielectric layer 311 has a width W1, the second dielectric layer 312 has a width W2, and the third dielectric layer 313 has a width W3. Figure 3D In the embodiments described, width W1 is greater than width W2, and width W2 is greater than width W3, giving the dielectric structure a bi-dimensional profile. It should be understood that... Figure 3D The widths shown are not to scale, and width W1 may be smaller than width W. D . Figure 3D The embodiments shown are beneficial to the yield and performance of semiconductor devices, depending on the intended application.

[0060] Although Figures 3A to 3D Various examples of multilayer dielectric structures are provided, and it should be understood that other multilayer dielectric structures not illustrated herein are within the scope of the embodiments of the present invention. For example, although the dielectric structure in the embodiments employs two or three dielectric layers, it should be understood that any number of dielectric layers can be used to control the profile of dielectric structures in various types of semiconductor devices and any other similar dielectric structures. Furthermore, although stepped profiles and linear profiles have been described above, other types of profiles such as oblique profiles, rounded profiles, pointed profiles, or various other profiles can be implemented in the multilayer dielectric structure to control the profile.

[0061] Figure 4A This is a flowchart of process 400 used to manufacture semiconductor device 100. Figures 4B to 4F This is a cross-sectional view of the semiconductor device 100 in various steps of process 400 (along... Figure 1 The cross-section shown is 180°. Process 400 typically includes forming... Figure 3A The method for constructing a dielectric structure as shown in the embodiment. The dielectric structure of this embodiment includes a two-layer stepped profile.

[0062] Step 401 forms the first dielectric layer in the trench (see Figure 4B ).like Figure 4B As shown in the cross-sectional view, the first dielectric layer 311 is formed in the trench 210, but does not fill all of the trench 210. Figure 4B In the middle, the groove 210 has a width W T A portion of the dummy gate 220 has a height H1, which is measured from the upper surface of the dummy gate dielectric layer 240 to the lower surface of the mask layer 230. Figure 2 similar, Figure 4B The virtual fin 142 in the middle has a width W D In some embodiments, the height H1 is between to Within this range, however, other heights outside this range can also be implemented. In some embodiments, the width W... T Between to However, other widths outside this range can also be implemented. Width W T It can be greater than, equal to, or less than the width W. D It depends on the application.

[0063] Step 402 forms a second dielectric layer in the trench (see...) Figure 4C ).like Figure 4C As shown in the cross-sectional view, a second dielectric layer 312 is formed in trench 210, which is typically filled into trench 210 along with the first dielectric layer 311. Various suitable methods can be employed to form the first dielectric layer 311 and the second dielectric layer 312 in trench 210. For example, a refill process can be used to form the first dielectric layer 311 and the second dielectric layer 312 in trench 210.

[0064] Step 403 Remove the first portion of the dummy gate adjacent to the first dielectric layer and the second dielectric layer (see...) Figure 4D ).like Figure 4D As shown in the cross-sectional view, a portion of the dummy gate 220 adjacent to the first dielectric layer 311 and the second dielectric layer 312 has been removed. Figure 4D In this example, the portion of the removed dummy gate 220 has a height H2. In this case, the height H2 is less than... Figure 4B The height H1 shown creates the stepped profile used in the dielectric structure. For example, Figure 4D The height H2 in the middle can be approximately 60% to 80%. Figure 4B The height H1, or other height variations, can be used to remove the first portion of the dummy gate 220. Various suitable processes can be employed, such as etching processes suitable for removing polysilicon material. This approach allows control over the amount of material removed from the dummy gate 220, ultimately controlling the profile of the dielectric structure.

[0065] Step 404: Remove a portion of the first dielectric layer (see...) Figure 4E ).like Figure 4E As shown in the cross-sectional view, two vertical portions of the first dielectric layer 311 on both sides of the second dielectric layer 312 are removed downwards until the upper surface of the retained material of the dummy gate 220. In step 404, a portion of the first dielectric layer 311 is removed such that the width of the bottom of the overall dielectric structure closest to the dummy fin 142 is greater than the width of the top of the overall dielectric structure relative to the bottom, as detailed below. In this way, the dielectric structure typically has a stepped profile, and the stepped profile is advantageous for specific applications.

[0066] Step 405 Removes the second portion of the dummy gate adjacent to the first dielectric layer and the second dielectric layer (see...) Figure 4F ).like Figure 4F As shown in the cross-sectional view, the retained material of the dummy gate 220 adjacent to the first dielectric layer 311, the second dielectric layer 312, the dummy gate dielectric layer 240, and the dummy fin 142 is removed. Similar to step 403, the method for removing the second portion of the dummy gate 220 can employ various suitable processes, such as etching processes suitable for removing polysilicon material. Figure 4F In the diagram, the bottom of the dielectric structure has a width W1, while the top of the dielectric structure has a width W2. As shown, width W1 is greater than width W2. In this example, width W1 is between... to However, other widths outside this range can also be implemented. Furthermore, in this example, the width W2 is between... to However, other widths outside this range can also be implemented.

[0067] Figure 5A This is a flowchart of another process 500 used to manufacture the semiconductor device 100. Figures 5B to 5F This is a cross-sectional view of the semiconductor device 100 in various steps of process 500 (along... Figure 1 The cross-section shown is 180°. Process 500 typically includes forming... Figure 3B The method for constructing a dielectric structure as shown in the embodiment. The dielectric structure of this embodiment includes a three-layered stepped profile.

[0068] Step 501: Form the first dielectric layer in the trench (see...) Figure 5B ).like Figure 5B As shown in the cross-sectional view, the first dielectric layer 311 is formed in the trench 210, but does not fill all of the trench 210. Figure 5B In the middle, the groove 210 has a width W T A portion of the dummy gate 220 has a height H1, which is measured from the upper surface of the dummy gate dielectric layer 240 to the lower surface of the mask layer 230. Figure 2 Similarly, Figure 5B the dummy fin 142 in has a width W D . In some embodiments, the height H1 is between and , however, other heights outside this range can also be implemented. In some embodiments, the width W T is between and , however, other widths outside this range can also be implemented. The width W T can be greater than, equal to, or less than the width W D , depending on the application.

[0069] Step 502 forms a second dielectric layer in the trench (see Figure 5C ). As shown in the cross-sectional view of Figure 5C , a second dielectric layer 312 is formed in the trench 210, which generally fills the trench 210 together with the first dielectric layer 311. Various suitable schemes can be adopted for the method of forming the first dielectric layer 311 and the second dielectric layer 312 in the trench 210. For example, the method of forming the first dielectric layer 311 and the second dielectric layer 312 in the trench 210 can adopt a refill process.

[0070] Step 503 removes the first part of the dummy gate adjacent to the first and second dielectric layers (see Figure 5D ). As shown in the cross-sectional view of Figure 5D , a part of the dummy gate 220 adjacent to the first dielectric layer 311 and the second dielectric layer 312 is removed. In Figure 5D , the removed part of the dummy gate 220 has a height H2. Different from step 403 of process 400 shown in Figure 4D , in this example, the height H2 is equal to or approximately equal to (within 10%) Figure 5B the height H1 shown. In this way, the dielectric structure does not have a stepped profile, but instead has a generally linear profile. Various suitable processes can be adopted for the method of removing the first part of the dummy gate 220, such as an etching process suitable for removing polysilicon materials.

[0071] Step 504 removes a part of the first dielectric layer (see Figure 5E ). As shown in Figure 5E ​​​​​As shown in the cross-sectional view, two vertical portions of the first dielectric layer 311 on both sides of the second dielectric layer 312 are removed, thus retaining only the horizontal portion of the first dielectric layer, which lies beneath the second dielectric layer 312. In step 504, a portion of the first dielectric layer 311 is removed such that the width of the bottom of the overall dielectric structure closest to the dummy fin 142 is equal to or substantially equal to (within 10%) the width of the top of the overall dielectric structure opposite the bottom, as detailed below. In this way, the dielectric structure typically has a linear profile, and a linear profile is advantageous for specific applications.

[0072] Step 505: Remove the second portion of the dummy gate adjacent to the first dielectric layer and the second dielectric layer (see...). Figure 5F ).like Figure 5F As shown in the cross-sectional view, the retained material of the dummy gate 220 adjacent to the first dielectric layer 311, the second dielectric layer 312, the dummy gate dielectric layer 240, and the dummy fin 142 is removed. Similar to step 503, the method for removing the second portion of the dummy gate 220 can employ various suitable processes, such as etching processes suitable for removing polysilicon material. Figure 5F In the diagram, the bottom of the dielectric structure has a width W1, while the top of the dielectric structure has a width W2. As shown, the width W1 is equal to or approximately equal to (within 10%) the width W2. In this example, the width W1 is between... to However, other widths outside this range can also be implemented. In this example, the width W2 can also be between approximately [missing information]. to However, other widths outside this range can also be implemented.

[0073] Figure 6A This is a flowchart of another process 600 used to manufacture the semiconductor device 100. Figures 6B to 6I This is a cross-sectional view of the semiconductor device 100 in various steps of process 600 (along... Figure 1 The cross-section shown is 180). Process 600 typically includes forming... Figure 3C The method for constructing a dielectric structure as shown in the embodiment. The dielectric structure of this embodiment includes a three-layered stepped profile.

[0074] Step 601 forms the first dielectric layer in the trench (see...) Figure 6B ).like Figure 6B As shown in the cross-sectional view, the first dielectric layer 311 is formed in the trench 210, but does not fill all of the trench 210. Figure 6B In the middle, the groove 210 has a width W T A portion of the dummy gate 220 has a height H1, which is measured from the upper surface of the dummy gate dielectric layer 240 to the lower surface of the mask layer 230. Figure 2 similar, Figure 6BThe virtual fin 142 in the middle has a width W D In some embodiments, the height H1 is between to Within this range, however, other heights outside this range can also be implemented. In some embodiments, the width W... T Between to However, other widths outside this range can also be implemented. Width W T It can be greater than, equal to, or less than the width W. D It depends on the application.

[0075] Step 602 forms a second dielectric layer in the trench (see...) Figure 6C ).like Figure 6C As shown, a second dielectric layer 312 is formed in the trench 210, but the combination of the first dielectric layer 311 and the second dielectric layer 312 does not completely fill the trench 210. Various suitable methods can be employed to form the first dielectric layer 311 and the second dielectric layer 312 in the trench 210. For example, a refill process can be used to form the first dielectric layer 311 and the second dielectric layer 312 in the trench 210.

[0076] Step 603 forms a third dielectric layer in the trench (see Figure 6D ).like Figure 6D As shown in the cross-sectional view, a third dielectric layer 313 is formed in the trench 210, which can generally be filled into the trench 210 together with the first dielectric layer 311 and the second dielectric layer 312. Various suitable methods can be employed to form the third dielectric layer 313 in the trench 210. For example, the third dielectric layer 313 can be formed in the trench 210 using a refill process.

[0077] Step 604: Remove the first portion of the dummy gate adjacent to the first dielectric layer, the second dielectric layer, and the third dielectric layer (see...). Figure 6E ).like Figure 6E As shown in the cross-sectional view, a portion of the dummy gate 220 adjacent to the first dielectric layer 311, the second dielectric layer 312, and the third dielectric layer 313 has been removed. Figure 6E In this example, the portion of the removed dummy gate 220 has a height H2. In this case, the height H2 is less than... Figure 6B The height H1 shown creates a stepped profile in the overall dielectric structure. For example, Figure 6E The height H2 can be Figure 6B The height H1 is approximately 60% to 80%, or other height variations. The method for removing the first portion of the dummy gate 220 can employ a variety of suitable processes, such as etching processes suitable for removing polysilicon material.

[0078] Step 605: Remove the first portion of the first dielectric layer (see...) Figure 6F ).like Figure 6F As shown in the cross-sectional view, two vertical portions of the first dielectric layer 311 on both sides of the second dielectric layer 312 and the third dielectric layer 313 are removed downwards until the upper surface of the retained material of the dummy gate 220. Removing the first portion of the first dielectric layer 311 in this manner ultimately helps to create a multilayer dielectric structure with a stepped profile.

[0079] Step 606: Remove a portion of the second dielectric layer (see...) Figure 6G ).like Figure 6G As shown in the cross-sectional view, two vertical portions of the second dielectric layer 312 on both sides of the third dielectric layer 313 are removed downwards until the upper surface of the retained material of the dummy gate 220. Removing portions of the second dielectric layer 312 in this manner ultimately helps to create a multilayer dielectric structure with a stepped profile.

[0080] Step 607 Removes the second portion of the dummy gate adjacent to the first dielectric layer, the second dielectric layer, and the third dielectric layer (see...). Figure 6H ).like Figure 6H As shown in the cross-sectional view, the retained material of the dummy gate 220 adjacent to the first dielectric layer 311, the second dielectric layer 312, the third dielectric layer 313, the dummy gate dielectric layer 240, and the dummy fin 142 is removed. Similar to step 604, a variety of suitable processes (such as etching processes suitable for removing polysilicon material) can be used to remove the second portion of the dummy gate 220.

[0081] Step 608: Remove the second portion of the dielectric layer (see...) Figure 6I ).like Figure 6I As shown in the cross-sectional view, the first dielectric layer 311, with its two remaining vertical portions, is removed to create a thinner profile used for the overall dielectric structure. Figure 6I In the diagram, the bottom of the dielectric structure has a width W1, while the top of the dielectric structure has a width W2. As shown, width W1 is greater than width W2. In this example, width W1 is between... to However, widths outside this range can also be used. Furthermore, in this example, the width W2 is between... to However, other widths outside this range can also be used. Using three dielectric layers allows the width W2 to be less than or equal to the width W. D The specific application depends on the intended use. By thinning the dielectric structure, the process tolerance for forming the gate 114 can be increased, thereby improving the formation method of the gate 114.

[0082] After completing steps 405 in process 400 and 608 in process 600, the fabrication process used for semiconductor device 100 typically continues to remove the dummy gate 220 and form the gate 114, as described above. It should be understood that the removal steps related to processes 400, 500, and 600 can employ various suitable etching processes such as wet etching or dry etching. Furthermore, these steps can utilize a variety of different etchant materials, depending on the intended application.

[0083] Those skilled in the art will understand that processes 400, 500, and 600 can be employed in various ways to form the multilayer dielectric structures used in semiconductor devices of different embodiments. For example, step 607 in process 600 can be adjusted to produce a multilayer dielectric structure with a two-dimensional profile, such as... Figure 3D The embodiments shown are illustrated. Furthermore, various methods for forming and removing various materials can be modified based on these processes, depending on the intended application. These modifications fall within the scope of the embodiments of the present invention.

[0084] As detailed above, various embodiments of the present invention provide semiconductor devices containing multilayer dielectric structures located on the fins of a semiconductor device (such as the fins of a fin field-effect transistor device) and methods for forming the same. The multilayer approach to forming the dielectric structures provides contour control for the dielectric structures, avoiding shading effects and other unwanted effects in many applications. The ability to control the dielectric structure contours helps reduce the variable impact of removing material from the semiconductor device (e.g., removing dummy gate structures) and increases the process tolerance for forming multiple structures (e.g., forming metal gate structures) in the semiconductor device. Thus, the solutions provided herein can improve the yield and performance of semiconductor devices.

[0085] One embodiment of the present invention relates to a semiconductor device. The semiconductor device includes an isolation structure; a fin extending above the isolation structure; a dielectric structure formed on the fin; and a gate formed on the isolation structure and the fin and adjacent to the dielectric structure. The dielectric structure includes a first dielectric layer and a second dielectric layer.

[0086] In some embodiments, the dielectric structure formed on the fin has a stepped profile derived from the removal of a portion of the first dielectric layer.

[0087] In some embodiments, the dielectric structure further includes a third dielectric layer adjacent to the second dielectric layer.

[0088] In some embodiments, the width of the bottom region of the dielectric structure closest to the fin is greater than the width of the top region of the dielectric structure on the bottom region, and the width of the dielectric structure is less than the width of the fin.

[0089] In some embodiments, the width of the dielectric structure is smaller than the width of the fin.

[0090] In some embodiments, the width of the bottom region of the dielectric structure closest to the fin is greater than the width of the top region of the dielectric structure on the bottom region.

[0091] In some embodiments, the width of the bottom region of the dielectric structure closest to the fin is greater than the width of the middle region of the dielectric structure on the bottom region, and the width of the middle region of the dielectric structure is greater than the width of the top region of the dielectric structure on the middle region.

[0092] Another embodiment of the present invention is a method for fabricating a semiconductor device. The method includes forming a trench on a fin of the semiconductor device; forming a first dielectric layer in the trench and forming a second dielectric layer in the trench to form a dielectric structure in the trench; and removing a portion of the first dielectric layer to control the contour of the dielectric structure.

[0093] In some embodiments, the step of forming a trench on the fin includes removing a portion of the dummy gate structure.

[0094] In some embodiments, the method further includes: removing a dummy gate structure adjacent to the dielectric structure; and forming a metal gate structure adjacent to the dielectric structure.

[0095] In some embodiments, the step of forming a dielectric structure in the trench further includes forming a third dielectric layer in the trench.

[0096] In some embodiments, the method further includes removing a portion of the second dielectric layer to control the outline of the dielectric structure, wherein the step of removing a portion of the first dielectric layer to control the outline of the dielectric structure makes the width of the bottom region of the dielectric structure closest to the fin greater than the width of the middle region of the dielectric structure on the bottom region; and the step of removing a portion of the second dielectric layer to control the outline of the dielectric structure makes the width of the middle region greater than the width of the top region of the dielectric structure on the middle region.

[0097] In some embodiments, the step of removing a portion of the first dielectric layer to control the outline of the dielectric structure makes the width of the bottom region of the dielectric structure closest to the fin greater than the width of the top region of the dielectric structure on the bottom region.

[0098] In some embodiments, the step of removing a portion of the first dielectric layer to control the profile of the dielectric structure gives the dielectric structure a stepped profile.

[0099] Another embodiment of the present invention relates to a method for fabricating a semiconductor device. The method includes forming a trench on a fin of the semiconductor device; forming a first dielectric layer in the trench, forming a second dielectric layer in the trench, and forming a third dielectric layer in the trench to form a dielectric structure in the trench; and removing a portion of the first dielectric layer to control the contour of the dielectric structure.

[0100] In some embodiments, the method further includes removing a portion of the second dielectric layer to control the profile of the dielectric structure.

[0101] In some embodiments, the step of removing a portion of the first dielectric layer to control the outline of the dielectric structure makes the width of the bottom region of the dielectric structure closest to the fin greater than the width of the middle region of the dielectric structure on the bottom region; and the step of removing a portion of the second dielectric layer to control the dielectric structure makes the width of the middle region greater than the width of the top region of the dielectric structure on the middle region.

[0102] In some embodiments, the steps of removing a portion of the first dielectric layer to control the outline of the dielectric structure and removing a portion of the second dielectric layer to control the outline of the dielectric structure make the width of the bottom region of the dielectric structure closest to the fin greater than the width of the top region of the dielectric structure on the bottom region.

[0103] In some embodiments, the step of forming trenches on the fins includes removing a portion of the dummy gate structure and a portion of the masking layer.

[0104] In some embodiments, the step of removing a portion of the first dielectric layer to control the profile of the dielectric structure gives the dielectric structure a stepped profile or a linear profile.

[0105] The features of the above embodiments are beneficial for those skilled in the art to understand the present invention. Those skilled in the art should understand that the present invention can be used as a basis to design and vary other processes and structures to achieve the same objectives and / or advantages as the above embodiments. Those skilled in the art should also understand that these equivalent substitutions do not depart from the concept and scope of the present invention, and changes, substitutions, or modifications can be made without departing from the concept and scope of the present invention.

Claims

1. A semiconductor device, comprising: An isolation structure; A fin-like structure extends above the isolation structure; A dielectric structure is formed on the fin, and the dielectric structure includes a first dielectric layer and a second dielectric layer, wherein the bottom surface of the dielectric structure is higher than the top surface of the fin; and A gate is formed on the isolation structure and the fin and is adjacent to the dielectric structure.

2. The semiconductor device of claim 1, wherein the dielectric structure formed on the fin has a stepped profile derived from the removal of a portion of the first dielectric layer.

3. The semiconductor device of claim 1, wherein the dielectric structure further comprises a third dielectric layer adjacent to the second dielectric layer.

4. The semiconductor device of claim 3, wherein the width of the bottom region of the dielectric structure closest to the fin is greater than the width of the top region of the dielectric structure on the bottom region, and the width of the dielectric structure is less than the width of the fin.

5. The semiconductor device of claim 1, wherein the width of the dielectric structure is smaller than the width of the fin.

6. The semiconductor device of claim 1, wherein the width of a bottom region of the dielectric structure closest to the fin is greater than the width of a top region of the dielectric structure on the bottom region.

7. The semiconductor device of claim 3, wherein the width of a bottom region of the dielectric structure closest to the fin is greater than the width of a middle region of the dielectric structure on the bottom region, and the width of the middle region of the dielectric structure is greater than the width of a top region of the dielectric structure on the middle region.

8. A method for manufacturing a semiconductor device, comprising: A trench is formed on a fin of a semiconductor device; A first dielectric layer is formed in the trench, and a second dielectric layer is formed in the trench to form a dielectric structure in the trench, wherein the bottom surface of the dielectric structure is higher than the top surface of the fin; A portion of the first dielectric layer is removed to control the profile of the dielectric structure.

9. The method of fabricating a semiconductor device as claimed in claim 8, wherein the step of forming the trench on the fin includes removing a portion of a dummy gate structure.

10. The method of manufacturing a semiconductor device as claimed in claim 8, further comprising: Remove a dummy gate structure adjacent to the dielectric structure; as well as A metal gate structure is formed adjacent to the dielectric structure.

11. The method of fabricating a semiconductor device as claimed in claim 8, wherein the step of forming the dielectric structure in the trench further comprises forming a third dielectric layer in the trench.

12. The method of fabricating a semiconductor device as claimed in claim 11, further comprising removing a portion of the second dielectric layer to control the profile of the dielectric structure, wherein: The step of removing the portion of the first dielectric layer to control the outline of the dielectric structure, such that the width of a bottom region of the dielectric structure closest to the fin is greater than the width of a middle region of the dielectric structure on the bottom region; and The step of removing a portion of the second dielectric layer to control the outline of the dielectric structure is to make the width of the intermediate region greater than the width of a top region of the dielectric structure on the intermediate region.

13. The method of fabricating a semiconductor device as claimed in claim 8, wherein the step of removing the portion of the first dielectric layer to control the profile of the dielectric structure causes the width of a bottom region of the dielectric structure closest to the fin to be greater than the width of a top region of the dielectric structure on the bottom region.

14. The method of fabricating a semiconductor device as claimed in claim 8, wherein the step of removing the portion of the first dielectric layer to control the profile of the dielectric structure gives the dielectric structure a first-order profile.

15. A method for manufacturing a semiconductor device, comprising: A trench is formed on a fin of a semiconductor device; A first dielectric layer is formed in the trench, a second dielectric layer is formed in the trench, and a third dielectric layer is formed in the trench to form a dielectric structure in the trench, wherein the bottom surface of the dielectric structure is higher than the top surface of the fin. as well as A portion of the first dielectric layer is removed to control the profile of the dielectric structure.

16. The method of fabricating a semiconductor device as claimed in claim 15, further comprising removing a portion of the second dielectric layer to control the profile of the dielectric structure.

17. The method of manufacturing a semiconductor device as claimed in claim 16, wherein: The step of removing the portion of the first dielectric layer to control the outline of the dielectric structure, such that the width of a bottom region of the dielectric structure closest to the fin is greater than the width of a middle region of the dielectric structure on the bottom region; and The step of removing this portion of the second dielectric layer to control the dielectric structure is to make the width of the intermediate region greater than the width of a top region of the dielectric structure on the intermediate region.

18. The method of fabricating a semiconductor device as claimed in claim 16, wherein the steps of removing a portion of the first dielectric layer to control the outline of the dielectric structure and removing a portion of the second dielectric layer to control the outline of the dielectric structure are such that the width of a bottom region of the dielectric structure closest to the fin is greater than the width of a top region of the dielectric structure on the bottom region.

19. The method of fabricating a semiconductor device as claimed in claim 15, wherein the step of forming the trench on the fin includes removing a portion of a dummy gate structure and a portion of a masking layer.

20. The method of fabricating a semiconductor device as claimed in claim 15, wherein the step of removing the portion of the first dielectric layer to control the profile of the dielectric structure causes the dielectric structure to have a stepped profile or a linear profile.

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