A fan-out packaging method

Abstract

This application discloses a fan-out packaging method, which includes: providing a first substrate; forming a first line layer on one side of a first surface of the first substrate, the first line layer including a plurality of first metal lines with a first spacing between adjacent first metal lines; forming a first dielectric layer on the side of the first line layer away from the first substrate, the first dielectric layer having a plurality of first vias; forming a second line layer along the inner wall of the first vias and on a portion of the first dielectric layer adjacent to the first vias; the second line layer including a plurality of second metal lines with a second spacing between adjacent second metal lines, the second spacing being larger than the first spacing; forming a second dielectric layer on the side of the second line layer away from the first line layer; removing the first substrate; and placing a chip on the side of the first line layer away from the second line layer, the pads on the functional surface of the chip being electrically connected to the first line layer. Through the above method, this application can reduce packaging costs and improve chip packaging yield.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technology, and in particular to a fan-out packaging method. Background Technology

[0002] In existing chip packaging methods, most employ a process of first fabricating a rewiring layer and then mounting the chip onto it. The rewiring layer is used for interconnection between the chip and other devices. The rewiring layer consists of multiple layers, typically with the layer closest to the chip being larger than the layer furthest from the chip, and the spacing between the layers closest to the chip being the smallest. During the fabrication of the rewiring layer, the layer furthest from the chip is usually fabricated first, and the layer connected to the chip is fabricated last. Due to the unevenness of the material coating during fabrication, this method easily leads to surface undulations on the layer closest to the chip, affecting the quality of the chip packaging and resulting in significant yield losses. To solve this problem, surface planarization can be performed after each layer is fabricated, but surface planarization is costly and inefficient. Summary of the Invention

[0003] The main technical problem addressed by this application is to provide a fan-out packaging method that can reduce packaging costs and improve chip packaging yield.

[0004] To solve the above-mentioned technical problems, one technical solution adopted in this application is: providing a fan-out packaging method, comprising: providing a first carrier board, the first carrier board including a first surface and a second surface disposed opposite to each other, forming a first line layer on one side of the first surface; wherein the first line layer includes a plurality of first metal lines, and there is a first interval between adjacent first metal lines; forming a first dielectric layer on the side of the first line layer away from the first carrier board, the first dielectric layer having a plurality of first vias, and a portion of the first line layer being exposed from the first vias; forming a second line layer along the inner wall of the first vias and on the portion of the first dielectric layer adjacent to the first vias; wherein the second line layer includes a plurality of second metal lines, and there is a second interval between adjacent second metal lines, the second interval being larger than the first interval; forming a second dielectric layer on the side of the second line layer away from the first line layer, the second dielectric layer covering the second line layer and filling the first vias; removing the first carrier board, and disposing of a chip on the side of the first line layer away from the second line layer, the chip including a functional surface and a non-functional surface disposed opposite to each other, the pads on the functional surface being electrically connected to the first line layer.

[0005] The step of forming a second dielectric layer on the side of the second line layer away from the first line layer includes: setting a second carrier plate on the side of the second dielectric layer away from the first line layer.

[0006] The step of forming a first line layer on one side of the first surface includes: forming a protective layer on the first surface; forming a first photoresist layer on the side of the protective layer away from the first substrate; forming a patterned first opening on the first photoresist layer, with a portion of the protective layer exposed from the first opening; forming a first line layer within the first opening; and removing the first photoresist layer.

[0007] The step of removing the first carrier board and placing the chip on the side of the first line layer away from the second line layer includes: removing the first carrier board and the protective layer; forming a third dielectric layer on the side of the first line layer away from the second line layer; forming a second opening in the third dielectric layer, with a portion of the first line layer exposed through the second opening; forming a first conductive pillar in the second opening, the first conductive pillar being electrically connected to the first line layer; forming a plurality of conductive bumps on the functional surface of the chip, the conductive bumps being electrically connected to the pads of the chip; and aligning the functional surface of the chip toward the first line layer, so that the conductive bumps are electrically connected to the first conductive pillar.

[0008] The step of setting the chip on the side of the first line layer away from the second line layer includes: forming an underfill on the side of the third dielectric layer away from the first line layer, wherein the underfill covers at least a portion of the first conductive pillar, the conductive bump, and the functional surface of the chip.

[0009] The step of setting the chip on the side of the first line layer away from the second line layer includes: forming a molding compound on the side of the third dielectric layer away from the first line layer, the molding compound covering the chip and the surface of the third dielectric layer away from the first line layer.

[0010] The fan-out packaging method proposed in this application includes: removing the second carrier board, forming a plurality of third openings on the second dielectric layer, with a portion of the second line layer exposed from the third openings; and forming solder balls within the third openings.

[0011] The method further includes, after the step of forming a first line layer on one side of the first surface, forming a fourth dielectric layer on the side of the first line layer away from the first carrier plate; forming a plurality of second vias on the fourth dielectric layer; wherein a portion of the first line layer is exposed through the second vias; filling the second vias with conductive metal to form the third line layer; wherein the third line layer includes a plurality of third metal lines, and there is a third interval between adjacent third metal lines, the third interval being larger than the first interval and smaller than the second interval.

[0012] In the direction away from the first carrier plate, the second through hole includes a first sub-through hole and a second sub-through hole that are interconnected, and the first sub-through hole is closer to the first line layer than the second sub-through hole, and the average inner diameter of the first sub-through hole is smaller than the average inner diameter of the second through hole.

[0013] Wherein, in the direction away from the first carrier plate, the inner diameter of the first sub-through hole gradually increases; and / or, in the direction away from the first carrier plate, the inner diameter of the second sub-through hole is the same.

[0014] The beneficial effects of this application are as follows: Unlike existing technologies, the fan-out packaging method proposed in this application preferentially fabricates a first line layer on a first substrate, closer to the chip, followed by the sequential fabrication of the remaining line layers. Furthermore, the spacing between the line layers gradually increases in the direction away from the chip, facilitating the connection of the chip to other devices or substrates through the multi-line layer structure. Finally, the first substrate is removed, and the chip is positioned on the side of the first line layer away from the remaining line layers. The method proposed in this application effectively solves the problem of unevenness on the surface of the line layers closer to the chip, and by fabricating multiple line layers using this method, the planarization process on the surface of the line layers closer to the chip is avoided, significantly reducing packaging costs. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:

[0016] Figure 1 This is a flowchart illustrating one embodiment of the fan-out packaging method of this application;

[0017] Figure 2 This is a cross-sectional structural schematic diagram corresponding to an embodiment of step S101;

[0018] Figure 3 This is a cross-sectional structural diagram corresponding to one embodiment of step S102;

[0019] Figure 4 This is a cross-sectional structural diagram corresponding to an embodiment after step S102;

[0020] Figure 5 This is a flowchart illustrating step S103 corresponding to one implementation method;

[0021] Figure 6 This is a cross-sectional structural schematic diagram of an embodiment corresponding to step S201;

[0022] Figure 7 This is a cross-sectional structural schematic diagram corresponding to one embodiment of step S202;

[0023] Figure 8 This is a cross-sectional structural diagram corresponding to one embodiment of step S203;

[0024] Figure 9 This is a cross-sectional structural schematic diagram corresponding to one embodiment of step S204;

[0025] Figure 10 This is a cross-sectional structural diagram corresponding to an embodiment after step S204;

[0026] Figure 11 This is a cross-sectional structural diagram corresponding to another embodiment after step S204;

[0027] Figure 12 This is a flowchart illustrating another embodiment of the fan-out packaging method proposed in this application;

[0028] Figure 13 This is a cross-sectional structural diagram corresponding to an embodiment of step S301;

[0029] Figure 14 This is a cross-sectional structural schematic diagram corresponding to one embodiment of step S302;

[0030] Figure 15 This is a cross-sectional structural diagram corresponding to one embodiment of step S303;

[0031] Figure 16 This is a cross-sectional structural diagram corresponding to another embodiment of step S303;

[0032] Figure 17 This is a flowchart illustrating another embodiment of the fan-out packaging method proposed in this application;

[0033] Figure 18 This is a cross-sectional structural schematic diagram corresponding to one embodiment of step S402;

[0034] Figure 19 This is a cross-sectional structural diagram corresponding to one embodiment of step S403;

[0035] Figure 20 This is a cross-sectional structural diagram corresponding to one embodiment of step S404;

[0036] Figure 21 This is a flowchart illustrating step S405 corresponding to one embodiment.

[0037] Figure 22 This is a cross-sectional structural schematic diagram corresponding to an embodiment of step S501;

[0038] Figure 23 This is a cross-sectional structural diagram corresponding to one embodiment of step S502;

[0039] Figure 24 This is a cross-sectional structural diagram corresponding to an embodiment of step S503;

[0040] Figure 25 This is a cross-sectional structural diagram corresponding to an embodiment of step S503;

[0041] Figure 26 This is a cross-sectional structural diagram corresponding to an embodiment after step S504.

[0042] Figure 27 This is a cross-sectional structural diagram corresponding to another embodiment after step S504;

[0043] Figure 28 This is a cross-sectional structural schematic diagram of another embodiment of the fan-out packaging method proposed in this application;

[0044] Figure 29 This is a cross-sectional structural schematic diagram of another embodiment of the fan-out packaging method proposed in this application;

[0045] Figure 30 This is a cross-sectional structural diagram corresponding to an embodiment after step S401;

[0046] Figure 31 This is a flowchart illustrating another embodiment of the fan-out packaging method of this application;

[0047] Figure 32 This is a flowchart illustrating step S601 corresponding to one embodiment.

[0048] Figure 33 This is a cross-sectional structural diagram corresponding to an embodiment after step S702;

[0049] Figure 34 This is a cross-sectional structural schematic diagram corresponding to an embodiment of step S602;

[0050] Figure 35 This is a cross-sectional structural diagram corresponding to one embodiment of step S603;

[0051] Figure 36 This is a cross-sectional structural diagram of an embodiment prior to step S604;

[0052] Figure 37 This is a cross-sectional structural diagram corresponding to one embodiment of step S604;

[0053] Figure 38 This is a cross-sectional structural diagram of another embodiment following step S604;

[0054] Figure 39 This is a cross-sectional structural diagram of another embodiment following step S604;

[0055] Figure 40 This is a cross-sectional structural schematic diagram of one embodiment of the fan-out packaged device of this application;

[0056] Figure 41 This is an enlarged cross-sectional view of part of the first and part of the second layer.

[0057] Figure 42 This is a cross-sectional structural schematic diagram of another embodiment of the fan-out packaged device of this application;

[0058] Figure 43 This is a cross-sectional structural schematic diagram of another embodiment of the fan-out packaged device of this application;

[0059] Figure 44 This is a cross-sectional structural schematic diagram of another embodiment of the fan-out packaged device of this application;

[0060] Figure 45 This is a cross-sectional structural schematic diagram of another embodiment of the fan-out packaged device of this application. Detailed Implementation

[0061] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0062] Please see Figure 1 , Figure 1 This is a flowchart illustrating one embodiment of the fan-out packaging method of this application, the method comprising:

[0063] S101: Provide a first carrier plate, and form a first line layer on one side of the first surface of the first carrier plate.

[0064] Please see Figure 2 , Figure 2 This is a cross-sectional structural diagram corresponding to one embodiment of step S101. Specifically, the specific implementation process of step S101 includes: as follows Figure 2 As shown in Figure a, a first carrier plate 80 is provided, which includes a first surface 81 and a second surface 82 disposed opposite to each other. The material of the first carrier plate 80 can be one of silicon, glass, metal, and organic composite materials.

[0065] Further, the step of forming the first line layer 10 on one side of the first surface 81 includes: as follows Figure 2 As shown in Figure b, a protective layer 12 is formed on the first surface 81. Specifically, a bonding adhesive layer (not shown) with a thickness of submicron level is formed on the first surface 81, and the protective layer 12 is formed by chemical deposition on the side of the bonding adhesive layer away from the first carrier plate 80. The material of the protective layer 12 can be one or more of titanium, tantalum, chromium, tungsten, copper, aluminum, nickel, gold, etc., preferably copper. In addition, the thickness of the protective layer 12 is submicron level. By forming the protective layer 12, the first line layer 10 can be avoided from being directly fabricated on the first carrier plate 80, so as to facilitate the subsequent separation of the first line layer 10 from the first carrier plate 80, and it can also provide a certain degree of protection for the first line layer 10.

[0066] Furthermore, such as Figure 2 As shown in Figure c, a first photoresist layer 14 is formed on the side of the protective layer 12 away from the first carrier substrate 80, and a patterned first opening 16 is formed on the first photoresist layer 14, with a portion of the protective layer 12 exposed through the first opening 16. The patterned first opening 16 can be formed by exposing and developing a portion of the first photoresist layer 14, and then removing the exposed and developed first photoresist layer 14; the specific process will not be detailed here. Next, as... Figure 2 As shown in Figure d, a first line layer 10 is formed within the first opening 16, and the first photoresist layer 14 is removed. The first line layer 10 can be formed by filling the first opening 16 with conductive metal. The material of the first line layer 10 can be copper or other conductive metals. The first line layer 10 includes a plurality of first metal lines 11, with a first spacing 13 between adjacent first metal lines 11. The first metal lines 11 of various specifications are interconnected.

[0067] S102: A second wire layer is provided on the side of the first wire layer away from the first carrier plate, and the second wire layer is electrically connected to the first wire layer.

[0068] Please see Figure 3 , Figure 3 This is a cross-sectional structural diagram corresponding to one embodiment of step S102. Specifically, step S102 includes: First, as... Figure 3 As shown in Figure a, a first dielectric layer 40 is formed on the side of the first line layer 10 away from the first carrier plate 80, and the first dielectric layer 40 covers the first line layer 10. In this embodiment, the first dielectric layer 40 fills the gaps between adjacent metal lines 11 in the first line layer 10. Furthermore, the material of the first dielectric layer 40 can be polyimide, poly(p-phenylenebenzobisoxazole) fiber, benzocyclobutene, or PSR material, etc. Forming the first dielectric layer 40 helps to protect the first line layer 10 and facilitates the subsequent step of forming the second line layer 20.

[0069] Furthermore, such as Figure 3As shown in Figure b, a plurality of first vias 41 are formed on the first dielectric layer 40. Specifically, the first vias 41 can be formed on the first dielectric layer 40 by means of grinding or the like. A portion of the first line layer 10 is exposed through the first vias 41. Forming the first vias 41 facilitates the subsequent formation of the second line layer 20 within the first vias 41. In this embodiment, in the direction away from the first substrate 80, the first vias 41 include interconnected first sub-vias 43 and second sub-vias 45, and the first sub-vias 43 are closer to the first line layer 10 than the second sub-vias 45, with the average inner diameter of the first sub-vias 43 being smaller than the average inner diameter of the second sub-vias 45. Furthermore, in this embodiment, in the direction away from the first substrate 80, the inner diameter of the first sub-vias 43 gradually increases, i.e., the inner diameter of the first sub-vias 43 at one end near the first substrate 80 is smaller than the inner diameter at the other end. And / or, in the direction away from the first substrate 80, the inner diameter of the second sub-vias 45 is the same. By setting a structure with first sub-vias 43 and second sub-vias 45 having different average inner diameters, and by setting the first sub-via 43 to have an inner diameter that gradually increases in the direction away from the first carrier plate 80, packaging costs can be saved and the stability of the packaging structure can be improved. Of course, in other embodiments, the inner diameter of the first sub-via 43 can also be the same in the direction away from the first carrier plate 80.

[0070] Furthermore, such as Figure 3 As shown in Figure c, a conductive metal is filled into the first through-hole 41 to form a second wire layer 20, which is electrically connected to the first wire layer 10. The second wire layer 20 can be made of copper or other conductive metal. The second wire layer 20 includes a plurality of second metal lines 21, with a second interval 23 between adjacent second metal lines 21. The plurality of second metal lines 21 are interconnected. In this embodiment, the first interval 13 between adjacent first metal lines 11 in the first wire layer 10 is smaller than the second interval 23 between adjacent second metal lines 21 in the second wire layer 20.

[0071] In this embodiment, please refer to Figure 4 , Figure 4 This is a cross-sectional structural diagram corresponding to one embodiment after step S102. Specifically, after step S102, the method further includes: firstly, as... Figure 4 As shown in Figure a, a second dielectric layer 50 is disposed on the side of the second line layer 20 away from the first carrier plate 80, covering the surface of the second line layer 20 on the side away from the first carrier plate 80. The material of the second dielectric layer 50 can be polyimide, poly(p-phenylenebenzobisoxazole) fiber, benzocyclobutene, or PSR material, etc. Forming the second dielectric layer 50 helps to protect the surface of the second line layer 20 away from the first carrier plate 80 and facilitates subsequent steps.

[0072] Furthermore, such as Figure 4 As shown in Figure b, a plurality of second vias 51 are formed on the second dielectric layer 50. A portion of the second line layer 20 is exposed through the second vias 51. The formation of the second vias 51 facilitates the subsequent formation of the third line layer 30 within them. In this embodiment, in the direction away from the first substrate 80, the second vias 51 include interconnected third sub-vias 53 and fourth sub-vias 55, with the third sub-vias 53 being closer to the second line layer 20 than the fourth sub-vias 55. The average inner diameter of the third sub-vias 53 is smaller than the average inner diameter of the fourth sub-vias 55. Furthermore, in this embodiment, the inner diameter of the third sub-vias 53 gradually increases in the direction away from the first substrate 80. And / or, the inner diameter of the fourth sub-vias 55 is the same in the direction away from the first substrate 80. The specific process of forming the plurality of second vias 51 in this embodiment can be referred to step S102, and will not be repeated here.

[0073] Furthermore, such as Figure 4 As shown in Figure c, a conductive metal is filled into the second via 51 to form a third line layer 30. The third line layer 30 is electrically connected to the second line layer 20. The material of the third line layer 30 can be copper or other conductive metals. The third line layer 30 includes multiple third metal lines 31, with a third spacing 33 between adjacent third metal lines 31, and the multiple third metal lines 31 are interconnected. Furthermore, in this embodiment, the second spacing 23 between adjacent second metal lines 21 in the second line layer 20 is smaller than the third spacing 33 between adjacent third metal lines 31 in the third line layer 30; that is, the first spacing 13 is smaller than the second spacing 23, and the second spacing 23 is smaller than the third spacing 33. In this embodiment, by setting a multi-layer line layer structure with gradually increasing spacing, it is helpful to achieve interconnection between the chip and other devices in the packaged device and reduce signal loss.

[0074] Furthermore, such as Figure 4 As shown in Figure d, after forming the third line layer 30, the process further includes forming a second carrier plate 90 on the side of the third line layer 30 away from the second line layer 20. Specifically, a bonding adhesive layer (not shown) can be coated on the surface of the third line layer 30 and the second dielectric layer 50 away from the first carrier plate 80, and the second carrier plate 90 is fixed to the third line layer 30 and the second dielectric layer 50 on the side away from the first carrier plate 80 by the bonding adhesive layer. The material of the second carrier plate 90 can be one of silicon, glass, metal, and organic composite materials. By setting the second carrier plate 90, a certain degree of protection can be provided to the surface of the third line layer 30 away from the first carrier plate 80.

[0075] It should be noted that in this embodiment, the fan-out packaging method proposed in this application forms a three-layer interconnected line structure on one side of the first carrier board 80, namely the first line layer 10, the second line layer 20 and the third line layer 30. However, in other embodiments, other numbers of line structures can be provided, such as 2, 4, 5, etc., and this application does not limit this.

[0076] S103: Remove the first substrate and place the chip on the side of the first line layer away from the second line layer.

[0077] Please see Figure 5 , Figure 5 This is a flowchart illustrating step S103 in one embodiment. Specifically, the implementation process of step S103 includes:

[0078] S201: Remove the first carrier board and protective layer.

[0079] Please see Figure 6 , Figure 6 This is a cross-sectional structural diagram corresponding to one embodiment of step S201. Specifically, the implementation process of step S201 includes: removing the first carrier plate 80 and the protective layer 12. Specifically, the first carrier plate 80 can be removed by melting the bonding adhesive layer between the first carrier plate 80 and the protective layer 12, and the protective layer 12 can be removed by etching. Further, the second carrier plate 90 is positioned with the side furthest from the third line layer 30 facing downwards to expose the first line layer 10.

[0080] S202: A third dielectric layer is formed on the side of the first line layer away from the second line layer, and a plurality of second openings are formed on the third dielectric layer.

[0081] Please see Figure 7 , Figure 7 This is a cross-sectional structural diagram corresponding to one embodiment of step S202. Specifically, the implementation process of step S202 includes: forming a third dielectric layer 60 on the side of the first line layer 10 away from the second line layer 20. The material of the third dielectric layer 60 can be polyimide, poly(p-phenylenebenzobisoxazole) fiber, benzocyclobutene, or PSR material, etc. Forming the third dielectric layer 60 can provide a certain degree of protection for the side of the first line layer 10 away from the second line layer 20 and facilitate the execution of subsequent steps.

[0082] For further information, please refer to [link / reference]. Figure 7 A plurality of second openings 62 are formed on the third dielectric layer 60, and a portion of the first line layer 10 is exposed through the second openings 62. The third dielectric layer 60 at corresponding locations can be etched away to form the plurality of second openings 62. Forming the plurality of second openings 62 facilitates the execution of step S203.

[0083] S203: A first conductive post is formed inside the second opening.

[0084] Please combine Figure 7 See Figure 8 , Figure 8 This is a cross-sectional structural diagram corresponding to one embodiment of step S203. Specifically, the implementation process of step S203 includes: filling the second opening 62 with conductive metal to form a first conductive pillar 64. One end of the first conductive pillar 64 is electrically connected to the first line layer 10, and the other end is exposed from the third dielectric layer 60. The material of the first conductive pillar 64 can be copper or other conductive metals. Forming the first conductive pillar 64 facilitates the execution of step S204.

[0085] S204: Multiple conductive bumps are formed on the functional surface of the chip, and the conductive bumps are electrically connected to the first conductive post.

[0086] Please combine Figure 8 See Figure 9 , Figure 9 This is a cross-sectional structural diagram corresponding to one embodiment of step S204. Specifically, the implementation process of step S204 includes: providing a chip 100, which includes a functional surface 101 and a non-functional surface 102 disposed opposite to each other. The functional surface 101 is provided with a plurality of pads 103. For ease of understanding, Figure 9 Only four pads 103 are schematically shown in the diagram. In actual applications, the number of pads 103 can be other values, and there is no limitation on this. Multiple conductive bumps 105 are formed on the functional surface 101 of the chip 100, and the conductive bumps 105 are electrically connected to the pads 103. The conductive bumps 105 facilitate the connection of the pads 103 to other devices.

[0087] Furthermore, the functional surface 101 of the chip 100 is oriented towards the first line layer 10, and the conductive bump 105 is electrically connected to the first conductive post 64. Solder 110 can be formed between the first conductive post 64 and the conductive bump 105, and the solder 110 can be melted through a reflow process, resulting in a tight connection between the first conductive post 64 and the conductive bump 105. The solder 110 can be made of Sn or SnAg alloy, or it can be made of low-melting-point metals such as SnBi or In.

[0088] The fan-out packaging method proposed in this application firstly fabricates a first line layer 10 on the first substrate 80, closer to the chip 100, and then sequentially fabricates the remaining line layers. The spacing between the line layers gradually increases in the direction away from the chip 100, facilitating the connection of the chip 100 to other devices or substrates through the multi-line layer structure. Finally, the first substrate 80 is removed, and the chip 100 is positioned on the side of the first line layer 10 away from the remaining line layers. The method proposed in this application effectively solves the problem of unevenness on the surface of the line layers closer to the chip 100. Furthermore, fabricating multiple line layers using this method avoids the need for planarization of the surface of the line layers closer to the chip 100, significantly reducing packaging costs.

[0089] In one implementation, please refer to Figure 10 , Figure 10 This is a cross-sectional structural diagram corresponding to one embodiment after step S204. Specifically, after step S204, the method further includes: forming an underfill 70 on the side of the third dielectric layer 60 away from the first line layer 10. The underfill 70 at least covers a portion of the first conductive pillars 64, conductive bumps 105, solder 110, and the functional surface 101 of the chip 100. By forming the underfill 70, the functional surface 101 of the chip 100, a portion of the first conductive pillars 64, and the conductive bumps 105 can be fixed and protected to a certain extent.

[0090] In one implementation, please refer to Figure 11 , Figure 11 This is a cross-sectional view of another embodiment following step S204. Specifically, after step S204, a molding compound 75 is formed on the side of the third dielectric layer 60 away from the first line layer 10. The molding compound 75 covers the chip 100 and the surface of the third dielectric layer 60 away from the first line layer 10. The molding compound 75 can be made of epoxy resin or the like. In this embodiment, an underfill 70 is provided on the side of the third dielectric layer 60 away from the first line layer 10, and the molding compound 75 covers the underfill 70. The molding compound 75 can provide a certain degree of fixation and protection for the chip 100. Alternatively, in other embodiments, the underfill 70 may not be provided; instead, the molding compound 75 fills the portion between the functional surface 101 of the chip 100 and the third dielectric layer 60, providing a certain degree of fixation and protection for the device on the side of the third dielectric layer 60 away from the first line layer 10.

[0091] In another implementation, please refer to Figure 12 , Figure 12 This is a flowchart illustrating another embodiment of the fan-out packaging method proposed in this application. The specific implementation steps of this embodiment include:

[0092] S301: Remove the second substrate and form a fourth dielectric layer on the side of the third line layer away from the second line layer.

[0093] Please combine Figure 11 See Figure 13 , Figure 13 This is a cross-sectional view of step S301 corresponding to one embodiment. Specifically, the implementation process of step S301 includes: removing the second carrier plate 90 to expose the third line layer 30. The second carrier plate 90 can be removed by melting the bonding adhesive layer between the second carrier plate 90 and the third line layer 30. Further, a fourth dielectric layer 120 is formed on the side of the third line layer 30 away from the second line layer 20, covering the portion of the third line layer 30 exposed from the second dielectric layer 50. The fourth dielectric layer 120 can be made of polyimide, poly(p-phenylenebenzobisoxazole) fiber, benzocyclobutene, or PSR material, etc. Forming the fourth dielectric layer 120 helps to protect the surface of the third line layer 30 away from the second line layer 20 and facilitates the connection of other devices to the third line layer 30 via the fourth dielectric layer 120.

[0094] S302: Multiple third openings are formed on the fourth dielectric layer.

[0095] Please see Figure 14 , Figure 14 This is a cross-sectional view of an embodiment corresponding to step S302. Specifically, the implementation process of step S302 includes: forming a plurality of third openings 122 on the fourth dielectric layer 120, with a portion of the third line layer 30 exposed through the third openings 122. The plurality of third openings 122 can be formed on the fourth dielectric layer 120 by means of polishing or the like. Forming the third openings 122 facilitates the execution of step S303.

[0096] S303: Form a solder ball within the third opening.

[0097] Please see Figure 15 , Figure 15 This is a cross-sectional view of an embodiment corresponding to step S303. Specifically, the implementation process of step S303 includes: forming solder balls 124 within the third opening 122. The solder balls 124 are electrically connected to a portion of the third line layer 30 through the third opening 122. The portion of the solder balls 124 exposed in the fourth dielectric layer 120 can be connected to the substrate or other devices to facilitate information interaction.

[0098] Optionally, please refer to Figure 16 , Figure 16This is a cross-sectional view of step S303 corresponding to another embodiment. Specifically, in other embodiments, step S303 includes: forming a copper pillar 126 within the third opening 122 using a sputtering process. One end of the copper pillar 126 is electrically connected to a portion of the third line layer 30, and the other end is exposed from the fourth dielectric layer 120. Further, a solder ball 124 is formed at the end of the copper pillar 126 away from the third line layer 30. The solder ball 124 can be connected to the substrate or other devices to achieve information interaction.

[0099] In another implementation, please refer to Figure 17 , Figure 17 This is a flowchart illustrating another embodiment of the fan-out packaging method proposed in this application. Specifically, in this embodiment, the fan-out packaging method proposed in this application includes:

[0100] S401: Provide a first carrier plate, the first carrier plate including a first surface and a second surface disposed opposite to each other, and a first line layer is formed on one side of the first surface.

[0101] Please see Figure 2 The specific implementation process of step S401 includes: providing a first carrier plate 80, which includes a first surface 81 and a second surface 82 disposed opposite to each other. The material of the first carrier plate 80 can be one of silicon, glass, metal, or organic composite materials.

[0102] Further, a protective layer 12 is formed on the first surface 81 of the first carrier 80, and a first photoresist layer 14 is formed on the side of the protective layer 12 away from the first carrier 80. A patterned first opening 16 is formed on the first photoresist layer 14, and a portion of the protective layer 12 is exposed through the first opening 16. Further, a first line layer 10 is formed by filling the first opening 16 with conductive metal, and the first photoresist layer 14 is removed. The first line layer 10 includes a plurality of first metal lines 11, with a first spacing 13 between adjacent first metal lines 11. The specific implementation process of step S401 can be found in [reference needed]. Figure 1 Step S101 will not be described in detail here.

[0103] S402: A first dielectric layer is formed on the side of the first line layer away from the first substrate, and a plurality of first vias are provided at the position of the first dielectric layer corresponding to the first line layer.

[0104] Please see Figure 18 , Figure 18This is a cross-sectional view of step S402 corresponding to one embodiment. Specifically, the implementation process of step S402 includes: forming a first dielectric layer 40 on the side of the first line layer 10 away from the first carrier plate 80, the first dielectric layer 40 covering the first line layer 10. The material of the first dielectric layer 40 can be polyimide, poly(p-phenylenebenzobisoxazole) fiber, benzocyclobutene, or PSR material, etc. Further, a plurality of first vias 41 are formed on the first dielectric layer 40, and a portion of the first line layer 10 is exposed through the first vias 41. Specifically, the first vias 41 can be formed on the first dielectric layer 40 by grinding or other methods. In this embodiment, the inner diameter of the first vias 41 gradually increases in the direction away from the first carrier plate 80. By forming a structure with a gradually increasing inner diameter in the direction away from the first carrier plate 80, the stability of the packaging structure can be improved.

[0105] S403: A second line layer is formed on the first dielectric layer along the inner wall of the first through hole and the portion adjacent to the first through hole.

[0106] Please see Figure 19 , Figure 19 This is a cross-sectional structural diagram corresponding to step S403 in one embodiment. Specifically, the implementation process of step S403 includes: forming a second line layer 20 along the inner wall of the first through hole 41 and on the portion of the first dielectric layer 40 adjacent to the first through hole 41. Specifically, a conductive metal can be first deposited on the inner wall of the first through hole 41 by sputtering, and then a conductive metal can be deposited on the portion of the first dielectric layer 40 adjacent to the first through hole 41. Of course, a conductive metal can also be deposited on the first through hole 41 and the portion of the first dielectric layer 40 adjacent to the first through hole 41 simultaneously to form the second line layer 20. The thickness of the deposited conductive metal is less than the depth of the first through hole 41, that is, the thickness of the second line layer 20 is less than the depth of the first through hole 41. The material of the conductive metal is copper or other conductive metal; the conductive metal on the inner wall of the first through hole 41 and the conductive metal on the portion of the first dielectric layer 40 adjacent to the first through hole 41 together constitute the second line layer 20, and the second line layer 20 is electrically connected to the first line layer 10 through the first through hole 41. The second line layer 20 includes a plurality of second metal lines 21, with a second interval 23 between adjacent second metal lines 21, and the second interval 23 is greater than the first interval 13.

[0107] S404: A second dielectric layer is formed on the side of the second line layer away from the first line layer.

[0108] Please see Figure 20 , Figure 20This is a cross-sectional structural diagram corresponding to one embodiment of step S404. Specifically, the implementation process of step S404 includes: forming a second dielectric layer 50 on the side of the second line layer 20 opposite to the first line layer 10, the second dielectric layer 50 covering the second line layer 20 and filling the first via 41. The material of the second dielectric layer 50 can be polyimide, poly(p-phenylenebenzobisoxazole) fiber, benzocyclobutene, or PSR material, etc.

[0109] For further information, please refer to [link / reference]. Figure 20 Following step S404, the process further includes: disposing a second carrier plate 90 on the side of the second dielectric layer 50 away from the first line layer. The second carrier plate 90 can be made of silicon, glass, metal, or organic composite materials. The second carrier plate 90 provides some protection for the second dielectric layer 50.

[0110] S405: Remove the first substrate and place the chip on the side of the first line layer away from the second line layer.

[0111] Please see Figure 21 , Figure 21 This is a flowchart illustrating step S405 in one embodiment. Specifically, the implementation process of step S405 includes:

[0112] S501: Remove the first carrier board and protective layer, and form a third dielectric layer on the side of the first line layer away from the second line layer.

[0113] Please see Figure 22 , Figure 22 This is a cross-sectional view of an embodiment corresponding to step S501. Specifically, the implementation process of step S501 includes: removing the first carrier plate 80 and the protective layer 12 to expose a portion of the first wire layer 10, with the exposed first wire layer 10 facing upwards. Further, a third dielectric layer 60 is formed on the side of the first wire layer 10 away from the second wire layer 20. The material of the third dielectric layer 60 can be polyimide, poly(p-phenylenebenzobisoxazole) fiber, benzocyclobutene, or PSR material, etc. Forming the third dielectric layer 60 can provide a certain degree of protection for the first wire layer 10 and facilitate the execution of step S502.

[0114] S502: A second opening is formed on the third dielectric layer.

[0115] Please see Figure 23 , Figure 23 This is a cross-sectional structural diagram corresponding to one embodiment of step S502. Specifically, the implementation process of step S502 includes: forming a second opening 62 on the third dielectric layer 60, with a portion of the first line layer 10 exposed through the second opening 62. The specific implementation process can be found in [reference needed]. Figure 5 Step S202 will not be described in detail here.

[0116] S503: A first conductive post is formed inside the second opening.

[0117] Please see Figure 24 , Figure 24 This is a cross-sectional structural diagram corresponding to one embodiment of step S503. Specifically, the implementation process of step S503 includes: forming a first conductive post 64 within the second opening 62, and the first conductive post 64 being electrically connected to the first line layer 10. For detailed implementation process, please refer to... Figure 7 Step S203 will not be described in detail here.

[0118] S504: Multiple conductive bumps are formed on the functional surface of the chip, so that the functional surface of the chip faces the first line layer.

[0119] Please combine Figure 24 See Figure 25 , Figure 25 This is a cross-sectional structural diagram corresponding to one embodiment of step S503. Specifically, the implementation process of step S504 includes: providing a chip 100, which includes a functional surface 101 and a non-functional surface 102 disposed opposite to each other. A plurality of conductive bumps 105 are formed on the functional surface 101 of the chip 100, and the conductive bumps 105 are electrically connected to the pads 103 of the chip 100. Further, the functional surface 101 of the chip 100 is oriented towards the first line layer 10, so that the conductive bumps 105 are electrically connected to the first conductive post 64. The specific implementation process can be found in [reference needed]. Figure 5 Step S204 will not be described in detail here.

[0120] The fan-out packaging method proposed in this application first fabricates a first line layer on a first substrate, closer to the chip, and then sequentially fabricates the remaining line layers. The spacing between the line layers gradually increases in the direction away from the chip, facilitating the chip's connection to other devices or substrates through the multi-line layer structure. Finally, the first substrate is removed, and the chip is positioned on the side of the first line layer away from the remaining line layers. This method effectively solves the problem of unevenness on the surface of the line layers closer to the chip, and by fabricating multiple line layers using this method, planarization of the surface of the line layers closer to the chip is avoided, significantly reducing packaging costs.

[0121] In one implementation, please refer to Figure 26 , Figure 26This is a cross-sectional structural diagram corresponding to one embodiment after step S504. Specifically, after step S204, the method further includes: forming an underfill 70 on the side of the third dielectric layer 60 away from the first line layer 10. The underfill 70 at least covers a portion of the first conductive pillars 64, conductive bumps 105, solder 110, and the functional surface 101 of the chip 100. By forming the underfill 70, the functional surface 101 of the chip 100, a portion of the first conductive pillars 64, and the conductive bumps 105 can be fixed and protected to a certain extent.

[0122] In one implementation, please refer to Figure 26 See Figure 27 , Figure 27 This is a cross-sectional view of another embodiment following step S504. Specifically, after step S504, a molding compound 75 is formed on the side of the third dielectric layer 60 away from the first line layer 10. The molding compound 75 covers the chip 100 and the surface of the third dielectric layer away from the first line layer 10. The molding compound 75 can be made of epoxy resin or the like. In this embodiment, an underfill 70 is provided on the side of the third dielectric layer 60 away from the first line layer 10, and the molding compound 75 covers the underfill 70. The molding compound 75 provides a certain degree of fixation and protection for the chip 100. Alternatively, in other embodiments, the underfill 70 may be omitted, and the molding compound 75 may fill the portion between the functional surface 101 of the chip 100 and the third dielectric layer 60, providing a certain degree of fixation and protection for the device on the side of the third dielectric layer 60 away from the first line layer 10.

[0123] In another embodiment, please refer to Figure 27 See Figure 28 , Figure 28 This is a cross-sectional structural schematic diagram of another embodiment of the fan-out packaging method proposed in this application. Specifically, the specific implementation steps of this embodiment include: removing the second carrier board 90 to expose the second dielectric layer 50. Further, forming a plurality of third openings 122 on the second dielectric layer 50, with a portion of the second line layer 20 exposed from the third openings 122. Solder balls 124 are formed within the third openings 122. The portion of the solder balls 124 exposed from the second dielectric layer 50 can be connected to the substrate or other devices to facilitate information interaction.

[0124] Optionally, please refer to Figure 29 , Figure 29This is a cross-sectional structural schematic diagram of another embodiment of the fan-out packaging method proposed in this application. Specifically, in this embodiment, a copper pillar 126 can be formed in the third opening 122 by a sputtering process. One end of the copper pillar 126 is electrically connected to a portion of the second line layer 20, and the other end is exposed from the second dielectric layer 50. Further, a solder ball 124 is formed at the end of the copper pillar 126 away from the second line layer 20 to facilitate the connection of the solder ball 124 with the substrate or other devices and to achieve information exchange.

[0125] In another embodiment, Figure 17 The corresponding fan-out packaging method can also include fabricating a multi-layer structure; for details, please refer to [link to relevant documentation]. Figure 30 , Figure 30 for Figure 17 A cross-sectional structural diagram corresponding to one embodiment following step S401. Figure 17 After forming the first line layer 10 on one side of the first surface 81 in step S401, the method further includes forming a fourth dielectric layer 120 on the side of the first line layer 10 away from the first substrate 80. A plurality of second vias 51 are formed on the fourth dielectric layer 120. A portion of the first line layer 10 is exposed through the second vias 51. Further, conductive metal is filled into the second vias 51 to form a third line layer 30. The third line layer 30 is electrically connected to the first line layer 10. The third line layer 30 includes a plurality of third metal lines 31, with a third spacing 33 between adjacent third metal lines 31, the third spacing 33 being larger than the first spacing 13. In this embodiment, in the direction away from the first substrate 80, the second via 51 includes a first sub-via 43 and a second sub-via 45 that are interconnected, and the first sub-via 43 is closer to the first line layer 10 than the second sub-via 45, and the average inner diameter of the first sub-via 43 is smaller than the average inner diameter of the second sub-via 45. Furthermore, in the direction away from the first carrier plate 80, the inner diameter of the first sub-via 43 gradually increases. And / or, in the direction away from the first carrier plate 80, the inner diameter of the second sub-via 45 is the same. In this embodiment, the specific fabrication process of the third line layer 30 can be referred to Figure 1 Step S102 will not be described again here. Optionally, in other embodiments, the third line layer 30 can also be formed by the method described in steps S402-S403.

[0126] In addition, after fabricating the third line layer 30, this embodiment also includes fabricating a second line layer 20 on the side of the third line layer 30 away from the first substrate 80. The specific process can be referred to steps S402-S405, and will not be repeated here. It should be noted that in this embodiment, the third line layer 30 is an intermediate structure between the first line layer 10 and the second line layer 20. The third interval 33 between adjacent third metal lines 31 in the third line layer 30 is smaller than the second interval 23 between adjacent second metal lines 21 in the second line layer 20, so as to facilitate the connection of the chip 100 with other devices or substrates through the multi-line layer structure.

[0127] In another implementation, please refer to Figure 31 , Figure 31 This is a flowchart illustrating another embodiment of the fan-out packaging method of this application. The specific implementation process of this embodiment includes:

[0128] S601: A first carrier plate is provided, the first carrier plate including a first surface and a second surface disposed opposite to each other, and a first line layer and a second line layer are sequentially formed on the first surface.

[0129] Please see Figure 32 , Figure 32 This is a flowchart illustrating step S601 corresponding to one embodiment. Specifically, step S601 includes:

[0130] S701: A protective layer is formed on the first surface of the first carrier plate. A first line layer is formed on the side of the protective layer away from the first carrier plate.

[0131] Please continue reading. Figure 2 Step S701 includes: providing a first carrier plate 80, the first carrier plate 80 including a first surface 81 and a second surface 82 disposed opposite to each other, and forming a protective layer 12 on the first surface 81 of the first carrier plate 80. A first photoresist layer 14 is formed on the side of the protective layer 12 away from the first carrier plate 80, and a patterned first opening 16 is formed on the first photoresist layer 14, with a portion of the protective layer 12 exposed through the first opening 16. Further, conductive metal is filled into the first opening 16 to form a first line layer 10, and the first photoresist layer 14 is removed. The first line layer 10 includes a plurality of first metal lines 11, with a first spacing 13 between adjacent first metal lines 11. The specific implementation process of this step can be found in [reference needed]. Figure 1 Step S101 will not be described in detail here.

[0132] S702: A second line layer is formed on the side of the first line layer away from the first carrier plate.

[0133] In one implementation, please refer to Figure 3Step S702 includes: forming a first dielectric layer 40 on the side of the first line layer 10 away from the first carrier plate 80, the first dielectric layer 40 covering the first line layer 10. A plurality of first vias 41 are formed on the first dielectric layer 40. A portion of the first line layer 10 is exposed through the first vias 41. Further, conductive metal is filled into all the first vias 41 to form a second line layer 20, and the thickness of the second line layer 20 is the same as the depth of the first vias 41. In the direction away from the first carrier plate 80, the first vias 41 include interconnected first sub-vias 43 and second sub-vias 45, and the first sub-vias 43 are closer to the first line layer 10 than the second sub-vias 45, with the average inner diameter of the first sub-vias 43 being smaller than the average inner diameter of the second sub-vias 45. Additionally, in the direction away from the first carrier plate 80, the inner diameter of the first sub-vias 43 gradually increases; and / or, in the direction away from the first carrier plate 80, the inner diameter of the second sub-vias 45 is the same. In this embodiment, the specific implementation process of step S702 can be referred to Figure 1 Step S102 will not be described in detail here.

[0134] In another implementation, please refer to Figure 18 and Figure 19 Step S702 includes: forming a first dielectric layer 40 on the side of the first line layer 10 away from the first carrier plate 80, and forming a plurality of first vias 41 on the first dielectric layer 40. A portion of the first line layer 10 is exposed through the first vias 41. A conductive metal is filled into the inner wall of the first vias 41 and the portion of the first dielectric layer adjacent to the inner wall on the side away from the first line layer 10 to form a second line layer 20. The thickness of the second line layer 20 is less than the depth of the first vias 41. In this embodiment, the specific implementation process of step S702 can be referred to... Figure 17 Steps S402-S403 will not be described in detail here.

[0135] In another embodiment, in response to the fan-out packaging method proposed in this application, a multi-layer structure can be fabricated. After forming the second layer 20, step S702 can also include fabricating a third layer on the side of the second layer 20 away from the first layer 10. The specific fabrication method can be referred to step S702 above, and will not be repeated here.

[0136] In yet another implementation, please refer to Figure 33 , Figure 33This is a cross-sectional structural diagram corresponding to one embodiment after step S702. Specifically, after step S702, the method further includes: forming a second dielectric layer 50 on the side of the second wire layer 20 away from the first carrier plate 80. The second dielectric layer 50 covers the portion of the second wire layer 20 exposed from the first dielectric layer 40, thereby providing some protection for the second wire layer 20. Further, a second carrier plate 90 is disposed on the side of the second dielectric layer 50 away from the second wire layer 20. Wherein, when the thickness of the second wire layer 20 is less than the depth of the first through-hole 41, such as... Figure 33 As shown in Figure a; when the thickness of the second line layer 20 is the same as the depth of the first through hole 41, as... Figure 33 As shown in Figure b.

[0137] S602: Remove the first carrier plate and form a plurality of first conductive pillars on the side of the first line layer away from the second line layer.

[0138] When the thickness of the second line layer 20 is the same as the depth of the first through-hole 41, please combine Figure 33 See Figure 34 , Figure 34 This is a cross-sectional structural diagram corresponding to one embodiment of step S602. Specifically, the implementation process of step S602 includes: Figure 34 As shown in Figure a, the first carrier plate 80 and the protective layer 12 are removed, and the second carrier plate 90 is positioned downwards on the side away from the first wire layer 10. A third dielectric layer 60 is formed on the side of the first wire layer 10 away from the second wire layer 20. The third dielectric layer 60 has multiple second openings 62 and multiple third openings 122. A portion of the first wire layer 10 is exposed through one of the second openings 62 or the third opening 122. Specifically, the second opening 62 is located around the third opening 122, and the inner diameter of the second opening 62 is larger than the inner diameter of the third opening 122. Further, as... Figure 34 As shown in Figure b, conductive metal is filled into the second opening 62 to form a connector 66, which protrudes from the third dielectric layer 60. Forming the connector 66 facilitates the formation of the first conductive pillar 64. A second conductive pillar 68 is formed in the third opening 122, also protruding from the third dielectric layer 60. The height of the connector 66 is the same as the height of the second conductive pillar 68. Forming the second conductive pillar 68 facilitates the execution of step S603.

[0139] Furthermore, such as Figure 34As shown in Figure c, a second photoresist layer 130 is formed on the side of the third dielectric layer 60 away from the first line layer 10. The second photoresist layer 130 covers the portions of the second conductive pillar 68 and the connector 66 exposed in the third dielectric layer 60. A fourth opening 132 is provided in the second photoresist layer 130 corresponding to the position of the connector 66, through which the connector 66 is exposed. The fourth opening 132 can be formed by removing a portion of the second photoresist layer 130 through exposure and development.

[0140] Furthermore, such as Figure 34 As shown in Figure d, conductive metal is filled into the fourth opening 132 to form a first conductive pillar 64, and the second photoresist layer 130 is removed. The first conductive pillar 64 is tightly connected to the connector 66 and electrically connected to the first line layer 10 through the connector 66. In this embodiment, the first conductive pillar 64 and the second conductive pillar 68 are cylindrical, and the diameter of the cross-section of the first conductive pillar 64 is larger than the diameter of the cross-section of the second conductive pillar 68. Optionally, in other embodiments, the first conductive pillar 64 and the second conductive pillar 68 may also be prismatic or the like, and the cross-sectional area of ​​the first conductive pillar 64 is larger than the cross-sectional area of ​​the second conductive pillar 68.

[0141] S603: The chip is placed on the side of the first line layer away from the second line layer.

[0142] When the thickness of the second line layer 20 is the same as the depth of the first via 41, please refer to... Figure 35 , Figure 35 This is a cross-sectional structural diagram corresponding to one embodiment of step S603. Specifically, the implementation process of step S603 includes: providing a chip 100, which includes a functional surface 101 and a non-functional surface 102 disposed opposite to each other. A plurality of pads 103 are disposed on the functional surface 101 of the chip 100. A plurality of conductive bumps 105 are formed on the functional surface 101 of the chip 100, and the conductive bumps 105 are electrically connected to the pads 103 of the chip 100. Further, the functional surface 101 of the chip 100 is oriented towards the first line layer 10, so that the conductive bumps 105 are electrically connected to the second conductive post 68. The specific implementation process can be referred to... Figure 5 Step S204 will not be described in detail here. It should be noted that in this embodiment, the first conductive post 64 surrounds the periphery of the chip 100, and the first conductive post 64 is electrically connected to the chip 100 through the first line layer 10, the second conductive post 68, and the conductive bump 105.

[0143] S604: A molding layer is formed on the side of the first line layer away from the second line layer.

[0144] Please see Figure 36 , Figure 36This is a cross-sectional structural diagram corresponding to one embodiment before step S604. Specifically, before step S604 is implemented, an underfill 70 is formed on the side of the third dielectric layer 60 away from the first line layer 10. The underfill 70 at least covers part of the second conductive pillar 68, the conductive bump 105, and the functional surface 101 of the chip 100, so as to play a certain role in fixing and protecting the device between the functional surface 101 and the first line layer 10.

[0145] Further, please refer to Figure 37 , Figure 37 This is a cross-sectional view of step S604 corresponding to one embodiment. Specifically, step S604 includes: forming a molding compound 75 on the side of the third dielectric layer 60 away from the first line layer 10, the molding compound 75 covering the chip 100 and the surface of the third dielectric layer 60 away from the first line layer 10. The molding compound 75 can be made of epoxy resin or the like. After forming the molding compound 75, the surface of the molding compound 75 away from the first line layer 10 is ground to expose the first conductive post 64. In this embodiment, an underfill 70 is provided on the side of the third dielectric layer 60 away from the first line layer 10, and the molding compound 75 covers the underfill 70. In other applications, the underfill 70 may not be provided; instead, the molding compound 75 fills the portion between the functional surface 101 of the chip 100 and the third dielectric layer 60, providing some fixation and protection for the device on the side of the third dielectric layer 60 away from the first line layer 10.

[0146] In another embodiment, Figure 31 The thickness of the second line layer 20 formed in step S601 can also be less than the depth of the first through hole 41. For specific structure details, please refer to [reference needed]. Figure 33 Figure a shows the steps after forming the second layer 20, which can be referred to. Figure 31 Steps S602-S604 will not be described in detail here.

[0147] The fan-out packaging method proposed in this application first fabricates a first line layer 10 on a first substrate, closer to the chip, and then sequentially fabricates the remaining line layers. The spacing between the line layers gradually increases in the direction away from the chip 100, facilitating the connection of the chip 100 to other devices or substrates through the multi-line layer structure. Finally, the first substrate 80 is removed, and the chip 100 is positioned on the side of the first line layer 10 away from the remaining line layers. The method proposed in this application effectively solves the problem of unevenness on the surface of the line layers closer to the chip 100. Furthermore, fabricating multiple line layers using the method proposed in this application avoids the need for planarization treatment on the surface of the line layers closer to the chip 100, significantly reducing packaging costs.

[0148] In one implementation, please refer to Figure 38 , Figure 38This is a cross-sectional structural diagram of another embodiment following step S604. Specifically, step S604 further includes: as... Figure 38 As shown in Figure a, a fourth dielectric layer 120 is formed on the side of the molding compound 75 away from the first line layer 10. The fourth dielectric layer 120 at the location corresponding to the first conductive post 64 is removed to form a sixth opening 128, exposing the first conductive post 64 through the sixth opening 128. Further, as... Figure 38 As shown in Figure b, a fourth line layer 140 is formed by filling the fourth dielectric layer 120 on the side away from the first line layer 10 and within the sixth opening 128 with conductive metal. The material of the fourth line layer 140 can be copper or other conductive metals. Further, as... Figure 38 As shown in Figure c, a fifth dielectric layer 150 is formed on the side of the fourth line layer 140 away from the first conductive pillar 64. Multiple seventh openings 152 are provided on the fifth dielectric layer 150, through which a portion of the fourth line layer 140 is exposed to facilitate subsequent connection of devices to the fourth line layer 140 via the seventh openings 152. The material of the fifth dielectric layer 150 can be polyimide, poly(p-phenylenebenzobisoxazole) fiber, benzocyclobutene, or PSR material, etc.

[0149] In one implementation, please refer to Figure 38 See Figure 39 , Figure 39 This is a cross-sectional view of another embodiment following step S604. Specifically, after step S604, the method may further include: removing the second substrate 90, forming a plurality of fifth openings 57 on the second dielectric layer 50, with a portion of the second line layer 20 exposed through the fifth openings 57. Further, solder balls 124 electrically connected to the second line layer 20 are formed in the fifth openings 57 to facilitate information interaction between the chip 100 and the substrate or other devices via the solder balls 124. Optionally, in other embodiments, a conductive metal pillar may be formed first within the fifth opening 57, with one end of the metal pillar electrically connected to the second line layer 20 through the fifth opening 57, and solder balls 124 disposed at the other end of the metal pillar. For details, please refer to... Figure 12 Step S303 will not be described in detail here.

[0150] Please see Figure 40 , Figure 40 This is a cross-sectional structural schematic diagram of an embodiment of the fan-out packaging device of this application. The fan-out packaging device proposed in this application includes: a chip 100, a first line layer 10, a second line layer 20, and a molding compound 75.

[0151] Specifically, chip 100 includes a functional surface 101 and a non-functional surface 102 arranged opposite to each other, and the functional surface 101 has multiple pads 103. It should be noted that... Figure 40Only four pads 103 are drawn on the functional surface 101 of the chip 100; however, in practical applications, the functional surface 101 of the chip 100 may include multiple pads 103. Furthermore, Figure 40 Only one chip 100 is shown in the figure. However, in practical applications, multiple chips 100 can be packaged at the same time. After the packaging of all chips 100 is completed, the middle part of adjacent chips 100 is removed to form a single fan-out package device.

[0152] Please combine Figure 40 See Figure 41 , Figure 41 This is an enlarged cross-sectional view of a portion of the first line layer 10 and a portion of the second line layer 20. The first line layer 10 is located on one side of the functional surface 101 of the chip 100 and is electrically connected to the pads 103. The material of the first line layer 10 can be copper or other conductive metals. The first line layer 10 includes a plurality of first metal lines 11, and there is a first spacing 13 between adjacent first metal lines 11.

[0153] Please continue to combine Figure 40 See Figure 41 The second line layer 20 is located on the side of the first line layer 10 away from the chip 100. The material of the second line layer 20 can be copper or other conductive metals. The second line layer 20 includes a plurality of second metal lines 21, with a second spacing 23 between adjacent second metal lines 21, and a first spacing 13 smaller than the second spacing 23. Furthermore, in the fan-out package device proposed in this application, the first line layer 10 is formed before the second line layer 20; that is, the first line layer 10 is fabricated first on the side closer to the chip 100, and then the second line layer 20 is fabricated on the side of the first line layer 10 away from the chip 100. By fabricating the first line layer 10 first, the unevenness problem of the line layer surface on the side closer to the chip 100 can be effectively solved, and the subsequent planarization treatment of the line layer surface on the side closer to the chip 100 can be avoided, greatly reducing the packaging cost.

[0154] The molding compound 75 is located on the side of the first line layer 10 away from the second line layer 20, and the chip 100 is located within the molding compound 75. The molding compound 75 can be made of epoxy resin or the like.

[0155] In the fan-out package device proposed in this application, a multi-layer line structure is provided in the direction away from the chip 100, and the spacing between the line layers gradually increases in the direction away from the chip 100, so as to facilitate the connection of the chip 100 with other devices or substrates through the multi-layer line structure. The fan-out package device proposed in this application first manufactures the first line layer 10 on the side close to the chip 100, and then manufactures the remaining line layers in sequence. This can effectively solve the problem of unevenness on the surface of the line layers on the side close to the chip 100, and can avoid the need to perform planarization treatment on the surface of the line layers on the side close to the chip 100, thus greatly reducing the packaging cost.

[0156] Please continue to combine Figure 40 See Figure 41 In one embodiment, the fan-out packaging device proposed in this application further includes a first dielectric layer 40, located on the side of the first line layer 10 facing away from the chip 100. The material of the first dielectric layer 40 can be polyimide, poly(p-phenylenebenzobisoxazole) fiber, benzocyclobutene, or PSR material, etc., and the first dielectric layer 40 can provide a certain degree of protection for the first line layer 10 and the second line layer 20. For example, Figure 41 The first dielectric layer 40 shown has a first via 41, through which a portion of the first line layer 10 is exposed. In this embodiment, the second line layer 20 fills all the first vias 41, and the thickness of the second line layer 20 is the same as the depth of the first vias 41. This structure is simpler to fabricate by filling all the first vias 41 with conductive metal. In this embodiment, in the direction away from the first line layer 10, the first via 41 includes a first sub-via 43 and a second sub-via 45 that are interconnected. The first sub-via 43 is closer to the first line layer 10 than the second sub-via 45, and the average inner diameter of the first sub-via 43 is smaller than the average inner diameter of the second sub-via 45. By setting the first sub-via 43 and the second sub-via 45 to have different inner diameters, it helps to save materials and reduce the manufacturing cost of the packaged device. Furthermore, the inner diameter of the first sub-via 43 gradually increases in the direction away from the first line layer 10; and / or, the inner diameter of the second sub-via 45 is the same in the direction away from the first line layer 10. Optionally, in other embodiments, the inner diameter of the first sub-via 43 may also be the same, but by fabricating a structure in which the inner diameter of the first sub-via 43 gradually increases in the direction away from the first line layer 10, it is more helpful to enhance the stability of the packaged device and improve its durability.

[0157] Please continue reading. Figure 40 In this embodiment, the fan-out packaged device proposed in this application further includes a second dielectric layer 50, located on the side of the first line layer 10 away from the second line layer 20, and covering the surface of the first line layer 10 on the side away from the second line layer 20. The material of the second dielectric layer 50 can be the same as that of the first dielectric layer 40, and the second dielectric layer 50 can provide a certain degree of protection for the surface of the first line layer 10 away from the second line layer 20. The second dielectric layer 50 includes a plurality of first openings 16, through which a portion of the first line layer 10 is exposed.

[0158] In this embodiment, the fan-out packaged device proposed in this application further includes a plurality of conductive bumps 105 and a plurality of first conductive posts 64. The plurality of conductive bumps 105 are located on the functional surface 101 of the chip 100, and are electrically connected to the pads 103 of the chip 100 to facilitate the connection of the chip 100 to other devices via the conductive bumps 105. The plurality of first conductive posts 64 are at least partially located within the first opening 16, with one end of each first conductive post 64 electrically connected to the first line layer 10 through the first opening 16, and the other end electrically connected to the conductive bumps 105. Through the first conductive posts 64 and the conductive bumps 105, the chip 100 can achieve electrical connection with the first line layer 10. In this embodiment, the molding layer 75 covers the conductive bumps 105 and the portions of the first conductive posts 64 exposed in the second dielectric layer 50, providing them with a certain degree of protection.

[0159] In this embodiment, please continue to refer to Figure 40 The fan-out package device proposed in this application further includes a third dielectric layer 60, located on the side of the second line layer 20 facing away from the chip 100. The third dielectric layer 60 covers the portion of the second line layer 20 exposed from the first dielectric layer 40, providing some protection for the exposed second line layer 20. Additionally, the third dielectric layer 60 has multiple second openings 62, through which a portion of the second line layer 20 is exposed. Solder balls 124 are disposed within each second opening 62, and the solder balls 124 are electrically connected to the second line layer 20 through the second opening 62. The solder balls 124 facilitate the connection of the package device to the substrate or other devices. Optionally, in other embodiments, metal pillars may also be disposed within the second openings 62, with a portion of the metal pillar exposed from the second opening 62. One end of the metal pillar is electrically connected to the second line layer 20, and the other end is provided with a solder ball 124. The specific structure is not described in detail here.

[0160] In yet another implementation, please refer to Figure 42 , Figure 42 This is a cross-sectional structural diagram of another embodiment of the fan-out packaging device of this application. The fan-out packaging device proposed in this application also includes an underfill 70, located on the side of the second dielectric layer 50 away from the first line layer 10. The underfill 70 covers the functional surface 101, conductive bumps 105 and part of the first conductive pillars 64 of the chip 100, and plays a certain role in fixing and protecting them.

[0161] In yet another implementation, please refer to Figure 43 , Figure 43This is a cross-sectional view of another embodiment of the fan-out packaged device of this application. In this embodiment, the second line layer 20 covers the inner wall of the first through-hole 41 and the portion of the first dielectric layer 40 adjacent to the inner wall on the side away from the first line layer 10. The inner diameter of the first through-hole 41 gradually increases in the direction away from the first line layer 10 to improve the stability of the packaged device; the thickness of the second line layer 20 is less than the depth of the first through-hole 41. Forming the second line layer 20 along the inner wall of the first through-hole 41 can effectively save on packaging material costs. In this embodiment, the third dielectric layer 60 covers the portion of the second line layer 20 exposed from the first dielectric layer 40 and fills the first through-hole 41 to provide some protection for the second line layer 20. The third dielectric layer 60 has multiple second openings 62, through which a portion of the second line layer 20 is exposed. Solder balls 124 are disposed within the second openings 62, and the solder balls 124 are electrically connected to the second line layer 20 through the second openings 62.

[0162] In yet another implementation, please refer to Figure 44 , Figure 44 This is a cross-sectional view of another embodiment of the fan-out packaged device of this application. In this embodiment, the fan-out packaged device proposed in this application may further include a multilayer line layer structure, that is, a fourth dielectric layer 120 is formed on the side of the second line layer 20 away from the first line layer 10, and a plurality of second vias 51 are provided on the fourth dielectric layer 120. The third line layer 30 fills the second vias 51, and the second vias 51 include a third sub-via 53 and a fourth sub-via 55. A third dielectric layer 60 is provided on the side of the third line layer 30 away from the chip 100, and a plurality of second openings 62 are provided on the third dielectric layer 60. The solder balls 124 are electrically connected to the third line layer 30 through the second openings 62. The structure of the second vias 51 can be referred to Figure 41 The structure of the first via 41 will not be described in detail here. Optionally, the third line layer 30 may also cover the inner wall of the second via 51 and the portion of the fourth dielectric layer 120 adjacent to the inner wall, that is, the structure of the third line layer 30 and the second via 51 may also be as follows. Figure 43 The structure of the first through-hole 41 and the second line layer 20 shown herein will not be described in detail here. It should be noted that the third line layer 30 also contains multiple metal lines, and the spacing between adjacent metal lines is greater than the spacing between adjacent metal lines in the second line layer 20.

[0163] In yet another implementation, please refer to Figure 45 , Figure 45This is a cross-sectional structural diagram of another embodiment of the fan-out packaged device of this application. In this embodiment, the fan-out packaged device of this application further includes: a second conductive post 68, surrounding the periphery of the chip 100. One end of the second conductive post 68 is electrically connected to the first line layer 10, and the other end is exposed from the molding compound layer 75. Specifically, a plurality of connectors 66 are disposed around the first conductive post 64, with portions of the connectors 66 located within the second dielectric layer 50 and electrically connected to the first line layer 10; the second conductive post 68 is electrically connected to the portion of the connectors 66 exposed from the second dielectric layer 50, that is, the second conductive post 68 is electrically connected to the first line layer 10 through the connectors 66. A portion of the second conductive post 68 is exposed from the molding compound layer 75. In response to the first line layer 10 being electrically connected to the chip 100, the second conductive post 68 is electrically connected to the chip 100.

[0164] Please continue reading. Figure 45 In this embodiment, the fan-out packaging device proposed in this application further includes a first photoresist layer 14, a fourth line layer 140, and a fifth dielectric layer 150. The first photoresist layer 14 is located on the side of the molding compound 75 away from the first line layer 10, and a third opening 122 is provided on the first photoresist layer 14, through which the second conductive post 68 is exposed. The fourth line layer 140 is located on the side of the first photoresist layer 14 away from the molding compound 75, and the fourth line layer 140 is electrically connected to the second conductive post 68 through the third opening 122. The fifth dielectric layer 150 is located on the side of the fourth line layer 140 away from the molding compound 75, and a plurality of fourth openings 132 are provided on the fifth dielectric layer 150, through which part of the fourth line layer 140 is exposed to facilitate electrical connection between other devices and the fourth line layer 140. Based on the electrical connection between the second conductive post 68 and the chip 100, the fourth line layer 140 can achieve electrical connection with the chip 100. The packaging device in this embodiment can be connected to the substrate or other devices on both sides to achieve information interaction.

[0165] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A fan-out packaging method, characterized in that, include: A first carrier plate is provided, the first carrier plate including a first surface and a second surface disposed opposite to each other, and a first line layer is formed on one side of the first surface; wherein, the first line layer includes a plurality of first metal lines, and a first interval is provided between adjacent first metal lines; A first dielectric layer is formed on the side of the first line layer away from the first carrier plate, and a plurality of first vias are provided on the first dielectric layer; A second line layer is formed on the first dielectric layer along the inner wall of the first through hole and on the portion of the first dielectric layer adjacent to the first through hole; wherein the second line layer includes a plurality of second metal lines, and there is a second spacing between adjacent second metal lines, the second spacing being larger than the first spacing; A second dielectric layer is formed on the side of the second line layer away from the first line layer, and the second dielectric layer covers the second line layer and fills the first via. Remove the first carrier board and place a chip on the side of the first line layer away from the second line layer. The chip includes functional and non-functional surfaces arranged opposite to each other, and the pads on the functional surface are electrically connected to the first line layer. The step of forming a first line layer on one side of the first surface includes: forming a protective layer on the first surface; forming a first photoresist layer on the side of the protective layer away from the first substrate; forming a patterned first opening on the first photoresist layer, with a portion of the protective layer exposed from the first opening; forming a first line layer within the first opening; and removing the first photoresist layer. The step of forming the first line layer on one side of the first surface further includes: A fourth dielectric layer is formed on the side of the first line layer away from the first carrier plate; A plurality of second vias are formed on the fourth dielectric layer; wherein a portion of the first line layer is exposed through the second vias; A conductive metal is filled into the second through-hole to form a third line layer; wherein the third line layer includes a plurality of third metal lines, and there is a third interval between adjacent third metal lines, the third interval being larger than the first interval and smaller than the second interval.

2. The method according to claim 1, characterized in that, After the step of forming a second dielectric layer on the side of the second line layer away from the first line layer, the method includes: A second carrier plate is disposed on the side of the second dielectric layer away from the first line layer.

3. The method according to claim 1, characterized in that, The step of removing the first carrier board and placing the chip on the side of the first line layer away from the second line layer includes: Remove the first carrier board and the protective layer, and form a third dielectric layer on the side of the first line layer away from the second line layer; A second opening is formed on the third dielectric layer, and a portion of the first line layer is exposed through the second opening; A first conductive post is formed in the second opening, and the first conductive post is electrically connected to the first line layer; Multiple conductive bumps are formed on the functional surface of the chip, and the conductive bumps are electrically connected to the pads of the chip; the functional surface of the chip is oriented toward the first line layer, so that the conductive bumps are electrically connected to the first conductive pillar.

4. The method according to claim 3, characterized in that, After the step of setting the chip on the side of the first line layer away from the second line layer, the method includes: An underfill is formed on the side of the third dielectric layer away from the first line layer, and the underfill covers at least a portion of the first conductive pillar, the conductive bump, and the functional surface of the chip.

5. The method according to claim 3, characterized in that, After the step of setting the chip on the side of the first line layer away from the second line layer, the method includes: A molding compound is formed on the side of the third dielectric layer away from the first line layer, and the molding compound covers the chip and the surface of the third dielectric layer away from the first line layer.

6. The method according to claim 2, characterized in that, include: Remove the second carrier board and form a plurality of third openings on the second dielectric layer, with a portion of the second line layer exposed from the third openings; A solder ball is formed within the third opening.

7. The method according to claim 1, characterized in that, In the direction away from the first carrier plate, the second through hole includes a first sub-through hole and a second sub-through hole that are interconnected, and the first sub-through hole is closer to the first line layer than the second sub-through hole, and the average inner diameter of the first sub-through hole is smaller than the average inner diameter of the second through hole.

8. The method according to claim 7, characterized in that, In the direction away from the first carrier plate, the inner diameter of the first sub-through hole gradually increases; and / or, in the direction away from the first carrier plate, the inner diameter of the second sub-through hole is the same.

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