A shallow trench isolation method and a shallow trench isolation structure

Abstract

The application discloses a shallow trench isolation method and a shallow trench isolation structure. The method comprises the following steps: providing a substrate, the substrate is provided with a storage unit array area and a peripheral circuit control area, the storage unit array area is provided with a first shallow trench, and the peripheral circuit control area is provided with a second shallow trench; forming oxide layers with different thicknesses in the first shallow trench and the second shallow trench, wherein the thickness of the oxide layer in the first shallow trench is smaller than the thickness of the oxide layer in the second shallow trench; and filling a dielectric layer in the second shallow trench. According to the above scheme, the oxide layers with different thicknesses are formed in the shallow trenches of the storage unit array area and the peripheral circuit control area, so that in the subsequent ion implantation process, the dopant can be effectively prevented from entering the peripheral circuit control area, the characteristics of the peripheral circuit control area are ensured, and the performance of the semiconductor device is guaranteed.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and more particularly to a shallow trench isolation method and a shallow trench isolation structure. Background Technology

[0002] In the fabrication of semiconductor devices, shallow trench isolation structures are typically formed on a semiconductor substrate, and oxides are deposited within these structures to provide isolation. However, with the continuous development of science and technology, the size of semiconductor devices is becoming smaller and smaller. After forming the shallow trench isolation, when performing well region ion implantation on the substrate, dopants can easily diffuse to other areas, thus affecting semiconductor performance. Summary of the Invention

[0003] This application provides a shallow trench isolation method and a shallow trench isolation structure, which solves the technical problem in the prior art where the performance of semiconductors is affected by the diffusion of dopants.

[0004] In a first aspect, embodiments of this specification provide a shallow trench isolation method, the method comprising:

[0005] A substrate is provided, on which a memory cell array region and a peripheral circuit control region are formed, the memory cell array region having a first shallow trench and the peripheral circuit control region having a second shallow trench.

[0006] Oxide layers of different thicknesses are formed in the first shallow trench and the second shallow trench, wherein the oxide layer thickness in the first shallow trench is less than the oxide layer thickness in the second shallow trench.

[0007] A dielectric layer is filled within the second shallow trench.

[0008] Optionally, forming oxide layers of different thicknesses in the first shallow trench and the second shallow trench includes:

[0009] A first oxide layer is deposited on the substrate to form oxide layers of the same thickness on the first shallow trench and the second shallow trench;

[0010] A first nitride layer is deposited on the first oxide layer so that the interior of the first shallow trench is completely filled by the first nitride layer;

[0011] Remove a portion of the first nitride layer in the first shallow trench and remove all of the first nitride layer in the second shallow trench;

[0012] A second oxide layer is deposited such that the thickness of the oxide layer in the first shallow trench is less than the thickness of the oxide layer in the second shallow trench.

[0013] Optionally, removing a portion of the first nitride layer in the first shallow trench and removing all of the first nitride layer in the second shallow trench includes:

[0014] By masking the surface of the first shallow trench, all the first nitride layer in the second shallow trench is removed;

[0015] By masking the surface of the second shallow trench, part of the first nitride layer in the first shallow trench is removed.

[0016] Optionally, the width of the first shallow trench is smaller than the width of the second shallow trench, and the thickness of the first nitride layer formed in the first shallow trench is greater than the thickness of the first nitride layer formed in the second shallow trench. Removing a portion of the first nitride layer in the first shallow trench and removing all of the first nitride layer in the second shallow trench includes:

[0017] The first nitride layer is etched to remove the first oxide layer of a target thickness, which is the thickness of the first nitride layer formed in the second shallow trench.

[0018] Optionally, before filling the dielectric layer in the second shallow trench, the method further includes: forming a second nitride layer over the oxide layer;

[0019] The step of filling the second shallow trench with a dielectric layer includes filling the dielectric layer on the second nitride layer within the second shallow trench.

[0020] Optionally, the thickness of the first oxide layer ranges from 1 nm to 100 nm.

[0021] Optionally, the thickness of the second oxide layer ranges from 1 nm to 100 nm.

[0022] Optionally, etching the first nitride layer includes:

[0023] The first nitride layer is etched using either a wet etching process or a dry etching process.

[0024] Secondly, embodiments of this specification provide a shallow trench isolation structure, the structure comprising:

[0025] The substrate includes a memory cell array region and a peripheral circuit control region;

[0026] The first shallow trench is located in the memory cell array area;

[0027] The second shallow trench is located in the peripheral circuit control area and is used to isolate the memory cell array area and the peripheral circuit control area.

[0028] An oxide layer covers the first shallow trench and the second shallow trench, wherein the thickness of the oxide layer in the first shallow trench is less than the thickness of the oxide layer in the second shallow trench.

[0029] The dielectric layer is located within the second shallow trench.

[0030] Optionally, the width of the first shallow trench is smaller than the width of the second shallow trench.

[0031] The technical solution provided in this application embodiment includes a memory cell array region and a peripheral circuit controller formed on a semiconductor substrate. A first shallow trench is formed in the memory cell array region, and a second shallow trench is formed in the peripheral circuit controller region. Oxide layers of different thicknesses are formed in the first and second shallow trenches, wherein the oxide layer thickness in the first shallow trench is less than the oxide layer thickness in the second shallow trench. A dielectric layer is filled in the second shallow trench. This solution, by forming oxide layers of different thicknesses in the shallow trenches of the memory cell array region and the peripheral circuit controller region, effectively prevents dopants from entering the peripheral circuit controller region during subsequent ion implantation, ensuring the characteristics of the peripheral circuit controller region and thus guaranteeing the performance of the semiconductor device. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a schematic cross-sectional view of the substrate provided in the embodiments of this specification;

[0034] Figure 2 A schematic cross-sectional view of a substrate in which a first oxide layer is formed in a first shallow trench and a second shallow trench, provided as an embodiment of this specification.

[0035] Figure 3 This is a schematic cross-sectional view of the substrate for depositing the first nitride layer, provided in an embodiment of this specification.

[0036] Figure 4 This is a schematic cross-sectional view of the substrate with the first nitride layer removed, provided in an embodiment of this specification.

[0037] Figure 5 This is a schematic cross-sectional view of a substrate with a second oxide layer deposited, provided for an embodiment of this specification.

[0038] Figure 6This is a schematic cross-sectional view of a substrate with a second nitride layer formed, provided for an embodiment of this specification.

[0039] Figure 7 This is a schematic cross-sectional view of a substrate filled with a dielectric layer provided in the embodiments of this specification;

[0040] Figure 8 A schematic diagram illustrating the ion penetration during ion implantation of a shallow trench isolation structure formed using the methods provided in the embodiments of this specification.

[0041] Figure 9 This is a schematic diagram of a shallow trench isolation structure provided in the embodiments of this specification. Detailed Implementation

[0042] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0043] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0044] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0045] This specification provides an embodiment of a shallow trench isolation method, such as... Figures 1-4 The diagram shown is a cross-sectional view of a shallow trench isolation structure formed using the shallow trench isolation method provided in the embodiments of this specification. The method includes the following steps:

[0046] A substrate is provided, on which a memory cell array region and a peripheral circuit control region are formed, the memory cell array region having a first shallow trench and the peripheral circuit control region having a second shallow trench.

[0047] Oxide layers of different thicknesses are formed in the first shallow trench and the second shallow trench, wherein the oxide layer thickness in the first shallow trench is less than the oxide layer thickness in the second shallow trench.

[0048] A dielectric layer is filled within the second shallow trench.

[0049] In the specific implementation process, such as Figure 1 The image shown is a schematic cross-sectional view of the substrate provided in an embodiment of this specification. Figure 1 In this embodiment, a memory cell array region and a peripheral circuit control region are formed on the substrate. The size and specific location of the memory cell array region and the peripheral circuit control region can be set according to actual needs and are not limited here. The memory cell array region may have one or more first shallow trenches, and the peripheral circuit control region may have second shallow trenches. The widths of the first and second shallow trenches may be the same or different. In the embodiments of this specification, the width of the first shallow trench may be smaller than the width of the second shallow trench.

[0050] The first shallow trench and the second shallow trench can be formed by etching the substrate with a mask. For example, silicon nitride is deposited as a mask on the substrate where no shallow trench is formed, the mask is patterned, and the substrate is etched based on the patterning result to form the first shallow trench and the second shallow trench.

[0051] Furthermore, an oxide layer, such as silicon oxide, is deposited on the substrate with the shallow trenches. In the embodiments of this specification, to ensure that the implanted dopants do not penetrate into the peripheral circuit control region during the subsequent ion implantation process, a thicker oxide layer needs to be formed in the second shallow trench, while a thinner oxide layer is formed in the first shallow trench. The formation of oxide layers of different thicknesses can be achieved in the following ways:

[0052] A first oxide layer is deposited on a substrate to form oxide layers of the same thickness on the first shallow trench and the second shallow trench; a first nitride layer is deposited on the first oxide layer to completely fill the interior of the first shallow trench; a portion of the first nitride layer in the first shallow trench and all of the first nitride layer in the second shallow trench are removed; a second oxide layer is deposited such that the thickness of the oxide layer in the first shallow trench is less than the thickness of the oxide layer in the second shallow trench.

[0053] Please refer to Figures 2-5 As shown, Figure 2 A schematic cross-sectional view of a substrate in which oxide layers of the same thickness are formed in the first shallow trench and the second shallow trench is shown, as follows: Figure 2 As shown, the bottom and sidewalls of both the first shallow trench and the second shallow trench are deposited with a first oxide layer.

[0054] Furthermore, a first nitride layer (e.g., silicon nitride) is deposited on the first oxide layer, such as... Figure 3 As shown, the first shallow trench is completely filled with the first nitride layer. For example, when the first shallow trenches in the memory cell array area are relatively dense, and the second shallow trenches in the peripheral circuit control area are relatively sparse (i.e., the width of the first shallow trench is smaller than the width of the second shallow trench), if filled with the same thickness of silicon nitride, the top of the first shallow trench will retain a certain thickness of silicon nitride after it is filled. The second shallow trench will only have a certain thickness of silicon nitride covering its sidewalls and bottom. That is, when the first shallow trench is filled with silicon nitride, the second shallow trench only has a certain thickness of silicon nitride deposited within it.

[0055] Next, a portion of the first nitride layer in the first shallow trench is removed, and all of the first nitride layer in the second shallow trench is removed, as follows: Figure 4 The image shows a schematic cross-sectional view of the substrate with the first nitride layer removed. The removal of the first nitride layer can be achieved in various ways; two of these methods will be illustrated here.

[0056] The first method involves etching the first nitride layer when the width of the first shallow trench is less than the width of the second shallow trench, and the thickness of the first nitride layer formed in the first shallow trench is greater than the thickness of the first nitride layer formed in the second shallow trench. This process removes the first oxide layer of a target thickness, which is the thickness of the first nitride layer formed in the second shallow trench.

[0057] Specifically, as described above, when the first shallow trenches in the memory cell array area are relatively dense and the trench width is small, after the first shallow trenches are filled with silicon nitride, a certain thickness of silicon nitride will remain on top. In this case, the first nitride layer of the target thickness can be removed directly using dry etching or wet etching processes. The target thickness is the thickness of the nitride layer in the second shallow trench, that is, the nitride in the second trench is completely removed. When removing the first nitride layer of the same thickness, the first nitride layer in the second shallow trench is removed first, while the first nitride in the first shallow trench is still retained. Only the silicon nitride retained on top and part of the silicon nitride in the trench are removed.

[0058] The second method involves using a mask to block the surface of the first shallow trench, thereby removing all the first nitride layer in the second shallow trench; and using a mask to block the surface of the second shallow trench, thereby removing part of the first nitride layer in the first shallow trench.

[0059] Specifically, the first nitride layer can be removed in stages: first, the first shallow trench is covered by a mask to remove all the first nitride layer in the second shallow trench; then, the second shallow trench is covered to remove the first nitride layer on the surface of the first shallow trench; or, the second shallow trench is covered by a mask to remove the first nitride layer on the surface of the first shallow trench; then, the first shallow trench is covered to remove all the first nitride layer in the second shallow trench.

[0060] Furthermore, after removing the first nitride layer, a second oxide layer is deposited, such as... Figure 5 The diagram shows a cross-sectional view of a substrate with a second oxide layer deposited. Since all nitride has been removed from the second shallow trench, the second oxide layer is deposited on top of the first oxide layer within the second shallow trench, thus increasing the thickness of the oxide at the bottom and sidewalls of the second shallow trench. In contrast, the second oxide layer does not deposit in the first shallow trench due to the obstruction of the first nitride layer; therefore, only the first oxide layer remains in the first shallow trench.

[0061] In the embodiments of this specification, the thickness of the first oxide layer and the thickness of the second oxide layer can be set according to actual needs. For example, the thickness range of the first oxide layer is 1nm to 100nm, and the thickness range of the second oxide layer is 1nm to 100nm.

[0062] After oxide layers of different thicknesses are formed in the first and second shallow trenches, a second nitride layer is formed on top of the oxide layers, such as... Figure 6 The diagram shown is a schematic cross-sectional view of the substrate in which the second nitride layer is formed. Further, a dielectric layer is filled on the second nitride layer within the second shallow trench, as shown... Figure 7 The diagram shown is a cross-sectional view of a substrate filled with a dielectric layer. The material of the dielectric layer can be selected according to actual needs; for example, silicon oxide can be used as the dielectric layer.

[0063] To better understand the shallow trench isolation method provided in the embodiments of this specification, please refer to... Figure 8 This is a schematic diagram illustrating the ion penetration during ion implantation of a shallow trench isolation structure formed using the method provided in the embodiments of this specification. Figure 8 As shown, due to the thickening of the oxide layer in the second shallow trench, ions can only penetrate into the oxide layer and will not penetrate into the peripheral circuit control area, thus ensuring the characteristics of the peripheral circuit control area.

[0064] In summary, the shallow trench isolation method provided in this specification, by forming oxide layers of different thicknesses in the first shallow trench and the outer second shallow trench, can effectively prevent dopants from entering the peripheral circuit control region during subsequent ion implantation, ensuring the characteristics of the peripheral circuit control region and thus guaranteeing the performance of the semiconductor device.

[0065] This specification also provides a shallow trench isolation structure, such as... Figure 9 The diagram shown is a schematic representation of a shallow trench isolation structure provided in an embodiment of this specification, comprising:

[0066] The substrate 91 includes a memory cell array region and a peripheral circuit control region; a first shallow trench 92 is located in the memory cell array region; a second shallow trench 93 is located in the peripheral circuit control region and is used to isolate the memory cell array region and the peripheral circuit control region; an oxide layer 94 covers the first shallow trench 92 and the second shallow trench 93, the thickness of the oxide layer in the first shallow trench 92 is less than the thickness of the oxide layer in the second shallow trench 93; and a dielectric layer 95 is located in the second shallow trench.

[0067] Optionally, the width of the first shallow trench 92 is smaller than the width of the second shallow trench 93.

[0068] The shallow trench isolation structure described above has been described in detail in the embodiments of the shallow trench isolation method provided in this specification, and will not be elaborated further here.

[0069] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0070] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the invention.

[0071] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A shallow trench isolation method, characterized in that, The method includes: A substrate is provided, on which a memory cell array region and a peripheral circuit control region are formed, wherein a first shallow trench is formed in the memory cell array region and a second shallow trench is formed in the peripheral circuit control region. Oxide layers of different thicknesses are formed in the first shallow trench and the second shallow trench, wherein the oxide layer thickness in the first shallow trench is less than the oxide layer thickness in the second shallow trench. A dielectric layer is filled into the second shallow trench; The formation of oxide layers of different thicknesses in the first shallow trench and the second shallow trench includes: A first oxide layer is deposited on the substrate to form oxide layers of the same thickness on the first shallow trench and the second shallow trench; A first nitride layer is deposited on the first oxide layer so that the interior of the first shallow trench is completely filled by the first nitride layer; Remove a portion of the first nitride layer in the first shallow trench and remove all of the first nitride layer in the second shallow trench; A second oxide layer is deposited such that the thickness of the oxide layer in the first shallow trench is less than the thickness of the oxide layer in the second shallow trench.

2. The method according to claim 1, characterized in that, The removal of a portion of the first nitride layer in the first shallow trench and the removal of all the first nitride layer in the second shallow trench include: By masking the surface of the first shallow trench, all the first nitride layer in the second shallow trench is removed; By masking the surface of the second shallow trench, part of the first nitride layer in the first shallow trench is removed.

3. The method according to claim 1, characterized in that, The width of the first shallow trench is smaller than the width of the second shallow trench, and the thickness of the first nitride layer formed in the first shallow trench is greater than the thickness of the first nitride layer formed in the second shallow trench. Removing a portion of the first nitride layer in the first shallow trench and removing all of the first nitride layer in the second shallow trench includes: The first nitride layer is etched to remove the first oxide layer of a target thickness, which is the thickness of the first nitride layer formed in the second shallow trench.

4. The method according to any one of claims 1 to 3, characterized in that, Before filling the dielectric layer in the second shallow trench, the method further includes: forming a second nitride layer over the oxide layer; The step of filling the second shallow trench with a dielectric layer includes filling the dielectric layer on the second nitride layer within the second shallow trench.

5. The method according to claim 1, characterized in that, The thickness of the first oxide layer ranges from 1 nm to 100 nm.

6. The method according to claim 1, characterized in that, The thickness of the second oxide layer ranges from 1 nm to 100 nm.

7. The method according to claim 3, characterized in that, The etching of the first nitride layer includes: The first nitride layer is etched using either a wet etching process or a dry etching process.

8. A shallow trench isolation structure, characterized in that, The structure includes: The substrate includes a memory cell array region and a peripheral circuit control region; The first shallow trench is located in the memory cell array area; The second shallow trench is located in the peripheral circuit control area and is used to isolate the memory cell array area and the peripheral circuit control area. An oxide layer covers the first shallow trench and the second shallow trench, wherein the thickness of the oxide layer in the first shallow trench is less than the thickness of the oxide layer in the second shallow trench. The dielectric layer is located within the second shallow trench; The oxide layer is formed by the following steps: depositing a first oxide layer on the substrate to form oxide layers of the same thickness on the first shallow trench and the second shallow trench; depositing a first nitride layer on the first oxide layer to completely fill the interior of the first shallow trench with the first nitride layer; removing a portion of the first nitride layer in the first shallow trench and removing all of the first nitride layer in the second shallow trench; and depositing a second oxide layer such that the thickness of the oxide layer in the first shallow trench is less than the thickness of the oxide layer in the second shallow trench.

9. The structure according to claim 8, characterized in that, The width of the first shallow trench is smaller than the width of the second shallow trench.

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