Method of self-aligned contact hole formation, method of device fabrication, device, and apparatus
By forming a gate oxide layer and a shielding gate on the substrate, and using the interlayer dielectric layer as a mask to selectively etch the source/well region, the problem of difficulty in controlling the spacing between the contact hole and the gate trench is solved, thereby achieving stable control of the threshold voltage and improving device performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- 上海芯导电子科技股份有限公司
- Filing Date
- 2022-03-21
- Publication Date
- 2026-07-31
AI Technical Summary
In products with small feature sizes, the spacing between contact holes and gate trenches is difficult to control, affecting the threshold voltage of the device. Traditional methods are not suitable for precise control.
By forming a gate oxide layer and a shielding gate on a substrate, and forming an inter-gate oxide layer on top of it, then filling the gate material, etching to form a gate cavity, and using the interlayer dielectric layer as a mask to selectively etch the source/well region to form a self-aligned contact hole, the spacing between the contact hole and the gate is controlled.
It enables precise control of the spacing between the contact hole and the gate trench, reducing product size, stabilizing the threshold voltage, and improving device performance.
Smart Images
Figure CN114975237B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductors, and more particularly to a method for forming contact holes by self-alignment, a method for fabricating devices, devices, and apparatus. Background Technology
[0002] SGT MOSFETs (Shielded Gate Field Effect Transistors) typically involve depositing an interlayer dielectric layer after forming the source poly and gate poly. Then, by illuminating the areas where contacts need to be made, the interlayer dielectric layer and silicon are etched to form contact holes.
[0003] In small feature size products, the spacing between the contact hole and the gate trench significantly affects the device's threshold voltage (Vth), and Vth increases exponentially as the spacing decreases. This has a substantial impact on device turn-on; however, the spacing between the contact hole and the gate trench is difficult to control using traditional methods for forming contact holes.
[0004] Therefore, how to make the spacing between the contact hole and the gate trench relatively fixed and controllable, thereby reducing the product size, has become a technical problem that the industry urgently needs to solve. Summary of the Invention
[0005] This invention provides a method for forming contact holes by self-alignment, a method for fabricating devices, devices, and equipment to solve the problem of difficulty in controlling the spacing between contact holes and gate trenches.
[0006] According to a first aspect of the present invention, a method for self-aligning the formation of a contact hole is provided, comprising:
[0007] Provide a substrate;
[0008] A plurality of first grooves are formed on the substrate;
[0009] A gate oxide layer and a shielding gate are sequentially formed in each of the first grooves, and an inter-gate oxide layer is formed on top of the shielding gate. Then, the gate material is filled in the first groove. The gate oxide layer is formed on the inner wall of the first groove, and the inter-gate oxide layer is formed between the gate material and the shielding gate.
[0010] The filled gate material is etched to remove part of the gate material and form a gate cavity, and the remaining gate material in the first groove forms the gate; and the substrate and the gate oxide layer around the gate cavity are etched away to form a substrate cavity, and the gate cavity and the substrate cavity constitute a gate cap cavity;
[0011] A source / well region is formed in the substrate surrounding the gate.
[0012] An interlayer dielectric layer is filled into the gate cap cavity to form a gate cap;
[0013] The source / well region is selectively etched using the gate cap as a mask to form contact holes; the contact holes are formed between the interlayer dielectric layers.
[0014] The size of the contact hole is determined by the size of the gate cap cavity.
[0015] Optionally, a plurality of first grooves are formed on the substrate, specifically including:
[0016] A patterned hard mask is formed on the substrate, the substrate is etched using the patterned hard mask as a mask, the patterned hard mask is removed, and a plurality of the first grooves are formed.
[0017] Optionally, a gate oxide layer and a shielding gate are sequentially formed in each of the first grooves, and an inter-gate oxide layer is formed on top of the shielding gate, and then the gate material is filled in the first groove; specifically including:
[0018] The gate oxide layer is formed in a plurality of the first grooves, the gate oxide layer covering the inner wall of the first grooves and the surface of the substrate outside the first grooves;
[0019] Deposit shielding gate material in several of the first grooves, and etch a portion of the shielding gate material to form the shielding gate, and over-etch the gate oxide layer around the top of the shielding gate to expose the top of the shielding gate;
[0020] An oxide layer is formed on the top of the exposed shielding gate, the sidewalls of the plurality of first grooves, and the surface of the substrate; wherein the oxide layer on the top of the shielding gate constitutes the inter-gate oxide layer; and the oxide layer formed on the sidewalls of the first grooves and the surface of the substrate constitutes the gate oxide layer.
[0021] A gate material is deposited in the first groove, and the gate material is polished by CMP so that the gate material fills the first groove.
[0022] Optionally, the formation of the source / well region specifically includes:
[0023] P-type ion and N-type ion implantation are performed in the substrate surrounding the gate to form the source / well region.
[0024] Optionally, an interlayer dielectric layer is filled into the gate cap cavity to form a gate cap, specifically including:
[0025] The interlayer dielectric layer is deposited in the gate cap cavity and on the surface of the substrate;
[0026] CMP polishing of the interlayer dielectric layer removes the surface of the substrate and the interlayer dielectric layer extending out of the top of the gate cap cavity; the interlayer dielectric layer filling the remaining gate cap cavity forms the gate cap.
[0027] Optionally, after selectively etching the source / well region using the gate cap as a mask to form a contact hole, the method further includes: depositing metal material in the contact hole and CMP polishing the metal material to form a contact hole plug.
[0028] According to a second aspect of the present invention, a method for fabricating a semiconductor device is provided, comprising the trench self-alignment method for forming contact holes as described in any of the first aspects of the present invention.
[0029] According to a third aspect of the present invention, a semiconductor device is provided, which is prepared using the semiconductor device preparation method described in the second aspect of the present invention.
[0030] According to a fourth aspect of the present invention, an electronic device is provided, which is the semiconductor device described in the third aspect of the present invention.
[0031] This invention provides a self-aligned method for forming contact holes. In each first groove formed on a substrate, a gate oxide layer and a shielding gate are sequentially formed, and an inter-gate oxide layer is formed on top of the shielding gate. Then, gate material is filled into the first groove. The filled gate material is etched to remove a portion of the gate material, forming a gate cavity. The remaining gate material in the first groove forms the gate. The substrate and the gate oxide layer surrounding the gate cavity are etched away to form a substrate cavity. An interlayer dielectric layer is then filled into the substrate cavity and the gate cavity. The source / well region is etched using the interlayer dielectric layer as a mask, thereby forming a contact hole. This method, which directly uses the interlayer dielectric layer as a mask to selectively etch the source / well region, makes it easier to control the distance between the etched contact hole and the gate, solving the problem of difficulty in controlling the distance between the etched contact hole and the gate. Since the threshold voltage is sensitive to changes in the distance between the contact hole and the gate, the threshold voltage can be controlled by controlling the distance between the contact hole and the gate. Attached Figure Description
[0032] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0033] Figure 1This is a flowchart illustrating a method for self-aligned contact hole formation in one embodiment of the present invention;
[0034] Figure 2 This is a schematic diagram of a device at different etching stages in one embodiment of the present invention. Figure 1 ;
[0035] Figure 3 This is a schematic diagram of a device at different etching stages in one embodiment of the present invention. Figure 2 ;
[0036] Figure 4 This is a schematic diagram of a device at different etching stages in one embodiment of the present invention. Figure 3 ;
[0037] Figure 5 This is a schematic diagram of a device at different etching stages in one embodiment of the present invention. Figure 4 ;
[0038] Figure 6 This is a schematic diagram of a device at different etching stages in one embodiment of the present invention. Figure 5 ;
[0039] Explanation of reference numerals in the attached figures:
[0040] 101-Substrate;
[0041] 102 - Gate oxide layer;
[0042] 103 - Shielding fence;
[0043] 104 - Intergate oxide layer;
[0044] 105 - Gate material;
[0045] 106 - Interlayer dielectric layer;
[0046] 107 - Contact hole plug. Detailed Implementation
[0047] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0048] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0049] SGT MOSFETs (Shielded Gate Field Effect Transistors) typically involve depositing an interlayer dielectric layer after forming the source poly and gate poly. Then, using photolithography, the areas requiring interconnection are etched to create contact holes by etching the interlayer dielectric layer and silicon. Traditional methods for forming contact holes present challenges in controlling the spacing between the contact holes and the gate trench.
[0050] Through experiments, the inventors discovered that by forming a sufficiently thick epitaxial layer, allowing for sufficient etching margin in the gate material, and etching the epitaxial layer around the top of the gate material to form a gate cap cavity, an interlayer dielectric layer is formed within the gate cap cavity. By utilizing a high selectivity ratio between oxide and silicon, self-aligned contact holes are formed. The etching method of this solution results in a relatively fixed and controllable distance between the etched contact holes and the gate trench.
[0051] The technical solution of the present invention will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.
[0052] Please refer to Figures 1-6 According to an embodiment of the present invention, a method for self-aligning contact hole formation is provided, comprising:
[0053] S11: Provide a substrate 101;
[0054] S12: A plurality of first grooves are formed on the substrate 101;
[0055] S13: A gate oxide layer 102 and a shielding gate 103 are sequentially formed in each of the first grooves, and an inter-gate oxide layer 104 is formed on top of the shielding gate 103. Then, the gate material 105 is filled into the first groove. The gate oxide layer is formed on the inner wall of the first groove; the inter-gate oxide layer 104 is formed between the gate material 105 and the shielding gate 103. The device structure diagram after this step is as follows: Figure 2 As shown;
[0056] S14: The filled gate material 105 is etched to remove part of the gate material 105, forming a gate cavity. The remaining gate material 105 in the first groove forms the gate. The substrate 101 and the gate oxide layer 102 surrounding the gate cavity are also etched away to form a substrate 101 cavity. The gate cavity and the substrate 101 cavity constitute a gate cap cavity. During this process, the surface layer of the substrate 101 is also damaged. The device after forming the gate cap cavity is as follows: Figure 3 As shown;
[0057] S15: Forming a source / well region, the source / well region being formed in the substrate 101 surrounding the gate;
[0058] S16: Fill the gate cap cavity with an interlayer dielectric layer 106 to form a gate cap; the device structure diagram after this step is as follows. Figure 4 As shown;
[0059] S17: Using the gate cap as a mask, selectively etch the source / well region to form contact holes; the contact holes are formed between the interlayer dielectric layers 106, and the device after forming the contact holes is as follows: Figure 5 As shown;
[0060] The size of the contact hole is determined by the size of the gate cap cavity.
[0061] The present invention provides a technical solution for selectively etching the source region / well region using the interlayer dielectric layer 106 as a mask, which solves the problem that the spacing between the etched contact hole and the gate trench is difficult to control. Controlling the spacing between the contact hole and the gate enables control of the threshold voltage.
[0062] The substrate 101 provided in step S11 includes a substrate and an epitaxial layer formed on the substrate. The thickness of the epitaxial layer is sufficient to make the plurality of first grooves formed on the substrate 101 in step S12 sufficiently deep. Thus, in step S13, the gate material 105 filled in the first groove is sufficiently thick to allow step S14 to be performed, namely: etching the filled gate material 105 to form a gate cavity, the remaining gate material 105 in the first groove forming a gate; and etching away the substrate 101 and the gate oxide layer 102 around the gate cavity to form a substrate 101 cavity; the gate cavity and the substrate 101 cavity form a gate cap cavity, which is used to fill the interlayer dielectric layer 106; and the thickness of the epitaxial layer is also set to satisfy the epitaxial layer loss of the surface substrate 101 in S14.
[0063] In one embodiment, S12: forming a plurality of first grooves on the substrate 101, specifically including:
[0064] S121: Forming a patterned hard mask on the substrate 101; specifically including: depositing a hard mask on the surface of the substrate 101; covering the hard mask with a layer of photoresist, patterning the photoresist, and etching the hard mask using the patterned photoresist as a mask, thereby forming a patterned hard mask.
[0065] S122: The substrate 101 is etched using the patterned hard mask as a mask to remove the patterned hard mask and form a plurality of the first grooves.
[0066] Specifically, an oxide layer may be formed between the formed hard mask and the substrate 101, so step 121 specifically includes: forming an oxide layer on the surface of the substrate 101, depositing a hard mask on the surface of the oxide layer; covering the hard mask with a layer of photoresist, patterning the photoresist, and etching the hard mask and the oxide layer with the patterned photoresist as a mask, thereby forming a patterned hard mask and a patterned oxide layer; so that the oxide layer protects the substrate 101 when etching the first groove.
[0067] In one embodiment, step S13 involves: sequentially generating a gate oxide layer 102 and a shielding gate 103 in each of the first grooves, forming an inter-gate oxide layer 104 on top of the shielding gate 103, and then filling the first groove with gate material 105; specifically including:
[0068] S131: The gate oxide layer 102 is formed in a plurality of the first grooves, the gate oxide layer 102 covering the inner wall of the first grooves and the surface of the substrate 101 outside the first grooves;
[0069] S132: Deposit shielding gate material in a plurality of the first grooves, and etch a portion of the shielding gate material to form the shielding gate 103, and over-etch the gate oxide layer 102 around the top of the shielding gate 103 to expose the top of the shielding gate 103;
[0070] S133: An oxide layer is formed on the top of the exposed shielding gate 103, the sidewalls of the plurality of first grooves, and the surface of the substrate 101; wherein the oxide layer on the top of the shielding gate 103 constitutes the inter-gate oxide layer; the oxide layer formed on the sidewalls of the first grooves and the surface of the substrate 101 constitutes the gate oxide layer 102.
[0071] S134: Deposit gate material 105 in the first groove, and CMP polish the gate material 105 so that the gate material 105 fills the first groove. The device after step 13 is as follows: Figure 2 As shown.
[0072] In one embodiment, step S15, forming the source / well region, specifically includes:
[0073] P-type ions and N-type ions are implanted into the substrate 101 surrounding the gate to form the source / well region.
[0074] In one embodiment, step S16, filling the gate cap cavity with an interlayer dielectric layer 106 to form a gate cap, specifically includes:
[0075] S161: Deposit the interlayer dielectric layer 106 in the gate cap cavity and on the surface of the substrate 101;
[0076] S162: CMP polishing of the interlayer dielectric layer 106 removes the surface of the substrate 101 and the interlayer dielectric layer 106 extending out of the top of the gate cap cavity; thereby, the interlayer dielectric layer 106 filling the remaining gate cap cavity forms the gate cap, and the device after forming the gate cap is as follows: Figure 4 As shown.
[0077] In forming the interlayer dielectric layer 106, an etching method with a high oxide-to-silicon etching selectivity ratio is used to etch the interlayer dielectric layer 106 and the epitaxial layer to form self-aligned contact holes. The self-aligned contact holes allow for a more fixed and controllable spacing between the contact holes and the gate trench, which is more conducive to reducing product size.
[0078] In one embodiment, after selectively etching the source / well region using the gate cap as a mask to form a contact hole, the method further includes: S18:
[0079] Metal material is deposited in the contact hole, and CMP polishing is performed to form the contact hole plug 107. The device formed after step 18 is as follows: Figure 6 As shown.
[0080] According to another embodiment, a method for fabricating a semiconductor device is provided, including the trench self-alignment method for forming contact holes as described in any of the foregoing embodiments of the present invention.
[0081] According to other embodiments of the present invention, a semiconductor device is provided, which is prepared using the semiconductor device preparation method described in the foregoing embodiments of the present invention.
[0082] In addition, according to yet another embodiment of the present invention, an electronic device is provided, including the semiconductor device described in the foregoing embodiments of the present invention.
[0083] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A method of self-aligned contact hole formation, characterized by, include: Provide a substrate; Forming a plurality of first grooves on the substrate includes: forming a patterned hard mask on the substrate, etching the substrate using the patterned hard mask as a mask, removing the patterned hard mask, and forming a plurality of first grooves; A gate oxide layer and a shielding gate are sequentially formed in each of the first grooves, and an inter-gate oxide layer is formed on top of the shielding gate. Then, the gate material is filled in the first groove. The gate oxide layer is formed on the inner wall of the first groove, and the inter-gate oxide layer is formed between the gate material and the shielding gate. The filled gate material is etched to remove part of the gate material and form a gate cavity, and the remaining gate material in the first groove forms the gate; and the substrate and the gate oxide layer around the gate cavity are etched away to form a substrate cavity, and the gate cavity and the substrate cavity constitute a gate cap cavity; A source / well region is formed in the substrate surrounding the gate. An interlayer dielectric layer is filled into the gate cap cavity to form a gate cap; The source / well region is selectively etched using the gate cap as a mask to form contact holes; the contact holes are formed between the interlayer dielectric layers. The size of the contact hole is determined by the size of the gate cap cavity.
2. The method for forming a contact hole by self-alignment according to claim 1, characterized in that, A gate oxide layer and a shielding gate are sequentially formed in each of the first grooves, and an inter-gate oxide layer is formed on top of the shielding gate. Then, the gate material is filled into the first groove; specifically including: The gate oxide layer is formed in a plurality of the first grooves, the gate oxide layer covering the inner wall of the first grooves and the surface of the substrate outside the first grooves; Deposit shielding gate material in several of the first grooves, and etch a portion of the shielding gate material to form the shielding gate, and over-etch the gate oxide layer around the top of the shielding gate to expose the top of the shielding gate; An oxide layer is formed on the top of the exposed shielding gate, the sidewalls of the plurality of first grooves, and the surface of the substrate; wherein the oxide layer on the top of the shielding gate constitutes the inter-gate oxide layer; and the oxide layer formed on the sidewalls of the first grooves and the surface of the substrate constitutes the gate oxide layer. A gate material is deposited in the first groove, and the gate material is polished by CMP so that the gate material fills the first groove.
3. The method for forming a contact hole by self-alignment according to claim 2, characterized in that, The formation of source / well regions specifically includes: P-type ion and N-type ion implantation are performed in the substrate surrounding the gate to form the source / well region.
4. The method for forming a contact hole by self-alignment according to claim 3, characterized in that, The gate cap cavity is filled with an interlayer dielectric layer to form a gate cap, specifically including: The interlayer dielectric layer is deposited in the gate cap cavity and on the surface of the substrate; CMP polishing of the interlayer dielectric layer removes the surface of the substrate and the interlayer dielectric layer extending from the top of the gate cap cavity; The gate cap is formed by filling the remaining gate cap cavity with the interlayer dielectric layer.
5. The method for forming a contact hole by self-alignment according to claim 4, characterized in that, After selectively etching the source / well region using the gate cap as a mask to form a contact hole, the process further includes: depositing metal material in the contact hole and CMP polishing the metal material to form a contact hole plug.
6. A method of manufacturing a semiconductor device, characterized by include: The method for forming a self-aligned contact hole according to any one of claims 1 to 5.
7. A semiconductor device, characterized by comprising: It is prepared using the semiconductor device preparation method described in claim 6.
8. An electronic device, comprising: Includes the semiconductor device as described in claim 7.