Interconnect structures and methods of forming the same

Abstract

Interconnect structures and methods of forming the same are disclosed. In some embodiments, the method includes forming a first dielectric layer over one or more devices, forming a first conductive feature in the first dielectric layer, and forming two dielectric features over the first dielectric layer and the first conductive feature. At least one of the two dielectric features has a first width, and each dielectric feature includes a first low-k dielectric layer, an oxide layer, and a first etch stop layer. The method also includes forming a second conductive feature between the two dielectric features, and the second conductive feature has a second width that is substantially the same as the first width.

Description

Technical Field

[0001] This disclosure generally relates to interconnect structures and methods for forming them. Background Technology

[0002] As the semiconductor industry introduces next-generation integrated circuits (ICs) with higher performance and more functionality, the density of components forming ICs is increasing, while the size, dimensions, and spacing between components or elements are decreasing. Previously, this reduction was limited only by the ability to define structures using photolithography; however, the smaller device geometry introduces new constraints. For example, as the aspect ratio of conductive features in the dielectric material of back-end process (BEOL) interconnect structures becomes higher, openings in the dielectric material of the conductive features may have tapered sidewalls, leading to deterioration in resistance-capacitance (RC) delay. Therefore, improved interconnect structures and their formation methods are needed. Summary of the Invention

[0003] According to a first aspect of this disclosure, a method of manufacturing a semiconductor device is provided, comprising: forming a first dielectric layer over one or more devices; forming a first conductive feature in the first dielectric layer; forming two dielectric features over the first dielectric layer and the first conductive feature, wherein at least one of the dielectric features has a first width, and wherein each dielectric feature includes a first low-k dielectric layer, an oxide layer, and a first etch stop layer; and forming a second conductive feature between the two dielectric features, wherein the second conductive feature has a second width substantially the same as the first width. According to a second aspect of this disclosure, a method of manufacturing a semiconductor device is provided, comprising: forming an oxide layer on a first etch stop layer; forming a sacrificial layer on the oxide layer; patterning the sacrificial layer to form a plurality of openings in the sacrificial layer; forming a first low-k dielectric layer on the patterned sacrificial layer and the oxide layer; removing portions of the first low-k dielectric layer disposed on a horizontal surface of the patterned sacrificial layer and a horizontal surface of the oxide layer to form a plurality of portions of the first low-k dielectric layer; removing the patterned sacrificial layer; and forming a conductive material between adjacent portions of the plurality of portions of the first low-k dielectric layer.

[0004] According to a third aspect of this disclosure, a method of manufacturing a semiconductor device is provided, comprising: forming a sacrificial layer on an oxide layer; forming a multilayer structure on the sacrificial layer, wherein the multilayer structure includes a photoresist layer disposed on one or more layers; removing portions of the one or more layers by a first plasma etching process, wherein the first plasma etching process includes using a first frequency; removing portions of the sacrificial layer by a second plasma etching process to form a patterned sacrificial layer having a plurality of openings, wherein the second plasma etching process includes using a second frequency significantly lower than the first frequency, wherein the first plasma etching process and the second plasma etching process are performed in the same etching chamber; forming a low-k dielectric layer on the patterned sacrificial layer, wherein the low-k dielectric layer partially fills the plurality of openings; and filling the plurality of openings with a conductive material. Attached Figure Description

[0005] The various aspects of this disclosure can be best understood by reading in conjunction with the accompanying drawings through the following detailed description. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0006] Figure 1A This is a perspective view of one of the various stages of manufacturing a semiconductor device structure according to some embodiments.

[0007] Figure 1B It is according to some embodiments along Figure 1A A cross-sectional side view of the stage of manufacturing a semiconductor device structure, taken by line AA.

[0008] Figure 2 This is a cross-sectional side view of a stage in the manufacturing of a semiconductor device structure according to some embodiments.

[0009] Figures 3A-3L These are cross-sectional side views of various stages of manufacturing interconnect structures according to some embodiments.

[0010] Figure 4 This is a cross-sectional side view of one of the various stages of manufacturing a semiconductor device structure according to some embodiments. Detailed Implementation

[0011] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples throughout this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0012] Furthermore, spatially related terms (e.g., "below," "under," "lower part," "above," "above," "top," "upper part," etc.) may be used herein to readily describe the relationship between one element or feature as shown in the figure and another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein can be interpreted similarly.

[0013] Figure 1A and Figure 1B The stages of manufacturing the semiconductor device structure 100 are illustrated. (For example...) Figure 1A and Figure 1B As shown, the semiconductor device structure 100 includes a substrate 102 and one or more devices 200 formed on the substrate 102. The substrate 102 may be a semiconductor substrate. In some embodiments, the substrate 102 includes at least a single-crystal semiconductor layer on the surface of the substrate 102. The substrate 102 may include crystalline semiconductor materials, such as, but not limited to, silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium antimony arsenide (GaAsSb), and indium phosphide (InP). For example, the substrate 102 is made of Si. In some embodiments, the substrate 102 is a silicon-on-insulator (SOI) substrate, which includes an insulating layer (not shown) disposed between two silicon layers. In one aspect, the insulating layer is an oxygen-containing material, such as an oxide.

[0014] Substrate 102 may include one or more buffer layers (not shown) located on the surface of substrate 102. The buffer layers may be used to gradually change the lattice constant from that of the substrate to the lattice constant of the source / drain region. The buffer layers may be formed from epitaxially grown crystalline semiconductor materials, such as, but not limited to, Si, Ge, Germanium-tin (GeSn), SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, GaP, and InP. In one embodiment, substrate 102 includes a SiGe buffer layer epitaxially grown on silicon substrate 102. The germanium concentration of the SiGe buffer layer may increase from 30 atomic percent germanium in the bottom buffer layer to 70 atomic percent germanium in the top buffer layer.

[0015] The substrate 102 may include various regions that have been appropriately doped with impurities (e.g., p-type or n-type impurities). Dopants are, for example, phosphorus for n-type fin field-effect transistors (FinFETs) and boron for p-type FinFETs.

[0016] As described above, device 200 can be any suitable device, such as a transistor, diode, imaging sensor, resistor, capacitor, inductor, memory cell, or a combination thereof. In some embodiments, device 200 is a transistor, such as a planar field-effect transistor (FET), FinFET, nanostructured transistor, or other suitable transistor. Nanostructured transistors can include nanosheet transistors, nanowire transistors, gate-all-around (GAA) transistors, multi-bridge-channel (MBC) transistors, or any transistor having a gate electrode surrounding a channel. An example of device 200 formed on substrate 102 is a FinFET, which... Figure 1A and Figure 1B As shown in the figure. Device 200 includes a source / drain (S / D) region 124 and a gate stack 140. Figure 1A (Only one is shown in the image). Each gate stack 140 may be disposed between the S / D region 124 used as the source region and the S / D region 124 used as the drain region. For example, each gate stack 140 may extend along the Y-axis between one or more S / D regions 124 used as the source region and one or more S / D regions 124 used as the drain region. Figure 1B As shown, two gate stacks 140 are formed on the substrate 102. In some embodiments, more than two gate stacks 140 are formed on the substrate 102. A channel region 108 is formed between the S / D region 124, which serves as the source region, and the S / D region 124, which serves as the drain region.

[0017] S / D region 124 may include semiconductor materials such as Si or Ge, III-V compound semiconductors, II-VI compound semiconductors, or other suitable semiconductor materials. Exemplary S / D region 124 may include, but is not limited to, Ge, SiGe, GaAs, AlGaAs, GaAsP, SiP, InAs, AlAs, InP, GaN, InGaAs, InAlAs, GaSb, AlP, GaP, etc. S / D region 124 may include p-type dopants, such as boron; n-type dopants, such as phosphorus or arsenic; and / or other suitable dopants, including combinations thereof. S / D region 124 may be formed by epitaxial growth methods using CVD, atomic layer deposition (ALD), or molecular beam epitaxy (MBE). Channel region 108 may include one or more semiconductor materials such as Si, Ge, GeSn, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, GaP, or InP. In some embodiments, the channel region 108 comprises the same semiconductor material as the substrate 102. In some embodiments, the device 200 is a FinFET, and the channel region 108 is a plurality of fins disposed below the gate stack 140. In some embodiments, the device 200 is a nanostructure transistor, and the channel region 108 is surrounded by the gate stack 140.

[0018] like Figure 1A and Figure 1BAs shown, each gate stack 140 includes a gate electrode layer 138 disposed over (or around) the channel region 108 of a nanostructure transistor. The gate electrode layer 138 may be a metallic material, such as tungsten, cobalt, aluminum, ruthenium, copper, or multiples thereof, and may be deposited by ALD, plasma-enhanced chemical vapor deposition (PECVD), MBD, physical vapor deposition (PVD), or any suitable deposition technique. Each gate stack 140 may also include a gate dielectric layer 136 disposed over the channel region 108. The gate electrode layer 138 may be disposed over the gate dielectric layer 136. In some embodiments, an interface layer (not shown) may be disposed between the channel region 108 and the gate dielectric layer 136, and one or more work function layers (not shown) may be formed between the gate dielectric layer 136 and the gate electrode layer 138. The interface dielectric layer may include a dielectric material, such as an oxygen-containing or nitrogen-containing material, or multiples thereof, and may be formed by any suitable deposition method, such as CVD, PECVD, or ALD. The gate dielectric layer 136 may include a dielectric material, such as an oxygen-containing or nitrogen-containing material, a high-k dielectric material with a k-value greater than that of silicon dioxide, or multiple layers thereof. The gate dielectric layer 136 may be formed by any suitable method, such as CVD, PECVD, or ALD. In some embodiments, the gate dielectric layer 136 may be a conformal layer. For ease of description, the term "conformal" may be used herein for layers having substantially the same thickness over different regions. One or more work function layers may include titanium aluminum carbide, titanium aluminum oxide, titanium aluminum nitride, etc.

[0019] Gate spacers 122 are formed along the sidewalls of the gate stack 140 (e.g., the sidewalls of the gate dielectric layer 136). Gate spacers 122 may comprise silicon oxycarbide, silicon nitride, silicon oxynitride, silicon carbonitride, etc., multilayers thereof, or combinations thereof, and may be deposited by CVD, ALD, or other suitable deposition techniques.

[0020] like Figure 1A As shown, fin sidewall spacers 123 may be disposed on opposite sides of each S / D region 124, and fin sidewall spacers 123 may comprise the same material as gate spacers 122. Portions of the gate stack 140, gate spacers 122, and fin sidewall spacers 123 may be disposed on an isolation region 114. Isolation region 114 is disposed on substrate 102. Isolation region 114 may comprise an insulating material, such as an oxygen-containing material, a nitrogen-containing material, or a combination thereof. In some embodiments, isolation region 114 is shallow trench isolation (STI). The insulating material may be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable chemical vapor deposition (FCVD), or other suitable deposition processes. In one aspect, isolation region 114 comprises silicon oxide formed by an FCVD process.

[0021] like Figure 1A and Figure 1B As shown, a contact etch stop layer (CESL) 126 is formed on the S / D region 124 and the isolation region 114, and an interlayer dielectric (ILD) layer 128 is formed on the CESL 126. The CESL 126 provides a mechanism to stop the etching process when an opening is formed in the ILD layer 128. The CESL 126 can be conformally deposited on the surfaces of the S / D region 124 and the isolation region 114. The CESL 126 can include oxygen-containing or nitrogen-containing materials, such as silicon nitride, silicon carbonitride, silicon oxynitride, carbon nitride, silicon oxide, silicon oxycarbide, etc., or combinations thereof, and can be deposited by CVD, PECVD, ALD, or any suitable deposition technique. The ILD layer 128 may comprise an oxide formed from tetraethyl orthosilicate (TEOS), undoped silicate glass, or doped silicon dioxide, such as borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), organosilicon glass (OSG), SiOC, and / or any suitable low-k dielectric material (e.g., a material with a dielectric constant lower than that of silicon dioxide), and may be deposited by spin coating, CVD, FCVD, PECVD, PVD, or any suitable deposition technique.

[0022] Conductive contacts (not shown) may be disposed in the ILD layer 128 and above the S / D region 124. The conductive contacts may be conductive and comprise one or more materials having Ru, Mo, Co, Ni, W, Ti, Ta, Cu, Al, TiN, or TaN, and may be formed by any suitable method, such as electro-chemical plating (ECP) or PVD. A silicide layer (not shown) may be disposed between the conductive contacts and the S / D region 124.

[0023] like Figure 2 As shown, the semiconductor device structure 100 may further include an interconnect structure 300 disposed over the device 200 and the substrate 102. The interconnect structure 300 includes various conductive features, such as a first plurality of conductive features 304 and a second plurality of conductive features 306, and includes an inter-metal dielectric (IMD) layer 302 to separate and isolate the various conductive features 304, 306. In some embodiments, the first plurality of conductive features 304 are wires, and the second plurality of conductive features 306 are conductive vias. The interconnect structure 300 includes multiple layers of conductive features 304, and the conductive features 304 are arranged in each layer to provide electrical paths to various devices 200 disposed below. The conductive features 306 provide vertical circuitry from the device 200 to the conductive features 304 and between the conductive features 304. For example, the bottommost conductive feature 306 of the interconnect structure 300 may be electrically connected to the S / D region 124 ( Figure 1B ) and gate electrode layer 138 ( Figure 1B The conductive contacts are located on the surface of the conductive contact. Conductive features 304 and 306 can be made of one or more conductive materials, such as metals, metal alloys, metal nitrides, or silicides. For example, conductive features 304 and 306 are made of copper, aluminum, aluminum-copper alloys, titanium, titanium nitride, tantalum, tantalum nitride, titanium nitride silicon, zirconium, gold, silver, cobalt, nickel, tungsten, tungsten nitride, tungsten nitride silicon, platinum, chromium, molybdenum, hafnium, other suitable conductive materials, or combinations thereof.

[0024] IMD layer 302 includes one or more dielectric materials to provide isolation to various conductive features 304, 306. IMD layer 302 may include multiple dielectric layers embedded with multiple layers of conductive features 304, 306. IMD layer 302 is made of a dielectric material, such as SiO2. x SiO x C y H z or SiO x C y , where x, y, and z are integers or non-integers. In some embodiments, the IMD layer 302 includes a dielectric material having a k value ranging from about 1 to about 5.

[0025] Figures 3A-3L These are cross-sectional side views of various stages of manufacturing the interconnect structure 300 according to some embodiments. Figure 3A As shown, the interconnect structure 300 includes a dielectric layer 310, which can be an ILD layer or an IMD layer. For example, the dielectric layer 310 can be an ILD layer 128 (…). Figure 1A and Figure 1B ) or IMD layer 302 ( Figure 2 The dielectric layer 310 may include the same material as the ILD layer 128 or the IMD layer 302. In some embodiments, the dielectric layer 310 includes a low-k dielectric material, such as SiOCH. The dielectric layer 310 may be formed by CVD, FCVD, ALD, spin coating, or other suitable processes. The dielectric layer 310 includes one or more conductive features 303 (only one is shown) disposed in the dielectric layer 310. The conductive feature 303 may include a conductive material, such as Cu, Co, Ru, Mo, Cr, W, Mn, Rh, Ir, Ni, Pd, Pt, Ag, Au, Al, alloys thereof, or other suitable materials. In some embodiments, the conductive feature 303 includes a metal. The conductive feature 303 may be formed by PVD, CVD, ALD, or other suitable processes. In some embodiments, the conductive feature 303 may be a conductive contact disposed in the ILD layer 128 or a conductive feature 304 or 306 disposed in the IMD layer 302.

[0026] An etch stop layer 312 is disposed on the dielectric layer 310. The etch stop layer 312 may comprise a nitrogen-containing material or an oxygen-containing material. For example, the etch stop layer 312 may be a nitride or oxide, such as silicon nitride, metal nitride, silicon oxide, or metal oxide. In some embodiments, the etch stop layer 312 includes a CESL 126 ( Figure 1A and Figure 1B The same material. The etch stop layer 312 can be formed by any suitable process, such as CVD, PECVD, ALD, or any suitable process. In some embodiments, the etch stop layer 312 is a conformal layer formed by ALD. The etch stop layer 312 can have a thickness of less than about 10 nm, for example from about 1 nm to about 10 nm. When an opening is formed in the layer disposed above the etch stop layer 312, the etch stop layer 312 provides a mechanism to stop the etch process. Therefore, if the thickness of the etch stop layer 312 is less than about 1 nm, the etch stop layer 312 may not be sufficient to provide a mechanism to stop the etch process. The k value of the etch stop layer 312 can be significantly larger than that of the low-k dielectric layer 326 subsequently formed above the etch stop layer 312. Figure 3D The value of k.

[0027] An oxide layer 314 is disposed on the etch stop layer 312. The oxide layer 314 may comprise a semiconductor or metal oxide. For example, the oxide layer 314 may be silicon dioxide formed from tetraethyl orthosilicate (TEOS). Compared to the etch stop layer 312 and the sacrificial layer 316 disposed on the oxide layer 314, the oxide layer 314 may have high etch selectivity. In some embodiments, the k-value of the oxide layer 314 is smaller than the k-value of the etch stop layer 312 to reduce parasitic capacitance. The oxide layer 314 may be formed by any suitable process, such as CVD, PECVD, ALD, or any suitable process. In some embodiments, the oxide layer 314 is a conformal layer formed by ALD. The oxide layer 314 may have a thickness of less than about 10 nm, for example, from about 1 nm to about 10 nm. The oxide layer 314 provides a mechanism for stopping the etch process when an opening is formed in the layer disposed on top of the oxide layer 314. Therefore, if the thickness of the oxide layer 314 is less than about 1 nm, the oxide layer 314 may be insufficient to provide a mechanism for stopping the etch process. The k-value of oxide layer 314 can be significantly larger than that of the low-k dielectric layer 326 subsequently formed on top of oxide layer 314. Figure 3D The value of k.

[0028] A sacrificial layer 316 is disposed on the oxide layer 314. The sacrificial layer 316 may comprise a semiconductor material, such as amorphous silicon. The sacrificial layer 316 can be formed by any suitable process, such as CVD, PECVD, ALD, or any suitable process. The thickness of the sacrificial layer 316 can range from about 20 nm to about 30 nm. The total thickness of the sacrificial layer 316, the oxide layer 314, and the etch stop layer 312 can be [missing information - likely a number]. Figure 2 The thickness of an IMD layer 302 is shown in the figure. Therefore, the thickness of the sacrificial layer 316 can be based on the thickness of the IMD layer 302. In some embodiments, the total thickness of the sacrificial layer 316, the oxide layer 314, and the etch stop layer 312 can be in the range of about 25 nm to about 50 nm.

[0029] like Figure 3B As shown, a multilayer structure 317 is disposed on a sacrificial layer 316. The multilayer structure 317 includes one or more layers 318 and a photoresist layer 320 disposed on the one or more layers 318. In some embodiments, the multilayer structure 317 is a three-layer photoresist. For example, the one or more layers 318 may include a bottom layer and an intermediate layer disposed on the bottom layer. The bottom layer and the intermediate layer are made of different materials, such that the optical properties and / or etching properties of the bottom layer and the intermediate layer differ from each other. In some embodiments, the bottom layer may be an absorber layer, such as a chromium layer, and the intermediate layer may be a silicon-rich layer designed to provide etch selectivity between the intermediate layer and the bottom layer. The photoresist layer 320 may be a chemically amplified photoresist layer and may be a positive or negative photoresist. The photoresist layer 320 may include polymers such as phenolic resins, poly(norbornene)-conmaleic anhydride (COMA) polymers, poly(4-hydroxystyrene) (PHS) polymers, phenol-formaldehyde (hakelite) polymers, polyethylene (PE) polymers, polypropylene (PP) polymers, polycarbonate polymers, polyester polymers, or acrylate-based polymers such as poly(methyl methacrylate) (PMMA) polymers or poly(methacrylic acid) (PMAA) polymers. The photoresist layer 320 may be formed by spin coating.

[0030] like Figure 3BAs shown, the photoresist layer 320 is patterned. Patterning the photoresist layer 320 may include exposing the photoresist layer 320 to exposure light / beams through a photomask (not shown). The exposure light / beams may be deep ultraviolet (DUV) light, such as KrF excimer lasers and ArF excimer lasers, extreme ultraviolet (EUV) light with a wavelength of approximately 13.5 nm, X-rays, and / or electron beams. In some embodiments, a multiple exposure process is performed. After the exposure process, a development process is performed to form the patterned photoresist layer 320. As a result of the patterning process, openings 321 are formed in the photoresist layer 320, exposing portions of one or more layers 318.

[0031] like Figure 3C As shown, the pattern of the photoresist layer 320 is transferred to the sacrificial layer 316. In some embodiments, exposed portions of one or more layers 318 are removed by one or more etching processes. In some embodiments, one or more layers 318 include an underlayer and an intermediate layer, and portions of the underlayer and intermediate layer are removed by two etching processes. For example, the exposed portions of the intermediate layer are first removed by a first etching process to expose portions of the underlayer, and the exposed portions of the underlayer are removed by a second etching process. In some embodiments, the first and second etching processes are performed in the same etching chamber. Different etchants can be used in the first and second etching processes to remove portions of the intermediate layer and portions of the underlayer. In some embodiments, the etchants include, but are not limited to, H2, Ar, CF4, CHF3, N2, O2, CH4, or combinations thereof. In some embodiments, the second etching process for removing portions of the underlayer uses H2 and CF4 as etchants, and the second etching process is a combination of chemical and physical etching. In some embodiments, both the first and second etching processes are dry etching, such as plasma etching processes with frequencies ranging from about 12.88 MHz to about 14.24 MHz.

[0032] Following the second etching process, a portion of the underlying layer is removed to expose a portion of the sacrificial layer 316. The exposed portion of the sacrificial layer 316 is then removed by a third etching process. In some embodiments, the third etching process is a dry etching process, such as a plasma etching process with a frequency significantly lower than that of the first and second etching processes. For example, the frequency of the third etching process can be in the range of about 1.9 MHz to about 2.1 MHz. With the low-frequency plasma etching process, the sidewalls 322 of the remaining sacrificial layer 316 can be substantially straight. In other words, the third etching process removes a portion of the sacrificial layer 316 to form an opening 324 thereby exposing a portion of the oxide layer 314, and the sidewalls 322 of the remaining sacrificial layer 316 can be substantially perpendicular to the exposed surface of the oxide layer 314. The low frequency of the third etching process increases the electric field in the etching chamber, resulting in increased power absorption capacity, which in turn leads to an increased plasma density. As a result of the increased plasma density, the sidewalls 322 of the remaining sacrificial layer 316 are substantially perpendicular to the exposed surface of the oxide layer 314. The characteristics of low-frequency plasma etching can be based on the following equation:

[0033]

[0034]

[0035] Among them, P ohmic It is power absorption; σ dc It is the DC plasma conductivity; ν m ω is the collision frequency; E is the driving frequency; J is the electric field; T It is the total current; σ p ε is the plasma conductivity; and ε0 is the vacuum permittivity.

[0036] The third etching process for removing portions of the sacrificial layer 316 can use any suitable etchant, such as Ar, O2, N2, He, HBr, Cl2, or combinations thereof. In some embodiments, the etchant used in the third etching process is a chlorine- or bromine-containing etchant. In some embodiments, the third etching process further includes both chemical etching and physical etching. The first, second, and third etching processes can be performed in the same etching chamber. The etching chamber can be a dual-frequency etching chamber, configured to change the frequency from a high frequency, such as above 12 MHz, to a low frequency, such as 2.1 MHz or lower.

[0037] like Figure 3D As shown, a low-k dielectric layer 326 is formed on the remaining sacrificial layer 316 and the oxide layer 314. The low-k dielectric layer 326 may include the same material as the dielectric layer 310. For example, the low-k dielectric layer 326 may include SiOCH. The low-k dielectric layer 326 may be a conformal layer formed by ALD. Figure 3DAs shown, the low-k dielectric layer 326 partially fills the opening 324. The thickness of the low-k dielectric layer 326 is in the range of about 10 nm to about 15 nm. The low-k dielectric layer 326 provides electrical isolation for the conductive features subsequently formed on the oxide layer 314. Therefore, if the thickness of the low-k dielectric layer 326 is less than about 10 nm, the low-k dielectric layer 326 may be insufficient to electrically isolate the conductive features. On the other hand, if the thickness of the low-k dielectric layer 326 is greater than about 15 nm, the opening 324 can be filled.

[0038] In some embodiments, the low-k dielectric layer 326 is a conformal layer formed by ALD. Because the sidewalls 322 of the sacrificial layer 316 are substantially straight, the sidewalls 328 of the low-k dielectric layer 326 are also substantially straight. In other words, the sidewalls 328 of the low-k dielectric layer 326 are substantially perpendicular to the top surface of the oxide layer 314. Figure 3D As shown, the remaining openings 324 have different widths. For example, in some regions, each opening 324 has a first width W1, and in some regions, each opening 324 has a second width W2 that is substantially greater than the width W1. The region with the first width W1 can be a dense region where a relatively large number of conductive features are formed. The region with the second width W2 can be an iso region where a relatively small number of conductive features are formed. In some embodiments, the width W1 is substantially the same as the thickness of the low-k dielectric layer 326. Since the openings 324 with widths W1 and W2 are not formed by a patterning process, the widths W1 and W2 can be smaller than the resolution limit of the patterning process. Furthermore, multiple patterning processes can be avoided. In some other embodiments, the low-k dielectric layer can be formed by FCVD, and an etching process can be performed to form openings in the low-k dielectric layer. In iso regions where most of the low-k dielectric layer can be removed, the etching process may result in tapered sidewalls, leading to deterioration of RC delay. The low-k dielectric layer 326 formed by ALD to create openings 324 with different widths W1 and W2 results in substantially straight sidewalls 328, leading to improved RC delay.

[0039] like Figure 3EAs shown, an anisotropic etching process is performed to remove portions of the low-k dielectric layer 326. In some embodiments, the anisotropic etching process is a selective plasma etching process that substantially does not affect the sacrificial layer 316 and the oxide layer 314. The selective plasma etching process can have a frequency in the range of about 12.88 MHz to about 14.24 MHz and can use etchants such as NF3, H2, N2, Ar, C4F8, O2, or combinations thereof. The anisotropic etching process removes portions of the low-k dielectric layer 326 formed on a horizontal surface, such as the top of the sacrificial layer 316 and the oxide layer 314. The remaining portions of the low-k dielectric layer 326 are in contact with the sidewalls 322 of the sacrificial layer 316. Each portion of the low-k dielectric layer 326 can be a low-k dielectric feature that separates subsequently formed conductive features. The low-k dielectric features have low-k values, such as from about 1 to about 3.5, which reduces RC.

[0040] like Figure 3F As shown, a multilayer structure 330 is disposed on a sacrificial layer 316, a portion of a low-k dielectric layer 326, and an opening 324. The multilayer structure 330 includes one or more layers 332 and a photoresist layer 334 disposed on the one or more layers 332. In some embodiments, the multilayer structure 330 is identical to the multilayer structure 317, the one or more layers 332 is identical to the one or more layers 318, and the photoresist layer 334 is identical to the photoresist layer 320. The photoresist layer 334 can be patterned using the same patterning process as the patterned photoresist layer 320. The pattern of the photoresist layer 334 may include a plurality of openings 336, and each opening 336 is aligned with a corresponding portion of the sacrificial layer 316.

[0041] like Figure 3G As shown, the pattern of the photoresist layer 334 is transferred to one or more layers 332 to expose the sacrificial layer 316, and then the exposed sacrificial layer 316 is removed. In other words, the opening 336 extends to expose a portion of the oxide layer 314, as... Figure 3G As shown. In some embodiments, the etching process for removing the sacrificial layer 316 is a selective plasma etching process that substantially does not affect the low-k dielectric layer 326 and the oxide layer 314. The selective plasma etching process can have a frequency in the range of about 12.88 MHz to about 14.24 MHz and can use etchants such as Cl2, HBr, N2, or combinations thereof. The above etching processes can all be performed in the same etching chamber, such as the dual-frequency etching chamber described above.

[0042] like Figure 3HAs shown, the multilayer structure 330 is removed. The multilayer structure 330 can be removed by one or more etching processes. For example, a first etching process is performed to remove the photoresist layer 334, a second etching process is performed to remove one or more intermediate layers 332, and a third etching process is performed to remove one or more bottom layers 332. The second and / or third etching processes can be selective etching processes that substantially do not affect portions of the low-k dielectric layer 326 and the oxide layer 314. As a result of one or more etching processes, portions of the low-k dielectric layer 326 or low-k dielectric features having substantially straight sidewalls 328 are spaced apart on the oxide layer 314. As described above, the spacing of the portions of the low-k dielectric layer 326 depends on widths W1 and W2 ( Figure 3D ) and the width of part of the sacrificial layer 316.

[0043] like Figure 3I As shown, exposed portions of oxide layer 314 are removed to expose portions of etch stop layer 312. The removal of exposed portions of oxide layer 314 can be performed using a selective plasma etching process that substantially does not affect portions of low-k dielectric layer 326 and etch stop layer 312. The selective plasma etching process can have frequencies ranging from approximately 12.88 MHz to approximately 14.24 MHz and can use etchants such as CHF3, He, or combinations thereof. The selective plasma etching process can be performed in the same etching chamber as other etching processes.

[0044] like Figure 3J As shown, the exposed portion of the etch stop layer 312 is removed. The removal of the exposed portion of the etch stop layer 312 can be performed using a wet cleaning process that substantially does not affect portions of the low-k dielectric layer 326, oxide layer 314, and dielectric layer 310. As a result of the wet cleaning process, dielectric features 338 are spaced apart on the dielectric layer 310. Each dielectric feature 338 includes a portion of the etch stop layer 312, a portion of the oxide layer 314, and a portion of the low-k dielectric layer 326. The thickness of the dielectric features 338 can range from approximately 25 nm to approximately 50 nm.

[0045] like Figure 3K As shown, conductive material 340 is disposed on portions of low-k dielectric layer 326 and dielectric layer 310. In some embodiments, a conformal barrier layer (not shown) may first be formed on portions of low-k dielectric layer 326 and dielectric layer 310, and conductive material 340 may be formed on the barrier layer. In some embodiments, a liner (not shown) or a seed layer (not shown) may be formed between the barrier layer and conductive material 340. Conductive material 340 may include the same material as conductive feature 303.

[0046] like Figure 3L As shown, a planarization process is performed to expose a portion of the low-k dielectric layer 326. The planarization process can be any suitable process, such as chemical mechanical polishing (CMP). The planarization process removes a portion of the conductive material 340 disposed above the low-k dielectric layer 326, and the remaining portion of the conductive material 340 is separated by dielectric features 338. Each portion of the conductive material 340 can be a conductive feature, such as a conductive line. At least a portion of the conductive material 340 is aligned with conductive feature 303. In some embodiments, a portion of the conductive material 340 is... Figure 2 The conductive feature 304 is shown. As described above, the low-k dielectric layer 326 is a conformal layer formed by ALD, and the opening 324 ( Figure 3D The opening 324 is not formed through a patterning process. It is defined by the thickness of the low-k dielectric layer 326. Figure 3D The width W1 of the patterning process and the width W3 of the dielectric feature 338 can be smaller than the resolution limit of the patterning process. In some embodiments, the widths W1 and W3 are substantially the same. For example, both the widths W1 and W3 are in the range of about 10 nm to about 15 nm.

[0047] Figure 4 This is a cross-sectional side view of a semiconductor device structure 100 according to some embodiments. For example... Figure 4 As shown, device 200 is disposed on substrate 102, ILD layer 128 is disposed above device 200, and conductive contact 360 is disposed in ILD layer 128 and above S / D epitaxial feature 124. A silicide layer (not shown) may be disposed between conductive contact 360 and S / D epitaxial feature 124. Dielectric layer 310 is disposed on ILD layer 128, and conductive feature 303 is aligned with conductive contact 360. A portion of conductive material 340 and dielectric feature 338 are disposed on dielectric layer 310 and conductive feature 303. In some embodiments, dielectric feature 338 is IMD layer 302, and a portion of conductive material 340 is... Figure 2 The conductive feature 304 is shown. An etch stop layer 350 is disposed on a portion of the conductive material 340 and the low-k dielectric layer 326. The etch stop layer 350 may include the same material as the etch stop layer 312. A low-k dielectric layer 352 is disposed on the etch stop layer 350, and a conductive feature 354 is disposed in the low-k dielectric layer 352. The low-k dielectric layer 352 may include the same material as the low-k dielectric layer 326, and the conductive feature 354 may include the same material as the conductive feature 303. In some embodiments, the low-k dielectric layer 352 is an IMD layer 302, and the conductive feature 354 is... Figure 2 The conductive feature 306 shown is illustrated.

[0048] This disclosure provides an interconnect structure and a method of forming the same in various embodiments. In some embodiments, the interconnect structure 300 includes a dielectric feature 338 that electrically isolates adjacent portions of a conductive material 340. The dielectric feature 338 may have a width substantially the same as the width of one of the adjacent portions of the conductive material 340. The dielectric feature 338 includes a low-k dielectric layer 326, an oxide layer 314, and an etch stop layer 312. The sidewalls 328 of the low-k dielectric layer 326 are substantially perpendicular to the top surface of the dielectric layer 310 disposed below it. Some embodiments may achieve advantages. For example, the substantially straight sidewalls 328 result in improved RC delay and reduce the number and complexity of processes used to form the interconnect structure 300.

[0049] One embodiment is a method. The method includes forming a first dielectric layer over one or more devices, forming a first conductive feature in the first dielectric layer, and forming two dielectric features over the first dielectric layer and the first conductive feature. At least one of the two dielectric features has a first width, and each dielectric feature includes a first low-k dielectric layer, an oxide layer, and a first etch stop layer. The method further includes forming a second conductive feature between the two dielectric features, and the second conductive feature has a second width substantially the same as the first width.

[0050] Another embodiment is a method. The method includes forming an oxide layer on a first etch stop layer, forming a sacrificial layer on the oxide layer, patterning the sacrificial layer to form a plurality of openings in the sacrificial layer, forming a first low-k dielectric layer on the patterned sacrificial layer and the oxide layer, removing portions of the first low-k dielectric layer disposed on horizontal surfaces of the patterned sacrificial layer and the oxide layer to form a plurality of portions of the first low-k dielectric layer, removing the patterned sacrificial layer, and forming a conductive material between adjacent portions of the plurality of portions of the first low-k dielectric layer.

[0051] Another embodiment is a method. The method includes forming a sacrificial layer on an oxide layer and forming a multilayer structure on the sacrificial layer. The multilayer structure includes photoresist layers disposed on one or more layers. The method further includes removing portions of the one or more layers by a first plasma etching process, the first plasma etching process including the use of a first frequency. The method further includes removing portions of the sacrificial layer by a second plasma etching process to form a patterned sacrificial layer having a plurality of openings, the second plasma etching process including the use of a second frequency significantly lower than the first frequency. The first and second plasma etching processes are performed in the same etching chamber. The method further includes forming a low-k dielectric layer on the patterned sacrificial layer, the low-k dielectric layer partially filling the plurality of openings. The method further includes filling the plurality of openings with a conductive material.

[0052] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0053] Example

[0054] Example 1. A method of manufacturing a semiconductor device, comprising: forming a first dielectric layer over one or more devices; forming a first conductive feature in the first dielectric layer; forming two dielectric features over the first dielectric layer and the first conductive feature, wherein at least one of the dielectric features has a first width, and wherein each dielectric feature includes a first low-k dielectric layer, an oxide layer and a first etch stop layer; and forming a second conductive feature between the two dielectric features, wherein the second conductive feature has a second width substantially the same as the first width.

[0055] Example 2. The method according to Example 1, wherein the oxide layer comprises a semiconductor oxide, and the first etch stop layer comprises a nitride or a metal oxide.

[0056] Example 3. The method according to Example 2, wherein the oxide layer is silicon dioxide and the first low-k dielectric layer comprises SiCOH.

[0057] Example 4. The method according to Example 1, wherein both the first width and the second width are in the range of about 10 nm to about 15 nm.

[0058] Example 5. The method according to Example 1, wherein the second conductive feature is aligned with the first conductive feature.

[0059] Example 6. The method according to Example 1 further includes: providing a second etch stop layer on the two dielectric features and the second conductive feature; providing a second low-k dielectric layer on the second etch stop layer; and providing a third conductive feature in the second low-k dielectric layer.

[0060] Example 7. A method of manufacturing a semiconductor device, comprising: forming an oxide layer on a first etch stop layer; forming a sacrificial layer on the oxide layer; patterning the sacrificial layer to form a plurality of openings in the sacrificial layer; forming a first low-k dielectric layer on the patterned sacrificial layer and the oxide layer; removing portions of the first low-k dielectric layer disposed on horizontal surfaces of the patterned sacrificial layer and the oxide layer to form a plurality of portions of the first low-k dielectric layer; removing the patterned sacrificial layer; and forming a conductive material between adjacent portions of the plurality of portions of the first low-k dielectric layer.

[0061] Example 8. The method according to Example 7 further includes: forming a first multilayer structure on the sacrificial layer before patterning the sacrificial layer, wherein the first multilayer structure includes a first layer or multiple layers and a first photoresist layer.

[0062] Example 9. The method according to Example 8 further includes: removing a portion of the first layer or multiple layers of the first multilayer structure before patterning the sacrificial layer.

[0063] Example 10. The method according to Example 9, wherein removing a portion of the first layer or multiple layers of the first multilayer structure and patterning the sacrificial layer are performed in the same etching chamber.

[0064] Example 11. The method according to Example 7, wherein the first low-k dielectric layer is a conformal layer formed by atomic layer deposition.

[0065] Example 12. The method according to Example 11, wherein forming a plurality of portions of the first low-k dielectric layer includes removing portions of the first low-k dielectric layer disposed on a horizontal surface.

[0066] Example 13. The method according to Example 12 further includes: forming a second multilayer structure on the patterned sacrificial layer before removing the patterned sacrificial layer, wherein the second multilayer structure includes a second layer or multiple layers and a second photoresist layer.

[0067] Example 14. The method according to Example 13 further includes: removing a portion of the second layer or multiple layers of the second multilayer structure before removing the patterned sacrificial layer.

[0068] Example 15. The method according to Example 14, wherein removing a portion of the second layer or multiple layers of the second multilayer structure and removing the patterned sacrificial layer are performed in the same etching chamber.

[0069] Example 16. The method according to Example 7 further includes: forming a second low-k dielectric layer over a portion of the first low-k dielectric layer and the conductive material.

[0070] Example 17. A method of manufacturing a semiconductor device, comprising: forming a sacrificial layer on an oxide layer; forming a multilayer structure on the sacrificial layer, wherein the multilayer structure includes a photoresist layer disposed on one or more layers; removing portions of the one or more layers by a first plasma etching process, wherein the first plasma etching process includes using a first frequency; removing portions of the sacrificial layer by a second plasma etching process to form a patterned sacrificial layer having a plurality of openings, wherein the second plasma etching process includes using a second frequency significantly lower than the first frequency, wherein the first plasma etching process and the second plasma etching process are performed in the same etching chamber; forming a low-k dielectric layer on the patterned sacrificial layer, wherein the low-k dielectric layer partially fills the plurality of openings; and filling the plurality of openings with a conductive material.

[0071] Example 18. The method according to Example 17, wherein the low-k dielectric layer is a conformal layer formed by atomic layer deposition.

[0072] Example 19. The method according to Example 17 further includes: removing a portion of the low-k dielectric layer.

[0073] Example 20. The method according to Example 19 further includes: removing a portion of the oxide layer and a portion of the etch stop layer disposed below the oxide layer.

Claims

1. A method for forming an interconnect structure, comprising: A first dielectric layer is formed on one or more devices; A first conductive feature is formed in the first dielectric layer; Two dielectric features are formed on top of the first dielectric layer and the first conductive feature, wherein at least one of the dielectric features has a first width, and wherein each dielectric feature includes a first low-k dielectric layer, an oxide layer, and a first etch stop layer; and A second conductive feature is formed between the two dielectric features, wherein the second conductive feature has a second width that is substantially the same as the first width.

2. The method according to claim 1, wherein, The oxide layer comprises a semiconductor oxide, and the first etch stop layer comprises a nitride or a metal oxide.

3. The method according to claim 2, wherein, The oxide layer is silicon dioxide, and the first low-k dielectric layer comprises SiCOH.

4. The method according to claim 1, wherein, Both the first width and the second width are in the range of about 10 nm to about 15 nm.

5. The method according to claim 1, wherein, The second conductive feature is aligned with the first conductive feature.

6. The method according to claim 1, further comprising: A second etch stop layer is provided on the two dielectric features and the second conductive feature; A second low-k dielectric layer is disposed on the second etch stop layer; as well as A third conductive feature is provided in the second low-k dielectric layer.

7. A method for forming an interconnect structure, comprising: An oxide layer is formed on the first etch stop layer; A sacrificial layer is formed on the oxide layer; The sacrificial layer is patterned to form multiple openings in the sacrificial layer; A first low-k dielectric layer is formed on the patterned sacrificial layer and the oxide layer; The portion of the first low-k dielectric layer disposed on the horizontal surface of the patterned sacrificial layer and the horizontal surface of the oxide layer is removed to form a plurality of portions of the first low-k dielectric layer; Remove the patterned sacrificial layer; as well as Conductive material is formed between adjacent portions of a plurality of portions of the first low-k dielectric layer.

8. The method according to claim 7, further comprising: A first multilayer structure is formed on the sacrificial layer before patterning, wherein the first multilayer structure includes a first layer or multiple layers and a first photoresist layer.

9. The method according to claim 8, further comprising: Before patterning the sacrificial layer, remove a portion of the first layer or multiple layers of the first multilayer structure.

10. The method according to claim 9, wherein, The removal of a portion of the first layer or multiple layers of the first multilayer structure and the patterning of the sacrificial layer are performed in the same etching chamber.

11. The method according to claim 7, wherein, The first low-k dielectric layer is a conformal layer formed by atomic layer deposition.

12. The method according to claim 11, wherein, The formation of the first low-k dielectric layer includes removing portions of the first low-k dielectric layer disposed on a horizontal surface.

13. The method of claim 12, further comprising: Before removing the patterned sacrificial layer, a second multilayer structure is formed on the patterned sacrificial layer, wherein the second multilayer structure includes a second layer or multiple layers and a second photoresist layer.

14. The method of claim 13, further comprising: Before removing the patterned sacrificial layer, remove a portion of the second layer or multiple layers of the second multilayer structure.

15. The method according to claim 14, wherein, The removal of a portion of the second layer or multiple layers of the second multilayer structure and the removal of the patterned sacrificial layer are performed in the same etching chamber.

16. The method of claim 7, further comprising: A second low-k dielectric layer is formed on a portion of the first low-k dielectric layer and on the conductive material.

17. A method for manufacturing a semiconductor device, comprising: A sacrificial layer is formed on the oxide layer; A multilayer structure is formed on the sacrificial layer, wherein the multilayer structure includes a photoresist layer disposed on one or more layers; The first plasma etching process is used to remove one or more layers of the material, wherein the first plasma etching process includes using a first frequency; A portion of the sacrificial layer is removed by a second plasma etching process to form a patterned sacrificial layer with multiple openings, wherein the second plasma etching process includes using a second frequency significantly lower than the first frequency, and wherein the first plasma etching process and the second plasma etching process are performed in the same etching chamber. A low-k dielectric layer is formed on the patterned sacrificial layer, wherein the low-k dielectric layer partially fills the plurality of openings; and The plurality of openings are filled with a conductive material.

18. The method according to claim 17, wherein, The low-k dielectric layer is a conformal layer formed by atomic layer deposition.

19. The method of claim 17, further comprising: Remove a portion of the low-k dielectric layer.

20. The method of claim 19, further comprising: The portion of the oxide layer to be removed and the portion of the etch stop layer to be disposed below the oxide layer.

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