Semiconductor device and method of forming the same

Abstract

Improved methods for forming gate isolation structures between portions of a gate electrode and semiconductor devices formed by the methods are disclosed. In embodiments, the methods include forming a channel structure over a substrate; forming a first isolation structure extending in a direction parallel to the channel structure; forming a dummy gate structure over the channel structure and the first isolation structure; depositing a hardmask layer over the dummy gate structure; etching the hardmask layer to form a first opening through the hardmask layer over the first isolation structure; conformally depositing a first dielectric layer over the hardmask layer, in the first opening, and over the dummy gate structure; etching the first dielectric layer to extend the first opening and expose the dummy gate structure; and etching the dummy gate structure to extend the first opening and expose the first isolation structure. Embodiments of the present application also relate to methods of forming semiconductor devices.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor devices and methods of forming the same. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing an insulating or dielectric layer, a conductive layer, and a semiconductor layer on a semiconductor substrate and using photolithography to pattern the individual material layers to form circuit components and elements thereon.

[0003] The semiconductor industry is constantly increasing the integration density of individual electronic components (such as transistors, diodes, resistors, capacitors, etc.) by continuously reducing the size of the smallest components, which allows more components to be integrated into a given area. Summary of the Invention

[0004] Some embodiments of this application provide a method for forming a semiconductor device, including: forming a channel structure over a substrate; forming a first isolation structure extending in a direction parallel to the channel structure; forming a dummy gate structure over the channel structure and the first isolation structure; depositing a hard mask layer over the dummy gate structure; etching the hard mask layer to form a first opening through the hard mask layer over the first isolation structure; conformally depositing a first dielectric layer over the hard mask layer, in the first opening, and over the dummy gate structure; etching the first dielectric layer to extend the first opening and expose the dummy gate structure; and etching the dummy gate structure to extend the first opening and expose the first isolation structure.

[0005] Other embodiments of this application provide a method for forming a semiconductor device, comprising: forming a gate structure over a semiconductor substrate; depositing a hard mask over the gate structure; etching the hard mask to form a first opening exposing the gate structure; depositing a first dielectric layer in the first opening; etching the first dielectric layer to form a first spacer and expose the gate structure; and etching the gate structure to expose dielectric fins disposed between the gate structure and the semiconductor substrate.

[0006] Some embodiments of this application provide a method for forming a semiconductor device, comprising: forming a hard mask over a dummy gate structure; etching a first opening extending through the hard mask and partially through the dummy gate structure; conformally depositing a first dielectric layer over the hard mask and the dummy gate structure and in the first opening; simultaneously etching through the first dielectric layer and the dummy gate structure to extend the first opening; and forming a gate isolation structure in the first opening. Attached Figure Description

[0007] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0008] Figure 1 Examples of semiconductor devices including fin field-effect transistors (FinFETs) are shown in three-dimensional views according to some embodiments.

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8A , Figure 8B , Figure 8C , Figure 9A , Figure 9B , Figure 9C , Figure 9D , Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 11A , Figure 11B , Figure 11C , Figure 11D , Figure 12A , Figure 12B , Figure 12C , Figure 12D , Figure 12E , Figure 13A , Figure 13B , Figure 13C , Figure 14A , Figure 14B , Figure 14C , Figure 14D , Figure 15A , Figure 15B , Figure 15C , Figure 15D , Figure 16A , Figure 16B , Figure 16C , Figure 16D , Figure 17A , Figure 17B , Figure 17C , Figure 17D , Figure 17E , Figure 18A , Figure 18B , Figure 18C , Figure 18D , Figure 19A , Figure 19B , Figure 19C , Figure 19D , Figure 20A , Figure 20B , Figure 20C , Figure 20D , Figure 21A , Figure 21B , Figure 21C , Figure 21D , Figure 22A , Figure 22B , Figure 23A , Figure 23B , Figure 24A , Figure 24B , Figure 24C , Figure 24D , Figure 25A , Figure 25B , Figure 25C , Figure 25D , Figure 26A , Figure 26B , Figure 26C , Figure 26D , Figure 27A , Figure 27B , Figure 27C , Figure 27D , Figure 28A , Figure 28B , Figure 28C , Figure 28D , Figure 29A , Figure 29B , Figure 29C , Figure 29D , Figure 30A and Figure 30B These are cross-sectional and top views of intermediate stages in the manufacture of semiconductor devices according to some embodiments.

[0010] Figure 31 Examples of semiconductor devices including nanostructured field-effect transistors (nanoFETs) are shown in three-dimensional views according to some embodiments.

[0011] Figure 32 , Figure 33 , Figure 34 , Figure 35A , Figure 35B , Figure 35C , Figure 36A , Figure 36B , Figure 36C , Figure 37A , Figure 37B , Figure 37C , Figure 37D , Figure 38A , Figure 38B , Figure 38C , Figure 39A , Figure 39B , Figure 39C , Figure 40A , Figure 40B , Figure 41A and Figure 41B These are cross-sectional and top views of intermediate stages in the manufacture of a semiconductor device according to some embodiments. Detailed Implementation

[0012] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0013] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used to describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientation shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0014] Various embodiments provide improved methods for forming isolation structures in gate electrodes and semiconductor devices formed by said methods. The methods include: forming a hard mask over a gate structure (e.g., a dummy gate structure); etching an opening through the hard mask; and depositing a conformal layer over the hard mask and in the opening. The conformal layer can be used to narrow the opening in the hard mask, reducing the critical size of the opening. The conformal layer can be deposited by atomic layer deposition (ALD), plasma-enhanced ALD (PEALD), thermal ALD, etc. The conformal layer can include a material with high etch selectivity to the material of the gate structure. For example, the gate structure can include polysilicon, and the conformal layer can include nitrides (e.g., silicon nitride), oxides (e.g., silicon oxide), metal oxides (e.g., aluminum oxide, titanium oxide, etc.). In some embodiments, the conformal layer can include a material with low etch selectivity to the material of the gate structure. For example, the gate structure can include polysilicon, and the conformal layer can include polysilicon, amorphous silicon, another silicon-based material, etc.

[0015] The opening can then be extended through the conformal layer and the gate structure using one or more etching processes (such as anisotropic etching) to separate adjacent portions of the gate structure from each other. A gate isolation structure can be formed within the opening. Forming a conformal layer within the opening can reduce the critical size of the opening and provide better control over its critical size. This helps reduce device size, improve device performance, and reduce device defects. Furthermore, in embodiments where the conformal layer is formed of a material with high etch selectivity to the gate structure, less slag is generated during the process to form the opening, which reduces device defects. In embodiments where the conformal layer is formed of a material with low etch selectivity to the gate structure, both the conformal layer and the gate structure can be etched simultaneously, reducing processing time and cost.

[0016] Figure 1 An example of a FinFET according to some embodiments is shown. The FinFET includes a fin 55 on a substrate 50 (e.g., a semiconductor substrate). Shallow trench isolation (STI) regions 58 are disposed in the substrate 50, and the fin 55 protrudes over and from between adjacent STI regions 58. Although the STI regions 58 are described / shown as being separated from the substrate 50, as used herein, the term "substrate" may be used to refer only to a semiconductor substrate or a semiconductor substrate including the STI regions. Furthermore, although the fin 55 is shown as a single, continuous material having the substrate 50, the fin 55 and / or the substrate 50 may comprise a single material or multiple materials. In this context, fin 55 refers to the portion extending between adjacent STI regions 58.

[0017] The gate dielectric layer 106 is located along the sidewall of the fin 55 and above the top surface of the fin 55, and the gate electrode 108 is located above the gate dielectric layer 106. Epitaxial source / drain regions 92 are disposed on opposite sides of the fin 55, the gate dielectric layer 106, and the gate electrode 108. Figure 1 Reference cross sections used in the following figures are also shown. Cross section A-A' is along the longitudinal axis of the gate electrode 108 and in a direction, for example, perpendicular to the current flow direction between the epitaxial source / drain regions 92 of the FinFET. Cross section B-B' is perpendicular to cross section A-A' and along the longitudinal axis of the fin 55 and in a direction, for example, between the epitaxial source / drain regions 92 of the FinFET. Cross section C-C' is parallel to cross section A-A' and extends through the epitaxial source / drain regions 92 of the FinFET. For clarity, the following figures refer to these reference cross sections.

[0018] Some embodiments discussed herein are discussed in the context of fin field-effect transistors (FinFETs) formed using a post-gate process. In some embodiments, a pre-gate process may be used. Moreover, some embodiments contemplate aspects used in planar devices (e.g., planar field-effect transistors), nanostructured field-effect transistors (NSFETs) (e.g., nanosheets, nanowires, all-around gates, etc.), etc.

[0019] Figures 2 to 30B This is a cross-sectional view of an intermediate stage in the fabrication of a FinFET according to some embodiments. Figures 2 to 7 , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 17E , Figure 18A , Figure 19A , Figure 20A , Figure 21A , Figure 22A , Figure 23A , Figure 24A , Figure 25A , Figure 26A , Figure 27A , Figure 28A , Figure 29A and Figure 30A along Figure 1 The reference section A-A' shown in the figure is illustrated. Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19B , Figure 20B , Figure 21B , Figure 22B , Figure 23B , Figure 24B , Figure 25B , Figure 26B , Figure 27B , Figure 28B , Figure 29B and Figure 30B along Figure 1 The reference section B-B' shown is illustrated. Figure 9D , Figure 10D , Figure 11D , Figure 12D and Figure 12E along Figure 1 The reference section C-C' shown in the figure is illustrated. Figure 14D , Figure 15D , Figure 16D , Figure 17D , Figure 18D , Figure 19D , Figure 20D , Figure 21D , Figure 24D , Figure 25D , Figure 26D , Figure 27D , Figure 28D and Figure 29D Along parallel to section B-B' and Figure 14C The reference section D-D' shown is illustrated. Figure 8C , Figure 9C , Figure 10C , Figure 11C , Figure 12C , Figure 13C , Figure 14C , Figure 15C , Figure 16C , Figure 17C , Figure 18C , Figure 19C , Figure 20C , Figure 21C , Figure 24C , Figure 25C , Figure 26C , Figure 27C , Figure 28C and Figure 29C This is a top view.

[0020] exist Figure 2 A substrate 50 is provided. The substrate 50 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which can be doped (e.g., having p-type or n-type dopants) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is provided on a substrate that is typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, can also be used. In some embodiments, the semiconductor material of the substrate 50 can include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide phosphide; or combinations thereof.

[0021] The substrate 50 may include an n-type region for forming an n-type device, such as an NMOS transistor, for example an n-type FinFET, and a p-type region for forming a p-type device, such as a PMOS transistor, for example a p-type FinFET. The n-type region may be physically separated from the p-type region, and any number of device components (e.g., other active devices, doped regions, isolation structures, etc.) may be disposed between the n-type region and the p-type region.

[0022] exist Figure 3 In this embodiment, fins 55 and pseudo-fins 57 are formed in substrate 50. Fins 55 and pseudo-fins 57 are semiconductor strips. In some embodiments, fins 55 and pseudo-fins 57 can be formed in substrate 50 by etching trenches in substrate 50. Etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. Etching can be anisotropic.

[0023] Fin 55 and pseudo-fin 57 can be patterned using any suitable method. For example, fin 55 and pseudo-fin 57 can be patterned using one or more photolithography processes including dual patterning or multiple patterning processes. Typically, dual patterning or multiple patterning processes combine photolithography and self-alignment processes, thereby allowing the creation of patterns with, for example, a smaller pitch than that achievable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed and patterned using a photolithography process over a substrate. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern fin 55 and pseudo-fin 57. In some embodiments, a mask (or other layer) can be retained on fin 55 and pseudo-fin 57. Fin 55 can have a width W1 ranging from about 5 nm to about 15 nm, pseudo-fin 57 can have a width W2 ranging from about 10 nm to about 20 nm, and the ratio of width W2 to width W1 can range from about 2 to about 4.

[0024] exist Figure 4In the process, an insulating material 56 is formed adjacent to the fins 55 and dummy fins 57. The insulating material 56 may be formed above the substrate 50 and between adjacent fins 55 and dummy fins 57. The insulating material 56 may be an oxide, such as silicon oxide, nitrides, or combinations thereof, and may be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system followed by post-curing to transform it into another material, such as an oxide), or combinations thereof. Other insulating materials formed by any acceptable process may be used. In the illustrated embodiment, the insulating material 56 is silicon oxide formed by an FCVD process. Once the insulating material 56 is formed, an annealing process may be performed. In some embodiments, the insulating material 56 is formed such that excess insulating material 56 covers the fins 55 and dummy fins 57. The insulating material 56 may comprise a single layer or may utilize multiple layers. For example, in some embodiments, a pad (not shown separately) may first be formed along the surfaces of the substrate 50, fins 55, and dummy fins 57. Subsequently, a filler material, such as those discussed above, may be formed over the pad.

[0025] Then, a removal process is applied to the insulating material 56 to remove excess insulating material above the fins 55 and dummy fins 57. In some embodiments, planarization processes, such as chemical mechanical polishing (CMP), etch-back processes, or combinations thereof, can be used. The planarization process can planarize the insulating material 56, fins 55, and dummy fins 57. The planarization process exposes the fins 55 and dummy fins 57, so that the top surfaces of the fins 55, dummy fins 57, and insulating material 56 are flush after the planarization process is completed.

[0026] exist Figure 5 In this configuration, the pseudo-fin 57 is replaced by a dielectric fin 61 (sometimes referred to as a hybrid fin 61 or fin isolation structure 61). The dielectric fin 61 is formed by etching the pseudo-fin 57 to form a groove in the insulating material 56, and then filling the groove with a dielectric material. The dielectric fin 61 can be deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. The dielectric material can include silicon nitride, silicon oxide, combinations thereof, or multilayers thereof. In some embodiments, the dielectric fin 61 can be formed of doped silicon nitride (e.g., silicon nitride doped with carbon (C), oxygen (O), combinations thereof, etc.). In some embodiments, the dielectric fin 61 can be formed of a material relative to the insulating material 56 and a subsequently formed pseudo-gate layer (such as pseudo-gate layer 62, hereinafter referred to as…). Figure 7The material (discussed) is a dielectric material with high etch selectivity. The bottom surface of the dielectric fin 61 can be configured to be higher than, lower than, or flush with the bottom surface of the insulating material 56. After depositing the dielectric fin 61, removal processes such as CMP, etch-back processes, etc., can be performed to planarize the dielectric fin 61, the insulating material 56, and the fin 55. The dielectric fin 61 can have a width W2 in the range of about 10 nm to about 20 nm.

[0027] exist Figure 6 In this process, the insulating material 56 is recessed to form shallow trench isolation (STI) regions 58. The insulating material 56 is recessed such that the upper portions of the fins 55, dielectric fins 61, and substrate 50 protrude from between adjacent STI regions 58. Furthermore, the top surface of the STI region 58 can have a flat surface, a convex surface, a concave surface (such as a recess), or a combination thereof, as shown. The top surface of the STI region 58 can be formed as flat, convex, and / or concave by appropriate etching. The STI region 58 can be recessed using acceptable etching processes, such as etching processes that are selective to the material of the insulating material 56 (e.g., etching the material of the insulating material 56 at a rate faster than the materials of the fins 55, dielectric fins 61, and substrate 50). For example, oxide removal can be used (using, for example, diluted hydrofluoric acid).

[0028] about Figures 2 to 6 The described process is merely one example of how fins 55 and dielectric fins 61 can be formed. In some embodiments, fins 55 can be formed by an epitaxial growth process. For example, a dielectric layer can be formed over the top surface of substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Homoepitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed, allowing the homoepitaxial structure to protrude from the dielectric layer to form fins 55. Furthermore, in some embodiments, heteroepitaxial structures can be used for fins 55. For example, a heteroepitaxial structure can be used... Figure 6 The fin 55 is recessed, and a material different from the fin 55 can be epitaxially grown over the recessed fin 55. In such an embodiment, the fin 55 includes a recessed material and an epitaxially grown material disposed over the recessed material. In some embodiments, a dielectric layer can be formed over the top surface of the substrate 50, and trenches can be etched through the dielectric layer. A heteroepitaxial structure can then be epitaxially grown in the trenches using a material different from the substrate 50, and the dielectric layer can be recessed so that the heteroepitaxial structure protrudes from the dielectric layer to form the fin 55. In some embodiments of epitaxially growing homoepitaxial or heteroepitaxial structures, the epitaxially grown material can be in-situ doped during growth, which avoids prior and subsequent implantation, but in-situ doping and implantation doping can be used together.

[0029] Furthermore, it may be advantageous to epitaxially grow a material different from the material in the p-type region in the n-type region. In some embodiments, the upper portion of fin 55 may be made of silicon-germanium (Si). x Ge 1-x (where x can be in the range of 0 to 1), silicon carbide, pure or nearly pure germanium, III-V compound semiconductors, II-VI compound semiconductors, etc. For example, materials that can be used to form III-V compound semiconductors include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, etc.

[0030] In addition Figure 6 In this process, suitable wells (not shown separately) may be formed in the fin 55 and / or the substrate 50. In some embodiments, a p-type well may be formed in an n-type region, and an n-type well may be formed in a p-type region. In some embodiments, a p-type well or an n-type well may be formed in both an n-type region and a p-type region.

[0031] In embodiments with different well types, different implantation steps for the n-type and p-type regions can be implemented using photoresist or other masks (not shown separately). For example, photoresist can be formed over fins 55, dielectric fins 61, and STI regions 58 in the n-type region. The photoresist is patterned to expose the p-type regions of the substrate 50. The photoresist can be formed using spin coating and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, n-type impurity implantation is performed in the p-type regions, and the photoresist can be used as a mask to prevent n-type impurities from being implanted into the n-type regions. The n-type impurity can be equal to or less than 1 x 10^6 m^2 implanted in the region. 18 atoms / cm 3 Concentrations of phosphorus, arsenic, antimony, etc., such as at approximately 1 x 10⁻⁶. 16 atoms / cm 3 1x10 18 atoms / cm 3 Between. After implantation, the photoresist is removed, such as through an acceptable ashing process.

[0032] Following implantation in the p-type region, photoresist is formed over the fin 55 and STI region 58 in the p-type region. The photoresist is patterned to expose the n-type region of the substrate 50. The photoresist can be formed using spin coating and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, p-type impurity implantation can be performed in the n-type region, and the photoresist can be used as a mask to prevent p-type impurities from being implanted into the p-type region. The p-type impurity can be equal to or less than 1 x 10^6 impurities implanted in the region. 18 atoms / cm 3 Concentrations of boron, boron fluoride, indium, etc., such as at approximately 1 x 10⁻⁶.16 atoms / cm 3 1x10 18 atoms / cm 3 Between. After implantation, the photoresist can be removed, such as through an acceptable ashing process.

[0033] Following implantation into the n-type and p-type regions, annealing can be performed to repair implantation damage and to activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fins can be doped in situ during growth, which can avoid implantation; however, in-situ doping and implantation doping can be used together.

[0034] exist Figure 7 In this process, a dummy dielectric layer 60 is formed on fin 55, substrate 50, and dielectric fin 61. The dummy dielectric layer 60 can be, for example, silicon oxide, silicon nitride, combinations thereof, etc., and can be deposited or thermally grown according to acceptable techniques. A dummy gate layer 62 is formed above the dummy dielectric layer 60, and a mask layer 64 is formed above the dummy gate layer 62. The dummy gate layer 62 can be deposited above the dummy dielectric layer 60 and then planarized by a process such as CMP. The mask layer 64 can be deposited above the dummy gate layer 62. The dummy gate layer 62 can be a conductive or non-conductive material and can be selected from the group consisting of amorphous silicon, polysilicon, poly-SiGe, metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 62 can be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques known in the art and used for depositing the selected material. The dummy gate layer 62 can be made of other materials that have high etch selectivity relative to the materials of the STI region 58 and the dielectric fin 61. The mask layer 64 can include, for example, silicon nitride, silicon oxynitride, etc. In some embodiments, a single dummy gate layer 62 and a single mask layer 64 are formed across the n-type and p-type regions. While the dummy dielectric layer 60 is in Figure 7 The dummy dielectric layer 60 is shown as being deposited on fin 55, substrate 50, dielectric fin 61 and STI region 58, but the dummy dielectric layer 60 may only cover fin 55, substrate 50 and dielectric fin 61, without being deposited on STI region 58.

[0035] Figures 8A to 30B The various additional steps in the fabrication of the embodiment device are shown. Figures 8A to 30B The diagram shows components in either an n-type or p-type region. For example, Figures 8A to 30B The structures shown can be applied to both n-type and p-type regions. Differences in the structures of n-type and p-type regions (if any) are described in the text accompanying each figure.

[0036] exist Figures 8A to 8C In the middle, mask layer 64 (see Figure 7The mask 74 can be patterned using acceptable photolithography and etching techniques. Acceptable etching techniques can be used to transfer the pattern of the mask 74 to the dummy gate layer 62 to form the dummy gate 72. In some embodiments, the pattern of the mask 74 can also be transferred to the dummy dielectric layer 60. The dummy gate 72 covers the corresponding channel region 68 of the fin 55. The pattern of the mask 74 can be used to separate each of the dummy gates 72 from its adjacent counterpart. The dummy gate 72 can have a longitudinal orientation perpendicular to the longitudinal direction of the fin 55. The dummy dielectric layer 60, the dummy gate 72, and the mask 74 can be collectively referred to as a "dummy gate stack". Figure 8C Sections A-A' and B-B' are also shown.

[0037] exist Figures 9A to 9D In Figures 8A to 8C A first spacer layer 80 and a second spacer layer 82 are formed above the structure shown. Figures 9A to 9D In this configuration, a first spacer layer 80 is formed on the top surface of the STI region 58, the top surface and sidewalls of the fin 55 and the mask 74, and the sidewalls of the dummy gate 72 and the dummy dielectric layer 60. A second spacer layer 82 is deposited above the first spacer layer 80. The first spacer layer 80 can be formed by thermal oxidation or deposited by CVD, ALD, etc. The first spacer layer 80 can be formed of silicon oxide, silicon nitride, silicon oxynitride, etc. The second spacer layer 82 can be deposited by CVD, ALD, etc. The second spacer layer 82 can be formed of silicon oxide, silicon nitride, silicon oxynitride, etc. Figure 9C Sections A-A', B-B', and C-C' are also shown.

[0038] exist Figures 10A to 10D In the process, a first spacer layer 80 and a second spacer layer 82 are etched to form a first spacer 81 and a second spacer 83. The first spacer layer 80 and the second spacer layer 82 can be etched using a suitable etching process, such as anisotropic etching (e.g., dry etching). The first spacer 81 and the second spacer 83 can be disposed on the sidewalls of the fin 55, dielectric fin 61, dummy dielectric layer 60, dummy gate 72, and mask 74. The heights of the first spacers 81 and 83 adjacent to the fin 55 and dielectric fin 61 can differ from the heights of the first spacers 81 and 83 adjacent to the dummy gate stack. The height difference in the first spacers 81 and 83 can be caused by the etching process used to etch the first spacer layer 80 and the second spacer layer 82, as well as the height difference between the dummy gate stack and the fin 55 / dielectric fin 61. Figure 10B and Figure 10DAs shown, in some embodiments, the first spacer 81 and the second spacer 83 may extend partially upward to the sidewalls of the fin 55, the dielectric fin 61, and the dummy gate stack. In some embodiments, the first spacer 81 and the second spacer 83 may extend to the top surface of the dummy gate stack, the top surface of the fin 55, and / or the top surface of the dielectric fin 61.

[0039] After the first spacer 81 and the second spacer 83 are formed, implantation for the lightly doped source / drain (LDD) region (not shown separately) can be performed. In embodiments with different device types, similar to the above... Figure 4 The implantation discussed earlier can involve forming a mask, such as photoresist, over the n-type region while exposing the p-type region, and implanting an impurity of an appropriate type (e.g., p-type) into the exposed fin 55 and substrate 50 in the p-type region. The mask can then be removed. The n-type impurity can be any n-type impurity discussed earlier, and the p-type impurity can be any p-type impurity discussed earlier. The lightly doped source / drain region can have approximately 1 x 102 15 atoms / cm 3 To approximately 1x10 19 atoms / cm 3 The concentration of impurities. Annealing can be used to repair implantation damage and reactivate implanted impurities.

[0040] It should be noted that the above disclosure generally describes the process for forming the spacers and LDD regions. Other processes and sequences can be used. For example, fewer or additional spacers can be used, different step sequences can be used (e.g., the first spacer 81 can be formed before the second spacer 83 is formed, additional spacers can be formed and removed, etc.). Furthermore, n-type and p-type devices can be formed using different structures and steps.

[0041] exist Figures 11A to 11D In the process, the substrate 50 and fin 55 are etched to form a first groove 86. For example... Figure 11DAs shown, the top surface of the STI region 58 may be flush with the top surface of the fin 55. In some embodiments, the bottom surface of the first groove 86 is disposed above or below the top surface of the STI region 58. The substrate 50 and the fin 55 are etched using anisotropic etching processes, such as RIE, NBE, etc. The first spacer 81, the second spacer 83, the mask 74, and the dielectric fin 61 mask portions of the substrate 50 and the fin 55 during the etching process used to form the first groove 86. A single etching process or multiple etching processes may be used to form the first groove 86. After the first groove 86 reaches the desired depth, a timing etching process may be used to stop the etching of the first groove 86.

[0042] exist Figures 12A to 12E In this process, an epitaxial source / drain region 92 is formed in the first groove 86 to apply stress to the channel region 68 of the fin 55, thereby improving performance. For example... Figure 12B As shown, epitaxial source / drain regions 92 are formed in the first recess 86, such that each dummy gate 72 is disposed between corresponding adjacent pairs of epitaxial source / drain regions 92. In some embodiments, a first spacer 81 is used to separate the epitaxial source / drain regions 92 from the dummy gates 72 by an appropriate lateral distance, such that the epitaxial source / drain regions 92 do not short-circuit the gate subsequently formed in the resulting FinFET.

[0043] The epitaxial source / drain region 92 in the n-type region can be formed by masking the p-type region. The epitaxial source / drain region 92 is then epitaxially grown in the first groove 86. The epitaxial source / drain region 92 can include any acceptable material, such as that suitable for an n-type FinFET. For example, if the fin 55 is silicon, the epitaxial source / drain region 92 can include a material on which tensile strain is applied, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. The epitaxial source / drain region 92 can have a surface protruding from the corresponding surface of the fin 55 and can have a facet.

[0044] The epitaxial source / drain region 92 in the p-type region can be formed by masking the n-type region. The epitaxial source / drain region 92 is then epitaxially grown in the first groove 86. The epitaxial source / drain region 92 can include any acceptable material, such as that suitable for a p-type finFET. For example, if the fin 55 is silicon, the epitaxial source / drain region 92 can include a material on which compressive strain is applied, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, etc. The epitaxial source / drain region 92 can also have a surface protruding from the corresponding surface of the fin 55 and can have a small facet.

[0045] The epitaxial source / drain regions 92, fins 55, and / or substrate 50 can be implanted with dopants to form source / drain regions, similar to the previously discussed process for forming lightly doped source / drain regions, followed by annealing. The source / drain regions can have a size of approximately 1 x 10⁻⁶. 19 atoms / cm 3 1x10 21 atoms / cm 3 The impurity concentrations between these values. The n-type and / or p-type impurities used for the source / drain regions can be any of the impurities discussed previously. In some embodiments, the epitaxial source / drain regions 92 can be doped in situ during growth.

[0046] Due to the epitaxial process used to form the epitaxial source / drain regions 92 in the n-type and p-type regions, the upper surface of the epitaxial source / drain regions 92 has small facets that extend laterally outward beyond the sidewalls of the fin 55. In some embodiments, these small facets cause adjacent epitaxial source / drain regions 92 of the same finFET to merge, such as... Figure 12D As shown. In some embodiments, after the epitaxial process is completed, adjacent epitaxial source / drain regions 92 remain separated, as shown. Figure 12E As shown. In Figure 12D and Figure 12E In the illustrated embodiment, the first spacer 81 and the second spacer may be formed as portions covering the sidewalls of the fin 55 extending over the STI region 58, thereby blocking epitaxial growth. In some embodiments, the spacer etching used to form the first spacer 81 and the second spacer 83 may be adjusted to remove spacer material to allow the epitaxial growth region to extend to the surface of the STI region 58.

[0047] The epitaxial source / drain region 92 may include one or more semiconductor material layers. For example, the epitaxial source / drain region 92 may include a first semiconductor material layer 92A, a second semiconductor material layer 92B, and a third semiconductor material layer 92C. Any number of semiconductor material layers can be used for the epitaxial source / drain region 92. Each of the first semiconductor material layer 92A, the second semiconductor material layer 92B, and the third semiconductor material layer 92C may be formed of different semiconductor materials and / or may be doped to different dopant concentrations. In some embodiments, the first semiconductor material layer 92A may have a dopant concentration less than that of the second semiconductor material layer 92B and greater than that of the third semiconductor material layer 92C. In embodiments where the epitaxial source / drain region 92 includes three semiconductor material layers, the first semiconductor material layer 92A may be deposited, the second semiconductor material layer 92B may be deposited over the first semiconductor material layer 92A, and the third semiconductor material layer 92C may be deposited over the second semiconductor material layer 92B.

[0048] exist Figures 13A to 13CIn, respectively in Figures 12A to 12C A first interlayer dielectric (ILD) 96 is deposited over the structure shown. The first ILD 96 can be formed of a dielectric material and can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. In some embodiments, the dielectric material for the first ILD 96 may include silicon oxide, silicon nitride, silicon oxynitride, etc. Other insulating materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) 94 is disposed between the first ILD 96 and the epitaxial source / drain region 92, mask 74, and first spacer 81. CESL 94 may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, etc., having an etch rate different from that of the first ILD 96 described above. In some embodiments, the first ILD 96 may be formed of silicon oxide or silicon nitride and the CESL 94 may be formed of silicon oxide or silicon nitride.

[0049] exist Figures 14A to 14D In this process, the mask 74 is etched to form a first opening 98 exposing the dummy gate 72. In some embodiments, the first spacer 81 may be formed of the same material as the mask 74 and may be etched simultaneously with the mask 74. For example, in some embodiments, the first spacer 81 and the mask 74 may comprise nitrides, such as silicon nitride. The mask 74 may be etched using anisotropic etching processes, such as RIE, NBE, etc. Figure 14A and Figure 14C As shown, the first opening 98 may have a width W3 in a direction perpendicular to the longitudinal axis of the dielectric fin 61. The width W3 may be in the range of about 18 nm to about 40 nm. In some embodiments, the width W3 may be increased to the range of about 30 nm to about 50 nm. Figure 14C Sections A-A', B-B', and D-D' are also shown.

[0050] exist Figures 15A to 15D In, respectively in Figures 14A to 14DA first dielectric layer 100 is deposited over the structure shown. The first dielectric layer 100 can be deposited using a conformal deposition process, such as ALD, PEALD, thermal ALD, etc. The first dielectric layer 100 may include a material with high etch selectivity relative to the material of the dummy gate 72. For example, in some embodiments, the dummy gate 72 may be formed of polysilicon, etc., and the first dielectric layer 100 may be formed of nitrides (e.g., silicon nitride), oxides (e.g., silicon oxide), metal oxides (e.g., aluminum oxide, titanium oxide, etc.). In some embodiments, the mask 74 and the first dielectric layer 100 may be formed of silicon nitride, which can improve the adhesion between the first dielectric layer 100 and the mask 74 and avoid peeling problems caused by stress between the first dielectric layer 100 and the mask 74. In some embodiments, the first dielectric layer 100 may be formed of silicon oxide, which can release the stress caused by the deposition of the first dielectric layer 100. In some embodiments, the first dielectric layer 100 may include a multilayer structure (the first dielectric layer 100 may be referred to as the first dielectric structure 100). For example, the first dielectric structure 100 may include Figures 14A to 14D The structure shown includes a silicon oxide layer above the silicon oxide layer and a silicon nitride layer above the silicon oxide layer. The silicon oxide layer can be used to release stress caused by the deposition of the first dielectric structure 100. Finally, forming the first dielectric layer 100 of silicon nitride using thermal ALD can increase the density of the first dielectric layer 100 and improve the control of the process used to deposit the first dielectric layer, thereby improving the quality of the first dielectric layer 100.

[0051] The first dielectric layer 100 can be formed with a thickness T1 ranging from about 3 nm to about 5 nm. Forming the first dielectric layer 100 with a thickness greater than 5 nm may require the first opening 98 to have a larger width and may increase the difficulty of the subsequent process for etching the first dielectric layer 100 (such as the following regarding...). Figures 16A to 16D (Described process). Forming the first dielectric layer 100 to a thickness of less than 3 nm may increase the difficulty of the process used to deposit the first dielectric layer 100.

[0052] exist Figures 16A to 16D In the middle, the first dielectric layer 100 is etched (see...) Figures 15A to 15DThe first dielectric layer 100 is etched using a suitable etching process, such as anisotropic etching (e.g., dry etching). In embodiments where the first dielectric layer 100 comprises silicon nitride, the first dielectric layer 100 can be etched using a dry etching process employing fluorocarbons, which selectively etches the material of the first dielectric layer 100 relative to the dummy gate 72. The etching process can remove the first dielectric layer 100 from the top surfaces of the first ILD 96, CESL 94, second spacer 83, and dummy gate 72. The remaining third spacer 101 can be disposed on the sidewall of the second spacer 83. Figure 16A and Figure 16C As shown, opposing third spacers 101 disposed in the same first opening 98 are separated from each other by a width W4 in a direction perpendicular to the longitudinal axis of the dielectric fin 61. The width W4 can be in the range of about 12 nm to about 30 nm. In some embodiments, the width W4 can be a distance from the width W2 of the dielectric fin 61 by about 1 nm to about 2 nm, and the ratio of the width W4 to the width W2 can be in the range of about 0.5 to about 1.5.

[0053] Forming the first opening 98 and then narrowing it using the third spacer 101 provides better control over the width of the first opening 98 and reduces its critical size. This helps improve device performance, reduce device defects, and decrease component size. Because the third spacer 101 is formed of a material with high etch selectivity to the underlying dummy gate 72, the dummy gate 72 can be etched with reduced dross. This allows the third spacer 101 to be formed with a width W4 of less than 16 nm. The improved etching process with reduced dross reduces leakage current, which improves device performance.

[0054] exist Figures 17A to 17EIn this process, a mask 74 and a third spacer 101 are used as masks to etch the dummy gate 72 and the dummy dielectric layer 60, extending the first opening 98. The dummy gate 72 can be etched using a suitable etching process, such as anisotropic etching (e.g., dry etching). In embodiments where the dummy gate 72 comprises polysilicon, the dummy gate 72 can be etched using a dry etching process using fluorine, which selectively etches the material of the dummy gate 72 relative to the third spacer 101, mask 74, first ILD 96, CESL 94, first spacer 81, and second spacer 83. After etching, the first opening 98 may have a width W4 flush with the top surface of the dummy gate 72, a width W5 flush with the bottom surface of the dummy dielectric layer 60 on the dielectric fin 61, and a depth D1 between the top surface of the dummy gate 72 and the bottom surface of the dummy dielectric layer 60 on the dielectric fin 61. Width W4 can range from about 12 nm to about 30 nm, as discussed above; width W5 can range from about 12 nm to about 25 nm; and depth D1 can range from about 80 nm to about 140 nm. While the first opening 98 is shown as having a tapered profile extending through the dummy gate 72 and the dummy dielectric layer 60, the first opening 98 can have vertical sidewalls or an inverted tapered profile (widening in the direction from the top surface of the dummy gate 72 to the bottom surface of the dummy dielectric layer 60). Forming the first opening 98 and then narrowing it using the third spacer 101 provides better control over the width of the first opening 98 and reduces its critical size. Because the third spacer 101 is formed of a material with high etch selectivity relative to the dummy gate 72, the dummy gate 72 can be etched for a sufficient time to completely etch through it, reducing slag left in the first opening 98, which reduces leakage current and allows for a smaller critical size. Therefore, the described method contributes to improved device performance, reduced device defects, and smaller part size.

[0055] Figure 17E An embodiment is shown in which the portion of the first opening 98 extending through the dummy gate 72 and the dummy dielectric layer 60 has a width greater than the width between the third spacers 101. The first opening 98 may have a width W6 flush with the top surface of the dummy gate 72 in the range of about 10 nm to about 28 nm and a width W7 flush with the bottom surface of the dummy dielectric layer 60 on the dielectric fin 61 in the range of about 10 nm to about 22 nm.

[0056] exist Figures 18A to 18D In, respectively in Figures 17A to 17DA gate isolation structure 102 is formed above the structure. The gate isolation structure 102 can fill the first opening 98, extends along the top surface of the dielectric fin 61 and along the side surfaces of the third spacer 101, the dummy gate 72, and the dummy dielectric layer 60, and extends along the top surfaces of the first ILD 96, CESL 94, the second spacer 83, the mask 74, and the third spacer 101. The gate isolation structure 102 can be used to isolate the dummy gate 72 from subsequent gate electrodes (such as gate electrode 108, as discussed below). Figures 21A to 21D (Discussion) Replacement section.

[0057] It should be understood that although the dummy gate 72 is diced and the gate isolation structure 102 is formed before the replacement gate stack is formed in the illustrated embodiment, the replacement gate stack can be diced and the gate isolation structure 102 can be formed after the replacement gate stack is formed. In some embodiments, the material of the gate isolation structure 102 can be deposited using a conformal deposition process, such as ALD, PEALD, thermal ALD, etc. The gate isolation structure 102 can be formed of a dielectric material, such as silicon nitride, silicon oxide, silicon carbide, silicon carbonitride, combinations thereof, or multilayers thereof.

[0058] exist Figures 19A to 19D In this context, planarization processes, such as CMP, can be implemented. Planarization processes can... Figures 18A to 18D The gate isolation structure 102 shown is divided into separated gate isolation regions 103, and the top surfaces of the gate isolation regions 103 and the first ILD 96 are flush with the top surface of the dummy gate 72. A planarization process may also remove portions of the mask 74, the third spacer 101, the second spacer 83, and the CESL 94 on the dummy gate 72. After the planarization process, the top surfaces of the dummy gate 72, the first spacer 81, the second spacer 83, the gate isolation region 103, the CESL 94, and the first ILD 96 are flush. Therefore, the top surface of the dummy gate 72 is exposed through the mask 74. After the planarization process, the top surface of the gate isolation region 103 may have a width W4 in the range of about 12 nm to about 30 nm, the bottom surface of the gate isolation region 103 may have a width W5 in the range of about 12 nm to about 25 nm, and the gate isolation region 103 may have a height H1 in the range of about 80 nm to about 120 nm.

[0059] exist Figures 20A to 20DIn the etching step, the dummy gate 72 is removed, thereby forming the second recess 104. A portion of the dummy dielectric layer 60 located in the second recess 104 may also be removed. In some embodiments, the dummy gate 72 is removed, the dummy dielectric layer 60 is retained, and the dummy dielectric layer 60 is exposed by the second recess 104. In some embodiments, the dummy dielectric layer 60 is removed from the second recess 104 in a first region of the die (e.g., a core logic region), and the dummy dielectric layer 60 is retained in the second recess 104 in a second region of the die (e.g., an input / output region). In some embodiments, the dummy gate 72 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using reactive gases that selectively etches the dummy gate 72 at a rate faster than the first ILD 96, CESL 94, first spacer 81, or second spacer 83. Each exposure of the second recess 104 is located over a channel region 68 of the corresponding fin 55. Each channel region 68 is disposed between adjacent pairs of epitaxial source / drain regions 92. During removal, the dummy dielectric layer 60 can be used as an etch stop layer when the dummy gate 72 is etched. After the dummy gate 72 is removed, the dummy dielectric layer 60 can optionally be removed.

[0060] exist Figures 21A to 21D In this process, a gate dielectric layer 106 and a gate electrode 108 are formed to replace the gate. The gate dielectric layer 106 can be formed by depositing one or more layers in the second recess 104, such as on the top surface and sidewalls of the fin 55, the first spacer 81, and the gate isolation region 103, and on the top surface of the STI region 58, the first ILD 96, the CESL 94, and the second spacer 83. The gate dielectric layer 106 may include one or more layers of silicon oxide, silicon nitride, metal oxide, metal silicate, etc. For example, in some embodiments, the gate dielectric layer 106 includes a silicon oxide interface layer formed by thermal or chemical oxidation and a high-k dielectric material thereon, such as a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, combinations thereof, etc. The gate dielectric layer 106 may include a dielectric layer having a k value greater than about 7.0. The gate dielectric layer 106 can be deposited by molecular beam deposition (MBD), ALD, PECVD, etc. In embodiments where a portion of the dummy dielectric layer 60 remains in the second recess 104, the gate dielectric layer 106 may include the material of the dummy dielectric layer 60 (e.g., SiO2).

[0061] Gate electrode 108 is deposited over gate dielectric layer 106 and fills the remainder of second groove 104. Gate electrode 108 may include a metallic material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multilayers thereof. For example, although Figures 21A to 21DA single-layer gate electrode 108 is shown, but the gate electrode 108 may include any number of pad layers, any number of power function adjustment layers, and filler material (not shown separately). After the second recess 104 is filled, a planarization process, such as CMP, is performed to remove excess portions of the gate dielectric layer 106 and the gate electrode 108 located above the top surfaces of the first ILD 96, CESL 94, first spacer 81, second spacer 83, and gate isolation region 103. The remaining portions of the gate electrode 108 and the gate dielectric layer 106 form the replacement gate of the resulting FinFET. The gate electrode 108 and the gate dielectric layer 106 may be collectively referred to as the “gate stack”. The gate stack may extend along the sidewalls of the channel region 68 of the fin 55.

[0062] The formation of the gate dielectric layer 106 in the n-type and p-type regions can occur simultaneously, such that the gate dielectric layer 106 in each region is formed of the same material. The formation of the gate electrode 108 can also occur simultaneously, such that the gate electrode 108 in each region is formed of the same material. In some embodiments, the gate dielectric layer 106 in each region can be formed using different processes, such that the gate dielectric layer 106 can be made of different materials. The gate electrode 108 in each region can be formed using different processes, such that the gate electrode 108 can be made of different materials. When different processes are used, the respective masking steps can be used to mask and expose appropriate regions.

[0063] exist Figure 22A and Figure 22BIn this process, a second ILD 112 is deposited over the first ILD 96, CESL 94, first spacer 81, second spacer 83, gate isolation region 103, gate dielectric layer 106, and gate electrode 108. In some embodiments, the second ILD 112 is a flowable film formed by FCVD. In some embodiments, the second ILD 112 is formed of a dielectric material, such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method, such as CVD, PECVD, etc. In some embodiments, the dielectric material for the second ILD 112 may include silicon oxide, silicon nitride, silicon oxynitride, etc. In some embodiments, prior to the formation of the second ILD 112, the gate stack (including the gate dielectric layer 106 and the corresponding upper gate electrode 108) is recessed, thereby forming a groove directly over each of the respective gate stacks and between the opposite portions of the first spacer 81. A gate mask 110 comprising one or more layers of dielectric material (such as silicon nitride, silicon oxynitride, etc.) is filled in the recess, followed by a planarization process to remove excess portions of the dielectric material extending over the first ILD 96, CESL 94, gate isolation region 103, first spacer 81, and second spacer 83. Gate contacts (such as gate contact 114, described below) are then formed. Figure 23A and Figure 23B (Discussion) Penetrates the gate mask 110 to contact the top surface of the recessed gate electrode 108.

[0064] exist Figure 23A and Figure 23B In this configuration, a gate contact 114 is formed through the second ILD 112 and the gate mask 110, and a source / drain contact 116 is formed through the second ILD 112, the first ILD 96, and the CESL 94. An opening for the source / drain contact 116 is formed through the second ILD 112, the first ILD 96, and the CESL 94, and an opening for the gate contact 114 is formed through the second ILD 112 and the gate mask 110. The openings can be formed using acceptable photolithography and etching techniques. In some embodiments, after forming the openings for the source / drain contacts through the second ILD 112, the first ILD 96, and the CESL 94, a silicide region 113 is formed over the epitaxial source / drain region 92. The silicide region 113 can be formed by first depositing a metal (not shown) capable of reacting with the semiconductor material (e.g., silicon, silicon-germanium, germanium) of the underlying epitaxial source / drain region 92 to form a silicide or germanide region (such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof) over the exposed portion of the epitaxial source / drain region 92, and then performing a thermal annealing process to form the silicide region 113.

[0065] A pad (such as a diffusion barrier layer, adhesive layer, etc.) and conductive material are formed in the opening. The pad may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process, such as CMP, may be performed to remove excess material from the surface of the second ILD112. The remaining pad and conductive material form source / drain contacts 116 and gate contacts 114 in the opening. The source / drain contacts 116 are electrically coupled to the epitaxial source / drain region 92 through the silicide region 113, and the gate contact 114 is electrically coupled to the gate electrode 108. The source / drain contacts 116 and the gate contact 114 may be formed in different processes or in the same process. Although shown as being formed in the same cross section, it should be understood that each of the source / drain contacts 116 and the gate contact 114 may be formed in a different cross section, which avoids short circuits of the contacts.

[0066] The embodiments can achieve various advantages. For example, forming the first opening 98 through mask 74, conformally depositing the first dielectric layer 100 in the first opening 98, and anisotropically etching the first dielectric layer 100 to form the third spacer 101 allows for a reduction in the critical size of the first opening 98 and provides better control over the critical size of the first opening 98. This reduces device defects and improves device performance. The third spacer 101 can be formed of a material with high etch selectivity to the dummy gate 72, and the dummy gate 72 can be etched for a sufficient time to remove dross in the first opening 98, which reduces leakage current. Subsequently, a gate isolation region 103 is formed in the first opening 98, which can be used to isolate adjacent gate stacks from each other.

[0067] Figures 24A to 30B An embodiment is shown in which the first dielectric layer 100 is formed of a material having low etch selectivity for the dummy gate 72. Figures 24A to 24D In the process, after etching mask 74, as mentioned above... Figures 14A to 14D As discussed, mask 74 is used as a mask to etch the dummy gate 72, extending the first opening 98. The dummy gate 72 can be etched using anisotropic etching processes, such as RIE, NBE, etc. Figure 24A and Figure 24C As shown, the first opening 98 may have a width W8 in a direction perpendicular to the longitudinal axis of the dielectric fin 61. The width W8 may be in the range of about 30 nm to about 45 nm. The first opening 98 may extend to a depth D2 in the range of about 20 nm to about 30 nm below the top surface of the dummy gate 72.

[0068] exist Figures 25A to 25D In, respectively in Figures 24A to 24DA first dielectric layer 100 is deposited over the structure shown. The first dielectric layer 100 can be deposited using a conformal deposition process, such as ALD, PEALD, thermal ALD, etc. The first dielectric layer 100 may include a material with low etch selectivity relative to the material of the dummy gate 72. For example, in some embodiments, the dummy gate 72 may be formed of polysilicon, etc., and the first dielectric layer 100 may be formed of polysilicon, amorphous silicon, other silicon-based materials, etc. The first dielectric layer 100 may be formed with a thickness T2 in the range of about 3 nm to about 5 nm. Forming the first dielectric layer 100 with a thickness greater than 5 nm may require the first opening 98 to have a larger width and may increase the difficulty of the subsequent process for etching the first dielectric layer 100 (as described below). Figures 26A to 26D (Described process). Forming the first dielectric layer 100 to a thickness of less than 3 nm can increase the difficulty of the process used to deposit the first dielectric layer 100.

[0069] exist Figures 26A to 26D In this process, the first dielectric layer 100 and the dummy gate 72 are etched to extend the first opening 98 through the dummy gate 72. The first dielectric layer 100 and the dummy gate 72 can be etched using a suitable etching process, such as anisotropic etching (e.g., dry etching). In embodiments where the dummy gate 72 and the first dielectric layer 100 comprise a silicon-based material, the dummy gate 72 and the first dielectric layer 100 can be etched using a dry etching process using fluorine, which selectively etches the material of the dummy gate 72 and the first dielectric layer 100 relative to the mask 74, the first ILD 96, the CESL 94, the first spacer 81, and the second spacer 83.

[0070] After etching, the first opening 98 can have a width W9 flush with the top surface of the mask 74 and a width W' flush with the bottom surface of the dummy dielectric layer 60 on the dielectric fin 61. 10 And the depth D3 between the top surface of the dummy gate 72 and the bottom surface of the dummy dielectric layer 60 on the dielectric fin 61. The width W9 can be in the range of approximately 12 nm to approximately 16 nm; the width W 10 It can be in the range of approximately 10 nm to approximately 20 nm; and the depth D3 can be in the range of approximately 80 nm to approximately 120 nm. Although the extension of the first opening 98 through the portion of the first dielectric layer 100 and the dummy gate 72 is in Figures 26A to 26DThe diagram shows a tapered profile, but the first opening 98 can have vertical sidewalls or an inverted tapered profile (widening in the direction from the top surface of the first dielectric layer 100 toward the dielectric fin 61). Forming the first opening 98 and then narrowing it using the first dielectric layer 100 provides better control over the width of the first opening 98 and reduces its critical size, which helps improve device performance, reduce device defects, and reduce component size. Furthermore, forming the first dielectric layer 100 from a material with low etch selectivity to the dummy gate 72 allows for simultaneous etching of both the first dielectric layer 100 and the dummy gate 72, reducing processing time and cost.

[0071] exist Figures 27A to 27D In, respectively in Figures 26A to 26D A gate isolation structure 102 is formed above the structure. The gate isolation structure 102 can fill the first opening 98, extend along the top surface of the dielectric fin 61 and along the sides of the first dielectric layer 100, the dummy gate 72 and the dummy dielectric layer 60, and extend along the top surfaces of the first ILD 96, CESL 94, the second spacer 83, the mask 74 and the third spacer 101. The gate isolation structure 102 can be used to isolate the dummy gate 72 subsequently formed by the gate electrode (such as the gate electrode 108, as discussed below). Figures 21A to 21D (Discussion) Replacement section.

[0072] It should be understood that although the dummy gate 72 is diced and the gate isolation structure 102 is formed before the replacement gate stack is formed in the illustrated embodiment, the replacement gate stack can be diced and the gate isolation structure 102 can be formed after the replacement gate stack is formed. In some embodiments, the material of the gate isolation structure 102 can be deposited using a conformal deposition process, such as ALD, PEALD, thermal ALD, etc. The gate isolation structure 102 can be formed of a dielectric material, such as silicon nitride, silicon oxide, silicon carbide, silicon carbonitride, combinations thereof, or multilayers thereof.

[0073] In addition, Figures 27A to 27DIn this process, planarization processes, such as CMP, can be implemented. The planarization process can divide the illustrated gate isolation structure 102 into separate gate isolation structures 102, and make the top surfaces of the gate isolation structure 102 and the first ILD 96 flush with the top surface of the dummy gate 72. The planarization process can also remove portions of the mask 74, the first dielectric layer 100, the second spacer 83, and the CESL 94 on the dummy gate 72. After the planarization process, the top surfaces of the dummy gate 72, the first dielectric layer 100, the first spacer 81, the second spacer 83, the gate isolation structure 102, the CESL 94, and the first ILD 96 are flush. Therefore, the top surface of the dummy gate 72 is exposed through the mask 74. After the planarization process, the top surface of the gate isolation structure 102 can have a width W9 in the range of about 25 nm to about 30 nm, and the bottom surface of the gate isolation structure 102 can have a width W in the range of about 10 nm to about 20 nm. 10 Furthermore, the gate isolation structure 102 may have a height H2 in the range of approximately 60 nm to approximately 100 nm.

[0074] exist Figures 28A to 28D In the etching step, the dummy gate 72 and the first dielectric layer 100 are removed to form the second recess 104. Because the first dielectric layer 100 is formed of a material with low etch selectivity to the material of the dummy gate 72, both the dummy gate 72 and the first dielectric layer 100 can be removed simultaneously. The portion of the dummy dielectric layer 60 located in the second recess 104 can also be removed. In some embodiments, the dummy gate 72 and the first dielectric layer 100 are removed, the dummy dielectric layer 60 is retained, and the dummy dielectric layer 60 is exposed by the second recess 104. In some embodiments, the dummy dielectric layer 60 is removed from the second recess 104 in a first region of the die (e.g., a core logic region), and the dummy dielectric layer 60 is retained in the second recess 104 in a second region of the die (e.g., an input / output region). In some embodiments, the dummy gate 72 and the first dielectric layer 100 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using reactive gases, which selectively etches the dummy gate 72 and the first dielectric layer 100 at a rate faster than the first ILD 96, CESL 94, first spacer 81, or second spacer 83. Each exposure of the second recess 104 is located over a channel region 68 of the corresponding fin 55. Each channel region 68 is disposed between adjacent pairs of epitaxial source / drain regions 92. During removal, the dummy dielectric layer 60 may serve as an etch stop layer while etching the dummy gate 72 and the first dielectric layer 100. After removing the dummy gate 72 and the first dielectric layer 100, the dummy dielectric layer 60 may optionally be removed. Figure 28C and Figure 28D As shown, the second groove 104 can separate the gate isolation structure 102 from the first spacer 81.

[0075] exist Figures 29A to 29D In this process, a gate dielectric layer 106 and a gate electrode 108 are formed to replace the gate. The gate dielectric layer 106 can be formed by depositing one or more layers in the second recess 104, such as on the top surface and sidewalls of the fin 55, the first spacer 81, and the gate isolation structure 102, and on the top surface of the STI region 58, the first ILD 96, the CESL 94, and the second spacer 83. The gate dielectric layer 106 can be formed by depositing layers as described above. Figures 21A to 21D The same or similar materials and processes discussed are used to form them. For example... Figure 29C and Figure 29D As shown, the gate dielectric layer 106 can fill the portion of the second groove 104 that separates the gate isolation structure 102 from the first spacer 81.

[0076] Gate electrode 108 is deposited above gate dielectric layer 106 and fills the remainder of second groove 104. Gate electrode 108 may be formed by the above-mentioned... Figures 21A to 21D The same or similar materials and processes discussed are used to form the structure. After the second recess 104 is filled, a planarization process, such as CMP, is performed to remove excess portions of the gate dielectric layer 106 and the gate electrode 108 located above the top surfaces of the first ILD 96, CESL 94, first spacer 81, second spacer 83, and gate isolation structure 102. The remaining portions of the gate electrode 108 and the gate dielectric layer 106 form the replacement gate of the resulting FinFET. The gate electrode 108 and the gate dielectric layer 106 may be collectively referred to as the “gate stack”. The gate stack may extend along the sidewalls of the channel region 68 of the fin 55.

[0077] exist Figure 30A and Figure 30BIn this process, a second ILD 112 is deposited over the first ILD 96, CESL 94, first spacer 81, second spacer 83, gate isolation structure 102, gate dielectric layer 106, and gate electrode 108. In some embodiments, the second ILD 112 is a flowable film formed by FCVD. In some embodiments, the second ILD 112 is formed of a dielectric material, such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method, such as CVD, PECVD, etc. In some embodiments, the dielectric material for the second ILD 112 may include silicon oxide, silicon nitride, silicon oxynitride, etc. In some embodiments, prior to the formation of the second ILD 112, the gate stack (including the gate dielectric layer 106 and the corresponding upper gate electrode 108) is recessed, thereby forming a groove directly over each of the respective gate stack and between the opposite portion of the first spacer 81. A gate mask 110 comprising one or more dielectric material layers (such as silicon nitride, silicon oxynitride, etc.) is filled in a recess, followed by a planarization process to remove excess portions of the dielectric material extending over the first ILD 96, CESL 94, gate isolation region 103, first spacer 81, and second spacer 83.

[0078] Further in Figure 30A and Figure 30B In the second ILD 112, a gate contact 114 is formed through the second ILD 112 and the gate mask 110, and a source / drain contact 116 is formed through the second ILD 112. An opening for the source / drain contact 116 is formed through the second ILD 112, and an opening for the gate contact 114 is formed through the second ILD 112 and the gate mask 110. The openings can be formed using acceptable photolithography and etching techniques. Pads (such as diffusion barrier layers, adhesive layers, etc.) and conductive material are formed within the openings. The pads can include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material can be copper, copper alloys, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process, such as CMP, can be performed to remove excess material from the surface of the second ILD 112. The remaining pads and conductive material form the source / drain contact 116 and the gate contact 114 within the openings. Source / drain contact 116 is electrically coupled to epitaxial source / drain region 92, and gate contact 114 is electrically coupled to gate electrode 108. Source / drain contact 116 and gate contact 114 can be formed in different processes or in the same process. Although shown as formed in the same cross-section, it should be understood that each of source / drain contact 116 and gate contact 114 can be formed in different cross-sections to avoid short circuits in the contacts.

[0079] The embodiments can achieve various advantages. For example, forming the first opening 98 through the mask 74 and partially through the dummy gate 72, conformally depositing the first dielectric layer 100 in the first opening 98, and anisotropically etching the first dielectric layer 100 allows for a reduction in the critical size of the first opening 98 and provides better control over the critical size of the first opening 98. This reduces device defects and improves device performance. Furthermore, forming the first dielectric layer 100 from a material with low etch selectivity to the material of the dummy gate 72 allows for simultaneous etching of the first dielectric layer 100 and the dummy gate 72, reducing processing time and cost. Subsequently, a gate isolation structure 102 that can be used to isolate adjacent gate stacks from each other is formed in the first opening 98.

[0080] The disclosed FinFET embodiments can also be applied to nanostructure devices, such as nanowire FETs, nanosheet FETs (nanoFETs), etc. Figure 31 An example of a nanoFET is shown in a three-dimensional view according to some embodiments. The nanoFET includes a nanostructure 359 (e.g., nanosheet, nanowire, etc.) above a fin 366 on a substrate 350 (e.g., a semiconductor substrate). The nanostructure 359 serves as a channel region for the nanoFET. The nanostructure 359 may include p-type nanostructures, n-type nanostructures, or combinations thereof. An isolation region 358 is disposed between adjacent fins 366, and the fins 366 may protrude over and from between adjacent isolation regions 358. Although the isolation region 358 is described / shown as separated from the substrate 350, as used herein, the term "substrate" may refer to a single semiconductor substrate or a combination of a semiconductor substrate and an isolation region. Furthermore, although the bottom of the fin 366 is shown as a single, continuous material having the substrate 350, the fin 366 and / or the bottom of the substrate 350 may include a single material or multiple materials. In this context, fin 366 refers to the portion extending between adjacent isolation regions 358.

[0081] The gate dielectric layer 306 extends along the top and sidewalls of the fin 366, along the top, sidewalls, and bottom of the nanostructure 359, and along the top surface of the isolation region 358. The gate electrode 308 is located above the gate dielectric layer 306. Epitaxial source / drain regions 392 are disposed on the fins 366 on opposite sides of the gate dielectric layer 306 and the gate electrode 308.

[0082] Figure 31Reference cross sections used in the following figures are also shown. Cross section A-A' is along the longitudinal axis of the gate electrode 306 and in a direction, for example, perpendicular to the direction of current flow between the epitaxial source / drain regions 392 of the nanoFET. Cross section B-B' is perpendicular to cross section A-A' and parallel to the longitudinal axis of the nanoFET fin 366 and in a direction, for example, the direction of current flow between the epitaxial source / drain regions 392 of the nanoFET. For clarity, the following figures refer to these reference cross sections.

[0083] Figures 32 to 41B This is a cross-sectional view of an intermediate stage in the fabrication of a nanoFET according to some embodiments. Figure 32 , Figure 33 , Figure 34 , Figure 35A , Figure 36A , Figure 37A , Figure 38A , Figure 39A , Figure 40A and Figure 41A along Figure 31 The reference section A-A' shown in the figure is illustrated. Figure 35B , Figure 36B , Figure 37B , Figure 38B , Figure 39B , Figure 40B and Figure 41B along Figure 31 The reference section B-B' shown is illustrated. Figure 35C , Figure 36C , Figure 37D , Figure 38C and Figure 39C Along parallel to section B-B' and Figure 37C The reference section D-D' shown is illustrated. Figure 37C This is a top view.

[0084] exist Figure 32 The above describes the provision of a substrate 350. The substrate 350 can be used in conjunction with the substrate described above. Figure 2 The substrate 50 discussed is the same or similar. Although not shown separately, substrate 350 may include an n-type region for forming an n-type device, such as an NMOS transistor, for example an n-type nanoFET, and a p-type region for forming a p-type device, such as a PMOS transistor, for example a p-type nanoFET.

[0085] A multilayer stack 364 is formed over a substrate 350. The multilayer stack 364 includes alternating layers of first semiconductor layers 351A-351C (collectively referred to as first semiconductor layer 351) and second semiconductor layers 353A-353C (collectively referred to as second semiconductor layer 353). For illustrative purposes and as discussed in more detail below, the first semiconductor layer 351 will be removed and the second semiconductor layer 353 will be patterned to form channel regions of the nanoFET in both the n-type and p-type regions. In such an embodiment, the channel regions in the n-type and p-type regions may have the same material composition (e.g., silicon or another semiconductor material) and may be formed simultaneously.

[0086] For illustrative purposes, the multilayer stack 364 is shown as comprising three first semiconductor layers 351 and three second semiconductor layers 353. In some embodiments, the multilayer stack 364 may include any number of first semiconductor layers 351 and second semiconductor layers 353. Each layer of the multilayer stack 364 may be epitaxially grown using processes such as CVD, ALD, VPE, MBE, etc. In some embodiments, the first semiconductor layer 351 may be formed of a first semiconductor material, such as silicon germanium, and the second semiconductor layer 353 may be formed of a second semiconductor material, such as silicon, silicon carbide, etc. For illustrative purposes, the multilayer stack 364 is shown as having a bottom first semiconductor layer 351 formed of a first semiconductor material. In some embodiments, the multilayer stack 364 may be formed as having a bottom second semiconductor layer 353 formed of a second semiconductor material.

[0087] The first semiconductor material and the second semiconductor material can be materials that have high etch selectivity towards each other. Therefore, the first semiconductor layer 351 of the first semiconductor material can be removed without significantly removing the second semiconductor layer 353 of the second semiconductor material. This allows the second semiconductor layer 353 to be patterned to form the channel region of the nanoFET. Similarly, in embodiments where the second semiconductor layer 353 is removed and the first semiconductor layer 351 is patterned to form the channel region, the second semiconductor layer 353 of the second semiconductor material can be removed without significantly removing the first semiconductor layer 351 of the first semiconductor material. This allows the first semiconductor layer 351 to be patterned to form the channel region of the nanoFET.

[0088] exist Figure 33In this embodiment, fins 366 are formed in a substrate 350 and nanostructures 359 are formed in a multilayer stack 364. In some embodiments, nanostructures 359 and fins 366 can be formed in the multilayer stack 364 and substrate 350, respectively, by etching trenches in the multilayer stack 364 and substrate 350. Etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. Etching can be anisotropic. Forming nanostructures 359 by etching the multilayer stack 364 can further define first nanostructures 352A-352C (collectively referred to as first nanostructures 352) from a first semiconductor layer 351 and second nanostructures 354A-354C (collectively referred to as second nanostructures 354) from a second semiconductor layer 353. First nanostructures 352 and second nanostructures 354 can be collectively referred to as nanostructure 359. Fins 366 and nanostructures 359 can be used in accordance with the above description. Figure 3 The same or similar processes used to form fins 55 and pseudofins 57 are discussed for patterning.

[0089] Fins 366 and nanostructures 359 can be patterned to form channel structures 355 and pseudostructures 357. As will be discussed below... Figure 34 The pseudo-structure 357 discussed can be replaced by subsequent processing. The channel structure 355 can have a width W1 in the range of about 5 nm to about 15 nm, the pseudo-structure 357 can have a width W2 in the range of about 10 nm to about 20 nm, and the ratio of width W2 to width W1 can be in the range of about 2 to about 4.

[0090] exist Figure 34 In this structure, an insulating material 356 is formed around the fin 366 and nanostructure 359, and the pseudostructure 357 is replaced by a dielectric fin 361 (sometimes referred to as a hybrid fin 361 or fin-isolating structure 361). The insulating material 356 can be related to the above-mentioned... Figure 4 The insulating material 56 discussed is the same as or similar to that discussed. Dielectric fins 361 can be formed by etching pseudo-structures 357 (including nanostructures 359 and fins 366) to form grooves in the insulating material 356, and then filling the grooves with a dielectric material. Dielectric fins 361 can be deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. The dielectric material can include silicon nitride, silicon oxide, combinations thereof, or multilayers thereof. In some embodiments, dielectric fins 361 can be formed from doped silicon nitride (e.g., silicon nitride doped with carbon (C), oxygen (O), combinations thereof, etc.). In some embodiments, dielectric fins 361 can be formed from a material relative to the insulating material 356 and subsequently formed pseudo-gates (such as pseudo-gate 372, hereinafter referred to as...). Figures 35A to 35CThe material (discussed) is a dielectric material with high etch selectivity. The bottom surface of the dielectric fin 361 can be configured to be higher than, lower than, or flush with the bottom surface of the insulating material 356. After depositing the dielectric fin 361, removal processes such as CMP, etch-back processes, etc., can be performed to planarize the dielectric fin 361, the insulating material 356, and the nanostructure 359. The dielectric fin 361 can have a width W2 in the range of about 10 nm to about 20 nm.

[0091] exist Figures 35A to 35C In the middle, implement the above regarding Figures 6 to 11C The same or similar processes discussed are used to form the STI region 358 (similar or identical to STI region 58) adjacent to fin 366; the dummy dielectric layer 360 (similar or identical to dummy dielectric layer 60), the dummy gate 372 (similar or identical to dummy gate 72), and the mask 374 (similar or identical to mask 74) above the nanostructure 359, fin 366, and STI region 358; the first spacer 381 (similar or identical to first spacer 81) and the second spacer 383 (similar or identical to second spacer 83) adjacent to the dummy dielectric layer 360, dummy gate 372, and mask 374; and the first groove 386 (similar or identical to first groove 86) adjacent to the first spacer 381 and the second spacer 383. The first groove 386 may extend through the first nanostructure 352 and the second nanostructure 354 and into the substrate 350. Figure 35B As shown, the top surface of the STI region 358 can be flush with the bottom surface of the first groove 386. In some embodiments, the fin 366 can be etched so that the bottom surface of the first groove 386 is located below the top surface of the STI region 358, etc.

[0092] Further in Figures 35A to 35C In the process, the sidewalls of the layers of the multilayer stack 364 are etched to form portions of the first semiconductor material (e.g., the first nanostructure 352) exposed by the first groove 386 to form sidewall grooves 388. While the sidewalls of the first nanostructure 352 adjacent to the sidewall grooves 388 are... Figure 35B The sidewalls are shown as straight, but they can be concave or convex. The sidewalls can be etched using isotropic etching processes, such as wet etching. In embodiments where the first nanostructure 352 comprises, for example, SiGe and the second nanostructure 354 comprises, for example, Si or SiC, wet or dry etching processes using hydrogen fluoride, another fluorine-based etchant, etc., can be used to etch the sidewalls of the second nanostructure 354.

[0093] exist Figures 36A to 36C In the middle, a first internal spacer 390 is formed in the sidewall groove 388. The first internal spacer 390 can be formed by... Figures 35A to 35CThe structure shown is formed by depositing an internal spacer layer (not shown separately) over it. The first internal spacer 390 serves as an isolation component between the subsequently formed source / drain regions and the gate structure. As will be discussed in more detail below, the source / drain regions will be formed in the first recess 386, while the second nanostructure 354 will be replaced by the corresponding gate structure.

[0094] The internal spacer layer can be deposited using conformal deposition processes such as CVD, ALD, etc. The internal spacer layer can comprise materials such as silicon nitride or silicon oxynitride, but any suitable material can be used, such as low-k materials having a k value less than about 3.5. The internal spacer layer can then be anisotropically etched to form the first internal spacer layer 390. Although the outer wall of the first internal spacer 390 is shown flush with the sidewall of the first nanostructure 352, the outer wall of the first internal spacer 390 may extend beyond or be recessed from the sidewall of the first nanostructure 352. Furthermore, although the outer wall of the first internal spacer 390 is... Figure 36B The diagram shows a straight line, but the outer wall of the first internal spacer 390 can be concave or convex. The internal spacer layer can be etched using anisotropic etching processes, such as RIE, NBE, etc. The first internal spacer 390 can be used to prevent subsequent etching processes (such as etching processes for forming the gate structure) from affecting the subsequently formed source / drain regions (such as epitaxial source / drain regions 392, as discussed below). Figures 37A to 37C (Discussion) damage.

[0095] exist Figures 37A to 37C In the middle, implement the above regarding Figures 12A to 14D The same or similar processes discussed are used to form an epitaxial source / drain region 392 (similar or identical to epitaxial source / drain region 92) in a first recess 386; a CESL 394 (similar or identical to CESL 94) and a first ILD 396 (similar or identical to first ILD 96) located above the epitaxial source / drain region 392 and adjacent to the second spacer 383; and a first opening 398 in a mask 374. The first opening 398, which can be etched through the mask 374, can expose the dummy gate 372. In some embodiments, the first spacer 381 can be formed of the same material as the mask 374 and can be etched simultaneously with the mask 374. For example, in some embodiments, the first spacer 381 and the mask 374 can include nitrides, such as silicon nitride. The mask 374 can be etched using anisotropic etching processes, such as RIE, NBE, etc. Figure 37AAs shown, the first opening 398 may have a width W3 in a direction perpendicular to the longitudinal axis of the dielectric fin 361. The width W3 may be in the range of about 18 nm to about 40 nm. In some embodiments, the width W3 may be increased to the range of about 30 nm to about 50 nm.

[0096] exist Figures 38A to 38C In the first opening 398, a third spacer 301 is formed, and the first opening 398 extends through the dummy gate 372 and the dummy dielectric layer 360 to the dielectric fin 361. The third spacer 301 may be formed by the same method as described above regarding the third spacer 101. Figures 15A to 16D Or regarding the first dielectric layer 100 Figures 25A to 26D The same or similar materials discussed above, and by reference to the third spacer 101 Figures 15A to 16D Or regarding the first dielectric layer 100 Figures 25A to 26D The same or similar processes discussed are formed. For example... Figure 38A and Figure 38C As shown, opposing third spacers 301 disposed in the same first opening 398 may be separated from each other by a width W4 in a direction perpendicular to the longitudinal axis of the dielectric fin 361. The width W4 may be in the range of about 12 nm to about 30 nm. In some embodiments, the width W4 may be a distance from the width W2 of the dielectric fin 361 by about 1 nm to about 2 nm, and the ratio of the width W4 to the width W2 may be in the range of about 0.5 to about 1.5.

[0097] Forming the first opening 398 and then narrowing it using the third spacer 301 provides better control over the width of the first opening 398 and reduces its critical size. This helps improve device performance, reduce device defects, and decrease component size. Because the third spacer 301 is formed of a material with high etch selectivity to the underlying dummy gate 372, the dummy gate 372 can be etched with reduced dross. This allows the third spacer 301 to be formed with a width W4 of less than 16 nm. The improved etching process with reduced dross reduces leakage current, which improves device performance.

[0098] The dummy gate 372 can be etched using a suitable etching process, such as anisotropic etching (e.g., dry etching). In embodiments where the dummy gate 372 comprises polysilicon, the dummy gate 372 can be etched using a dry etching process employing fluorine, which selectively etches the material of the dummy gate 372 relative to the third spacer 301, mask 374, first ILD 396, CESL 394, first spacer 381, and second spacer 383. After etching, the first opening 398 may have a width W4 flush with the top surface of the dummy gate 372, a width W5 flush with the bottom surface of the dummy dielectric layer 360 on the dielectric fin 361, and a depth D1 between the top surface of the dummy gate 372 and the bottom surface of the dummy dielectric layer 360 on the dielectric fin 361. The width W4 may be in the range of about 12 nm to about 30 nm, as discussed above; the width W5 may be in the range of about 12 nm to about 25 nm; and the depth D1 may be in the range of about 80 nm to about 140 nm. Although the first opening 398 is shown as having a tapered profile extending through the dummy gate 372 and the dummy dielectric layer 360, the first opening 398 may have vertical sidewalls or an inverted tapered profile (widening in the direction from the top surface of the dummy gate 372 to the bottom surface of the dummy dielectric layer 60). Forming the first opening 398 and then narrowing it using the third spacer 301 provides better control over the width of the first opening 398 and reduces its critical size. Because the third spacer 301 is formed of a material with high etch selectivity relative to the dummy gate 372, the dummy gate 372 can be etched for a sufficient time to completely etch through it, reducing slag left in the first opening 398, which reduces leakage current and allows for a smaller critical size. Therefore, the described method helps to improve device performance, reduce device defects, and reduce part size. In some embodiments, regarding Figures 25A to 26D The described process and materials can be used to replace the third spacer 101 to form the first opening 398.

[0099] exist Figures 39A to 39C In the first opening 398, a gate isolation region 303 is formed. The gate isolation region may be formed by the same method as described above regarding gate isolation region 103. Figures 18A to 19D The same or similar materials discussed above, and by reference to the gate isolation region 103 Figures 18A to 19D The same or similar processes discussed are used to form it. Gate isolation region 303 can be used to isolate the dummy gate 72 subsequently formed by the gate electrode (such as gate electrode 308, discussed below). Figure 41A and Figure 41B(Discussion) Replacement portion. The top surface of the gate isolation region 303 may have a width W4 in the range of about 12 nm to about 30 nm, the bottom surface of the gate isolation region 303 may have a width W5 in the range of about 12 nm to about 25 nm, and the gate isolation region 303 may have a height H1 in the range of about 80 nm to about 120 nm.

[0100] exist Figure 40A and Figure 40B In one or more etching steps, the dummy gate 372, the dummy dielectric layer 360, and the first nanostructure 352 are removed to form a second recess 304. In some embodiments, the dummy gate 372 and the dummy dielectric layer 360 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using reactive gases that selectively etches the dummy gate 372 at a rate faster than the first ILD 396, CESL 394, the first spacer 381, the second spacer 383, or the gate isolation region 303. During removal, the dummy dielectric layer 360 may serve as an etch stop layer while the dummy gate 372 is etched. After the removal of the dummy gate 372, the dummy dielectric layer 360 may then be removed. Each exposure of the second recess 304 is located above a portion of the nanostructure 359 that serves as a channel region in the subsequently completed nanoFET. The portions of the nanostructure 359 that serve as channel regions are disposed between adjacent pairs of epitaxial source / drain regions 392.

[0101] The first nanostructure 352 is then removed, extending the second groove 304. The first nanostructure 352 can be removed by performing an isotropic etching process, such as wet etching, using an etchant selective for the material of the first nanostructure 352. Compared to the first nanostructure 352, the second nanostructure 354, substrate 350, STI region 358, first ILD 396, CESL 394, first spacer 381, second spacer 383, first internal spacer 390, gate isolation region 303, and dielectric fin 361 remain relatively unetched. In embodiments where the first nanostructure 352 comprises, for example, SiGe and the second nanostructure 354 comprises, for example, Si or SiC, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc., can be used to remove the first nanostructure 352.

[0102] exist Figure 41A and Figure 41B In the middle, implement the above regarding Figures 20A to 23BThe same or similar processes discussed are used to form a gate dielectric layer 306 (similar or identical to gate dielectric layer 106) and a gate electrode 308 (similar or identical to gate electrode 108) in the second recess 304; a gate mask 310 (similar or identical to gate mask 110) above the gate electrode 308; a second ILD 312 (similar or identical to second ILD 112) above the gate mask 310, first ILD 396, CESL 394, gate isolation region 303, first spacer 381 and second spacer 383; extending through the second ILD 312 and the first ILD The source / drain contacts 316 of 396 and CESL394 (similar or identical to source / drain contacts 116); electrically coupling the source / drain contacts 316 to the silicide region 313 of the epitaxial source / drain region 392 (similar or identical to silicide region 113); and the gate contact 314 (similar or identical to gate contact 114) extending through the second ILD 312 and the gate mask 310. The gate dielectric layer 306 and the gate electrode 308 can be formed by conformal deposition processes such as CVD, ALD, molecular beam deposition (MBD), etc. The gate dielectric layer 306 is deposited on the top and sidewalls of the fin 66 and on the top, sidewalls, and bottom surfaces of the second nanostructure 354.

[0103] The embodiments can achieve various advantages. For example, forming the first opening 398 through the mask 374 and forming the third spacer 301 in the first opening 398 allows for a reduction in the critical size of the first opening 398 and provides better control over the critical size of the first opening 398. This reduces device defects and improves device performance. The third spacer 301 can be formed of a material with high etch selectivity to the dummy gate 372, and the dummy gate 372 can be etched for a sufficient time to remove slag in the first opening 398, which reduces leakage current. Subsequently, a gate isolation region 303 is formed in the first opening 398, which can be used to isolate adjacent gate stacks from each other.

[0104] According to an embodiment, the method includes: forming a channel structure over a substrate; forming a first isolation structure extending in a direction parallel to the channel structure; forming a dummy gate structure over the channel structure and the first isolation structure; depositing a hard mask layer over the dummy gate structure; etching the hard mask layer to form a first opening through the hard mask layer over the first isolation structure; conformally depositing a first dielectric layer over the hard mask layer, in the first opening, and over the dummy gate structure; etching the first dielectric layer to extend the first opening and expose the dummy gate structure; and etching the dummy gate structure to extend the first opening and expose the first isolation structure. In an embodiment, forming the first isolation structure includes: forming a first dummy structure over a substrate; forming an isolation region adjacent to the channel structure and the first dummy structure; etching the first dummy structure to form a second opening in the isolation region; and forming the first isolation structure in the second opening. In an embodiment, the dummy gate structure comprises polysilicon, and the first dielectric layer comprises silicon nitride. In an embodiment, the method further includes: depositing a gate isolation structure in the first opening after etching the dummy gate structure. In an embodiment, the method further includes: removing the hard mask layer and the first dielectric layer using a planarization process. In one embodiment, the method further includes: removing the dummy gate structure to form a second opening; and forming a replacement gate structure in the second opening, the replacement gate structure contacting the first isolation structure and the gate isolation structure.

[0105] According to another embodiment, the method includes: forming a gate structure over a semiconductor substrate; depositing a hard mask over the gate structure; etching the hard mask to form a first opening exposing the gate structure; depositing a first dielectric layer in the first opening; etching the first dielectric layer to form a first spacer and expose the gate structure; and etching the gate structure to expose dielectric fins disposed between the gate structure and the semiconductor substrate. In an embodiment, the gate structure comprises polysilicon, and the first dielectric layer comprises silicon nitride. In an embodiment, the gate structure comprises polysilicon, the first dielectric layer comprises silicon, and the etchant used to etch the first dielectric layer is the same as the etchant used to etch the gate structure. In an embodiment, the gate structure comprises polysilicon, and the first dielectric layer comprises silicon oxide. In an embodiment, the method further includes: depositing a second dielectric layer in the first opening over the first dielectric layer, and etching the first dielectric layer further includes etching the second dielectric layer to expose the gate structure. In an embodiment, the method further includes: forming a first fin structure, a second fin structure, and a third fin structure extending from the semiconductor substrate, the second fin structure being located between the first fin structure and the third fin structure; and replacing the second fin structure with dielectric fins. In an embodiment, the dielectric fins comprise silicon nitride.

[0106] According to another embodiment, the method includes: forming a hard mask over a dummy gate structure; etching a first opening extending through the hard mask and partially through the dummy gate structure; conformally depositing a first dielectric layer over the hard mask and the dummy gate structure and the first opening; simultaneously etching through the first dielectric layer and the dummy gate structure to extend the first opening; and forming a gate isolation structure in the first opening. In an embodiment, the method further includes: forming a first fin and a second fin extending from a semiconductor substrate, the first fin and the second fin comprising a semiconductor material; replacing the second fin with a dielectric fin; and forming a dummy gate structure over the first fin and the dielectric fin. In an embodiment, the dielectric fin and the gate isolation structure are formed of a material comprising silicon nitride. In an embodiment, the dummy gate structure and the first dielectric layer are formed of a material comprising polysilicon. In an embodiment, simultaneously etching through the first dielectric layer and the dummy gate structure comprises dry etching using an etchant comprising fluorine. In an embodiment, the method further includes: performing a planarization process on the hard mask and the first dielectric layer to remove the hard mask, after which at least a portion of the first dielectric layer is retained. In one embodiment, the method further includes: simultaneously removing the dummy gate structure and the first dielectric layer to form a second opening; and forming a replacement gate structure in the second opening.

[0107] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the invention.

Claims

1. A method for forming a semiconductor device, comprising: A channel structure is formed above the substrate; A first isolation structure is formed extending in a longitudinal direction parallel to the channel structure; A pseudo-gate structure is formed above the channel structure and the first isolation structure; A hard mask layer is deposited over the pseudo-gate structure; The hard mask layer is etched to form a first opening through the hard mask layer above the first isolation structure; A first dielectric layer is conformally deposited over the hard mask layer, in the first opening, and over the dummy gate structure; Etch the first dielectric layer to extend the first opening and expose the dummy gate structure; as well as The dummy gate structure is etched to extend the first opening and expose the first isolation structure.

2. The method according to claim 1, wherein, The formation of the first isolation structure includes: A first pseudo-structure is formed above the substrate; An isolation region is formed adjacent to the channel structure and the first pseudo-structure; Etching the first pseudo-structure to form a second opening in the isolation region; and The first isolation structure is formed in the second opening.

3. The method according to claim 1, wherein, The pseudo-gate structure comprises polysilicon, and wherein the first dielectric layer comprises silicon nitride.

4. The method according to claim 1, further comprising: After etching the dummy gate structure, a gate isolation structure is deposited in the first opening.

5. The method according to claim 4, further comprising: The hard mask layer and the first dielectric layer are removed using a planarization process.

6. The method of claim 5, further comprising: Remove the dummy gate structure to form a second opening; as well as A replacement gate structure is formed in the second opening, the replacement gate structure contacting the first isolation structure and the gate isolation structure.

7. A method for forming a semiconductor device, comprising: A first fin structure, a second fin structure, and a third fin structure are formed extending from a semiconductor substrate, wherein the second fin structure is located between the first fin structure and the third fin structure; and The second fin structure is replaced with a dielectric fin; A gate structure is formed above the first fin structure, the dielectric fin, and the third fin structure; A hard mask is deposited over the gate structure; The hard mask is etched to form a first opening that exposes the gate structure; A first dielectric layer is deposited in the first opening; Etching the first dielectric layer to form the first spacer and expose the gate structure; and The gate structure is etched to expose the dielectric fins disposed between the gate structure and the semiconductor substrate.

8. The method according to claim 7, wherein, The gate structure comprises polysilicon, and wherein the first dielectric layer comprises silicon nitride.

9. The method according to claim 7, wherein, The gate structure comprises polysilicon, wherein the first dielectric layer comprises silicon, and wherein the etchant used to etch the first dielectric layer is the same as the etchant used to etch the gate structure.

10. The method according to claim 7, wherein, The gate structure comprises polysilicon, and wherein the first dielectric layer comprises silicon oxide.

11. The method of claim 7, further comprising: A second dielectric layer is deposited in the first opening above the first dielectric layer, wherein etching the first dielectric layer further includes etching the second dielectric layer to expose the gate structure.

12. The method of claim 7, further comprising: A gate isolation region is formed that is in direct contact with the exposed top surface of the dielectric fin.

13. The method according to claim 12, wherein, The dielectric fins comprise silicon nitride.

14. A method of forming a semiconductor device, comprising: A hard mask is formed above the pseudo-gate structure; The etching extends through the hard mask and partially through the first opening of the dummy gate structure; A first dielectric layer is conventionally deposited over the hard mask and the dummy gate structure, and over the first opening; Simultaneously, etching is performed through the first dielectric layer and the dummy gate structure to extend the first opening; as well as A gate isolation structure is formed in the first opening. The method further includes: forming a first fin and a second fin extending from a semiconductor substrate, the first fin and the second fin comprising a semiconductor material; replacing the second fin with a dielectric fin; and forming the dummy gate structure above the first fin and the dielectric fin.

15. The method according to claim 14, wherein, The portion of the first opening extending through the first dielectric layer and the dummy gate structure has a tapered profile.

16. The method according to claim 15, wherein, The dielectric fins and the gate isolation structure are formed of a material including silicon nitride.

17. The method according to claim 16, wherein, The pseudo-gate structure and the first dielectric layer are formed of a material including polysilicon.

18. The method according to claim 14, wherein, Simultaneous etching through the first dielectric layer and the dummy gate structure includes dry etching using an etchant comprising fluorine.

19. The method of claim 14, further comprising: A planarization process is performed on the hard mask and the first dielectric layer to remove the hard mask, wherein at least a portion of the first dielectric layer is retained after the planarization process is performed.

20. The method of claim 14, further comprising: Simultaneously, the dummy gate structure and the first dielectric layer are removed to form a second opening; as well as A replacement gate structure is formed in the second opening.

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