Semiconductor device and method of manufacturing the same

Abstract

Embodiments of the present invention provide a semiconductor device and a method of manufacturing the same. The semiconductor device includes a first conductive pattern on a substrate, a second conductive pattern on the first conductive pattern, and a third conductive pattern on the first conductive pattern, all of which extend in a first direction. The first conductive pattern is electrically connected in parallel to the second conductive pattern and the third conductive pattern.

Description

Technical Field

[0001] The embodiments of the present invention generally relate to the field of semiconductors, and more specifically, to semiconductor devices and methods of manufacturing the same. Background Technology

[0002] This invention generally relates to semiconductor devices and methods for manufacturing the same. Specifically, this invention relates to semiconductor devices with reduced resistance and methods for manufacturing the same.

[0003] Semiconductor structures may include multiple circuits electrically connected by conductive metal interconnects and lines. These circuits may be derived from standard cells. Standard cells may include transistors or inverters. With technological advancements, the demand for faster operating speeds in semiconductor devices has increased. Historically, semiconductor devices with higher resistance have experienced slower operating speeds. Therefore, research has been conducted to reduce resistance during the layout design of standard cells. Summary of the Invention

[0004] One aspect of the present invention provides a semiconductor device comprising: a first conductive pattern located on a substrate and extending along a first direction; a second conductive pattern located above the first conductive pattern and extending along the first direction; and a third conductive pattern located above the first conductive pattern and extending along the first direction; wherein the first conductive pattern is electrically connected in parallel with the second conductive pattern and the third conductive pattern.

[0005] Another aspect of the present invention provides a semiconductor device comprising: a first gate electrode located on a substrate and extending along a first direction; and a first conductive pattern located on the substrate and extending along the first direction; wherein the first gate electrode is electrically connected in parallel with the first conductive pattern, and the first gate electrode extends continuously from a first cell region to a second cell region.

[0006] Another aspect of the present invention provides a method for manufacturing a semiconductor device, comprising: forming a first conductive pattern extending along a first direction on a substrate; forming a second conductive pattern extending along a second direction perpendicular to the first direction on the first conductive pattern; forming a third conductive pattern extending along the first direction on the second conductive pattern; forming a fourth conductive pattern extending along the first direction on the second conductive pattern; forming a first conductive via electrically connected between the first conductive pattern and the second conductive pattern; forming a second conductive via electrically connected between the second conductive pattern and the third conductive pattern; and forming a third conductive via electrically connected between the second conductive pattern and the fourth conductive pattern. Attached Figure Description

[0007] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0008] Figure 1A This is a top view of a semiconductor layout according to some embodiments of the present invention.

[0009] Figure 1B This is a cross-sectional view of a semiconductor device according to some embodiments of the present invention.

[0010] Figure 1C This is a top view of a semiconductor layout according to some embodiments of the present invention.

[0011] Figure 2A This is a top view of a semiconductor layout according to some embodiments of the present invention.

[0012] Figure 2B This is a top view of a semiconductor layout according to some embodiments of the present invention.

[0013] Figure 2C This is a top view of a semiconductor layout according to some embodiments of the present invention.

[0014] Figure 2D This is a top view of a semiconductor layout according to some embodiments of the present invention.

[0015] Figure 3A This is a top view of a semiconductor layout according to some embodiments of the present invention.

[0016] Figure 3B This is a top view of a semiconductor layout according to some embodiments of the present invention.

[0017] Figure 4A This is a top view of a semiconductor layout according to some embodiments of the present invention.

[0018] Figure 4B This is a top view of a semiconductor layout according to some embodiments of the present invention.

[0019] Figure 5A This is a top view of a semiconductor layout according to some embodiments of the present invention.

[0020] Figure 5B This is a top view of a semiconductor layout according to some embodiments of the present invention.

[0021] Figure 6 This is a top view of a semiconductor layout according to some embodiments of the present invention.

[0022] Figure 7This is a top view of a semiconductor layout according to some embodiments of the present invention.

[0023] Figure 8A and Figure 8B This is a flowchart of operations for manufacturing semiconductor devices according to some embodiments of the present invention.

[0024] Figure 9 This is a top view of a semiconductor layout according to some comparative embodiments of the present invention.

[0025] Figure 10 It is a block diagram of a system generated based on IC layout diagrams of some embodiments.

[0026] Figure 11 This is a block diagram of an IC manufacturing system and its associated IC manufacturing process according to some embodiments. Detailed Implementation

[0027] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter to achieve different features of the invention. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0028] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “down,” “above,” “upper,” “above,” and “upper part” may be used to describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientation shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0029] As used herein, although terms such as “first,” “second,” and “third” describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms may be used only to distinguish one element, component, area, layer, or part from another element, component, area, layer, or part. Unless the context clearly indicates otherwise, terms such as “first,” “second,” and “third” as used herein do not imply order or sequence.

[0030] While the numerical ranges and parameters illustrating the broad scope of the invention are approximate, the values ​​described in specific examples are reported as precisely as possible. However, any numerical value inherently contains some error, which must be caused by the standard deviation found in the corresponding test measurement. Furthermore, as used herein, the terms “basically,” “about,” and “approximately” generally mean values ​​or ranges that would be expected by one of ordinary skill in the art. Optionally, the terms “basically,” “about,” and “approximately” mean within an acceptable standard error of the average as considered by one of ordinary skill in the art. One of ordinary skill in the art will understand that acceptable standard errors will vary depending on the technology. Except in operational / working examples, or unless expressly stated otherwise, all numerical ranges, quantities, values, and percentages, such as material quantities, time durations, temperatures, operating conditions, quantity ratios, and similar terms disclosed herein, should be understood to be modified in all cases by the terms “basically,” “about,” or “approximately.” Therefore, unless indicated to the contrary, the numerical parameters set forth in the invention and the appended claims are approximate values ​​that may vary as needed. At a minimum, each numerical parameter should be interpreted based on the number of significant figures reported and by applying ordinary rounding techniques. A range may be expressed in this document as a distance from one endpoint to another or between two endpoints. Unless otherwise stated, all ranges disclosed herein include endpoints.

[0031] Figures 1A to 7 and Figure 9 These are schematic diagrams of corresponding IC devices according to some embodiments. Figures 1A to 7 Each schematic diagram represents an IC device embodiment and an IC layout embodiment that can be used in the manufacturing process as part of defining the features of the respective IC device.

[0032] In some embodiments, the IC layout diagram can be used with the following information. Figure 10 The IC layout generation system 1000 discussed below and / or related to the following... Figure 11 The discussion pertains to the IC manufacturing process performed in an IC manufacturing system 1100, which is part of defining one or more features of a corresponding IC device. In some embodiments, the IC layout diagram is stored in an IC design storage medium, such as the following regarding... Figure 10The IC design for the storage device 1007 is discussed.

[0033] Figure 1A A top view of a semiconductor layout according to some embodiments of the present invention is shown.

[0034] Figure 1A Layout 100 is shown. Layout 100 may correspond to an electronic device. Layout 100 may correspond to a semiconductor device. Layout 100 may correspond to a logic semiconductor structure. Layout 100 may correspond to an integrated circuit (IC) system. Layout 100 includes active regions OD_1 and OD_2 extending along the x-axis, a plurality of bottom conductive patterns (e.g., MD_1, MD_2, MD_3, and MD_4) extending along the y-axis, a plurality of polycrystalline material patterns (e.g., PO_1) extending along the y-axis, a plurality of intermediate conductive patterns (e.g., M0_1, M0_2, M0_3, M0_4, and M0_5) extending along the x-axis, and a plurality of top conductive patterns (e.g., M1_1, M1_2, M1_3, M1_4, and M1_5) extending along the y-axis.

[0035] The modifiers "top," "middle," and "bottom" are used to indicate the structural relationships of these different groups of conductive patterns. The top conductive patterns (e.g., M1_1, M1_2, M1_3, M1_4, and M1_5) are positioned above the middle conductive patterns (e.g., M0_1, M0_2, M0_3, M0_4, and M0_5). The middle conductive patterns (e.g., M0_1, M0_2, M0_3, M0_4, and M0_5) are positioned above the bottom conductive patterns (e.g., MD_1, MD_2, MD_3, and MD_4). Although... Figure 1A Not depicted, but layout 100 may also include conductive patterns above the top conductive patterns M1_1, M1_2, M1_3, M1_4 and M1_5.

[0036] Active region OD_1 is set parallel to active region OD_2. Active regions OD_1 and OD_2 are spaced apart from each other. Active region OD_1 can be a p-type active region and active region OD_2 can be an n-type active region. In some embodiments, active region OD_1 is an n-type active region and active region OD_2 is a p-type active region.

[0037] Multiple bottom conductive patterns (e.g., MD_1, MD_2, MD_3, and MD_4) are arranged parallel to each other. The multiple bottom conductive patterns are spaced apart from each other. The bottom conductive patterns comprise any type of suitable conductive material. In some embodiments, the bottom conductive patterns comprise conductive materials such as metals, such as copper (Cu), tungsten (W), gold (Au), cobalt (Co), silver (Ag), or combinations thereof. In some embodiments, the bottom conductive patterns comprise conductive materials such as metal alloys.

[0038] Multiple polycrystalline material patterns (e.g., PO_1) are arranged in parallel with each other. The multiple polycrystalline material patterns are spaced apart from each other. In some embodiments, the multiple polycrystalline material patterns may include metallic conductive materials and / or non-metallic conductive materials, such as polycrystalline silicon. In some embodiments, the polycrystalline material pattern, such as polycrystalline material pattern PO_1, is referred to as a gate electrode comprising one or more conductive materials.

[0039] Multiple intermediate conductive patterns (e.g., MO_1, MO_2, MO_3, MO_4, and MO_5) are arranged parallel to each other. The multiple intermediate conductive patterns are spaced apart from each other. The intermediate conductive patterns comprise any type of suitable conductive material. In some embodiments, the intermediate conductive patterns comprise conductive materials such as metals, such as copper (Cu), tungsten (W), gold (Au), cobalt (Co), silver (Ag), or combinations thereof. In some embodiments, the intermediate conductive patterns comprise conductive materials such as metal alloys.

[0040] Multiple top conductive patterns (e.g., M1_1, M1_2, M1_3, M1_4, and M1_5) are arranged parallel to each other. The multiple top conductive patterns are spaced apart from each other. The top conductive patterns comprise any type of suitable conductive material. In some embodiments, the top conductive patterns comprise conductive materials such as metals, such as copper (Cu), tungsten (W), gold (Au), cobalt (Co), silver (Ag), or combinations thereof. In some embodiments, the top conductive patterns comprise conductive materials such as metal alloys.

[0041] Layout 100 includes isolation structures for dividing a conductive pattern into electrically isolated segments. The isolation structure may be referred to as a "cut" or "cutter". For example, isolation structure CM0_1 may be configured to divide an intermediate conductive pattern M0_1 into two segments. In another example, isolation structure CM0_2 may be configured to divide an intermediate conductive pattern M0_5 into two segments. In yet another example, isolation structures CMD_1 and CMD_2 may be configured to divide a bottom conductive pattern MD_1 into segments that are electrically isolated from each other. The isolation structures comprise a suitable non-conductive material.

[0042] Layout 100 includes a plurality of conductive vias (e.g., VD2_1 and VD2_2) configured to contact a bottom conductive pattern. Conductive via VD2_1 may be electrically connected to a power source to receive a power supply voltage, such as VDD. Conductive via VD2_2 may be electrically connected to a power source to receive a reference voltage, such as VSS.

[0043] Layout 100 includes a plurality of conductive vias (e.g., VD_1 and VD_2) configured to contact a bottom conductive pattern (e.g., MD_2). Conductive via VD_1 electrically connects the bottom conductive pattern MD_2 to an intermediate conductive pattern M0_1. Conductive via VD_2 electrically connects the bottom conductive pattern MD_2 to an intermediate conductive pattern M0_5.

[0044] Layout 100 includes a plurality of conductive vias (e.g., V0_1, V0_2, V0_3, V0_4, V0_5, V0_6, V0_7, V0_8, and V0_9) configured to contact intermediate conductive patterns (e.g., M0_1 and M0_5). Conductive vias V0_1, V0_3, V0_5, V0_7, and V0_9 electrically connect the intermediate conductive pattern M0_1 to the corresponding top conductive patterns M1_1, M1_2, M1_3, M1_4, and M1_5. Conductive vias V0_2, V0_4, V0_6, and V0_8 electrically connect the intermediate conductive pattern M0_5 to the corresponding top conductive patterns M1_1, M1_2, M1_3, and M1_4.

[0045] The layout 100 includes a plurality of conductive vias (e.g., VG_1) configured to contact a polycrystalline material pattern (e.g., PO_1). The conductive vias VG_1 electrically connect the polycrystalline material pattern PO_1 to an intermediate conductive pattern M0_3.

[0046] The top conductive pattern M1_5 can be configured to receive an input signal. The top conductive pattern M1_5 can be an input stage of layout 100. The top conductive patterns M1_1, M1_2, M1_3 and M1_4 can be configured to provide output signals. The top conductive patterns M1_1, M1_2, M1_3 and M1_4 can be output stages of layout 100.

[0047] The top conductive patterns M1_1, M1_2, M1_3, and M1_4 are connected in parallel. The top conductive patterns M1_1, M1_2, M1_3, and M1_4 are also connected in parallel through conductive vias V0_1, V0_2, V0_3, V0_4, V0_5, V0_6, V0_7, and V0_8, as well as the middle conductive patterns M0_1 and M0_5.

[0048] Bottom conductive patterns MD_1, MD_2, and MD_3 are electrically connected in parallel. These bottom conductive patterns MD_1, MD_2, and MD_3 are also electrically connected in parallel with the intermediate conductive patterns M0_1 and M0_5 via the upper conductive vias (e.g., conductive vias VD_1 and VD_2). The conductive vias configured to contact the bottom conductive patterns MD_1 and MD_3 are... Figure 1A They are not visible in the middle and are covered by the top conductive patterns M1_1 and M1_4, respectively.

[0049] The top conductive patterns M1_1, M1_2, M1_3, and M1_4 are electrically connected in parallel with the bottom conductive patterns MD_1, MD_2, and MD_3. For example, the bottom conductive pattern MD_3 is electrically connected in parallel with the top conductive patterns M1_1 and M1_3 through conductive vias VD_1, VD_2, V0_3, V0_4, V0_5, and V0_6, as well as the middle conductive patterns M0_1 and M0_2.

[0050] The parallel connection of the bottom conductive patterns MD_1, MD_2, and MD_3 can reduce the overall resistance of layout 100. The parallel connection of the bottom conductive patterns MD_1, MD_2, and MD_3 can improve the operating speed of semiconductor devices manufactured according to layout 100.

[0051] The parallel connection of the top conductive patterns M1_1, M1_2, M1_3, and M1_4 can reduce the overall resistance of layout 100. The parallel connection of the top conductive patterns M1_1, M1_2, M1_3, and M1_4 can improve the operating speed of semiconductor devices manufactured according to layout 100.

[0052] The parallel connection of conductive patterns MD_1, MD_2, and MD_3 with the top conductive patterns M1_1, M1_2, M1_3, and M1_4 can reduce the overall resistance of layout 100. The parallel connection of conductive patterns MD_1, MD_2, and MD_3 with the top conductive patterns M1_1, M1_2, M1_3, and M1_4 can improve the operating speed of semiconductor devices manufactured according to layout 100.

[0053] Figure 1B A cross-sectional view of a semiconductor device according to some embodiments of the present invention is shown.

[0054] Figure 1B This is a cross-sectional view of semiconductor device 102. Figure 1B The purpose is to show the connection with what can be made Figure 1A Non-limiting examples of vertical architectures associated with active regions, bottom conductive patterns, middle conductive patterns, top conductive patterns, polycrystalline material patterns, conductive vias, and isolation structures found in layout 100.

[0055] refer to Figure 1B In a non-limiting example, semiconductor device 102 includes substrate 10. In some embodiments, substrate 10 includes a silicon substrate. Optionally, substrate 10 may include other basic semiconductor materials, such as, for example, germanium. Substrate 10 may also include compound semiconductors, such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide. Substrate 10 may include alloy semiconductors, such as silicon germanium, silicon germanium carbide, gallium arsenide phosphide, or gallium indium phosphide.

[0056] The active region OD is located on the substrate 10. The active region OD may be embedded within the substrate 10. In some embodiments, the active region OD is an n-type active region. In some embodiments, the active region OD is a p-type active region.

[0057] A bottom conductive pattern MD is located on substrate 10. The bottom conductive pattern MD is in contact with substrate 10. A polycrystalline material pattern PO is disposed on substrate 10. The polycrystalline material pattern PO is in contact with substrate 10. The bottom conductive pattern MD and the polycrystalline material pattern PO are separated by a certain gap. The bottom conductive pattern MD is separated by an isolation structure CMD. The isolation structure CMD divides the bottom conductive pattern MD into two electrically isolated parts, MDa and MDb.

[0058] The intermediate conductive pattern M0 is located above the bottom conductive pattern MD and the polycrystalline material pattern PO. The intermediate conductive pattern M0 is separated by the isolation structure CM0. The isolation structure CM0 divides the intermediate conductive pattern M0 into two electrically isolated parts, M0a and M0b. The top conductive pattern M1 is disposed above the intermediate conductive pattern M0.

[0059] The bottom conductive pattern MD is electrically connected to the intermediate conductive pattern M0 through a conductive via VD. The polycrystalline material pattern PO is electrically connected to the intermediate conductive pattern M0 through a conductive via VG. The intermediate conductive pattern M0 is electrically connected to the top conductive pattern M1 through a conductive via V0.

[0060] Dielectric layer 12, also referred to in some embodiments as intermetallic dielectric layer 12, is located between the bottom conductive pattern MD and the intermediate conductive pattern M0, and between the polycrystalline material pattern PO and the intermediate conductive pattern M0. Dielectric layer 14, also referred to in some embodiments as intermetallic dielectric layer 14, is located between the intermediate conductive pattern M0 and the top conductive pattern M1. Dielectric layers 12 and 14 isolate the different conductive patterns.

[0061] Figure 1C A top view of a semiconductor layout according to some embodiments of the present invention is shown.

[0062] Figure 1C Layout 104 is shown. Layout 104 may correspond to Figure 1A This refers to part of layout 100. Specifically, layout 104 corresponds to the output stage of layout 100.

[0063] refer to Figure 1C The top conductive patterns M1_1, M1_2, M1_3, and M1_4 are electrically connected in parallel with the bottom conductive patterns MD_1, MD_2, and MD_3. The top conductive patterns M1_1, M1_2, M1_3, and M1_4 are electrically connected in parallel with the bottom conductive patterns MD_1, MD_2, and MD_3 through conductive vias V0_1 to V0_8, conductive vias VD_1 to VD_6, and the middle conductive patterns M0_1 and M0_5.

[0064] The parallel connection of conductive patterns MD_1, MD_2 and MD_3 with top conductive patterns M1_1, M1_2, M1_3 and M1_4 can reduce the overall resistance and improve the operating speed of semiconductor devices.

[0065] Figure 2A A top view of a semiconductor layout according to some embodiments of the present invention is shown.

[0066] Figure 2A Layout 100A is shown. Layout 100A illustrates a non-limiting example where bottom and top conductive patterns are disposed within the cell boundary b1 of a single logic cell. In layout 100A, three top conductive patterns are disposed within the cell boundary b1. In layout 100A, the three top conductive patterns are electrically connected in parallel with the bottom conductive patterns.

[0067] Figure 2A The illustrated logic cell includes a width W1. In some embodiments, the width W1 of the logic cell is approximately 153 nanometers (nm). In other embodiments, the width W1 of the logic cell exceeds 153 nm. In other embodiments, the width W1 of the logic cell is less than 153 nm. The bottom conductive patterns MD_1, MD_2, and MD_3 are spaced apart from each other by a pitch P1. In some embodiments, the pitch P1 is approximately 51 nm. In other embodiments, the pitch P1 exceeds 51 nm. In other embodiments, the pitch P1 is less than 51 nm.

[0068] The top conductive pattern M1_1 is aligned with the bottom conductive pattern MD_1 on the x-axis. The top conductive pattern M1_2 is aligned with the bottom conductive pattern MD_2 on the x-axis. The top conductive pattern M1_3 is aligned with the bottom conductive pattern MD_3 on the x-axis.

[0069] Along the x-axis, the edge of the top conductive pattern M1_1 is aligned with the edge of the bottom conductive pattern MD_1. Along the x-axis, the edge of the top conductive pattern M1_2 is aligned with the edge of the bottom conductive pattern MD_2. Along the x-axis, the edge of the top conductive pattern M1_3 is aligned with the edge of the bottom conductive pattern MD_3.

[0070] For example, the edge e1 of the bottom conductive pattern MD_2 is aligned with the edge e2 of the top conductive pattern M1_2.

[0071] From a top view, the top conductive pattern M1_1 partially covers the bottom conductive pattern MD_1 and exposes a portion of the bottom conductive pattern MD_1. From a top view, the top conductive pattern M1_2 partially covers the bottom conductive pattern MD_2 and exposes a portion of the bottom conductive pattern MD_2. From a top view, the top conductive pattern M1_3 partially covers the bottom conductive pattern MD_3 and exposes a portion of the bottom conductive pattern MD_3.

[0072] Figure 2BA non-limiting example of layout 100B is shown, wherein a bottom conductive pattern and a top conductive pattern are disposed within the cell boundary b1 of a single logic cell. In layout 100B, two top conductive patterns are disposed within the cell boundary b1. In layout 100B, the two top conductive patterns are electrically connected in parallel with the bottom conductive pattern.

[0073] Figure 2B The logic unit shown includes a width W1 and conductive patterns MD_1, MD_2 and MD_3 spaced apart from each other by a pitch P1.

[0074] Along the x-axis, the top conductive pattern M1_1 is located between the bottom conductive patterns MD_1 and MD_2. Along the x-axis, the top conductive pattern M1_2 is located between the bottom conductive patterns MD_2 and MD_3.

[0075] From a top view, the top conductive pattern M1_1 covers a portion of the polycrystalline material pattern PO_1 and exposes a portion of the polycrystalline material pattern PO_1. From a top view, the top conductive pattern M1_2 covers a portion of the polycrystalline material pattern PO_2 and exposes a portion of the polycrystalline material pattern PO_2.

[0076] Figure 2C A non-limiting example of layout 100C is shown, wherein a bottom conductive pattern and a top conductive pattern are located within the cell boundary b1 of a single logic cell. In layout 100C, three top conductive patterns are disposed within the cell boundary b1. In layout 100C, the three top conductive patterns are electrically connected in parallel with the bottom conductive pattern.

[0077] Figure 2C The illustrated logic cell includes a width W1. The bottom conductive patterns MD_1, MD_2, and MD_3 are spaced apart from each other by a pitch P2. In some embodiments, the pitch P2 is approximately 34 nm. In other embodiments, the pitch P2 is greater than 34 nm. In still other embodiments, the pitch P2 is less than 34 nm.

[0078] From a top view, portions of the top conductive pattern M1_1 overlap with portions of the bottom conductive pattern MD_1 and the polycrystalline material pattern PO_1. From a top view, portions of the top conductive pattern M1_3 overlap with portions of the bottom conductive pattern MD_3 and the polycrystalline material pattern PO_2.

[0079] The top conductive pattern M1_2 and the bottom conductive pattern MD_2 are aligned along the x-axis. Along the x-axis, the edge e1 of the bottom conductive pattern MD_2 is aligned with the edge e2 of the top conductive pattern M1_2.

[0080] Layout 100C also includes top conductive patterns M1_4 and M1_5. Because a portion of each of the top conductive patterns M1_4 and M1_5 is located outside the cell boundary b1, they are not included in the density calculation of the top conductive patterns of layout 100C.

[0081] Figure 2D A non-limiting example of layout 100D is shown, wherein bottom conductive patterns and top conductive patterns are located within the cell boundary b1 of a single logic cell. In layout 100D, four top conductive patterns are disposed within the cell boundary b1. In layout 100D, the four top conductive patterns are electrically connected in parallel with the bottom conductive patterns.

[0082] Figure 2D The logic unit shown includes bottom conductive patterns MD_1, MD_2, and MD_3 with a width W1 and a pitch P2 between them.

[0083] From a top view, portions of the top conductive pattern M1_2 overlap with portions of the bottom conductive pattern MD_2 and the polycrystalline material pattern PO_1. From a top view, portions of the top conductive pattern M1_3 overlap with portions of the bottom conductive pattern MD_2 and the polycrystalline material pattern PO_2.

[0084] The top conductive pattern M1_1 and the bottom conductive pattern MD_1 are aligned along the x-axis. Along the x-axis, the edge e1 of the bottom conductive pattern MD_1 is aligned with the edge e2 of the top conductive pattern M1_1.

[0085] The top conductive pattern M1_4 and the bottom conductive pattern MD_3 are aligned on the x-axis. Along the x-axis, the edge e3 of the bottom conductive pattern MD_3 is aligned with the edge e4 of the top conductive pattern M1_4.

[0086] Layout 100D also includes top conductive patterns M1_5 and M1_6. Because a portion of each of the top conductive patterns M1_5 and M1_6 is outside the cell boundary b1, they are not included in the density calculation of the top conductive patterns of layout 100D.

[0087] Figure 3A A top view of a semiconductor layout according to some embodiments of the present invention is shown.

[0088] Figure 3A Layout 200 is shown. Layout 200 may correspond to an electronic device. Layout 200 may correspond to a semiconductor device. Layout 200 may correspond to a logic semiconductor structure. Layout 200 may correspond to an integrated circuit (IC) system.

[0089] The layout 200 includes active regions OD_1, OD_2, OD_3 and OD_4 extending along the x-axis, a plurality of bottom conductive patterns (e.g., MD_1) extending along the y-axis, a plurality of polycrystalline material patterns (e.g., PO_1, PO_2 and PO_3) extending along the y-axis, a plurality of intermediate conductive patterns (not shown) extending along the x-axis, and a plurality of top conductive patterns (e.g., M1_1, M1_2 and M1_3) extending along the y-axis.

[0090] Layout 200 includes areas for cells C1 and C2. Cells C1 and C2 may each have a "single-height" area, and layout 200 may be referred to as a layout with "double-height" areas. Layout 200 is designed using a "double-height" scheme.

[0091] Layout 200 includes isolation structures for dividing a polycrystalline material pattern into electrically isolated segments. The isolation structures may be referred to as “cutouts” or “cutters.” For example, isolation structures CPO_1 and CPO_3 are disposed at the boundaries of cells C1 and C2 to isolate the polycrystalline material pattern (such as PO_1, PO_2, and PO_3) from other cells adjacent to cells C1 and C2. The isolation structures comprise a suitable non-conductive material.

[0092] In a typical layout design, an additional isolation structure is placed at the boundary between units C1 and C2. That is, in a typical layout design, the isolation structure CPO_2 extends continuously from left to right to divide each of the polycrystalline material patterns PO_1, PO_2, and PO_3 into two electrically isolated segments. However, for... Figure 3A The illustrated embodiment does not demonstrate this.

[0093] exist Figure 3A In layout 200, the polycrystalline material patterns PO_1, PO_2, and PO_3 are not separated by the isolation structure CPO_2. Across the boundary between unit C1 and unit C2, the polycrystalline material patterns PO_1, PO_2, and PO_3 extend continuously from unit C1 to unit C2.

[0094] Polycrystalline material patterns PO_1, PO_2, and PO_3 are electrically connected in parallel. Polycrystalline material patterns PO_1, PO_2, and PO_3 are also electrically connected in parallel with the bottom conductive pattern MD_1. Polycrystalline material patterns PO_1, PO_2, and PO_3 are electrically connected to the bottom conductive pattern MD_1 through conductive vias VG_1, VG_3, VG_5, and VD_1, and through an intermediate conductive pattern (not shown) extending along the x-axis. Polycrystalline material patterns PO_1, PO_2, and PO_3 are also electrically connected to the bottom conductive pattern MD_1 through conductive vias VG_2, VG_4, VG_6, and VD_2, and through an intermediate conductive pattern (not shown) extending along the x-axis.

[0095] The parallel connection of polycrystalline material patterns PO_1, PO_2, and PO_3 with the bottom conductive pattern MD_1 can reduce the overall resistance of layout 200. The parallel connection of polycrystalline material patterns PO_1, PO_2, and PO_3 with the bottom conductive pattern MD_1 can improve the operating speed of semiconductor devices manufactured according to layout 200.

[0096] Figure 3B A top view of a semiconductor layout according to some embodiments of the present invention is shown.

[0097] Figure 3B Layout 202 is shown. Layout 202 is... Figure 3A A non-limiting example of a portion of layout 200. Layout 202 is a simplified schematic diagram illustrating the electrical connection between the polycrystalline material pattern and the underlying conductive pattern.

[0098] The layout 202 includes active regions OD_1, OD_2, OD_3 and OD_4 extending along the x-axis, a bottom conductive pattern (e.g., MD_1) extending along the y-axis, a polycrystalline material pattern (e.g., PO_1) extending along the y-axis, and intermediate conductive patterns (e.g., M0_1 and M0_2) extending along the x-axis.

[0099] The boundary b2 of the polycrystalline material pattern PO_1 between unit cells C1 and C2 extends continuously from unit cell C1 to unit cell C2. The bottom conductive pattern MD_1 also extends continuously from unit cell C1 to unit cell C2 through the boundary b2 between unit cells C1 and C2.

[0100] The polycrystalline material pattern PO_1 is electrically connected in parallel with the bottom conductive pattern MD_1. The polycrystalline material pattern PO_1 is electrically connected to the bottom conductive pattern MD_1 through conductive vias VG_1 and VD_1 and the intermediate conductive pattern M0_1. The polycrystalline material pattern PO_1 is also electrically connected to the bottom conductive pattern MD_1 through conductive vias VG_2 and VD_2 and the intermediate conductive pattern M0_2.

[0101] exist Figure 3B In this configuration, two active regions, OD_2 and OD_3, are located between conductive vias VG_1 and VG_2 (or between intermediate conductive patterns M0_1 and M0_2). In some embodiments, more than two active regions are located between conductive vias VG_1 and VG_2. In other embodiments, only one active region is located between conductive vias VG_1 and VG_2.

[0102] Figure 4A A top view of a semiconductor layout according to some embodiments of the present invention is shown.

[0103] Figure 4A Layout 300 is shown. Layout 300 may correspond to an electronic device. Layout 300 may correspond to a semiconductor device. Layout 300 may correspond to a logic semiconductor structure. Layout 300 may correspond to an integrated circuit (IC) system.

[0104] The layout 300 includes active regions OD_1, OD_2, OD_3 and OD_4 extending along the x-axis, a plurality of bottom conductive patterns extending along the y-axis, a plurality of polycrystalline material patterns (e.g. PO_1, PO_2 and PO_3) extending along the y-axis, a plurality of intermediate conductive patterns (not shown) extending along the x-axis, and a plurality of top conductive patterns (e.g. M1_1) extending along the y-axis.

[0105] Layout 300 includes areas for cells C1 and C2. Cells C1 and C2 may each have a "single-height" area, and layout 300 may be referred to as a layout with "double-height" areas. Layout 300 is designed using a "double-height" scheme.

[0106] Layout 300 includes isolation structures for dividing a polycrystalline material pattern into electrically isolated segments. Isolation structures CPO_1 and CPO_3 may be disposed at the boundaries of cells C1 and C2 to isolate the polycrystalline material pattern (such as PO_1, PO_2, and PO_3) from other cells adjacent to cells C1 and C2. The isolation structures comprise a suitable non-conductive material.

[0107] In a typical layout design, an additional isolation structure is placed at the boundary between units C1 and C2. That is, in a typical layout design, the isolation structure CPO_2 extends continuously from left to right to divide each of the polycrystalline material patterns PO_1, PO_2, and PO_3 into two electrically isolated segments. However, for... Figure 4A The illustrated embodiment does not demonstrate this.

[0108] exist Figure 4A In layout 300, the polycrystalline material patterns PO_1, PO_2, and PO_3 are not separated by the isolation structure CPO_2. Across the boundary between unit C1 and unit C2, the polycrystalline material patterns PO_1, PO_2, and PO_3 extend continuously from unit C1 to unit C2.

[0109] Polycrystalline material patterns PO_1, PO_2, and PO_3 are electrically connected in parallel. Polycrystalline material patterns PO_1, PO_2, and PO_3 are also electrically connected in parallel to the top conductive pattern M1_1. Polycrystalline material patterns PO_1, PO_2, and PO_3 are electrically connected to the top conductive pattern M1_1 through conductive vias VG_1, VG_3, VG_5, and V0_1, as well as an intermediate conductive pattern (not shown) extending along the x-axis. Polycrystalline material patterns PO_1, PO_2, and PO_3 are also electrically connected to the top conductive pattern M1_1 through conductive vias VG_2, VG_4, VG_6, and V0_2, as well as an intermediate conductive pattern (not shown) extending along the x-axis.

[0110] The parallel connection of polycrystalline material patterns PO_1, PO_2, and PO_3 with the top conductive pattern M1_1 can reduce the overall resistance of layout 300. The parallel connection of polycrystalline material patterns PO_1, PO_2, and PO_3 with the top conductive pattern M1_1 can improve the operating speed of semiconductor devices manufactured according to layout 300.

[0111] Figure 4B A top view of a semiconductor layout according to some embodiments of the present invention is shown.

[0112] Figure 4BLayout 302 is shown. Layout 302 is... Figure 4A A non-limiting example of a portion of layout 300. Layout 302 is a simplified schematic diagram illustrating the electrical connection between the polycrystalline material pattern and the top conductive pattern.

[0113] The layout 302 includes active regions OD_1, OD_2, OD_3 and OD_4 extending along the x-axis, a top conductive pattern M1_1 extending along the y-axis, polycrystalline material patterns PO_1 and PO_2 extending along the y-axis, and intermediate conductive patterns (e.g., M0_1 and M0_2) extending along the x-axis.

[0114] The boundary b2 of the polycrystalline material pattern PO_1 between units C1 and C2 extends continuously from unit C1 to unit C2. The top conductive pattern M1_1 extends continuously from unit C1 to unit C2 through the boundary b2 between units C1 and C2.

[0115] Polycrystalline material patterns PO_1 and PO_2 are electrically connected in parallel to the top conductive pattern M1_1. Polycrystalline material patterns PO_1 and PO_2 are electrically connected to the top conductive pattern M1_1 through conductive vias VG_1, V0_1, and VG_3, and the intermediate conductive pattern M0_1. Polycrystalline material patterns PO_1 and PO_2 are electrically connected to the top conductive pattern M1_1 through conductive vias VG_2, V0_2, and VG_4, and the intermediate conductive pattern M0_2.

[0116] exist Figure 4B In this configuration, two active regions, OD_2 and OD_3, are located between conductive vias VG_1 and VG_2 (or between intermediate conductive patterns M0_1 and M0_2). In some embodiments, more than two active regions are located between conductive vias VG_1 and VG_2. In other embodiments, only one active region is located between conductive vias VG_1 and VG_2.

[0117] Figure 5A A top view of a semiconductor layout according to some embodiments of the present invention is shown.

[0118] Figure 5A Layout 400 is shown. Layout 400 may correspond to an electronic device. Layout 400 may correspond to a semiconductor device. Layout 400 may correspond to a logic semiconductor structure. Layout 400 may correspond to an integrated circuit (IC) system.

[0119] The layout 400 includes active regions OD_1, OD_2, OD_3 and OD_4 extending along the x-axis, a plurality of bottom conductive patterns (e.g. MD_1, MD_2 and MD_3) extending along the y-axis, a plurality of polycrystalline material patterns (not shown) extending along the y-axis, a plurality of intermediate conductive patterns (not shown) extending along the x-axis, and a plurality of top conductive patterns (e.g. M1_1 and M1_2) extending along the y-axis.

[0120] Layout 400 includes areas for cells C1 and C2. Cells C1 and C2 may each have a "single-height" area, and layout 400 may be referred to as a layout with "double-height" areas.

[0121] Layout 400 includes isolation structures for dividing a bottom conductive pattern into electrically isolated segments. For example, isolation structures CMD_1 and CMD_2 can divide the bottom conductive pattern MD_3 into electrically isolated segments.

[0122] exist Figure 5A In layout 400, the bottom conductive patterns MD_1 and MD_2 are not separated by any isolation structure. The boundary between cell C1 and cell C2 of the bottom conductive patterns MD_1 and MD_2 extends continuously from cell C1 to cell C2.

[0123] Bottom conductive patterns MD_1 and MD_2 are connected in parallel. Bottom conductive patterns MD_1 and MD_2 are also connected in parallel with top conductive patterns M1_1 and M1_2.

[0124] Bottom conductive patterns MD_1 and MD_2 are electrically connected to top conductive patterns M1_1 and M1_2 via conductive vias VD_1, V0_1, V0_3 and VD_3, and an intermediate conductive pattern (not shown) extending along the x-axis. Bottom conductive patterns MD_1 and MD_2 are electrically connected to top conductive patterns M1_1 and M1_2 via conductive vias VD_2, V0_2, V0_4 and VD_4, and an intermediate conductive pattern (not shown) extending along the x-axis.

[0125] The parallel connection of bottom conductive patterns MD_1 and MD_2 with top conductive patterns M1_1 and M1_2 can reduce the overall resistance of layout 400. The parallel connection of bottom conductive patterns MD_1 and MD_2 with top conductive patterns M1_1 and M1_2 can improve the operating speed of semiconductor devices manufactured according to layout 400.

[0126] Figure 5B A top view of a semiconductor layout according to some embodiments of the present invention is shown.

[0127] Figure 5B Layout 402 is shown. Layout 402 is... Figure 5A A non-limiting example of a portion of layout 400. Layout 402 is a simplified schematic diagram showing the electrical connection between the bottom conductive pattern and the top conductive pattern.

[0128] The layout 402 includes active regions OD_1, OD_2, OD_3 and OD_4 extending along the x-axis, top conductive patterns M1_1 and M1_2 extending along the y-axis, intermediate conductive patterns M0_1 and M0_2 ​​extending along the x-axis, and bottom conductive patterns MD_1 and MD_2 extending along the y-axis.

[0129] The bottom conductive patterns MD_1 and MD_2 extend continuously from cell C1 to cell C2 across the boundary b2 between cells C1 and C2. The top conductive patterns M1_1 and M1_2 extend continuously from cell C1 to cell C2 across the boundary b2 between cells C1 and C2.

[0130] Bottom conductive patterns MD_1 and MD_2 are electrically connected in parallel with top conductive patterns M1_1 and M1_2. Bottom conductive patterns MD_1 and MD_2 are electrically connected to top conductive patterns M1_1 and M1_2 through conductive vias VD_1, V0_1, V0_3, and VD_3, and the intermediate conductive pattern M0_1. Bottom conductive patterns MD_1 and MD_2 are electrically connected to top conductive patterns M1_1 and M1_2 through conductive vias VD_2, V0_2, V0_4, and VD_4, and the intermediate conductive pattern M0_2.

[0131] exist Figure 5B In this configuration, two active regions, OD_2 and OD_3, are located between conductive vias VD_1 and VD_2 (or between intermediate conductive patterns M0_1 and M0_2). In some embodiments, more than two active regions are located between conductive vias VD_1 and VD_2. In other embodiments, only one active region is located between conductive vias VD_1 and VD_2.

[0132] Figure 6 A top view of a semiconductor layout according to some embodiments of the present invention is shown.

[0133] Figure 6 Layout 500 is shown. Layout 500 includes a plurality of active regions extending along the x-axis, a plurality of bottom conductive patterns extending along the y-axis, a plurality of polycrystalline material patterns extending along the y-axis, a plurality of intermediate conductive patterns (not shown) extending along the x-axis, and a plurality of top conductive patterns extending along the y-axis.

[0134] In layout 500, input stage S1 is located at the center of the layout, while output stage S2 is adjacent to input stage S1. Compared to methods that include a single input stage and a single output stage, the signal transmitted from input stage S1 will travel a shorter distance before potentially reaching output stage S2. Therefore, the arrangement of stages S1 and S2 in layout 500 provides a better balance and can produce semiconductor devices with better performance.

[0135] Figure 7 A top view of a semiconductor layout according to some embodiments of the present invention is shown.

[0136] Figure 7Layout 600 is shown. Layout 600 includes a plurality of active regions extending along the x-axis, a plurality of bottom conductive patterns extending along the y-axis, a plurality of polycrystalline material patterns (e.g., PO_1, PO_2, PO_3, PO_4, PO_5, PO_6, PO_7, PO_8, PO_9, PO_10, PO_11, and PO_12) extending along the y-axis, a plurality of intermediate conductive patterns (not shown) extending along the x-axis, and a plurality of top conductive pattern axes extending along the y-axis.

[0137] In layout 600, input stage S1 is located at the center of the layout, while output stage S2 is adjacent to input stage S1. Compared to methods that include a large number (e.g., six or more) of polycrystalline material patterns, the relatively small number of polycrystalline material patterns allows the signal transmitted from input stage S1 to propagate along a shorter distance before potentially reaching output stage S2.

[0138] Furthermore, the intermediate conductive pattern (not shown) extending along the x-axis is relatively short, and therefore layout 600 can exhibit relatively low resistance.

[0139] In some embodiments, if the number of polycrystalline material patterns within the semiconductor layout is equal to or greater than six, a "double-height" scheme is preferably used to design such a semiconductor layout (i.e., using...). Figure 7 The layout 600 shown has areas with units C1 and C2.

[0140] Figure 8A and Figure 8B A flowchart illustrating operations for manufacturing semiconductor devices is shown according to some embodiments of the present invention.

[0141] Figure 8A and Figure 8B This includes operations 702, 704, 706, 708, 710, 712, 714, 716, 718, 720, 722, and 724 used for manufacturing semiconductor devices. Although operations 702, 704, 706, 708, 710, 712, 714, 716, 718, 720, 722, and 724... Figure 8A and Figure 8B The operations 702, 704, 706, 708, 710, 712, 714, 716, 718, 720, 722, and 724 can be described in a different manner. Figure 8A and Figure 8B The operations are performed in the order shown. In some embodiments, performing some or all of operations 702 to 724 includes performing the following as described below regarding IC manufacturing system 1100 and Figure 11 One or more operations are being discussed.

[0142] In operation 702, in some embodiments, a substrate is formed. The substrate formed in operation 702 may include, for example, but not limited to, silicon (Si), doped Si, silicon carbide (SiC), germanium silicide (SiGe), gallium arsenide (GaAs), or other semiconductor materials. The substrate formed in operation 702 may include, for example, but not limited to, sapphire, silicon-on-insulator (SOI), or other suitable materials. In some embodiments, the substrate formed in operation 702 comprises a silicon material. In some embodiments, the substrate formed in operation 702 is a silicon substrate.

[0143] In operation 704, in some embodiments, a first conductive pattern extending along a first direction (y-axis) is formed on the substrate. The first conductive pattern formed in operation 704 may correspond to... Figure 1A The bottom conductive pattern MD_2.

[0144] In operation 706, in some embodiments, a second conductive pattern extending along a second direction (x-axis) perpendicular to the first conductive pattern is formed on the first conductive pattern. The second conductive pattern formed in operation 706 may correspond to... Figure 1A The intermediate conductive pattern M0_1.

[0145] In operation 708, in some embodiments, a third conductive pattern extending along a first direction (x-axis) is formed on the second conductive pattern base. Figure 1A (M1_2 in the example). The third conductive pattern formed in operation 708 can correspond to... Figure 1A The top conductive pattern M1_2.

[0146] In operation 710, in some embodiments, a fourth conductive pattern extending along a first direction (x-axis) is formed on the second conductive pattern. Figure 1A (M1_3 in the example). The fourth conductive pattern formed in operation 710 can correspond to M1_3). Figure 1A The top conductive pattern M1_3.

[0147] In operation 712, in some embodiments, a first conductive via is formed electrically connected between the first conductive pattern and the second conductive pattern. The first conductive via formed in operation 712 may correspond to... Figure 1A The conductive via VD_1. (Reference) Figure 1A The conductive via VD_1 electrically connects the bottom conductive pattern MD_2 to the middle conductive pattern M0_1.

[0148] In operation 714, in some embodiments, a second conductive via is formed electrically connected between the second conductive pattern and the third conductive pattern. The second conductive via formed in operation 714 may correspond to... Figure 1A The conductive via V0_3. (Reference) Figure 1AThe conductive via V0_3 electrically connects the intermediate conductive pattern M0_1 to the top conductive pattern M1_2.

[0149] In operation 716, in some embodiments, a third conductive via is formed electrically connected between the second conductive pattern and the fourth conductive pattern. The third conductive via formed in operation 716 may correspond to... Figure 1A The conductive via V0_5. (Reference) Figure 1A The conductive via V0_5 electrically connects the intermediate conductive pattern M0_1 to the top conductive pattern M1_3.

[0150] In operation 718, in some embodiments, a fifth conductive pattern extending along a second direction (x-axis) is formed on the first conductive pattern. Figure 1A (M0_5 in the example). The fifth conductive pattern formed in operation 718 can correspond to... Figure 1A The intermediate conductive pattern M0_5.

[0151] In operation 720, in some embodiments, a fourth conductive via is formed electrically connected between the first conductive pattern and the fifth conductive pattern. The fourth conductive via formed in operation 720 may correspond to... Figure 1A The conductive via VD_2. (Reference) Figure 1A The conductive via VD_2 electrically connects the bottom conductive pattern MD_2 to the middle conductive pattern M0_5.

[0152] In operation 722, in some embodiments, a fifth conductive via is formed electrically connected between the fifth conductive pattern and the third conductive pattern. The fifth conductive via formed in operation 722 may correspond to... Figure 1A The conductive via V0_4. (Reference) Figure 1A The conductive via V0_4 electrically connects the intermediate conductive pattern M0_5 to the top conductive pattern M1_2.

[0153] In operation 724, in some embodiments, a sixth conductive via is formed electrically connected between the fifth conductive pattern and the fourth conductive pattern. The sixth conductive via formed in operation 724 may correspond to... Figure 1A The conductive via V0_6. (Reference) Figure 1A The conductive via V0_6 electrically connects the intermediate conductive pattern M0_5 to the top conductive pattern M1_3.

[0154] Figure 9 A top view of a semiconductor layout according to some comparative embodiments of the present invention is shown.

[0155] Figure 9The layout 100' is shown. The layout 100' includes a plurality of active regions extending along the x-axis, a plurality of bottom conductive patterns (e.g., MD_1, MD_2 and MD_3) extending along the y-axis, a plurality of polycrystalline material patterns extending along the y-axis, a plurality of intermediate conductive patterns (e.g., M0_1 and M0_2) extending along the x-axis, and a plurality of top conductive patterns (e.g., M1_1) extending along the y-axis.

[0156] refer to Figure 9 As shown in the dashed box A, in the output stage of layout 100, only one top conductive pattern M1_1 is electrically connected in parallel with the bottom conductive patterns MD_1, MD_2, and MD_3. As a result, Figure 9 100' layout Figure 1A The layout 100 shown exhibits higher resistance.

[0157] The top conductive pattern M1_1 is electrically connected to the bottom conductive patterns MD_1, MD_2, and MD_3 through conductive vias V0_1, VD_1, VD_3, and VD_5, as well as the middle conductive pattern M0_1. Furthermore, the top conductive pattern M1_1 is electrically connected to the bottom conductive patterns MD_1, MD_2, and MD_3 through conductive vias V0_2, VD_2, VD_4, and VD_6, as well as the middle conductive pattern M0_5.

[0158] Figure 10 This is a block diagram of an IC design system 1000 according to some embodiments. The design IC layout diagrams described herein according to one or more embodiments can be implemented, for example, using the IC design system 1000 according to some embodiments. In some embodiments, the IC design system 1000 is an APR system, includes an APR system, or is a portion of an APR system that can be used to perform APR methods.

[0159] In some embodiments, the IC design system 1000 is a general-purpose computing device including a hardware processor 1002 and a non-transitory computer-readable storage medium 1004. Among other things, the storage medium 1004 is encoded with computer program code 1006 (i.e., an executable instruction set), i.e., stores the computer program code. The execution of the instructions 1006 by the hardware processor 1002 represents (at least partially) the implementation of part or all of the EDA tools of the method, such as the method for generating the IC layout diagram described above (hereinafter, the processes and / or methods mentioned).

[0160] Processor 1002 is electrically connected to computer-readable storage medium 1004 via bus 1008. Processor 1002 is also electrically connected to input / output (I / O) interface 1010 via bus 1008. Network interface 1012 is also electrically connected to processor 1002 via bus 1008. Network interface 1012 is connected to network 1014 so that processor 1002 and computer-readable storage medium 1004 can be connected to external components via network 1014. Processor 1002 is configured to execute computer program code 1006 encoded in computer-readable storage medium 1004 to enable IC design system 1000 to perform some or all of the aforementioned processes and / or methods. In one or more embodiments, processor 1002 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0161] In one or more embodiments, the computer-readable storage medium 1004 is an electronic, magnetic, optical fiber, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, the computer-readable storage medium 1004 includes semiconductor or solid-state memory, magnetic tape, mobile electronic disk, random access memory (RAM), read-only memory (ROM), hard disk, and / or optical disk. In one or more embodiments using optical disk, the computer-readable storage medium 1004 includes optical disc read-only memory (CD-ROM), optical disc read / write memory (CD-R / W), and / or digital video optical disc (DVD).

[0162] In one or more embodiments, storage medium 1004 stores computer program code 1006 configured to enable IC design system 1000 (where such execution represents, at least partially, an EDA tool) to perform some or all of the aforementioned processes and / or methods. In one or more embodiments, storage medium 1004 also stores information that facilitates the execution of some or all of the mentioned processes and / or methods. In one or more embodiments, storage medium 1004 includes information configured to store one or more IC layout diagrams (e.g., those mentioned above regarding...). Figures 1A to 7 and Figure 9 The IC design of memory 1007 (discussed IC layout diagram) is shown.

[0163] IC design system 1000 includes I / O interface 1010. I / O interface 1010 is connected to external circuitry. In one or more embodiments, I / O interface 1010 includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and / or cursor arrow keys for transmitting information and commands to processor 1002.

[0164] The IC design system 1000 also includes a network interface 1012 connected to the processor 1002. The network interface 1012 allows the IC design system 1000 to communicate with a network 1014, to which one or more other computer systems are connected. The network interface 1012 includes a wireless network interface such as BlueTooth, Wi-Fi, WiMAX, GPRS, or WCDMA, or a wired network interface such as Ethereum, USB, or IEEE-1364. In one or more embodiments, some or all of the described processes and / or methods are implemented in two or more IC design systems 1000.

[0165] The IC design system 1000 is configured to receive information via I / O interface 1010. The information received via I / O interface 1010 includes one or more instructions, data, design rules, standard cell libraries, and / or other parameters for processing by processor 1002. The information is transmitted to processor 1002 via bus 1008. The IC design system 1000 is also configured to receive information associated with a user interface (UI) via I / O interface 1010. This information is stored as a user interface (UI) 1042 on computer-readable medium 1004.

[0166] In some embodiments, part or all of the mentioned processes and / or methods are implemented as a standalone software application executed by a processor. In some embodiments, part or all of the mentioned processes and / or methods are implemented as a software application as part of an additional software application. In some embodiments, part or all of the mentioned processes and / or methods are implemented as a plug-in to a software application. In some embodiments, part or all of the described processes and / or methods are executed as part of a software application for an EDA tool. In some embodiments, part or all of the mentioned processes and / or methods are implemented as a software application used by an IC design system 1000. In some embodiments, a layout diagram including standard cells is generated using a tool such as VIRTUOSO, available from CADENCEDESIGNSYSTEMS, Inc., or another suitable layout generation tool.

[0167] In some embodiments, the process is implemented as the function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage devices or storage units, such as optical discs such as DVDs, magnetic disks such as hard disks, and one or more semiconductor memories such as ROM, RAM, and memory cards.

[0168] Figure 11This is a block diagram of an IC manufacturing system 1100 and its associated IC manufacturing process according to some embodiments. In some embodiments, the manufacturing system 1100 is used to manufacture at least one of the following, based on an IC layout diagram: (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit.

[0169] exist Figure 11 In this IC manufacturing system 1100, entities interact with each other throughout the design, development, and manufacturing cycles, such as design studio 1120, mask room 1130, and IC manufacturer / producer (“fab”) 1150 and / or services related to the manufacture of IC devices 1160. The entities in system 1100 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of the design studio 1120, mask room 1130, and IC foundry 1150 are owned by a single, larger company. In some embodiments, two or more of the design studio 1120, mask room 1130, and IC foundry 1150 coexist in a shared facility and use shared resources.

[0170] Design studio (or design team) 1120 generates IC design layout 1122. IC design layout 1122 includes various geometric patterns, such as the IC layout discussed above. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute the various elements of the IC device 1160 to be manufactured. The various layers combine to form various IC components. For example, a portion of IC design layout 1122 includes various IC components, such as active regions, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnects, and openings for bonding pads, to be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on a semiconductor substrate. Design studio 1120 implements appropriate design procedures to form IC design layout 1122. The design process includes one or more of logic design, physical design, or placement and routing. IC design layout 1122 is presented in one or more data files containing information about the geometric patterns. For example, IC design layout 1122 may be represented in GDSII or DFII file format.

[0171] Mask chamber 1130 includes data preparation 1132 and mask fabrication 1144. Mask chamber 1130 uses an IC design layout 1122 to fabricate one or more masks 1145 to fabricate various layers of an IC device 1160 according to the IC design layout 1122. Mask chamber 1130 performs mask data preparation 1132, in which the IC design layout 1122 is converted into a representative data file (RDF). Mask data preparation 1132 provides the RDF to mask fabrication 1144. Mask fabrication 1144 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (intermediate mask) 1145 or a semiconductor wafer 1153. The design layout 1122 is manipulated through mask data preparation 1132 to conform to the specific characteristics of the mask writer and / or the requirements of the IC foundry 1150. Figure 11 In this diagram, mask data preparation 1132 and mask manufacturing 1144 are shown as separate elements. In some embodiments, mask data preparation 1132 and mask manufacturing 1144 can be collectively referred to as mask data preparation.

[0172] In some embodiments, mask data preparation 1132 includes optical proximity correction (OPC), which uses lithographic enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, or other processing effects. OPC adjusts the IC design layout (Figure 1122). In some embodiments, mask data preparation 1132 includes additional resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution auxiliary features, phase-shift masks, other suitable techniques, or combinations thereof. In some embodiments, inverse lithography (ILT) is also used, which treats OPC as an inverse imaging problem.

[0173] In some embodiments, mask data preparation 1132 includes a mask rule checker (MRC) that checks the IC design layout 1122, which has already been processed in the OPC, against a set of mask creation rules. These rules include certain geometric and / or connectivity constraints to ensure sufficient margin to address issues such as variability in semiconductor manufacturing processes. In some embodiments, the MRC modifies the IC design layout 1122 to compensate for constraints during mask fabrication 1144, which can reverse some modifications performed by the OPC to satisfy the mask creation rules.

[0174] In some embodiments, mask data preparation 1132 includes lithography process inspection (LPC), an LPC simulation performed by IC foundry 1150 to manufacture IC device 1160. The LPC simulates this process based on IC design layout 1122 to create a simulated manufactured device, such as IC device 1160. Process parameters in the LPC simulation may include parameters associated with various processes in the IC manufacturing cycle, parameters associated with the tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC inspection takes into account various factors, such as aerial image contrast, depth of focus (“DOF”), mask error enhancement factor (“MEEF”), and other suitable factors, or combinations thereof. In some embodiments, after a simulated manufactured device has been created by the LPC, if the shape of the simulated device is not close enough to meet design rules, OPC and / or MRC are repeated to further refine the IC design layout 1122.

[0175] It should be understood that, for clarity, the above description of mask data preparation 1132 has been simplified. In some embodiments, data preparation 1132 includes additional features such as logic operations (LOPs) to modify the IC design layout 1122 according to manufacturing rules. Furthermore, the processes applied to the IC design layout 1122 during data preparation 1132 can be performed in various different sequences.

[0176] Following mask data preparation 1132 and during mask fabrication 1144, a mask 1145 or a set of masks 1145 is fabricated based on a modified IC design layout 1122. In some embodiments, mask fabrication 1144 includes performing one or more photolithographic exposures based on the IC design layout 1122. In some embodiments, a mechanism of electron beams (e-beams) or multiple electron beams is used to pattern the mask (photomask or intermediate mask) 1145 according to the modified IC design layout 1122. The mask 1145 can be formed using various techniques. In some embodiments, a binary technique is used to form the mask 1145. In some embodiments, the mask pattern includes opaque areas and transparent areas. Radiation beams, such as ultraviolet (UV) or EUV beams, used to expose an image-sensitive material layer (e.g., photoresist) already coated on the wafer are blocked by the opaque areas and transmitted through the transparent areas. In one example, the binary intermediate mask of mask 1145 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, mask 1145 is formed using a phase-shifting technique. In a phase-shifting mask (PSM) version of mask 1145, various features in the pattern formed on the phase-shifting mask are configured to have appropriate phase differences to enhance resolution and imaging quality. In various examples, the phase-shifting mask may be a decaying PSM or an alternating PSM. One or more masks generated by mask fabrication 1144 are used in various processes. For example, such masks are used in ion implantation processes to form various doped regions in semiconductor wafer 1153, in etching processes to form various etched regions in semiconductor wafer 1153, and / or in other suitable processes.

[0177] IC foundry 1150 is an IC manufacturing enterprise that includes one or more manufacturing facilities for manufacturing a variety of different IC products. In some embodiments, IC foundry 1150 is a semiconductor foundry. For example, there may be manufacturing equipment for front-end manufacturing (front-end process (FEOL) manufacturing) of multiple IC products, while a second manufacturing equipment can provide back-end manufacturing (back-end process (BEOL) manufacturing) for interconnecting and packaging IC products, and a third manufacturing equipment may provide additional services for casting operations.

[0178] IC foundry 1150 includes wafer fabrication tools 1152 configured to perform various manufacturing operations on semiconductor wafers 1153 to fabricate IC devices 1160 according to one or more masks (e.g., mask 1145). In various embodiments, fabrication tools 1152 include one or more of the following: wafer stepper, ion implanter, coater, process chamber (e.g., CVD chamber or LPCVD furnace), CMP system, plasma etching system, wafer cleaning system, or other fabrication equipment as discussed herein capable of performing one or more suitable manufacturing processes.

[0179] IC foundry 1150 uses mask 1145, fabricated through mask chamber 1130, to fabricate IC device 1160. Therefore, IC foundry 1150 uses IC design layout 1122 at least indirectly to fabricate IC device 1160. In some embodiments, using mask 1145, IC foundry 1150 fabricates semiconductor wafer 1153 to form IC device 1160. In some embodiments, IC fabrication includes performing one or more photolithographic exposures at least indirectly based on IC design layout 1122. Semiconductor wafer 1153 includes a silicon substrate or other suitable substrate having multiple material layers formed thereon. Semiconductor wafer 1153 also includes one or more of various doped regions, dielectric components, and multilayer interconnects (formed in subsequent fabrication steps).

[0180] Regarding IC manufacturing systems (e.g., Figure 11 The details of the system 1100 and the associated IC manufacturing process can be found, for example, in U.S. Patent No. 9,256,709, granted February 9, 2016; U.S. Patent No. 20150278429, published October 1, 2015; U.S. Patent No. 20140040838, published February 6, 2014; and U.S. Patent No. 7,260,442, granted August 21, 2007, the entire contents of each of which are incorporated herein by reference.

[0181] Some embodiments of the present invention provide a semiconductor device. The semiconductor device includes: a first conductive pattern located on a substrate and extending along a first direction; a second conductive pattern located above the first conductive pattern and extending along the first direction; and a third conductive pattern located above the first conductive pattern and extending along the first direction. The first conductive pattern is electrically connected in parallel with the second and third conductive patterns.

[0182] In some embodiments, the semiconductor device further includes: a fourth conductive pattern located on the substrate and extending along a second direction perpendicular to the first direction; and a fifth conductive pattern located on the substrate and extending along the second direction; wherein the first conductive pattern is electrically connected to the second conductive pattern through a first conductive via, the fourth conductive pattern, and the second conductive via.

[0183] In some embodiments, the first conductive pattern is also electrically connected to the second conductive pattern through a third conductive via, the fifth conductive pattern, and the fourth conductive via.

[0184] In some embodiments, the semiconductor device further includes: a first active region extending along the second direction; and a second active region extending along the second direction, wherein the first active region and the second active region are located between the first conductive via and the third conductive via.

[0185] In some embodiments, the semiconductor device further includes: a fourth conductive pattern located on the substrate and extending along a second direction; and a fifth conductive pattern located on the substrate and extending along the second direction; wherein the first conductive pattern is electrically connected to the third conductive pattern through a first conductive via, the fourth conductive pattern, and a second conductive via.

[0186] In some embodiments, the first conductive pattern is also electrically connected to the third conductive pattern through the third conductive via, the fifth conductive pattern, and the fourth conductive via.

[0187] In some embodiments, the second conductive pattern is located on top of the first conductive pattern, and wherein the edge of the first conductive pattern is aligned with the edge of the second conductive pattern.

[0188] In some embodiments, the first conductive pattern is located between the second conductive pattern and the third conductive pattern, and wherein the first conductive pattern is spaced apart from the second conductive pattern and the third conductive pattern.

[0189] In some embodiments, the semiconductor device further includes: a polycrystalline material pattern located on the substrate and extending along the first direction; wherein a first portion of the second conductive pattern overlaps with a portion of the polycrystalline material pattern in a second direction perpendicular to the first direction, and a second portion of the second conductive pattern overlaps with the first conductive pattern in the second direction.

[0190] In some embodiments, the first conductive pattern extends continuously from the first cell region to the second cell region, and wherein the second conductive pattern extends continuously from the first cell region to the second cell region.

[0191] In some embodiments, the semiconductor device further includes: a first region configured to receive a first input signal; a second region configured to provide a first output signal; and a third region configured to provide a second output signal, wherein the first region is located between the second region and the third region.

[0192] Some embodiments of the present invention provide a semiconductor device. The semiconductor device includes: a first gate electrode located on a substrate and extending along a first direction; and a first conductive pattern located on the substrate and extending along the first direction. The first gate electrode and the first conductive pattern are electrically connected in parallel. The first gate electrode extends continuously from a first cell region to a second cell region.

[0193] In some embodiments, the semiconductor device further includes: a second conductive pattern located on the substrate and extending along a second direction perpendicular to the first direction; and a third conductive pattern located on the substrate and extending along the second direction; wherein the first gate electrode is electrically connected to the first conductive pattern through a first conductive via, the second conductive pattern, and the second conductive via.

[0194] In some embodiments, the first gate electrode is also electrically connected to the first conductive pattern through a third conductive via, the third conductive pattern, and a fourth conductive via.

[0195] In some embodiments, the first gate electrode and the first conductive pattern are located on the substrate and in contact with the substrate.

[0196] In some embodiments, the first gate electrode is located between the substrate and the first conductive pattern.

[0197] In some embodiments, the semiconductor device further includes a second gate electrode extending along the first direction, wherein the second polycrystalline material pattern is electrically connected in parallel with the first conductive pattern and the first gate electrode.

[0198] Some embodiments of the present invention provide a method for manufacturing a semiconductor device. The method includes: forming a first conductive pattern extending along a first direction on a substrate. The method includes: forming a second conductive pattern extending along a second direction perpendicular to the first direction on the first conductive pattern. The method includes: forming a third conductive pattern extending along the first direction on the second conductive pattern. The method includes: forming a fourth conductive pattern extending along the first direction on the second conductive pattern. The method includes: forming a first conductive via electrically connected between the first conductive pattern and the second conductive pattern. The method includes: forming a second conductive via electrically connected between the second conductive pattern and the third conductive pattern. The method includes: forming a third conductive via electrically connected between the second conductive pattern and the fourth conductive pattern.

[0199] In some embodiments, the method further includes: forming a fifth conductive pattern extending along the second direction on the first conductive pattern; and forming a fourth conductive via electrically connected between the first conductive pattern and the fifth conductive pattern.

[0200] In some embodiments, the method further includes: forming a fifth conductive via electrically connected between the fifth conductive pattern and the third conductive pattern; and forming a sixth conductive via electrically connected between the fifth conductive pattern and the fourth conductive pattern.

[0201] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the invention.

Claims

1. A semiconductor device, comprising: A first conductive pattern is located on a substrate and extends along a first direction; The second conductive pattern is located above the first conductive pattern and extends along the first direction; as well as The third conductive pattern is located above the first conductive pattern and extends along the first direction; A fourth conductive pattern is located between the first conductive pattern, the second conductive pattern, and the third conductive pattern, and extends along a second direction perpendicular to the first direction; as well as The fifth conductive pattern is located between the first conductive pattern, the second conductive pattern, and the third conductive pattern, and extends along the second direction; in, The first conductive pattern is electrically connected in parallel with the second and third conductive patterns between the fourth and fifth conductive patterns.

2. The semiconductor device according to claim 1, wherein, The first conductive pattern is electrically connected to the second conductive pattern through the first conductive via, the fourth conductive pattern, and the second conductive via.

3. The semiconductor device according to claim 2, wherein, The first conductive pattern is also electrically connected to the second conductive pattern through the third conductive via, the fifth conductive pattern, and the fourth conductive via.

4. The semiconductor device according to claim 3, further comprising: The first active region extends along the second direction; as well as The second active region extends along the second direction, wherein The first active region and the second active region are located between the first conductive via and the third conductive via.

5. The semiconductor device according to claim 1, further comprising: in, The first conductive pattern is electrically connected to the third conductive pattern through the first conductive via, the fourth conductive pattern, and the second conductive via.

6. The semiconductor device according to claim 5, wherein, The first conductive pattern is also electrically connected to the third conductive pattern through the third conductive via, the fifth conductive pattern, and the fourth conductive via.

7. The semiconductor device according to claim 1, wherein, The second conductive pattern is located on top of the first conductive pattern, and the edge of the first conductive pattern is aligned with the edge of the second conductive pattern.

8. The semiconductor device according to claim 1, wherein, The first conductive pattern is located between the second conductive pattern and the third conductive pattern, and wherein the first conductive pattern is spaced apart from the second conductive pattern and the third conductive pattern.

9. The semiconductor device according to claim 1, further comprising: A polycrystalline material pattern is located on the substrate and extends along the first direction; in A first portion of the second conductive pattern overlaps with a portion of the polycrystalline material pattern in the second direction, and The second portion of the second conductive pattern overlaps with the first conductive pattern in the second direction.

10. The semiconductor device according to claim 1, wherein, The first conductive pattern extends continuously from the first unit region to the second unit region, and the second conductive pattern extends continuously from the first unit region to the second unit region.

11. The semiconductor device according to claim 1, further comprising: The first zone is configured to receive the first input signal; The second zone is configured to provide the first output signal; as well as The third zone is configured to provide a second output signal, in which The first zone is located between the second zone and the third zone.

12. A semiconductor device, comprising: A first gate electrode is located on the substrate and extends along a first direction; as well as A first conductive pattern is located on the substrate and extends along the first direction; The second conductive pattern is located on the substrate and extends along a second direction perpendicular to the first direction; A third conductive pattern is located on the substrate and extends along the second direction, wherein The first gate electrode is electrically connected in parallel with the first conductive pattern. The first gate electrode extends continuously from the first cell region to the second cell region. The first gate electrode is electrically connected in parallel with the first conductive pattern through a first conductive via, the second conductive pattern, the second conductive via, the third conductive via, the third conductive pattern, and the fourth conductive via.

13. The semiconductor device according to claim 12, wherein, Each of the first gate electrode and the first conductive pattern extends across the first active region in the first cell region and the second active region in the second cell region.

14. The semiconductor device according to claim 13, wherein, The first active region and the second active region are located between the first conductive via and the third conductive via in the first direction.

15. The semiconductor device according to claim 12, wherein, The first gate electrode and the first conductive pattern are located on the substrate and in contact with the substrate.

16. The semiconductor device according to claim 12, wherein, The first gate electrode is located between the substrate and the first conductive pattern.

17. The semiconductor device of claim 12, further comprising: A second gate electrode extends along the first direction, wherein the second gate electrode is electrically connected in parallel with the first conductive pattern and the first gate electrode.

18. A method for manufacturing a semiconductor device, comprising: A first conductive pattern extending in a first direction is formed on the substrate; A second conductive pattern is formed on the first conductive pattern, extending in a second direction perpendicular to the first direction; A third conductive pattern extending along the first direction is formed on the second conductive pattern; A fourth conductive pattern extending along the first direction is formed on the second conductive pattern; A first conductive via is formed that is electrically connected between the first conductive pattern and the second conductive pattern; A second conductive via is formed that is electrically connected between the second conductive pattern and the third conductive pattern; as well as A third conductive via is formed that is electrically connected between the second conductive pattern and the fourth conductive pattern; A fifth conductive pattern extending along the second direction is formed on the first conductive pattern; as well as A fourth conductive via is formed, electrically connected between the first conductive pattern and the fifth conductive pattern; A fifth conductive via is formed, electrically connected between the fifth conductive pattern and the third conductive pattern; as well as A sixth conductive via is formed, electrically connected between the fifth conductive pattern and the fourth conductive pattern.

19. The method of claim 18, further comprising: in, Forming the third conductive pattern includes aligning the edges of the third conductive pattern with the edges of the first conductive pattern.

20. The method of claim 19, wherein: The first conductive pattern extends across the first active region in the first unit region and the second active region in the second unit region.

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