Integrated circuit and method of manufacturing the same

Abstract

The present disclosure provides an integrated circuit and a method of fabricating the same. The method of fabricating the integrated circuit includes forming a fin of a fin field effect transistor of the integrated circuit in a device region of a semiconductor wafer, forming at least one seal ring including a monitoring pattern surrounding the fin of the device region in a seal ring region surrounding the device region, and forming a gate of the fin field effect transistor of the integrated circuit in the device region. A polysilicon structure is formed on the fin of the monitoring pattern in a connection region of the monitoring pattern. Epitaxial material is grown on the fin of the monitoring pattern between the polysilicon structures by a combination of epitaxial growth upward from the fin and epitaxial growth inward from the polysilicon structure. At least one electronic contact is formed to electrically contact the epitaxial material.

Description

Technical Field

[0001] This disclosure relates to integrated circuits and methods for their manufacture. Background Technology

[0002] The following content concerns semiconductor integrated circuits using fin field-effect transistors (finFETs) or other three-dimensional (3D) transistors and their manufacturing methods. Summary of the Invention

[0003] According to embodiments of this disclosure, a method for manufacturing an integrated circuit is provided, comprising forming one or more device region fin field-effect transistors (FFETs) in a device region of a semiconductor wafer, each FFET including one or more device region fins formed rising from the semiconductor wafer and a device region gate formed surrounding the one or more device region fins. The method includes forming an inner sealing ring surrounding the device region and an outer sealing ring surrounding both the inner sealing ring and the device region in a sealing ring region surrounding the semiconductor wafer. The method includes forming a monitoring pattern disposed between the inner and outer sealing rings in the sealing ring region, the monitoring pattern including one or more monitoring pattern fins formed rising from the semiconductor wafer. The method includes forming a first virtual polysilicon structure and a second virtual polysilicon structure in a connection region of the monitoring pattern, each first virtual polysilicon structure and the second virtual polysilicon structure formed surrounding the one or more monitoring pattern fins. The method includes epitaxially growing an epitaxial material on the monitoring pattern fins between the first and second virtual polysilicon structures, and forming electronic contacts of the electrical contact epitaxial material between the first and second virtual polysilicon structures.

[0004] According to embodiments of this disclosure, an integrated circuit is provided. The integrated circuit includes a device region, wherein the device region includes at least one device region three-dimensional transistor, the device region three-dimensional transistor including one or more three-dimensional structures and a device region gate of a contact three-dimensional structure. The integrated circuit includes a sealing ring region surrounding the device region, wherein the sealing ring region includes at least one sealing ring. The integrated circuit includes a monitoring pattern disposed in the sealing ring region, wherein the at least one sealing ring includes a set of sealing ring three-dimensional structures, the monitoring pattern includes a set of monitoring pattern three-dimensional structures and a connection region, the connection region including a first polysilicon structure and a second polysilicon structure surrounding the set of monitoring pattern three-dimensional structures and an electronic contact disposed between the first polysilicon structure and the second polysilicon structure.

[0005] According to embodiments of the present disclosure, a method for manufacturing an integrated circuit is provided, comprising forming multiple fins of a plurality of fin field-effect transistors of the integrated circuit in a device region of a semiconductor wafer, forming at least one sealing ring including multiple sealing ring fins surrounding the device region in a sealing ring region surrounding the device region, and a monitoring pattern including multiple monitoring pattern fins surrounding the device region, forming multiple gates of the fin field-effect transistors of the integrated circuit in the device region, forming multiple polysilicon structures on the monitoring pattern fins in a connection region of the monitoring pattern, epitaxially growing epitaxial material on the monitoring pattern fins between the polysilicon structures, and forming at least one electronic contact of the electrically contacting epitaxial material. Attached Figure Description

[0006] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial methods, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 A perspective view illustrating the fin field-effect transistors used in some of the exemplary embodiments disclosed herein;

[0008] Figure 2 A top view is illustrated, showing a semiconductor structure and / or wafer having defined regions and / or disposed therein, according to some exemplary embodiments disclosed herein;

[0009] Figure 3 Draw Figure 2 A magnified or expanded view of the selected portion (magnified area A), such as including the connecting area of ​​the monitoring pattern;

[0010] Figure 4 A flowchart illustrating a semiconductor device manufacturing process according to some embodiments described herein is shown;

[0011] Figure 5A , Figure 5B and Figure 5C The diagram illustrates the differences between the effective epitaxial growth directions of the source and / or drain structures, where, as described herein, the difference lies in the absence of a virtual polycrystalline silicon structure. Figure 5A ) and the existence of virtual polycrystalline silicon structures ( Figure 5B and Figure 5C );

[0012] Figure 6A and Figure 6B The illustration shows the differences that epitaxial growth source and / or drain structures may result with or without virtual polysilicon structures during growth, as described herein.

[0013] Figure 7The illustrations depict enlarged or partially expanded top views of semiconductor structures and / or wafers having defined regions identified and / or disposed therein, according to some exemplary embodiments disclosed herein.

[0014] [Symbol Explanation]

[0015] 10: Fin Field-Effect Transistor

[0016] 12: Gate

[0017] 14: Fins

[0018] 16:Substrate

[0019] 100: Device Area

[0020] 100a: Connecting area

[0021] 102: Fins

[0022] 104: Contacts

[0023] 106, 108: Virtual polycrystalline silicon structure

[0024] 110: First Edge

[0025] 120: Second Edge

[0026] 200: Sealing ring area

[0027] 210: Inner sealing ring

[0028] 212: Sealing ring fin

[0029] 220: Outer sealing ring

[0030] 222: Sealing ring fin

[0031] 230: Surveillance image

[0032] 230a, 230b: Connecting areas

[0033] 232: Monitoring pattern fins

[0034] 232a: Fin sidewall

[0035] 232b: Fin bottom surface

[0036] 234: Contact element

[0037] 236: Virtual Polycrystalline Silicon Structure

[0038] 2361: Gate Stack

[0039] 2362: Outer surface

[0040] 238: Virtual Polycrystalline Silicon Structure

[0041] 240, 242: Arrows

[0042] 250: Epitaxial materials

[0043] 252: Gap

[0044] 260: Back-end process products

[0045] 300: Process

[0046] 302, 304, 306, 307, 308, 310: Steps

[0047] 400: Trap Region

[0048] A: Enlarged area

[0049] M1, M2, M3: Metallization layers

[0050] S: Space

[0051] SS: Section

[0052] V0, V1, V2: Through-hole layer

[0053] W: Wafer Detailed Implementation

[0054] To achieve the different features of the mentioned subject matter, the following disclosure provides many different embodiments or examples. Specific examples of components, configurations, etc., are described below to simplify this disclosure. Of course, these are merely examples and not limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself represent a relationship between the various embodiments and / or configurations discussed.

[0055] Furthermore, this document may use spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” etc., to facilitate the description of the relationship between one element or feature and another element or feature as shown in the figure. In addition to the orientations shown in the figure, spatial relative terms are intended to include different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other directions), and the spatial relative descriptive symbols used herein may be interpreted accordingly.

[0056] In general, some embodiments disclosed herein relate to semiconductor devices in which one or more fin field-effect transistors (finFETs) are used and / or formed. The name finFET derives from the fact that the channel between the source and drain regions of a field-effect transistor (FET) is typically formed as a three-dimensional (3D) vertical wall or "fin" built on and / or raised from the semiconductor wafer. Therefore, a finFET is a three-dimensional transistor. The fins serve as the transistor channel, and the gate generally contacts the top and sides of the fins. Typically, finFET devices have significantly faster switching times and higher current densities compared to planar transistor devices.

[0057] In some embodiments, the semiconductor wafer includes a device region in which one or more transistors and / or other semiconductor devices and / or similar integrated circuits (ICs) are formed. In some embodiments, the device region and / or integrated circuits suitably integrate one or more three-dimensional transistors therein, such as fin field-effect transistors. See also Figure 1 Each fin field-effect transistor 10 is a multi-gate device, wherein the metal (or other suitable material or material stack) gate 12 of the fin field-effect transistor 10 surrounds or is located above one or more silicon (or other suitable material) walls or fins 14 extending vertically from a silicon (or other suitable material) substrate 16. The fins 14 serve as selective conductive channels between the source and drain of the fin field-effect transistor 10. Figure 1 A fin field-effect transistor 10 is shown with a single fin 14 forming the source and drain channels, whereas in some designs the source and drain channels are formed by a set of parallel fins. In practice, one or more layers of oxides, high-dielectric-constant dielectrics, insulators, and / or other similar suitable materials (not labeled) are formed and / or used to separate and / or isolate the gate 12 from the substrate 16 and / or the fin 14. The fin field-effect transistor 10 is used as an example in the illustration, but generally another type of three-dimensional transistor can also be applied to the fin field-effect transistor 10, such as a gate-all-around (GAA) field-effect transistor.

[0058] In some embodiments, the sealing ring region surrounds or encompasses the device region, wherein the sealing ring region includes one or more sealing rings that surround and / or encompass the device region. For example, one or more sealing rings include a first inner sealing ring and a second outer sealing ring. In some embodiments, the inner sealing ring is adjacent to and / or closer to the device region relative to the outer sealing ring, and the outer sealing ring appropriately surrounds and / or encompasses the inner sealing ring.

[0059] In some embodiments, each sealing ring includes a plurality of fins formed in and / or on a semiconductor wafer. Suitablely, the sealing ring fins are concentric and surround or encircle a device region. In practice, transistors, electronic functional devices, and / or other similar semiconductor devices are not formed in or on the sealing rings or fins. Instead, the sealing rings protect the device region from moisture and / or other contamination, such as during subsequent wafer fabrication processes. Nevertheless, the sealing ring fins can be formed from the same or similar materials and / or during the same manufacturing process step and / or in a similar manner as the fins of the electronic functional fin field-effect transistors formed in the device region. For example, the sealing rings can be formed in a single formation step together with the fins (or other three-dimensional structures) of the fin field-effect transistor (or other three-dimensional transistor) of the integrated circuit, wherein the single formation step uses photolithography to define both the fins of the fin field-effect transistor of the integrated circuit and the rings of the sealing ring. Because the three-dimensional properties of the sealing ring correspond to the three-dimensional properties of the fins of the simultaneously formed integrated circuit fin field-effect transistor, the sealing ring rises from the semiconductor wafer to approximately the same height as the fins of the integrated circuit fin field-effect transistor. Therefore, the sealing ring forms a protective barrier preventing particles from entering the device area from the outside, which would otherwise occur during, for example, the dicing of the semiconductor wafer.

[0060] In some embodiments, a monitoring pattern is also formed on the semiconductor wafer. Suitably, the monitoring pattern is formed between an inner sealing ring and an outer sealing ring, and similarly surrounds and / or encircles a device region. In some embodiments, the monitoring pattern includes one or more fins. In practice, the monitoring pattern fins may surround and encircle or encircle the device region. The monitoring pattern fins may be formed of the same or similar materials and / or during the same manufacturing process step and / or in a similar manner compared to the fins of the electronic functional fin field-effect transistors formed in the device region. For example, the monitoring pattern may be formed together with the fins of the fin field-effect transistors of the integrated circuit in a single formation step, wherein the single formation step uses photolithography to define both the fins of the fin field-effect transistors of the integrated circuit and the sealing rings and monitoring pattern rings.

[0061] In some embodiments, one or more electronically functional fin field-effect transistors are formed in the connection region of the monitoring pattern. In some embodiments, the monitoring pattern fins in the connection region of the monitoring pattern have a longitudinal axis direction substantially the same as that of the main fins formed in the device region. Herein, the longitudinal axis direction represents the longest dimension direction corresponding to the length direction of the element or parallel to the surface of the semiconductor wafer.

[0062] Suitablely, a monitoring pattern is established by forming one or more fins surrounding and / or electronic contacts above them. In practice, the longitudinal axis of the monitoring pattern electronic contacts is substantially orthogonal to the longitudinal axis of the monitoring pattern fins at the location of the monitoring pattern electronic contacts. In this document, the longitudinal axis represents the direction corresponding to the length of the element or the longest dimension direction parallel to the surface of the semiconductor wafer. Suitablely, the longitudinal axis of the monitoring pattern electronic contacts is aligned with and / or parallel to the longitudinal axis of the gate of the fin field-effect transistor formed in the device region. In practice, the monitoring pattern electronic contacts can be formed from the same or similar materials and / or during the same manufacturing process steps and / or in a similar manner compared to the gate of the electronically functional fin field-effect transistor formed in the device region.

[0063] In some embodiments, a pair of polysilicon virtual structures (referred to herein independently as “virtual polysilicon” structures) are also formed in the monitoring pattern and on opposite sides of the monitoring pattern electronic contacts, i.e., such that the monitoring pattern electronic contacts are disposed or located between the pairs of virtual polysilicon structures. In some embodiments, the virtual polysilicon structure includes an electronically unused structure formed by a stack of gates (selectively formed together with the gates of fin field-effect transistors) on the outer surfaces of a polysilicon material having a high dielectric constant. The virtual polysilicon structures are suitably formed to surround one or more monitoring pattern fins and / or above them, in a manner substantially identical or similar to the electronically functional fin field-effect transistor gates in the device region. In some embodiments, the longitudinal axis direction of each virtual polysilicon structure of a given pair of virtual polysilicon structures is substantially parallel to the longitudinal axis direction of the monitoring pattern electronic contacts between the given pair of virtual polysilicon structures. Suitably, the longitudinal axis direction of the virtual polysilicon structure is aligned with and / or parallel to the longitudinal axis direction of the fin field-effect transistor gates formed in the device region.

[0064] Given paired dummy polysilicon structures, they generally do not provide electronic functionality in the monitoring pattern, but can be used to facilitate improved epitaxial growth of the epitaxial material on the fins of the monitoring pattern, i.e., improving the effective growth rate and / or size compared to when the dummy polysilicon structures are absent. For example, when growing epitaxial material without dummy polysilicon structures, epitaxial growth generally achieves only a single growth direction, such as growing upwards from the top of the monitoring pattern fins. In contrast, when growing epitaxial material with dummy polysilicon structures, epitaxial growth generally achieves multiple (e.g., three) growth directions, such as growing upwards from the top of the monitoring pattern fins and growing laterally inwards from either side of the fin field-effect transistor gate. This can accelerate epitaxial growth, thus producing a greater height of the deposited epitaxial material. In a non-limiting example, the epitaxial material may include a semiconductor material (e.g., germanium (Ge) or silicon (Si)), a compound semiconductor material (e.g., gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs)), or a semiconductor alloy (e.g., silicon germanium (SiGe), gallium arsenide phosphide (GaAsP)). In some embodiments, the lattice constant of the epitaxial source / drain structure may differ from the lattice constant of the monitoring pattern fins, thereby straining or applying stress to the epitaxial material to improve carrier mobility and enhance device performance.

[0065] refer to Figure 2 A top view of a semiconductor wafer W is shown according to some exemplary embodiments described herein. As shown, the wafer W includes a device region 100 and a sealing ring region 200 surrounding and / or enclosing the device region 100.

[0066] In practice, an integrated circuit comprising one or more transistors and / or other semiconductor devices and / or the like is formed in device region 100. In some embodiments, device region 100 and / or the integrated circuit formed therein appropriately integrate one or more fin field-effect transistors (or other types of three-dimensional transistors). In practice, each fin field-effect transistor is a multi-gate device, wherein the gate of the fin field-effect transistor surrounds or is on top of one or more silicon walls or fins (more generally, one or more three-dimensional structures of a three-dimensional transistor), the silicon walls or fins serving as a power-carrying path between the source and drain of the fin field-effect transistor or other type of three-dimensional transistor. For example, device region fin field-effect transistors can be essentially as follows: Figure 1 As shown, it may include a set of parallel fins instead. Figure 1 The fin field-effect transistor 10 has a single fin 14. In some embodiments, the main fins in the device region 100 have a common orientation and / or alignment in a given direction, which is referred to herein as the main fin orientation in the device region 100. However, this is not a necessary feature.

[0067] like Figure 2As shown, the sealing ring region 200 includes a first inner sealing ring 210 and a second outer sealing ring 220, both of which surround and / or enclose the device region 100. As also shown, the sealing ring region 200 includes a monitoring pattern 230 formed between the first inner sealing ring 210 and the second outer sealing ring 220. In some suitable embodiments, the gap between the first inner sealing ring 210 and the second outer sealing ring 220 may be, for example, about 1.8 μm. As shown, the inner sealing ring 210 is adjacent to and / or closer to the device region 100 than the monitoring pattern 230 and the outer sealing ring 220. Suitablely, as shown, the monitoring pattern 230 surrounds and / or encloses both the inner sealing ring 210 and the device region 100, and the outer sealing ring 220 surrounds and / or encloses the monitoring pattern 230, the inner sealing ring 210, and the device region 100. The monitoring pattern 230 shown in the figure surrounds the device area 100, but this is not necessary, and in some embodiments one or more separate monitoring patterns occupy the space between the outer sealing ring 220 and the inner sealing ring 210.

[0068] Add reference Figure 3 And as Figure 3 As shown, in some embodiments, the inner sealing ring 210 includes a plurality of sealing ring fins 212 formed in and / or on the semiconductor wafer W, and the outer sealing ring 220 similarly includes a plurality of sealing ring fins 222 formed in and / or on the semiconductor wafer W. Suitably, the respective sealing ring fins 212 and 222 of the inner sealing ring 210 and the outer sealing ring 220 are concentric and surround or enclose the device region 100. In practice, transistors, electronic functional devices, and / or other similar semiconductor devices are not formed in or on the inner sealing ring 210 and the outer sealing ring 220 or their sealing ring fins 212 and 222. Instead, the inner sealing ring 210 and the outer sealing ring 220 serve as physical barriers to protect the device region 100 from moisture and / or other contamination, for example, during subsequent wafer fabrication processes. Compared to the fins of the electronic functional fin field-effect transistor formed in device region 100, the sealing ring fins 212 and 222 can be formed from the same or similar materials and / or during the same manufacturing process steps and / or in a similar manner. For example, during the lithography process defining the fins 14 of the integrated circuit fin field-effect transistor 10, the lithography pattern can also define the inner sealing ring 210 and the outer sealing ring 220 or some sub-combinations thereof, such that the inner sealing ring 210 and the outer sealing ring 220 are formed together with the fins 14 of the integrated circuit fin field-effect transistor 10.

[0069] In some embodiments, the respective sealing ring fins 212 and 222 may form a closed loop surrounding the device region 100. In some embodiments, the respective sealing ring fins 212 and 222 are formed along a path substantially parallel to the edge of the device region 100, wherein the path is adjacent to the device region 100. That is, the device region 100 may have a first edge 110 extending in a first direction and a second edge 120 extending in a second direction, wherein the second direction is orthogonal to (and / or substantially different from) the first direction. Thus, the sealing ring fins 212 and 222 follow a path along the first edge 110 of the device region 100, and these sealing ring fins 212 and 222 follow a path along the second edge 120 of the device region 100, these sealing ring fins 212 and 222 being substantially parallel to the second edge 120. For illustrative purposes, the inner sealing ring 210 and the outer sealing ring 220 shown form a 90-degree angle. In practice, in some embodiments, these angles may be rounded or cut.

[0070] In some embodiments, the monitoring pattern 230 includes a plurality of monitoring pattern fins 232 formed in and / or on the semiconductor wafer W. Suitably, the monitoring pattern fins 232 are concentric and surround or encircle the device region 100. In practice, the monitoring pattern fins 232 may be formed from the same or similar materials and / or during the same manufacturing process steps and / or in a similar manner as the fins of the electronic functional fin field-effect transistors formed in the device region 100. For example, during the lithography process defining the fins 14 of the integrated circuit fin field-effect transistor 10, the lithography pattern may also define the monitoring pattern fins 232 or some sub-combinations thereof, such that the monitoring pattern fins 232 are formed together with the fins 14 of the integrated circuit fin field-effect transistor 10 (and possibly along the sealing ring fins 212 and 222 of the inner sealing ring 210 and the outer sealing ring 220).

[0071] In some embodiments, the individual monitoring pattern fins 232 may form a closed loop surrounding or encircling the device region 100, although this is not necessary, and in other embodiments, the fins may only partially surround the device region 100; for example, in a non-limiting exemplary example, the individual fins may have a length of 1 mm. In some embodiments, the individual monitoring pattern fins 232 are formed along a path substantially parallel to the edge of the device region 100, wherein the path is adjacent to the device region 100. For example, where the monitoring pattern fins 232 follow a path along a first edge 110 of the device region 100, these monitoring pattern fins 232 are substantially parallel to the first edge 110, and where the monitoring pattern fins 232 follow a path along a second edge 120 of the device region 100, these monitoring pattern fins 232 are substantially parallel to the second edge 120. For illustrative purposes herein, the corners of the illustrated monitoring patterns 230 are formed at 90 degrees; in practice, in some embodiments, these corners may be rounded or chamfered.

[0072] As previously described, one or more connection regions 230a are formed in the monitoring pattern 230. In some embodiments, the multiple connection regions 230a are spaced approximately between the monitoring pattern 230, for example, at an interval of approximately 1 mm. Figure 3 The connecting region 230a is displayed as an overlay of circles, and an enlarged view of the drawn connecting region 230a is shown in... Figure 3 At the lower right. Appropriately, the monitoring pattern fins 232 in the connecting area 230a of the monitoring pattern 230 have a common orientation and / or alignment with a given direction, which is substantially the same as the orientation of the main fins in the device area 100. For example... Figure 3 As shown, the monitoring pattern connection region 230a includes an electronic contact 234 that contacts the monitoring pattern fin 232 formed in the monitoring pattern 230. To facilitate such contact, epitaxial material is deposited on the monitoring pattern fin 232. In practice, the longitudinal axis of the monitoring pattern electronic contact 234 is substantially orthogonal to the longitudinal axis of the monitoring pattern fin 232 at the location of the monitoring pattern electronic contact 234. In this document, the longitudinal axis represents the longest dimension direction corresponding to the length of the element or directly parallel to the surface plane of the semiconductor wafer. Appropriately, the longitudinal axis of the monitoring pattern electronic contact 234 is aligned with and / or parallel to the longitudinal axis of the fin field-effect transistor gate formed in the device region 100.

[0073] More specifically, Figure 3 Show Figure 3The cross-sectional view of the specified section SS is shown in the top view. Section SS depicts one of the monitoring pattern fins 232, on which epitaxial material 250 is grown. Monitoring pattern electronic contacts 234 are disposed on the epitaxial material 250. Section SS further shows the proximal portion of the back end-of-line (BEOL) process product 260, including metallization layers that provide electronic paths for interconnecting fin field-effect transistors and other circuit components formed in device region 100. In integrated circuit design, the front end-of-line (FEOL) process typically refers to the formation of fin field-effect transistors and other circuit devices, while the back end-of-line process refers to the metallization stage. For complex integrated circuits, there is typically a considerable number of metallization layers (e.g., 10 or more in some integrated circuits), and vias that provide interconnections between the metallization layers and / or between devices formed during the metallization and front end processes. Intermetallic dielectrics (IMDs, not shown) provide structural support for the metallization layers and vias. In a non-limiting exemplary method, the cross section SS shown in the figure represents three metallization layers M1, M2, and M3, and three levels of vias (labeled as via layer V0, via layer V1, and via layer V2). During the front-end process, sealing ring fins 212, sealing ring fins 222, and monitoring pattern fins 232 are formed, typically simultaneously forming the fins of fin field-effect transistors (FETs). For example, the fins of the FETs, sealing ring fins 212 and 222, and monitoring pattern fins 232 of the device region 100 are simultaneously defined using photolithography patterning deposition and etching processes. The back-end process uses deposition and photolithography patterning of consecutive metallization layers M1, M2, and M3 to define the electronic paths of the integrated circuit, and photolithography patterning to form via layers V0, V1, and V2.

[0074] In particular, the contacts of the devices in the "lowest" via electrical connection device region 100 of the via layer V0, and also the monitoring pattern electronic contacts 234 in the connection region 230a of the via contact monitoring pattern 230 in the via layer V0 as shown in section SS. Although a single connection region 230a is shown, more generally one, two, three, four or more (possibly hundreds) similar connection regions may be distributed in the region between the inner sealing ring 210 and the outer sealing ring 220. The electrical connection of the connection region 230a of the monitoring pattern 230 can be used for a wide range of purposes. In one embodiment, a trap region 400 is formed during the front-end process, which electrically connects the device region 100 and the connection region 230a. In a similar embodiment, another connection region 230b (which may generally be indicated in section SS) may be similarly connected to the device region 100 by another trap region (not shown). Circuitry in device region 100 can be provided to form an electronic monitoring circuit, which includes a monitoring pattern fin 232 in the portion between the two connection regions 230a and 230b, and circuitry in device region 100 connected by the well region 400. For example, such a monitoring circuit can measure the electrical continuity of the monitoring pattern fin 232 between the two connection regions 230a and 230b, thereby detecting whether wafer dicing has caused harmful cracking or other damage across the connection regions 230a and 230b. In a non-limiting exemplary example, with a gap of approximately 1 mm between the two connection regions 230a and 230b, and such a 1 mm monitoring circuitry daisy-chaining around device region 100 in the space between the inner sealing ring 210 and the outer sealing ring 220, it may be possible to detect any breakage that causes a short circuit or open circuit across the periphery of device region 100. Furthermore, based on the monitoring circuit that detects short circuits or open circuits, such breakage locations can be located with a resolution of approximately 1 mm. (It is worth noting that the 1 mm gap in the monitoring circuit is merely a non-limiting example, and more generally, the gap can be selected based on the resistance per unit length of the monitoring pattern fin 232 and other factors). The aforementioned continuous test monitoring is merely an example, and it is understood that the monitoring pattern 230 can be used similarly to monitor a variety of other types of conditions.

[0075] Regardless of the type of monitoring circuit implemented, connection areas 230a and 230b connect the monitoring circuit to one or more metallization layers M1, M2, M3, etc., and conversely, connect the monitoring circuit to circuits within device area 100 to provide integrated circuit self-testing based on the output of the monitoring circuit. Alternatively, connection areas 230a and 230b can connect the monitoring circuit to the topmost contact pad via metallization layers M1, M2, M3, etc., where probes of an external test device can contact the topmost contact pad, allowing the test device to measure the monitoring circuit output to evaluate the integrity of the integrated circuit.

[0076] Continuing with reference to section SS, connection regions 230a and 230b, etc., should form low-resistance electronic contacts with the vias of the corresponding via layer V0, where via layer V0 connects these regions and the subsequent process product 260. For this purpose, the electronic contact 234 and the epitaxial material 250 beneath it should have sufficient thickness (or "height" in the cross-sectional view of section SS) to allow the electronic contact 234 and epitaxial material 250 to contact the via layer V0. However, the monitoring pattern fin 232 is relatively thin, and generally, the epitaxial growth direction is from the top of the monitoring pattern fin 232 upwards. This may result in a low growth rate of the epitaxial material 250, potentially leading to insufficient thickness of the epitaxial material 250 and causing high resistance between the monitoring pattern fin 232 and the connecting via of via layer V0. This phenomenon can also be referenced... Figure 6A .

[0077] As disclosed herein, the growth rate of the epitaxial material 250 can be increased by forming a pair of virtual polysilicon structures 236 and 238 on opposite sides of the monitoring pattern fin 232 where the epitaxial material 250 and electronic contact 234 will be formed. Advantageously, the virtual polysilicon structures 236 and 238 can be formed simultaneously with the polysilicon gate structure of the fin field-effect transistor in the device region 100, for example, by simultaneously defining the functional polysilicon gate structure of the fin field-effect transistor and the virtual polysilicon structures 236 and 238 using photolithography patterning deposition and etching processes. By placing the virtual polysilicon structures 236 and 238 sufficiently close to the region where the epitaxial material 250 will grow, the virtual polysilicon structures 236 and 238 disclosed herein facilitate epitaxial growth in three directions, including upward growth (as in an example where the virtual polysilicon structures 236 and 238 are absent) and inward growth from each of the two virtual polysilicon structures 236 and 238. This provides a greater thickness to the epitaxial material 250 and thus improves the electronic contact with the vias of the via layer V0.

[0078] like Figure 3 As shown, in some embodiments, a pair of virtual polysilicon structures 236 and 238 are also formed in the connection region 230a of the monitoring pattern 230 and on opposite sides of the monitoring pattern electronic contact 234, i.e., the monitoring pattern electronic contact 234 is positioned or located between the pair of virtual polysilicon structures 236 and 238. In some embodiments, the virtual polysilicon structures 236 and 238 are essentially electrically unused structures formed by a stack of gates on the outer surfaces of a polysilicon material with a high dielectric constant. Therefore, in some embodiments, the virtual polysilicon structures 236 and 238 may be at least partially formed during the formation of the gate of the fin field-effect transistor 10 in the device region 100. The virtual polysilicon structures 236 and 238 are suitably formed to surround and / or over one or more monitoring pattern fins 232 in a manner substantially identical or similar to the electronic functional gate 12 of the fin field-effect transistor 10. In some embodiments, the longitudinal direction of each virtual polysilicon structure 236 and virtual polysilicon structure 238 is substantially parallel to the longitudinal direction of the monitoring pattern electronic contact 234 disposed between the virtual polysilicon structures 236 and 238. Suitably, the longitudinal orientation of the virtual polysilicon structures 236 and 238 is aligned with and / or parallel to the longitudinal orientation of the fin field-effect transistor gate formed in the device region 100.

[0079] For the virtual polysilicon structures 236 and 238 that provide accelerated epitaxial growth rates, the space S between them should be sufficiently small so that epitaxial growth from the virtual polysilicon structures 236 and 238 can combine with epitaxial growth from the monitoring pattern fins 232. This affects the maximum value of the space S between the virtual polysilicon structures 236 and 238. For example, in some embodiments, the semiconductor device has a 16nm node and / or feature size, and the space S between the virtual polysilicon structures 236 and 238 is no greater than 0.2 micrometers, and in some embodiments, approximately 0.118 μm. In other embodiments, the semiconductor device has larger or smaller node and / or feature sizes, thus allowing for variations in the space S, and the maximum space providing an improved epitaxial growth rate can be theoretically determined for a given node size. In any case, the appropriate proximity of the space S helps ensure that the virtual polysilicon structure 236 and the virtual polysilicon structure 238 can effectively improve and / or assist the epitaxial growth between the virtual polysilicon structure 236 and the virtual polysilicon structure 238.

[0080] Now add references Figure 4This illustrates an example process 300 used in the manufacture of a semiconductor device according to some embodiments described herein. It is worth understanding that... Figure 4 The manufacturing process has been simplified, and it can be used in the manufacturing process. Figure 4 Additional steps are not shown.

[0081] As shown in the figure, in process step 302, a semiconductor wafer W is provided and appropriately prepared for subsequent processes. This may involve, for example, wafer cleaning, deposition of one or more epitaxial layers, and / or the like.

[0082] In process step 304, fins are formed in and / or on the prepared semiconductor wafer W. Suitablely, during the same process step 304, the fins of the fin field-effect transistors, sealing ring fins 212 and 222, and the monitoring pattern fins 232 in device region 100 may be virtually all formed, and process step 304 includes one or more photolithography, masking, deposition of layers and / or materials, etching, and / or other similar semiconductor structure formation sub-steps. In some embodiments, the monitoring pattern fins 232 are formed in the connection region 230a of the monitoring pattern 230, thereby having a common orientation substantially the same as the main direction of the fins formed in device region 100.

[0083] In process step 306, the gate 12 of the fin field-effect transistor 10 in device region 100 is formed, surrounding and / or over one or more pre-formed fins to define the fin field-effect transistor at a designed location, and a virtual polysilicon structure is formed at the designed location surrounding and / or over one or more pre-formed fins. Suitably, during the same process step 306, the virtual polysilicon structures 236 and 238 may be substantially entirely formed, and process step 306 includes one or more photolithography, masking, layer and / or material deposition, etching, and / or other similar semiconductor structure formation sub-steps. In some embodiments, the virtual polysilicon structures 236 and 238 are formed to have a common orientation substantially identical to the main orientation of the fin field-effect transistor gate formed in device region 100.

[0084] In process step 307, an appropriate etching or other similar material removal process is performed to selectively remove the monitoring pattern fins 232 of the portion between the virtual polysilicon structure 236 and the virtual polysilicon structure 238, thereby exposing the vertically extending lateral fin sidewalls 232a and the fin bottom surface 232b (see, for example...). Figure 5BEpitaxial material 250 can then be epitaxially grown from the fin sidewalls 232a and the fin bottom surface 232b. In some suitable embodiments, during the etching and / or material removal processes described above, the monitoring pattern fins 232 located below and / or covered by the virtual polysilicon structures 236 and 238 are protected from the etching or material removal processes and are therefore not removed. Thus, the exposed vertically extending lateral fin sidewalls 232a extend substantially to the original fin height. The exposed fin bottom surface 232b is positioned below the original fin height or set back from the original fin height, but still above the wafer substrate. Although in Figure 5B Only one side is shown in the image; it should be understood that the pair of virtual polysilicon structures 236 and 238 have a pair of exposed vertically extending transverse fin sidewalls 232a disposed at either end of the exposed fin bottom surface 232b. Therefore, as Figure 5B As shown, three epitaxial growth directions of the epitaxial material 250 can be achieved, namely, transverse inward growth from each of the two exposed and / or disposed vertically extending transverse fin sidewalls 232a (marked as arrow 242), and vertical upward growth from the top of the exposed and / or disposed fin bottom surface 232b (marked as arrow 240).

[0085] Return to reference Figure 4 In process step 308, epitaxial material is epitaxially grown on the monitoring pattern fin 232 of the monitoring pattern 230. In some embodiments, multiple epitaxial growth directions of the epitaxial material can be implemented, such as three growth directions, namely, upward from the top of the monitoring pattern fin 232 and laterally inward from each of the paired virtual polysilicon structures 236 and 238. Suitably, in some embodiments, the epitaxial material of the source and / or drain structures of the fin field-effect transistors in device region 100 and the epitaxial material grown on the monitoring pattern fin 232 of the monitoring pattern 230 can both be epitaxially grown during the same process step 308.

[0086] In process step 310, electronic contacts or contacts 234 of the monitoring pattern connection region 230a are formed, which contact the epitaxial material grown on the monitoring pattern fin 232 of the monitoring pattern 230. Because the paired virtual polysilicon structures 236 and 238 increase the epitaxial growth rate of the epitaxial material between them, the epitaxial material grows to a greater height, and the electronic contacts 234 formed in process step 310 more easily contact the epitaxial material. In some embodiments, the electronic contacts or contacts 234 of the monitoring pattern connection region 230a are formed together with the electronic contacts of the source and drain regions of the fin field-effect transistor 10 during the same process step 310.

[0087] Optionally, in some suitable embodiments, at some point after the completion of epitaxial growth step 308, one or more dummy polysilicon structures 236 and 238 may be partially or completely removed, for example by suitable etching or other material removal processes and / or steps. In some embodiments, the removed dummy polysilicon structures may be replaced by selectively subsequently depositing and / or otherwise forming a metal (or other material) gate. For example, sidewall spacers may be formed along the polysilicon material, the polysilicon material may be removed, and a metal gate material may be deposited to replace the removed polysilicon material. In fact, the dummy polysilicon structures are not replaced in this manner until the dummy polysilicon structures 236 and 238 have fulfilled their purpose (as described herein, to facilitate the epitaxial growth of the epitaxial material).

[0088] refer to Figure 5A , Figure 5B and Figure 5C The diagram illustrates the difference in effective epitaxial growth directions between the epitaxial materials with and without virtual polysilicon structures 236 and 238 in process step 308. (Special Reference) Figure 5B In some embodiments, the virtual polysilicon structure 236 (as shown, and which can be simulated to virtual polysilicon structure 238) includes a gate stack 2361 with an outer surface 2362 of a polysilicon material having a high dielectric constant. Figure 5A As shown, when the virtual polysilicon structure is absent, the epitaxial growth of the epitaxial material 250 on the monitoring pattern fin 232 of the monitoring pattern 230 generally only reaches one direction, that is, it grows upward from the top of the monitoring pattern fin 232, as shown. Figure 5A Arrow 240, representing the upward growth direction, is shown in the center. Conversely, as... Figure 5B and Figure 5CAs shown, when virtual polysilicon structures 236 and / or 238 are present, the epitaxial growth of the epitaxial material 250 can generally achieve multiple growth directions, such as upward from the top of the monitoring pattern fin 232 (as indicated by arrow 240 representing the upward growth direction) and laterally inward from the side of the virtual polysilicon structure 236 (as shown by arrow 240 representing the upward growth direction). Figure 5B (Arrow 242 represents the direction of inward growth). For the sake of simplicity and / or clarity, [the text is incomplete]. Figure 5B and Figure 5C Only one virtual polysilicon structure 236 is shown as a pair of virtual polysilicon structures 236 and 238. However, according to some embodiments, there are actually both virtual polysilicon structures 236 and 238, so source and / or drain structures can be epitaxially grown laterally from the sides of each virtual polysilicon structure 236 and 238. Figure 5C The diagram illustrates the epitaxial material 250 produced prior to process step 310, in which the electronic contact 234 begins to form. As previously described, to combine inward epitaxial growth (arrow 242) and upward epitaxial growth (arrow 240) to accelerate the overall upward epitaxial growth rate, the space S (reference) between the virtual polysilicon structure 236 and the virtual polysilicon structure 238 is [missing information]. Figure 3 The size should be small enough, for example, no more than 0.2 micrometers in some embodiments and about 0.118 μm in others.

[0089] In some embodiments, it should be understood that a plurality of monitoring pattern fins 232 may initially form the monitoring pattern 230 to have substantially uniform vertical height (e.g., Figure 1 The fins 14 shown are suitably formed in a similar manner and / or substantially simultaneously. However, as Figure 5B As shown, an etching process or other similar material removal process is performed and / or has been performed to remove selected portions of the monitoring pattern fins 232 and expose vertically extending lateral fin sidewalls 232a and fin bottom surfaces 232b, from which epitaxial material 250 can subsequently be epitaxially grown. However, specifically, during the aforementioned etching and / or material removal processes, the monitoring pattern fins 232 located below and / or covered by the virtual polysilicon structures 236 and 238 are protected from the etching or material removal processes and are therefore not removed. Thus, the exposed vertically extending lateral fin sidewalls 232a extend substantially to the original fin height, and the exposed fin bottom surfaces 232b are positioned below or recessed from the original fin height, but still relatively above the wafer substrate. Although Figure 5BOnly one side is shown in the image; it should be understood that the paired virtual polysilicon structures 236 and 238 place a pair of exposed, vertically extending transverse fin sidewalls 232a at either end of the exposed fin bottom surface 232b. Therefore, as... Figure 5B As shown, the epitaxial material 250 is realized in three epitaxial growth directions: from each of the two exposed and / or provided vertically extending transverse fin sidewalls 232a laterally inward (as shown by arrow 242), and from the top of the exposed and / or provided fin bottom surface 232b vertically upward (as shown by arrow 240).

[0090] refer to Figure 6A and Figure 6B The diagram illustrates the potential differences arising from the presence or absence of virtual polycrystalline silicon structures 236 and 238 during the growth of epitaxial material 250. For example... Figure 6A As shown, when there is no virtual polycrystalline silicon structure during the epitaxial growth of the epitaxial material 250, the epitaxial material 250 above the monitoring pattern fin 232 may face the risk of not being large enough or high enough (i.e., insufficient height), making it difficult to effectively monitor the surface. Figure 4 In process step 310, the electronic contact 234 formed achieves good electrical contact, for example, due to the absence of a virtual polysilicon structure, experiencing and / or reaching a limited epitaxial growth direction. As a result, a partial or complete gap 252 may exist between the epitaxial material 250 and the subsequently formed electronic contact 234, which will increase the resistance of the electronic contact 234 or prevent the complete fabrication of the electronic contact. Conversely, as... Figure 6B As shown, when virtual polysilicon structures 236 and / or 238 are present during the epitaxial growth of the epitaxial material 250, the epitaxial material 250 above the monitoring pattern fin 232 can be grown more easily, quickly, efficiently, and / or readily and effectively to be large enough or tall enough (i.e., to reach a sufficient height), in order to... Figure 4 The electronic contact 234 formed in process step 310 effectively forms a good contact. Due to the presence of virtual polysilicon structures 236 and 238, it undergoes and / or reaches multiple epitaxial growth directions (arrows 240, 242, see reference). Figure 5B This allows for a more efficient epitaxial growth rate. Therefore, the epitaxial material 250 will not form effective and / or partial electronic open circuits with the electronic contacts 234 formed in process step 310 due to insufficient epitaxial growth.

[0091] refer to Figure 7 A partial top view of a semiconductor device is shown according to some other embodiments. Figure 7As shown, a well region 400 is formed in the semiconductor wafer W. The well region 400 provides electronic connection and / or communication between the selected circuitry formed in the connection region 230a of the monitoring pattern 230 and the connection region 100a of the device region 100. The well region 400 may substantially include a quantum well or potential well and / or one or more quantum wires or the like.

[0092] In some embodiments, one or more fins 102 and one or more electrical contacts 104 are formed in the connection region 100a of the device region 100. For example, the device region fin field-effect transistor can be essentially as follows: Figure 1 As shown in the diagram. Appropriately, the device region fins 102 in the connecting region 100a of the device region 100 have a common orientation and / or alignment substantially the same as the orientation of the main fins in the device region 100. Furthermore, the device region fins 102 in the connecting region 100a of the device region 100 and the monitoring pattern fins 232 in the connecting region 230a of the monitoring pattern 230 may have substantially the same or substantially the same orientation and / or be aligned with each other; that is, they have substantially parallel orientations.

[0093] In some embodiments, one or more electronic contacts 104 are formed in the connection region 100a of the device region 100. As shown, according to some embodiments, the device region electronic contacts 104 have a longitudinal axis direction substantially orthogonal to the longitudinal axis direction of the device region fins 102 at the location of the device region electronic contacts 104. In this document, the longitudinal axis direction represents the direction corresponding to the length of the element or the direction of the longest dimension. Suitably, the longitudinal axis direction of the device region electronic contacts 104 is aligned with and / or substantially parallel to the longitudinal axis direction of the electronic contacts 234 formed in the connection region 230a of the monitoring pattern 230. In practice, the device region electronic contacts 104 and the monitoring pattern electronic contacts 234 may be formed from the same or similar materials and / or during the same manufacturing process steps and / or in a similar manner.

[0094] like Figure 7 As shown, a pair of virtual polysilicon structures 106 and 108 are also formed in the connection region 100a of the device region 100 and on opposite sides of the device region electronic contact 104, i.e., such that the device region electronic contact 104 is disposed or located between the pair of virtual polysilicon structures 106 and 108. These operations increase the growth rate of the epitaxial material epitaxially grown on the device region fin 102, thereby increasing the height of the epitaxial material and promoting good electrical contact with the subsequently formed electronic contact 104, in a manner similar to the epitaxial material 250 in the described monitoring pattern example (e.g., reference). Figure 5B and Figure 5CIn some embodiments, virtual polysilicon structures 106 and 108 are again essentially electrically unused structures, formed by a stack of gates on the outer surfaces of a polysilicon material having a high dielectric constant. Virtual polysilicon structures 106 and 108 are suitably formed to surround and / or over one or more device region fins 102, wherein the device region fins 102 are substantially identical or similar to the gates 12 of the electronic functional device region fin field-effect transistors 10 of the device region 100. In some embodiments, the longitudinal axis direction of each virtual polysilicon structure 106 and 108 is substantially parallel to the longitudinal axis direction of the device region electronic contacts 104 between the paired virtual polysilicon structures 106 and 108. Suitably, the longitudinal axis orientation of virtual polysilicon structures 106 and 108 is aligned with and / or substantially parallel to the longitudinal axis orientation of virtual polysilicon structures 236 and 238.

[0095] In some embodiments, such as when the semiconductor device has a 16nm node and / or feature size, the space between the virtual polysilicon structure 106 and the virtual polysilicon structure 108 is no greater than 0.2 micrometers, and in some embodiments about 0.118 μm. In other embodiments, the space can therefore vary when the semiconductor device has a larger or smaller node and / or feature size. In any case, a suitable proximity of space helps ensure that the virtual polysilicon structure 106 and the virtual polysilicon structure 108 can effectively improve and / or assist the epitaxial growth of material on the fin 102 between the virtual polysilicon structures 236 and 238 in the connection region 100a of the device region 100.

[0096] In some embodiments, the monitoring pattern connection region 230a of the monitoring pattern 230 is electrically connected to and / or otherwise communicates with the device region connection region 100a of the device region 100 via the well region 400. Therefore, by appropriate probing of the connection region 230a in the monitoring pattern 230, selected circuitry within the device region 100 can be read (e.g., via the connection region 100a of the device region 100). In this manner, suitable process monitoring, testing, and / or analysis (e.g., based on the selected circuitry) can be performed on the semiconductor wafer W and / or the integrated circuit formed in the device and / or device region 100, without direct probing of the device region 100.

[0097] It is understood that, in some embodiments, the monitoring pattern 230 disclosed herein can be used to perform circuit or contact probe (CP) testing (e.g., on a wafer pedestal) and / or final testing (FT) (e.g., on a die pedestal). Contact probe testing is performed using wafer probes, and may include, for example, applying an input signal through the probes and measuring feedback through the same or different probes. Final testing is performed after wafer dicing to separate the individually diced wafers, and the wafer, serving as a device-under-test (DUT), is placed on a probing machine and probes for electrical contact with selected contact pads (or metal bumps, solder balls, or the like). One benefit or advantage achieved by some embodiments disclosed herein is, for example, the ability to detect die-level defects that may occur during die dicing or packaging of components, where die dicing or packaging may result in die breakage or delamination. Even though this type of failure rate may be relatively low, it can still manifest as a non-insignificant defect (e.g., defective parts per million, dppm), which is undesirable for quality considerations. Furthermore, the multiple intervals between the connecting regions 230a and 230b in the monitoring pattern 230 disclosed herein allow for continuous testing of a relatively large coverage area and / or relatively high resolution, for example, compared to conventional contact detection functional tests such as scan / chain. In particular, this improved resolution allows for the detection and / or localization of relatively small defects.

[0098] In some suitable embodiments, a comparator or other similar test circuit can be formed in the integrated circuit or device region 100 and connected to electronic contacts. Thus, in practice, defect detection in the monitoring pattern 230, for example via the trap region 400, can be achieved by electrically connecting connection regions 230a and 230b to the comparator or test circuit in device region 100. The comparator and / or test circuit in device region 100 can then be used to detect defects and / or interruptions in the continuity of the monitoring pattern 230 between the connected connection regions 230a and 230b. And, for example, the comparator and / or test circuit in device region 100 can be used to amplify the received signal and / or compare the received signal with a reference voltage or reference resistor.

[0099] The following describes some other non-limiting exemplary embodiments.

[0100] In some embodiments disclosed herein, a method for manufacturing an integrated circuit is described. The method includes forming one or more device region fin field-effect transistors (FFETs) in a device region of a semiconductor wafer, each FFET including one or more device region fins formed rising from the semiconductor wafer and a device region gate formed surrounding the one or more device region fins. The method includes forming an inner sealing ring surrounding the device region and an outer sealing ring surrounding both the inner sealing ring and the device region in a sealing ring region surrounding the semiconductor wafer. The method includes forming a monitoring pattern disposed between the inner and outer sealing rings in the sealing ring region, the monitoring pattern including one or more monitoring pattern fins formed rising from the semiconductor wafer. The method includes forming a first virtual polysilicon structure and a second virtual polysilicon structure in a connection region of the monitoring pattern, each of the first and second virtual polysilicon structures formed surrounding the one or more monitoring pattern fins. The method includes epitaxially growing an epitaxial material on the one or more monitoring pattern fins between the first and second virtual polysilicon structures. The method includes forming electronic contacts of an electrically conductive epitaxial material between a first virtual polysilicon structure and a second virtual polysilicon structure. In some embodiments, forming the first and second virtual polysilicon structures and forming the device region gate of a device region fin field-effect transistor are performed in the same process step. In some embodiments, the method further includes removing a portion of at least one monitoring pattern fin between the first and second virtual polysilicon structures, thereby setting a first fin surface that is recessed from the height of the monitoring pattern fin remaining below the first and second virtual polysilicon structures, and thereby exposing a pair of fin sidewalls that extend from the first fin surface to the height of the monitoring pattern fin remaining below the first and second virtual polysilicon structures. During the epitaxial growth step, the epitaxial material is epitaxially grown in a plurality of growth directions, including a first direction upward from the first fin surface, and a second and a third direction laterally inward from the pair of fin sidewalls. In some embodiments, the epitaxial material is epitaxially grown in multiple growth directions, including a first direction upward from the top of the monitoring pattern fins, and a second and a third direction laterally inward from the first and second virtual polysilicon structures, respectively. In some embodiments, the space between the first and second virtual polysilicon structures is no greater than 0.2 micrometers. In some embodiments, the monitoring pattern fins in the connection region are aligned parallel to the fins in the device region. In some embodiments, the formed electronic contacts, as well as the first and second virtual polysilicon structures, are orthogonal to the monitoring pattern fins in the connection region. In some embodiments, the electronic contacts, as well as the first and second virtual polysilicon structures, are aligned parallel to the gate of the device region.In some embodiments, the method further includes forming a well region in a semiconductor wafer, the well region providing an electrical connection between a connection region in a monitoring pattern and circuitry formed in a device region. In some embodiments, device region fins and monitoring pattern fins are formed in a single forming step.

[0101] In some embodiments disclosed herein, an integrated circuit includes a device region comprising at least one device region three-dimensional transistor, the device region three-dimensional transistor comprising one or more three-dimensional structures and a device region gate contacting one or more three-dimensional structures. The integrated circuit includes a sealing ring region surrounding the device region, the sealing ring region comprising at least one sealing ring. The integrated circuit includes a monitoring pattern disposed in the sealing ring region. The at least one sealing ring comprises a set of sealing ring three-dimensional structures. The monitoring pattern comprises a set of monitoring pattern three-dimensional structures and a connection region, wherein the connection region comprises a first polysilicon structure and a second polysilicon structure surrounding the set of monitoring pattern three-dimensional structures and an electronic contact disposed between the first polysilicon structure and the second polysilicon structure. In some embodiments, the respective monitoring pattern three-dimensional structures or the set of monitoring pattern three-dimensional structures form a closed loop surrounding the device region. In some embodiments, the integrated circuit may further include an epitaxial material between the electronic contact and the set of monitoring pattern three-dimensional structures. In some embodiments, the epitaxial material contacts all of the aforementioned elements: the first polysilicon structure, the second polysilicon structure, the monitoring pattern three-dimensional structures, and the electronic contact. In some embodiments, the at least one device region three-dimensional transistor is a fin field-effect transistor, and the three-dimensional structure is a fin. In some embodiments, at least one sealing ring includes a first inner sealing ring and a second outer sealing ring, and a monitoring pattern is disposed between the first inner sealing ring and the second outer sealing ring. In some embodiments, the integrated circuit further includes a well, the well providing an electrical connection between a connection area of ​​the monitoring pattern and a circuit disposed in the device region.

[0102] In some embodiments disclosed herein, a method of manufacturing an integrated circuit includes forming fins of a fin field-effect transistor of the integrated circuit in a device region of a semiconductor wafer. The method includes forming at least one sealing ring including a sealing ring fin surrounding the device region and a monitoring pattern including a monitoring pattern fin surrounding the device region in a sealing ring region surrounding the device region. The method includes forming the gate of the fin field-effect transistor of the integrated circuit in the device region. The method includes forming a polysilicon structure on a monitoring pattern fin in a connection region of the monitoring pattern. The method includes epitaxially growing an epitaxial material on a monitoring pattern fin between polysilicon structures. The method includes forming at least one electronic contact of the epitaxial material for electrical contact. In some embodiments, the method further includes removing a portion of the monitoring pattern fin formed in the monitoring pattern between two adjacent polysilicon structures, thereby setting a first fin surface between the two adjacent polysilicon structures for each monitoring pattern fin, the first fin surface being recessed from the height of the monitoring pattern fin remaining below the two adjacent polysilicon structures, and exposing a pair of fin sidewalls extending from the first fin surface to the height of the monitoring pattern fin remaining below the two adjacent polysilicon structures. In some embodiments, epitaxial material is grown on monitoring pattern fins of a monitoring pattern between polysilicon structures through a combination of upward epitaxial growth from the fin and inward epitaxial growth from the polysilicon structure. In some embodiments, the fins of the fin field-effect transistor, the sealing ring fins of at least one sealing ring, and the monitoring pattern fins of the monitoring pattern are formed simultaneously. In some embodiments, the gate of the fin field-effect transistor and the polysilicon structure are formed simultaneously.

[0103] The foregoing outlines features of some embodiments to enable those skilled in the art to better understand the ideas presented in this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A method for manufacturing an integrated circuit, characterized in that, include: One or more device region fin field-effect transistors are formed in a device region of a semiconductor wafer, each device region fin field-effect transistor including one or more device region fins formed and raised from the semiconductor wafer and a device region gate formed and surrounding one or more of the device region fins. An inner sealing ring is formed around the device region and an outer sealing ring is formed around both the inner sealing ring and the device region in a sealing ring region of the semiconductor wafer surrounding the device region. A monitoring pattern is formed in the sealing ring region between the inner sealing ring and the outer sealing ring, the monitoring pattern including one or more monitoring pattern fins formed and raised from the semiconductor wafer; A first virtual polysilicon structure and a second virtual polysilicon structure are formed in a connecting region of the monitoring pattern, and each of the first virtual polysilicon structure and the second virtual polysilicon structure is formed to surround one or more of the monitoring pattern fins; Epitaxial growth of an epitaxial material on the monitoring pattern fins between the first virtual polysilicon structure and the second virtual polysilicon structure; and An electronic contact is formed between the first virtual polysilicon structure and the second virtual polysilicon structure to form an electrical contact with the epitaxial material.

2. The method as described in claim 1, characterized in that, The formation of the first virtual polysilicon structure and the second virtual polysilicon structure, as well as the formation of the device region gate of the device region fin field-effect transistor, are performed in the same steps.

3. The method as described in claim 1, characterized in that, Further includes: At least a portion of one of the monitoring pattern fins between the first virtual polysilicon structure and the second virtual polysilicon structure is removed to form a first fin surface that is recessed from a height of the monitoring pattern fins remaining below the first virtual polysilicon structure and the second virtual polysilicon structure, thereby exposing a pair of fin sidewalls that extend from the first fin surface to the height of the monitoring pattern fins remaining below the first virtual polysilicon structure and the second virtual polysilicon structure; During the epitaxial growth step, the epitaxial material grows in multiple growth directions, including a first direction upward from the surface of the first fin, a second direction and a third direction laterally inward from the sidewall of the pair of fins.

4. The method as described in claim 1, characterized in that, The space between the first virtual polysilicon structure and the second virtual polysilicon structure is no greater than 0.2 micrometers.

5. The method as described in claim 1, characterized in that, The monitoring pattern fins in the connection area are aligned parallel to the device area fins.

6. The method as described in claim 1, characterized in that, The formed electronic contact, as well as the first virtual polysilicon structure and the second virtual polysilicon structure, are orthogonal to the monitoring pattern fins in the connection region.

7. The method as described in claim 1, characterized in that, The electronic contact, as well as the first and second virtual polysilicon structures, are aligned parallel to the gate of the device regions.

8. The method as described in claim 1, characterized in that, Further includes: A well region is formed in the semiconductor wafer, which provides an electrical connection between the connection region in the monitoring pattern and the circuitry formed in the device region.

9. The method as described in claim 1, characterized in that, The device area fins and the monitoring pattern fins are formed in a single forming step.

10. An integrated circuit, characterized in that, include: A device region including at least one device region three-dimensional transistor, the device region three-dimensional transistor including one or more three-dimensional structures and a device region gate contacting the three-dimensional structures; A sealing ring region surrounding the device region, the sealing ring region including a first inner sealing ring and a second outer sealing ring; and A monitoring pattern is positioned between the first inner sealing ring and the second outer sealing ring; The first inner sealing ring and the second outer sealing ring each include a set of three-dimensional sealing ring structures; and The monitoring pattern includes a set of three-dimensional monitoring pattern structures and a connecting area. The connecting area includes a first polysilicon structure and a second polysilicon structure surrounding the set of three-dimensional monitoring pattern structures, and an electronic contact disposed between the first polysilicon structure and the second polysilicon structure.

11. The integrated circuit as claimed in claim 10, characterized in that, The three-dimensional structure of the monitoring pattern forms a closed loop around the area of ​​the device.

12. The integrated circuit as claimed in claim 10, characterized in that, It further includes an epitaxial material between the electronic contact and the three-dimensional structure of the monitoring pattern.

13. The integrated circuit as claimed in claim 12, characterized in that, The epitaxial material contacts all of the aforementioned components, including the first polycrystalline silicon structure, the second polycrystalline silicon structure, the three-dimensional structure of the monitoring pattern, and the electronic contact.

14. The integrated circuit as claimed in claim 10, characterized in that, The at least one device region three-dimensional transistor is a fin field-effect transistor, and the three-dimensional structure is a plurality of fins.

15. The integrated circuit as claimed in claim 14, characterized in that, The three-dimensional structure of the monitoring pattern in the connected area is aligned parallel to the fins.

16. The integrated circuit as claimed in claim 10, characterized in that, Further includes: A trap provides an electrical connection between the connection area of ​​the monitoring pattern and the circuitry disposed in the device area.

17. A method for manufacturing an integrated circuit, characterized in that, include: Multiple fins of a multi-fin field-effect transistor are formed in a device region of a semiconductor wafer to form an integrated circuit; A first inner sealing ring and a second outer sealing ring, comprising multiple sealing ring fins surrounding the device area, and a monitoring pattern comprising multiple monitoring pattern fins surrounding the device area are formed in a sealing ring area, wherein the monitoring pattern is disposed between the first inner sealing ring and the second outer sealing ring. Multiple gates of the fin field-effect transistors of the integrated circuit are formed in this device region; Multiple polysilicon structures are formed on the monitoring pattern fins of the monitoring pattern in a connecting region of the monitoring pattern, wherein the polysilicon structures surround the monitoring pattern fins; Epitaxial growth of an epitaxial material on the monitoring pattern fins between the polycrystalline silicon structures; and At least one electronic contact is formed to electrically contact the epitaxial material.

18. The method of manufacturing an integrated circuit as described in claim 17, characterized in that, Further includes: A portion of the fins formed in the monitoring pattern is removed between adjacent pairs of the polysilicon structures, thereby providing a first fin surface between adjacent pairs of the polysilicon structures for each fin. The first fin surface is recessed from a height of the fins remaining below the adjacent pairs of the polysilicon structures, and exposes a pair of fin sidewalls that extend from the first fin surface to the height of the fins remaining below the adjacent pairs of the polysilicon structures. The epitaxial material is grown on the fins of the monitoring pattern between the polycrystalline silicon structures through a combination of epitaxial growth upward from the surface of the first fin and epitaxial growth laterally inward from the sidewalls of the pair of fins.

19. The method of manufacturing an integrated circuit as described in claim 17, characterized in that, Simultaneously forming the fins of the fin field-effect transistors, the fins of the first inner sealing ring and the second outer sealing ring, and the fins of the monitoring pattern.

20. The method of manufacturing an integrated circuit as described in claim 17, characterized in that, Simultaneously forming the gates of these fin field-effect transistors and these polysilicon structures.

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