Semiconductor devices and methods

Abstract

An embodiment includes a device having: a first set of nanostructures located on a substrate, the first set of nanostructures including a first channel region; a second set of nanostructures located on the substrate, the second set of nanostructures including a second channel region; a gate dielectric layer surrounding each of the first and second sets of nanostructures; a first work function adjustment layer located on the gate dielectric layer of the first set of nanostructures, the first work function adjustment layer surrounding each of the first set of nanostructures; a adhesive layer located on the first work function adjustment layer, the adhesive layer surrounding each of the first set of nanostructures; a second work function adjustment layer located on the adhesive layer of the first set of nanostructures and on the gate dielectric layer of the second set of nanostructures; and a filler layer located on the second work function adjustment layer. Embodiments of this application relate to semiconductor devices and methods.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor devices and methods. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by the following steps: depositing an insulating or dielectric layer, a conductive layer, and a semiconductor material layer sequentially over a semiconductor substrate; and using photolithography to pattern the multiple material layers to form circuit components and elements on the multiple material layers.

[0003] The semiconductor industry continuously improves the integration density of individual electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the size of the smallest component, which allows more components to be integrated into a given area. However, as the size of the smallest component decreases, other problems arise that need to be addressed. Summary of the Invention

[0004] The embodiment includes a device having a first set of nanostructures on a substrate, the first set of nanostructures including a first channel region. The device also includes a second set of nanostructures on the substrate, the second set of nanostructures including a second channel region. The device further includes a gate dielectric layer surrounding each of the first and second sets of nanostructures. The device also includes a first work function adjustment layer on the gate dielectric layer of the first set of nanostructures, the first work function adjustment layer surrounding each of the first set of nanostructures, the first work function adjustment layer including an n-type work function metal. The device also includes a adhesive layer on the first work function adjustment layer, the adhesive layer surrounding each of the first set of nanostructures. The device further includes a second work function adjustment layer on the adhesive layer of the first set of nanostructures and on the gate dielectric layer of the second set of nanostructures, the second work function adjustment layer including a p-type work function metal, the p-type work function metal being different from the n-type work function metal. The device also includes a fill layer on the second work function adjustment layer.

[0005] The embodiment includes a method comprising forming a first set of nanostructures and a second set of nanostructures on a substrate, the first set of nanostructures including a first channel region and the second set of nanostructures including a second channel region. The method further includes forming a gate dielectric layer having a first portion and a second portion, the first portion being deposited on the first channel region and the second portion being deposited on the second channel region. The method further includes forming a first work function adjustment layer on the first portion and the second portion of the gate dielectric layer. The method further includes forming a binder layer on the first work function adjustment layer. The method further includes removing the binder layer and the first work function adjustment layer from the second portion of the gate dielectric layer. The method further includes forming a second work function adjustment layer on the remaining binder layer and the second portion of the gate dielectric layer. The method further includes forming a filler layer on the second work function adjustment layer.

[0006] The embodiment includes a method comprising forming a first set of nanostructures and a second set of nanostructures on a substrate, the first set of nanostructures including a first channel region and the second set of nanostructures including a second channel region. The method further includes forming a first gate dielectric layer on the first channel region. The method further includes forming a second gate dielectric layer on the second channel region. The method further includes forming a sacrificial layer between the second set of nanostructures. The method further includes forming an n-type work function adjustment layer on the first gate dielectric layer, the second gate dielectric layer, and the sacrificial layer, the n-type work function adjustment layer surrounding each of the first set of nanostructures. The method further includes forming a binder layer on the n-type work function adjustment layer, the binder layer surrounding each of the first set of nanostructures. The method further includes removing the binder layer, the n-type work function adjustment layer, and the sacrificial layer from the second gate dielectric layer. The method further includes forming a p-type work function adjustment layer on the binder layer and the second gate dielectric layer of the first set of nanostructures. The method further includes forming a filler layer on the p-type work function adjustment layer. Attached Figure Description

[0007] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components can be arbitrarily increased or decreased.

[0008] Figure 1 An example of a nanostructured field-effect transistor (nanoFET) according to some embodiments is shown in a three-dimensional view.

[0009] Figures 2 to 27B This is a view of an intermediate stage in the fabrication of a nanoFET according to some embodiments.

[0010] Figure 28 This is a flowchart of an example method for forming an alternative gate for a nanoFET according to some embodiments. Detailed Implementation

[0011] The following disclosure provides various embodiments or examples to achieve different features of the invention. Specific examples of components and arrangements will be described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is merely for brevity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0012] Furthermore, for ease of description, spatial relation terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spatial relation terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relation descriptors used herein can be interpreted accordingly.

[0013] According to various embodiments, alternative gate electrodes are formed for p-type and n-type devices. In some embodiments, the work function adjustment layer of the n-type device is formed before the work function adjustment layer of the p-type device to allow for greater control over the threshold voltage of the resulting device. A method of forming the work function adjustment layer of the n-type device before the work function adjustment layer of the p-type device includes forming and patterning a sacrificial layer to prevent the work function adjustment layer of the n-type device from forming between the nanostructures of the p-type device. This helps prevent the work function adjustment layer from remaining on the p-type device, which would degrade the performance of the p-type device. In some embodiments, a protective layer is formed between the work function adjustment layer and the adhesive layer to suppress (e.g., substantially prevent or at least reduce) the diffusion of the work function adjustment layer. Therefore, the threshold voltage of the resulting device can be tuned more precisely.

[0014] The embodiments are described in a specific context, including dies for nanoFETs. However, various embodiments can be applied to dies that include other types of transistors (e.g., fin field-effect transistors (FinFETs), planar transistors, etc.) that replace or are combined with nanoFETs.

[0015] Figure 1 Examples of nanoFETs (e.g., nanowire FETs, nanosheet FETs, etc.) according to some embodiments are shown. Figure 1This is a 3D view, in which some components of the nanoFET are omitted for clarity. A nanoFET can be a nanosheet field-effect transistor (NSFET), a nanowire field-effect transistor (NWFET), a gate-all-around field-effect transistor (GAAFET), etc.

[0016] The nanoFET includes a nanostructure 66 (e.g., nanosheet, nanowire, etc.) above a fin 62 on a substrate 50 (e.g., a semiconductor substrate), wherein the nanostructure 66 serves as a channel region for the nanoFET. The nanostructure 66 may include p-type nanostructures, n-type nanostructures, or combinations thereof. Isolation regions 70 (such as shallow trench isolation (STI) regions) are disposed between adjacent fins 62, which may protrude above and between adjacent isolation regions 70. Although the isolation regions 70 are described / shown as separate from the substrate 50, as used herein, the term "substrate" may refer to a single semiconductor substrate or a combination of a semiconductor substrate and an isolation region. Furthermore, although the bottom of the fin 62 is shown as being a single, continuous material with respect to the substrate 50, the bottom of the fin 62 and / or the substrate 50 may include a single material or multiple materials. In this document, fin 62 refers to the portion extending above and between adjacent isolation regions 70.

[0017] A gate dielectric 122 is located above the top surface of fin 62 and along the top, sidewalls, and bottom surface of nanostructure 66. A gate electrode 124 is located above the gate dielectric 122. Epitaxial source / drain regions 98 are disposed on fin 62 on opposite sides of the gate dielectric 122 and the gate electrode 124. Epitaxial source / drain regions 98 can be shared between the various fins 62. For example, adjacent epitaxial source / drain regions 98 can be electrically connected, such as by coalescing epitaxially grown epitaxial source / drain regions 98 or by coupling epitaxial source / drain regions 98 to the same source / drain contact.

[0018] Figure 1 Reference cross sections used in subsequent figures are also shown. Cross section A-A' is along the longitudinal axis of the gate electrode 124 and in a direction, for example, perpendicular to the current direction between the epitaxial source / drain regions 98 of the nanoFET. Cross section B-B' is along the longitudinal axis of the fin 62 and in the direction of the current, for example, between the epitaxial source / drain regions 98 of the nanoFET. Cross section C-C' is parallel to cross section A-A' and extends through the epitaxial source / drain regions 98 of the nanoFET. For clarity, the subsequent figures refer to these reference cross sections.

[0019] Some embodiments discussed herein are presented in the context of nanoFETs formed using a post-gate process. In other embodiments, a pre-gate process may be used. Furthermore, some embodiments are contemplated for use in planar devices such as planar FETs or fin field-effect transistors (FinFETs). For example, a FinFET may include fins located on a substrate, where the fins serve as the channel region of the FinFET. Similarly, a planar FET may include a substrate, where a portion of the substrate serves as the channel region of the planar FET.

[0020] Figures 2 to 27B This is a view of an intermediate stage in the fabrication of a nanoFET according to some embodiments. Figure 2 , Figure 3 , Figure 4 , Figure 5 and Figure 6 It is shown that... Figure 1 A similar three-dimensional view. Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 18A , Figure 18B , Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figure 21A , Figure 21B , Figure 22A , Figure 22B , Figure 23A , Figure 23B , Figure 24A , Figure 24B , Figure 25A , Figure 26A and Figure 27A Show Figure 1 The reference section A-A' shown is shown, but two fins are depicted. Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 25B , Figure 26B and Figure 27B Show Figure 1 The reference section B-B' is shown in the figure. Figure 9C and Figure 9D Show Figure 1 The reference section C-C' shown is shown, but two fins are depicted.

[0021] exist Figure 2 The image shows a substrate 50 for forming a nano-FET. The substrate 50 can be a doped (e.g., doped with p-type or n-type impurities) or undoped semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc. The substrate 50 can be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. For example, the insulating layer can be a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is provided on a substrate that is typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, can also be used. In some embodiments, the semiconductor material of the substrate 50 can include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, potassium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or combinations thereof; etc.

[0022] Substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device, such as an NMOS transistor, for example, an n-type nanoFET, while the p-type region 50P can be used to form a p-type device, such as a PMOS transistor, for example, a p-type nanoFET. The n-type region 50N can be physically separated from the p-type region 50P (not shown separately), and any number of device components (e.g., other active devices, doped regions, isolation structures, etc.) can be disposed between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are shown, any number of n-type regions 50N and p-type regions 50P can be provided.

[0023] The substrate 50 may be lightly doped with p-type or n-type impurities. Back-through (APT) implantation may be performed on the upper portion of the substrate 50 to form an APT region. During APT implantation, impurities may be implanted into the substrate 50. The impurities may have a conductivity type opposite to that of the source / drain regions subsequently formed in each of the n-type region 50N and p-type region 50P. The APT region may extend below the source / drain regions in the nanoFET. The APT region can be used to reduce leakage from the source / drain regions to the substrate 50. In some embodiments, the doping concentration in the APT region may be 10... 18 cm -3 Up to 10 19 cm -3 Within the range.

[0024] A multilayer stack 52 is formed over a substrate 50. The multilayer stack 52 includes alternating first semiconductor layers 54 and second semiconductor layers 56. The first semiconductor layers 54 are formed of a first semiconductor material, and the second semiconductor layers 52 are formed of a second semiconductor material. The semiconductor materials may be selected from candidate semiconductor materials of the substrate 50. In the illustrated embodiment, the multilayer stack 52 includes three layers of each of the first semiconductor layers 54 and the second semiconductor layers 56. It should be understood that the multilayer stack 52 may include any number of first semiconductor layers 54 and second semiconductor layers 56.

[0025] In the illustrated embodiment, and as will be described in more detail later, the first semiconductor layer 54 is removed and the second semiconductor layer 56 is patterned to form the channel region of the nanoFET in both the n-type region 50N and the p-type region 50P. The first semiconductor layer 54 is a sacrificial layer (or dummy layer) that is removed in a subsequent process to expose the top and bottom surfaces of the second semiconductor layer 56. The first semiconductor material of the first semiconductor layer 54 is a material having high etch selectivity for etching the second semiconductor layer 56, such as silicon germanium. The second semiconductor material of the second semiconductor layer 56 is a material suitable for both n-type and p-type devices, such as silicon.

[0026] In another embodiment (not shown separately), the first semiconductor layer 54 will be patterned to form the channel region of the nanoFET in one region (e.g., p-type region 50P), and the second semiconductor layer 56 will be patterned to form the channel region of the nanoFET in another region (e.g., n-type region 50N). The first semiconductor material of the first semiconductor layer 54 may be a material suitable for p-type devices, such as silicon germanium (e.g., Si). x Ge 1-x The first semiconductor material 56 can be a material suitable for n-type devices, such as silicon, silicon carbide, III-V compound semiconductors, II-VI compound semiconductors, etc. The second semiconductor material 56 can have high etch selectivity relative to each other, allowing the first semiconductor layer 54 to be removed without removing the second semiconductor layer 56 in the n-type region 50N, and the second semiconductor layer 56 to be removed without removing the first semiconductor layer 54 in the p-type region 50P.

[0027] Each layer of the multilayer stack 52 can be grown using processes such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), and deposited using processes such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). Each layer can have a small thickness, such as in the range of 5 nm to 30 nm. In some embodiments, some layers (e.g., the second semiconductor layer 56) are formed to be thinner than other layers (e.g., the first semiconductor layer 54). For example, in an embodiment where the first semiconductor layer 54 is a sacrificial layer (or dummy layer) and the second semiconductor layer 56 is patterned to form the channel region of the nanoFET in both the n-type region 50N and the p-type region 50P, the first semiconductor layer 54 can have a first thickness T1, and the second semiconductor layer 56 can have a second thickness T2, which is 30% to 60% smaller than the first thickness T1. Forming the second semiconductor layer 56 to a smaller thickness allows the channel region to be formed at a greater density.

[0028] exist Figure 3 In this process, trenches are patterned in substrate 50 and multilayer stack 52 to form fins 62, a first nanostructure 64, and a second nanostructure 66. Fin 62 is a semiconductor strip patterned in substrate 50. The first nanostructure 64 and the second nanostructure 66 respectively comprise the remainders of the first semiconductor layer 54 and the second semiconductor layer 56. The trenches can be patterned using any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. The etching can be anisotropic.

[0029] Fins 62 and nanostructures 64, 66 can be patterned using any suitable method. For example, one or more photolithography processes can be used to pattern fins 66 and nanostructures 64, 66, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, thereby allowing the creation of patterns with, for example, a spacing smaller than that achievable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used as a mask to pattern fins 62 and nanostructures 64, 66. In some embodiments, a mask (or other layer) may be retained on nanostructures 64, 66.

[0030] Fins 62 and nanostructures 64, 66 may each have a width ranging from 8 nm to 40 nm. In the illustrated embodiment, fins 62 and nanostructures 64, 66 have substantially equal widths in the n-type region 50N and the p-type region 50P. In another embodiment, fins 62 and nanostructures 64, 66 in one region (e.g., n-type region 50N) are wider or narrower than those in another region (e.g., p-type region 50P).

[0031] exist Figure 4 In this embodiment, an STI region 70 is formed above the substrate 50 and between adjacent fins 62. The STI region 70 is disposed around at least a portion of the fins 62 such that at least a portion of the nanostructures 64, 66 protrudes between adjacent STI regions 70. In the illustrated embodiment, the top surface of the STI region 70 is coplanar with the top surface of the fin 62 (within the range of process variations). In some embodiments, the top surface of the STI region 70 is higher or lower than the top surface of the fin 62. The STI region 70 separates components of adjacent devices.

[0032] The STI region 70 can be formed by any suitable method. For example, an insulating material can be formed over the substrate 50 and the nanostructures 64, 66 and between adjacent fins 62. The insulating material can be an oxide such as silicon oxide, a nitride such as silicon nitride, or a combination thereof, which can be formed by a chemical vapor deposition (CVD) process, such as high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), or a combination thereof. Other insulating materials formed by any acceptable process can be used. In some embodiments, the insulating material is silicon oxide formed by FCVD. Once the insulating material is formed, an annealing process is performed. In embodiments, the insulating material is formed such that excess insulating material covers the nanostructures 64, 66. Although the STI regions 70 are all shown as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a liner (not shown separately) can be formed first along the surfaces of the substrate 50, fins 62, and nanostructures 64, 66. Subsequently, a filler material, such as those previously described, can be formed over the liner.

[0033] Then, a removal process is applied to the insulating material to remove excess insulating material above the nanostructures 64, 66. In some embodiments, planarization processes such as chemical mechanical polishing (CMP), etch-back processes, or combinations thereof can be utilized. The planarization process exposes the nanostructures 64, 66 such that, after the planarization process is completed, the top surfaces of the nanostructures 64, 66 and the insulating material are coplanar (within the range of process variations). In embodiments where the mask remains on the nanostructures 64, 66, the planarization process may expose or remove the mask such that, after the planarization process is completed, the top surfaces of the mask or the nanostructures 64, 66 are coplanar with the top surfaces of the insulating material (within the range of process variations). The insulating material is then slotted to form the STI region 70. The insulating material is slotted such that at least a portion of the nanostructures 64, 66 protrudes from between adjacent portions of the insulating material. Furthermore, the top surface of the STI region 70 may have a flat surface (as shown), a convex surface, a concave surface (such as a recess), or a combination thereof. The top surface of the STI region 70 can be formed as flat, convex, and / or concave by appropriate etching. The insulating material can be grooved using any acceptable etching process, such as a material-selective process (e.g., selectively etching the insulating material of the STI region 70 at a faster rate than the materials of fins 62 and nanostructures 64, 66). For example, dilute hydrofluoric acid (dHF) can be used for oxide removal.

[0034] The previously described process is merely one example of how the fins 62 and nanostructures 64, 66 can be formed. In some embodiments, the fins 62 and / or nanostructures 64, 66 can be formed using masking and epitaxial growth processes. For example, a dielectric layer can be formed over the top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Epitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be slotted so that the epitaxial structure protrudes from the dielectric layer to form the fins 62 and / or nanostructures 64, 66. The epitaxial structures can include the alternating semiconductor materials described previously, such as a first semiconductor material and a second semiconductor material. In some embodiments in which epitaxial structures are epitaxially grown, although in-situ and implantation doping can be used together, the material to be epitaxially grown can be doped in-situ during growth, which avoids implantation before and after.

[0035] Furthermore, suitable wells (not shown separately) may be formed in the substrate 50, fins 62, and / or nanostructures 64, 66. The wells may have a conductivity type opposite to that of the source / drain regions subsequently formed in each of the n-type region 50N and the p-type region 50P. In some embodiments, a p-type well is formed in the n-type region 50N, and an n-type well is formed in the p-type region 50P. In some embodiments, a p-type well or an n-type well is formed in both the n-type region 50N and the p-type region 50P.

[0036] In embodiments with different well types, different implantation steps for the n-type region 50N and the p-type region 50P can be implemented using a mask such as photoresist (not shown separately). For example, photoresist can be formed over the fins 62, nanostructures 64, 66, and STI region 70 in the n-type region 50N. The photoresist is patterned to expose the p-type region 50P. The photoresist can be formed using spin coating and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, n-type impurity implantation is performed in the p-type region 50P, and the photoresist can be used as a mask to substantially prevent n-type impurity implantation into the n-type region 50N. The n-type impurity can be phosphorus, arsenic, antimony, etc., implanted into the region at a concentration of 10. 13 cm -3 Up to 10 14 cm -3 Within the range. After implantation, the photoresist is removed, for example, by any acceptable ashing process.

[0037] After or before implantation of the p-type region 50P, a mask, such as photoresist (not shown separately), is formed over the fins 62, nanostructures 64, 66, and STI region 70 in the p-type region 50P. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed using spin coating and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, p-type impurity implantation is performed in the n-type region 50N, and the photoresist can be used as a mask to substantially prevent p-type impurity implantation into the p-type region 50P. The p-type impurity can be boron, boron fluoride, indium, etc., implanted in the region at a concentration of 10. 13 cm -3 Up to 10 14 cm -3 Within the range. After implantation, the photoresist is removed, for example, by any acceptable ashing process.

[0038] Following implantation of the n-type region 50N and the p-type region 50P, annealing can be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments where epitaxial structures are grown for fins 62 and / or nanostructures 64, 66, the grown material can be doped in situ during growth, which avoids implantation, although in-situ doping and implantation doping can be used together.

[0039] exist Figure 5In this structure, a pseudo-dielectric layer 72 is formed on fins 62 and nanostructures 64 and 66. The pseudo-dielectric layer 72 can be formed of a dielectric material, such as silicon oxide, silicon nitride, or combinations thereof, which can be deposited or thermally grown according to acceptable techniques. A pseudo-gate layer 74 is formed above the pseudo-dielectric layer 72, and a mask layer 76 is formed above the pseudo-gate layer 74. The pseudo-gate layer 74 can be deposited above the pseudo-dielectric layer 72, and then the pseudo-gate layer 60 can be planarized, for example, by CMP. The mask layer 76 can be deposited above the pseudo-gate layer 74. The pseudo-gate layer 74 can be formed of a conductive or non-conductive material, such as amorphous silicon, polysilicon, poly-SiGe, metal, metal nitride, metal silicide, metal oxide, etc., which can be deposited by physical vapor deposition (PVD), CVD, etc. The pseudo-gate layer 74 can be formed of a material with high etch selectivity for etching insulating materials (e.g., STI region 70 and / or pseudo-dielectric layer 72). The mask layer 76 can be formed of a dielectric material, such as silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 74 and a single mask layer 76 are formed across an n-type region 50N and a p-type region 50P. In the illustrated embodiment, a dummy dielectric layer 72 covers the fins 62, nanostructures 64, 66, and the STI region 70, such that the dummy dielectric layer 72 extends over the STI region 70 and between the dummy gate layer 74 and the STI region 70. In another embodiment, the dummy dielectric layer 72 covers only the fins 62 and the nanostructures 64, 66.

[0040] exist Figure 6 In this process, a mask layer 76 is patterned using acceptable photolithography and etching techniques to form a mask 86. The pattern of mask 86 is then transferred to a dummy gate layer 74 using any acceptable etching technique to form a dummy gate 84. Optionally, the pattern of mask 86 can be further transferred to a dummy dielectric layer 72 using any acceptable etching technique to form a dummy dielectric 82. The dummy gate 84 covers portions of nanostructures 64, 66 that will be exposed in subsequent processing to form channel regions. Specifically, the dummy gate 84 extends along portions of nanostructures 66 that will be patterned to form channel regions with 68. The pattern of mask 86 can be used to physically separate adjacent dummy gates 84. The dummy gate 84 can also have a longitudinal direction substantially perpendicular (within process variations) to the longitudinal direction of fins 62. Mask 86 can optionally be removed after patterning, such as by any acceptable etching technique.

[0041] Figures 7A to 22B Various additional steps in manufacturing the embodiment device are shown. Figures 7A to 13B and Figures 21A to 22BComponents in either the n-type region 50N or the p-type region 50P are shown. For example, the structure shown can be applied to both the n-type region 50N and the p-type region 50P. The differences in the structure of the n-type region 50N and the p-type region 50P (if any) are described in the text accompanying each figure. Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A and Figure 20A The components in the n-type region 50N are shown. Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19B and Figure 20B The components in p-type region 50P are shown.

[0042] exist Figure 7A and Figure 7B In this embodiment, a gate spacer 90 is formed over nanostructures 64 and 66, on the exposed sidewalls of mask 86 (if present), dummy gate 84, and dummy dielectric 82. The gate spacer 90 can be formed by conformally depositing one or more dielectric materials and subsequently etching the dielectric material. Acceptable dielectric materials include: oxides, such as silicon oxide or aluminum oxide; nitrides, such as silicon nitride; carbides, such as silicon carbide; etc.; or combinations thereof, such as silicon oxynitride, silicon carbon oxynitride, silicon carbonitride, silicon carbonitride, etc.; multilayers thereof; etc. The dielectric material can be formed by conformal deposition processes, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), etc. In the illustrated embodiments, the gate spacer 90 comprises multiple layers, such as a first spacer layer 90A and a second spacer layer 90B. In some embodiments, the first spacer layer 90A and the second spacer layer 90B are made of silicon carbonitride (e.g., SiO2). x N y C 1-x-y (where x and y are in the range of 0 to 1). For example, the first spacer layer 90A may be formed of a silicon carbonitride composition similar to or different from that of the second spacer layer 90B. Acceptable etching processes, such as dry etching, wet etching, or combinations thereof, may be performed to pattern the dielectric material. The etching may be anisotropic. The dielectric material has portions remaining on the sidewalls of the dummy gate 84 when etched (thus forming the gate spacer 90). After etching, the gate spacer 90 may have straight sidewalls (as shown) or may have curved sidewalls (not shown). As will be described in more detail later, the dielectric material may have portions remaining on the sidewalls of the fins 62 and / or nanostructures 64, 66 when etched (thus forming fin spacers).

[0043] Furthermore, implantation can be performed to form lightly doped source / drain (LDD) regions (not shown separately). In embodiments with different device types, similar to the implantation previously described for wells, a mask such as photoresist (not shown separately) can be formed over the n-type region 50N while exposing the p-type region 50P, and an impurity of an appropriate type (e.g., p-type) can be implanted into the fins 62 and / or nanostructures 64, 66 exposed in the p-type region 50P. The mask can then be removed. Subsequently, while exposing the n-type region 50N, a mask such as photoresist (not shown separately) is formed over the p-type region 50P, and an impurity of an appropriate type (e.g., n-type) can be implanted into the fins 62 and / or nanostructures 64, 66 exposed in the n-type region 50N. The mask can then be removed. The n-type impurity can be any n-type impurity previously described, and the p-type impurity can be any p-type impurity previously described. During implantation, the channel region 68 remains covered by the dummy gate 84, such that the channel region 68 remains substantially free of impurities implanted to form the LDD region. The LDD region can have a value of 10. 15 cm -3 Up to 10 19 cm -3 The impurity concentration is within a certain range. Annealing can be used to repair implantation damage and reactivate implanted impurities.

[0044] It should be noted that previous disclosures generally describe the processes for forming spacers and LDD regions. Other processes and sequences can be used. For example, fewer or additional spacers can be used, different step sequences can be used, additional spacers can be formed and removed, and so on. Furthermore, different structures and steps can be used to form n-type and p-type devices.

[0045] exist Figure 8A and Figure 8BIn the illustrated embodiment, source / drain recesses 94 are formed within nanostructures 64, 66. In the illustrated embodiment, the source / drain recesses 94 extend through nanostructures 64, 66 and into fin 62. The source / drain recesses 94 may also extend into substrate 50. In various embodiments, the source / drain recesses 94 may extend to the top surface of substrate 50 without etching substrate 50; fin 62 may be etched such that the bottom surface of the source / drain recesses 94 is disposed below the top surface of STI region 70; etc. The source / drain recesses 94 can be formed by etching nanostructures 64, 66 using anisotropic etching processes such as RIE, NBE, etc. During the etching process used to form the source / drain recesses 94, gate spacer 90 and dummy gate 84 jointly mask fin 62 and / or a portion of nanostructures 64, 66. Each of nanostructures 64, 66 can be etched using a single etching process, or multiple etching processes can be used to etch nanostructures 64, 66. A timed etching process can be used to stop etching the source / drain trench 94 after it has reached the desired depth.

[0046] Optionally, internal spacers 96 are formed on the sidewalls of the remaining portion of the first nanostructure 64 (e.g., those sidewalls exposed by the source / drain recesses 94). As will be described in more detail later, source / drain regions will subsequently be formed in the source / drain recesses 94, and the first nanostructure 64 will subsequently be replaced by a corresponding gate structure. The internal spacers 96 serve as an isolation component between the subsequently formed source / drain regions and the subsequently formed gate structure. Furthermore, the internal spacers 96 can be used to substantially prevent damage to the subsequently formed source / drain regions by subsequent etching processes, such as etching processes for the subsequent removal of the first nanostructure 64.

[0047] As an example of forming the internal spacer 96, the source / drain groove 94 may extend laterally. Specifically, a portion of the sidewall of the first nanostructure 64 exposed by the source / drain groove 94 may be grooved. Although the sidewall of the first nanostructure 64 is shown as straight, it may be concave or convex. The sidewall may be grooved by any acceptable etching process, such as a process selective to the material of the first nanostructure 64 (e.g., selectively etching the material of the first nanostructure 64 at a faster rate than the material of the second nanostructure 66). The etching may be isotropic. For example, when the second nanostructure 66 is formed of silicon and the first nanostructure 64 is formed of silicon-germanium, the etching process may be a wet etching using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc. In another embodiment, the etching process may be a dry etching using a fluorine-based gas such as hydrogen fluoride (HF). In some embodiments, the same etching process may be performed consecutively to form the source / drain groove 94 and the sidewall groove of the first nanostructure 64. The internal spacer 96 can then be formed by conformally forming an insulating material and subsequently etching the insulating material. The insulating material can be silicon nitride or silicon oxynitride, but any suitable material can be used, such as a low-k material with a k value less than 3.5. The insulating material can be deposited using a conformal deposition process such as ALD, CVD, etc. The etching of the insulating material can be anisotropic. For example, the etching process can be dry etching such as RIE, NBE, etc. Although the outer wall of the internal spacer 96 is shown flush with the sidewall of the gate spacer 90, the outer wall of the internal spacer 96 may extend beyond or be recessed from the sidewall of the gate spacer 90. In other words, the internal spacer 96 may partially fill, fully fill, or overfill the sidewall recess. Furthermore, although the sidewall of the internal spacer 96 is shown as straight, the sidewall of the internal spacer 96 may be concave or convex.

[0048] exist Figure 9A and Figure 9B In this configuration, epitaxial source / drain regions 98 are formed in source / drain recesses 94. The epitaxial source / drain regions 98 are formed in the source / drain recesses 94 such that each dummy gate 84 (and corresponding channel region 68) is disposed between corresponding adjacent pairs of epitaxial source / drain regions 98. In some embodiments, gate spacers 90 and internal spacers 96 are used to separate the epitaxial source / drain regions 98 from the dummy gates 84 and the first nanostructure 64 by appropriate lateral distances, such that the epitaxial source / drain regions 98 do not short-circuit with the subsequently formed gate of the resulting nanoFET. The material of the epitaxial source / drain regions 98 can be selected to apply stress in the corresponding channel regions 68, thereby improving performance.

[0049] The epitaxial source / drain region 98 in the n-type region 50N can be formed by masking the p-type region 50P. Then, the epitaxial source / drain region 98 in the n-type region 50N is epitaxially grown in the source / drain trench 94 in the n-type region 50N. The epitaxial source / drain region 98 can include any acceptable material suitable for an n-type device. For example, the epitaxial source / drain region 98 in the n-type region 50N can include a material on which tensile strain is applied to the channel region 68, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. The epitaxial source / drain region 98 in the n-type region 50N can have surfaces raised from the corresponding surfaces of the fins 62 and nanostructures 64, 66, and can have facets.

[0050] The epitaxial source / drain region 98 in the p-type region 50P can be formed by masking the n-type region 50N. Then, the epitaxial source / drain region 98 in the p-type region 50P is epitaxially grown in the source / drain groove 94 in the p-type region 50P. The epitaxial source / drain region 98 can include any acceptable material suitable for a p-type device. For example, the epitaxial source / drain region 98 in the p-type region 50P can include a material on which compressive strain is applied to the channel region 68, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, etc. The epitaxial source / drain region 98 in the p-type region 50P can have surfaces raised from the corresponding surfaces of the fins 62 and nanostructures 64, 66, and can have facets.

[0051] Epitaxial source / drain regions 98, nanostructures 64, 66, and / or fins 62 can be implanted with impurities to form source / drain regions, similar to the previously described process for forming LDD regions, followed by annealing. The source / drain regions can have a [value missing] 10 [value missing] 19 cm -3 Up to 10 21 cm -3 The impurity concentration is within the range specified. The n-type and / or p-type impurities used for the source / drain regions can be any impurities previously described. In some embodiments, the epitaxial source / drain regions 98 can be doped in situ during growth.

[0052] As a result of the epitaxial process used to form the epitaxial source / drain regions 98, the upper surface of the epitaxial source / drain regions has facets that extend laterally outward beyond the sidewalls of the fins 62 and nanostructures 64, 66. In some embodiments, these facets cause adjacent epitaxial source / drain regions 98 to merge into a single structure. Figure 9C As shown. In some embodiments, as Figure 9DAs shown, after the epitaxial process is completed, adjacent epitaxial source / drain regions 98 remain separated. In the illustrated embodiment, the spacer etching for forming the gate spacer 90 is adjusted to also form fin spacers 92 on the sidewalls of fins 62 and / or nanostructures 64, 66. The fin spacers 92 are formed to cover a portion of the sidewalls of fins 62 and / or nanostructures 64, 66 extending over the STI region 70, thereby preventing epitaxial growth. In another embodiment, the spacer etching for forming the gate spacer 90 is adjusted not to form fin spacers, thereby allowing the epitaxial source / drain regions 98 to extend to the surface of the STI region 70.

[0053] The epitaxial source / drain region 98 may include one or more semiconductor material layers. For example, the epitaxial source / drain region 98 may each include a substrate 98A, a main layer 98B, and a finishing layer 98C (or more generally, a first semiconductor material layer, a second semiconductor material layer, and a third semiconductor material layer). Any number of semiconductor material layers may be used for the epitaxial source / drain region 98. Each of the substrate 98A, the main layer 98B, and the finishing layer 98C may be formed of different semiconductor materials and may be doped with different impurity concentrations. In some embodiments, the substrate 98A may have a lower impurity concentration than the main layer 98B, and the finishing layer 98C may have a higher impurity concentration than the substrate 98A and a lower impurity concentration than the main layer 98B. In embodiments where the epitaxial source / drain region 98 includes three semiconductor material layers, the substrate 98A may be grown in the source / drain trench 94, the main layer 98B may be grown on the substrate 98A, and the finishing layer 98C may be grown on the main layer 98B.

[0054] exist Figure 10A and Figure 10B In this configuration, the first interlayer dielectric (ILD) 104 is deposited over the epitaxial source / drain region 98, the gate spacer 90, the mask 86 (if present), or the dummy gate 84. The ILD 104 can be formed of a dielectric material, which can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), FCVD, etc. Acceptable dielectric materials may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process may be used.

[0055] In some embodiments, a contact etch stop layer (CESL) 102 is formed between the first ILD 104 and the epitaxial source / drain region 98, gate spacer 90, and mask 86 (if present) or dummy gate 84. The CESL 102 can be formed of a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, etc., having high etch selectivity for etching the first ILD 104. The CESL 102 can be formed by any suitable method, such as CVD, ALD, etc.

[0056] exist Figure 11A and Figure 11B In this process, a removal process is performed to align the top surface of the first ILD 104 with the top surface of the mask 86 (if present) or the dummy gate 84. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), etch-back, or a combination thereof may be utilized. The planarization process may also remove the mask 86 on the dummy gate 84 and portions of the gate spacer 90 along the sidewalls of the mask 86. After the planarization process, the top surfaces of the gate spacer 90, the first ILD 104, CESL 102, the mask 86 (if present), or the dummy gate 84 are coplanar (within the range of process variations). Therefore, the top surface of the mask 86 (if present) or the dummy gate 84 is exposed through the first ILD 104. In the illustrated embodiment, the mask 86 is retained, and the planarization process aligns the top surface of the first ILD 104 with the top surface of the mask 86.

[0057] exist Figure 12A and Figure 12B In the etching process, the mask 86 (if present) and the dummy gate 84 are removed to form a recess 110. A portion of the dummy dielectric 82 in the recess 110 is also removed. In some embodiments, the dummy gate 84 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using reactive gases, which selectively etches the dummy gate 84 at a faster rate than the first ILD 104 or the gate spacer 90. During removal, the dummy dielectric 82 may serve as an etch stop layer while etching the dummy gate 84. The dummy dielectric 82 is then removed. Each recess 110 exposes and / or covers a portion of the channel region 68. A portion of the second nanostructure 66 serving as the channel region 68 is disposed between adjacent pairs of epitaxial source / drain regions 98.

[0058] The remaining portion of the first nanostructure 64 is then removed to enlarge the groove 110. The remaining portion of the first nanostructure 64 can be removed by any acceptable etching process that selectively etches the material of the first nanostructure 64 at a faster rate than the material of the second nanostructure 66. The etching can be isotropic. For example, when the first nanostructure 64 is formed of silicon-germanium and the second nanostructure 66 is formed of silicon, the etching process can be wet etching using tetramethylammonium hydroxide (TMAH), NH4OH, H2O2, H2O, HF, C3H8O2, C2H4C3, or combinations thereof. In some embodiments, a trimming process (not shown separately) is performed to reduce the thickness of the exposed portion of the second nanostructure 66. Figures 14A to 20B As shown more clearly (and described in more detail later), the second nanostructure 66 can have rounded corners.

[0059] exist Figure 13A and Figure 13B In the second nanostructure 66, a gate dielectric layer 112 is formed in the groove 110. A gate electrode layer 114 is formed on the gate dielectric layer 112. The gate dielectric layer 112 and the gate electrode layer 114 are layers that replace the gate, and each surrounds all (e.g., four) sides of the second nanostructure 66.

[0060] A gate dielectric layer 112 is disposed on the sidewalls and / or top surface of the fin 62; the top surface, sidewalls, and bottom surface of the second nanostructure 66; and the sidewalls of the gate spacer 90. The gate dielectric layer 112 may also be formed on the top surface of the first ILD 104 and the gate spacer 90. The gate dielectric layer 112 may include oxides such as silicon oxide or metal oxides, silicates such as metal silicates, combinations thereof, multilayers thereof, etc. The gate dielectric layer 112 may include dielectric materials with a k-value greater than 7.0, such as metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. Although in Figure 13A and Figure 13B The diagram shows a single-layer gate dielectric layer 112, which will be described in more detail later, but the gate dielectric layer 112 may include an interface layer and a main layer.

[0061] The gate electrode layer 114 may include a metallic material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. Although Figure 13A and Figure 13B The diagram shows a single-layer gate electrode layer 114, as will be described in more detail later, but the gate electrode layer 114 may include any number of work function adjustment layers, any number of barrier layers, any number of adhesive layers, and filler materials.

[0062] Figures 14A to 24B The process of forming a layer for replacing the gate in the recess 110 is shown. This is illustrated in relation to... Figure 13AComponents in area 50R, which are similar to those in other areas. Figure 28 This is a flowchart of an example method 200 for forming an alternative gate layer according to some embodiments. (In conjunction with...) Figure 28 describe Figures 14A to 24B .

[0063] exist Figure 14A and Figure 14B In step 202 of method 200, the gate dielectric layer 112 is deposited in the recess 110 in both the first region (e.g., n-type region 50N) and the second region (e.g., p-type region 50P). The gate dielectric layer 112 may also be deposited on the top surface of the first ILD 104 and the gate spacer 90 (see...). Figure 13B In the illustrated embodiment, the gate dielectric layer 112 is multilayered, including an interface layer 112A (or more generally, a first gate dielectric layer) and an overlying high-k dielectric layer 112B (or more generally, a second gate dielectric layer). The interface layer 112A may be formed of silicon oxide, and the high-k dielectric layer 112B may be formed of hafnium oxide, lanthanum oxide, or the like. Methods for forming the gate dielectric layer 112 may include molecular beam deposition (MBD), ALD, PECVD, etc. The gate dielectric layer 112 surrounds all (e.g., four) sides of the second nanostructure 66.

[0064] In some embodiments, the second nanostructure 66 has a width W1 in the range of 1 nm to 50 nm, such as from 15 nm to 25 nm. In some embodiments, adjacent second nanostructures 66 are spaced apart by a pitch S1 in the range of 0.1 nm to 40 nm, such as from 3 nm to 8 nm. If the pitch S1 is greater than 40 nm, seams or gaps may form between adjacent second nanostructures 66 after the subsequent formation of the gate structure. If the pitch S1 is less than 0.1 nm, adjacent second nanostructures 66 can easily short-circuit with each other.

[0065] exist Figure 15A and Figure 15BIn step 204 of method 200, a first sacrificial layer 116A is deposited on the gate dielectric layer 112 in a first region (e.g., n-type region 50N) and a second region (e.g., p-type region 50P). As will be described in more detail later, the first sacrificial layer 116A is patterned to remove portions of the first sacrificial layer 116A in the first region (e.g., n-type region 50N) while retaining portions of the first sacrificial layer 116A in the second region (e.g., p-type region 50P). Specifically, the first sacrificial layer 116A is used to facilitate the removal of the work function layer from the second region (e.g., p-type region 50P) by disallowing the work function layer from entering between the second nanostructures 66. The first sacrificial layer 116A comprises any acceptable material that can be formed on and removed from between the second nanostructures 66 and can be deposited using any acceptable deposition process. For example, the first sacrificial layer 116A is formed of TiN, WCN, WCl5, TaCl5, SnCl4, combinations thereof, etc., which can be deposited by ALD, CVD, PVD, etc. Although the first sacrificial layer 116A is shown as a single layer, it can be multilayered. The first sacrificial layer 116A can fill the portion of the second groove 110 that extends between vertically adjacent nanostructures 66 and between nanostructures 66 and fins 62.

[0066] exist Figure 16A and Figure 16B In step 206 of method 200, a portion of the first sacrificial layer 116A is removed from the first region (e.g., n-type region 50N) and the second region (e.g., p-type region 50P). Removing a portion of the first sacrificial layer 116A allows for the subsequent formation of a second sacrificial layer 116B to protect the gate dielectric layer 112, while potentially providing etch selectivity for the first sacrificial layer 116A. Removal can be performed using acceptable photolithography and etching techniques. Etching can include any acceptable etching process such as reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. Etching can be anisotropic. Figure 16A and Figure 16B As shown, the removal of a portion of the first sacrificial layer 116A removes the outer portion of the first sacrificial layer 116A to expose the gate dielectric layer 112, but retains the first sacrificial layer 116A extending between vertically adjacent nanostructures 66 and between nanostructures 66 and fins 62 in both the first and second regions 50N and 50P. This process of removing the outer portion of the first sacrificial layer 116A while leaving the inner portion can be called a trimming process.

[0067] After removing a portion of the first sacrificial layer 116A, the gate dielectric layer 112 remains above and covers the isolation region 70 (see, for example). Figure 13AThese portions of the gate dielectric layer 112 help protect the isolation region 70 from damage during subsequent deposition and removal processes.

[0068] In some embodiments, a single etch is performed to remove a portion of the first sacrificial layer 116A. The single etch may be selective in its application to the material of the first sacrificial layer 116A (e.g., selectively etching the material of the first sacrificial layer 116A at a faster rate than the material of the gate dielectric layer 112). In some embodiments, multiple etch steps / processes are performed to remove a portion of the first sacrificial layer 116A.

[0069] exist Figure 17A and Figure 17B In step 208 of method 200, a second sacrificial layer 116A is deposited on the gate dielectric layer 112 and the remaining first sacrificial layer 116A in the first region (e.g., n-type region 50N) and the second region (e.g., p-type region 50P). As will be described in more detail later, the second sacrificial layer 116B is patterned to remove the second sacrificial layer and the first sacrificial layer 116A in the first region (e.g., n-type region 50N), while retaining the second sacrificial layer 116B and the first sacrificial layer 116A in the second region (e.g., p-type region 50P). Specifically, by not allowing the first mask layer 118A to be formed directly on the gate dielectric layer 112, the second sacrificial layer 116B serves to protect the gate dielectric layer 112 from the first mask layer 118A formed in the first and second regions. The second sacrificial layer 116B comprises any acceptable material that can be formed and removed on the gate dielectric layer 112 without damaging it, and can be deposited using any acceptable deposition process. For example, the second sacrificial layer 116B is formed of TiN, WCN, WCl5, TaCl5, SnCl4, or combinations thereof, and can be deposited by ALD, CVD, PVD, or the like. In some embodiments, the second sacrificial layer 116B is formed of a different material than the first sacrificial layer 116A. Although the second sacrificial layer 116B is shown as a single layer, it can be multilayered.

[0070] In some embodiments, the second sacrificial layer 116B is formed of the same material as the first sacrificial layer 116A, and there is no visible interface between layers 116A and 116B. In some embodiments, the second sacrificial layer 116B is omitted and the first sacrificial layer 116A is not patterned, as... Figure 16A and Figure 16B As shown, the first sacrificial layer 116A protects the dielectric layer 112 from the influence of the first mask layer 118A.

[0071] exist Figure 18A and Figure 18BIn step 210 of method 200, a first mask layer 118A is formed in a second groove 110 above the second sacrificial layer 116B in the first and second regions 50N and 50P. The first mask layer 118A can be deposited by spin coating or the like. The first mask layer 118A may include polymeric materials such as poly(meth)acrylate, poly(maleimide), phenolic varnish, poly(ether), combinations thereof, etc. In some embodiments, the first mask layer 118A may be a bottom antireflective coating (BARC) material.

[0072] like Figure 18A and Figure 18B As shown, a first mask layer 118A is patterned to remove the first mask layer 118A from a groove 110 in the first region 50N. The first mask layer 118A can be removed by plasma ashing, etching processes such as isotropic or anisotropic etching processes, etc. After patterning the first mask layer 118A, the first and second sacrificial layers 116A and 116B are removed from the first region 50N using the first mask layer 118A as a mask. Removal can be performed by acceptable photolithography and etching techniques. Etching can include any acceptable etching process, such as RIE, NBE, wet etching, etc., or combinations thereof. Etching can be anisotropic.

[0073] In some embodiments, a single etch is performed to remove portions of the first and second sacrificial layers 116A and 116B. The single etch may be selective in its application to the materials of the first and second sacrificial layers 116A and 116B (e.g., selectively etching the materials of the first and second sacrificial layers 116A and 116B at a faster rate than the material of the gate dielectric layer 112). For example, when the first and second sacrificial layers 116A and 116B are formed of titanium nitride, they can be removed by an inductively coupled plasma etching process using Ar / CHF3, Ar / Cl2, Ar / BCl3, or combinations thereof. In some embodiments, multiple etch steps / processes are performed to remove the first and second sacrificial layers 116A and 116B.

[0074] exist Figure 19A and Figure 19B In this process, a first mask layer 118A is patterned to remove the first mask layer 118A from a groove 110 in the second region 50P. The first mask layer 118A can be removed by plasma ashing, etching processes such as isotropic or anisotropic etching processes, etc. After removing the first mask layer 118A from the groove 110 in the second region 50P, a second sacrificial layer 116B is removed from the second region 50P. Removal can be performed by acceptable photolithography and etching techniques. Etching can include any acceptable etching process such as RIE, NBE, or combinations thereof. Etching can be anisotropic.

[0075] In some embodiments, a single etch is performed to remove the second sacrificial layer 116B. The single etch may be selective in its application to the material of the second sacrificial layer 116B (e.g., selectively etching the material of the second sacrificial layer 116B at a faster rate than the materials of the gate dielectric layer 112 and / or the first sacrificial layer 116A). In some embodiments, multiple etch steps / processes are performed to remove the second sacrificial layer 116B.

[0076] like Figure 19A and Figure 19B As shown, the removal of the second sacrificial layer 116B removes the outer portion of the second sacrificial layer 116B to expose a portion of the gate dielectric layer 112, but retains the first sacrificial layer 116A extending in the second region 50P between vertically adjacent nanostructures 66 and between nanostructures 66 and fins 62. This process of removing the outer portion of the second sacrificial layer 116B while leaving the inner portion can be called a trimming process.

[0077] exist Figure 20A and Figure 20B In step 214 of method 200, a first work function adjustment layer 114A is deposited on the gate dielectric layer 112 in a first region (e.g., n-type region 50N) and on the gate dielectric layer 112 and the first sacrificial layer 116A in a second region (e.g., p-type region 50P). As will be described in more detail later, the first work function adjustment layer 114A is patterned to remove a portion of the first work function adjustment layer 114A in the second region (e.g., p-type region 50P), while retaining a portion of the first work function adjustment layer 114A in the first region (e.g., n-type region 50N). When the first work function adjustment layer 114A is removed from the second region (e.g., p-type region 50P), it can be referred to as an "n-type work function adjustment layer". The first work function adjustment layer 114A comprises any acceptable material to adjust the work function of the device to an ideal amount according to the application of the device to be formed, and can be deposited using an acceptable deposition process. For example, when the first work function adjustment layer 114A is an n-type work function adjustment layer, it can be formed from an n-type work function metal (NWFM), such as titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), TiAlC:N, titanium aluminum nitride (TiAlN), tantalum aluminum silicon (TaSiAl), WCl5, SnCl4, NbCl5, MoCl4, and combinations thereof, which can be deposited by ALD, CVD, PVD, etc. Although the first work function adjustment layer 114A is shown as a single layer, it can be multilayered. For example, the first work function adjustment layer 114A may include a TiAlN layer and a TiAlC layer.

[0078] The first work function adjustment layer 114A is formed to a thickness that does not cause portions of the first work function adjustment layer 114A to merge between the second nanostructures 66 in the first region (e.g., n-type region 50N). As described in more detail below, the ALD process used to form the first work function adjustment layer 114A allows for a thinner first work function adjustment layer 114A (which does not merge between the second nanostructures 66 in the cross-section shown in the first region 50N) while still having the desired effective work function value. Due to the remaining portion of the first sacrificial layer 116A in the second region, the first work function adjustment layer 114A cannot merge between the second nanostructures 66 in the second region (e.g., p-type region 50P) in the cross-section shown. By not depositing the first work function adjustment layer 114A between the second nanostructures 66 in the second region (e.g., p-type region 50P), fabrication ease can be improved, especially in advanced semiconductor nodes with small part sizes, because work function adjustment layer material is difficult to remove from confined spaces. In some embodiments, the first work function adjustment layer 114A is formed to be in to Thickness within a range, such as in to Within the range.

[0079] In some embodiments, the first work function adjustment layer 114A is formed of aluminum titanium carbide deposited via an ALD process. Specifically, the first work function adjustment layer 114A can be formed by placing a substrate 50 in a deposition chamber and circulating a plurality of source precursors into the deposition chamber. The first pulse of the ALD cycle is performed by distributing titanium source precursors into the deposition chamber. Acceptable titanium source precursors include titanium chloride (TiCl4), etc. The first pulse can be performed at a temperature in the range of 100°C to 600°C and a pressure in the range of 1 torr to 100 torr, for example, by maintaining the deposition chamber at such temperature and pressure. The first pulse can be performed for a duration in the range of 0.5 seconds to 20 seconds, for example, by maintaining the titanium source precursors in the deposition chamber for such a duration. The titanium source precursors are then removed from the deposition chamber, such as by an acceptable vacuum process and / or by introducing an inert gas (sometimes referred to as a carrier gas) into the deposition chamber. The second pulse of the ALD cycle is performed by distributing aluminum source precursors into the deposition chamber. Acceptable aluminum source precursors include triethylaluminum (TEA) (Al2(C2H5)6), etc. The second pulse can be performed at a temperature ranging from 100°C to 600°C and a pressure ranging from 1 to 100 torr, for example, by maintaining the deposition chamber at such temperatures and pressures. The second pulse can be performed for a duration ranging from 0.5 seconds to 20 seconds, for example, by maintaining the aluminum source precursor in the deposition chamber for such a duration. The aluminum source precursor is then removed from the deposition chamber, such as by an acceptable vacuum process and / or by introducing an inert gas into the deposition chamber. Performing any ALD pulse at temperatures above 600°C may negatively impact the uniformity of the deposition and result in inconsistent material concentrations in the deposited layer. Performing any ALD pulse at temperatures below 100°C may negatively impact the yield and / or productivity of the manufacturing process and may result in higher manufacturing costs. Each ALD cycle results in the deposition of an atomic layer (sometimes referred to as a monolayer) of aluminum titanium carbide. The ALD cycle is repeated until the first work function adjustment layer 114A has the desired thickness (as previously described). The ALD cycle can be repeated 1 to 10 times. Performing the ALD process with parameters within these ranges allows the first work function adjustment layer 114A to be formed with the desired thickness (previously described), quality, and composition. Performing the ALD process with parameters outside these ranges may not allow the first work function adjustment layer 114A to be formed with the desired thickness, quality, or composition.

[0080] The ALD process described above for forming the first work function adjustment layer 114A has the same number of titanium pulses as aluminum pulses in each ALD cycle. In some embodiments, each ALD cycle has more aluminum pulses than titanium pulses. For example, each ALD cycle may include one titanium pulse and two aluminum pulses. As another example, each ALD cycle may include two titanium pulses and three aluminum pulses. By ensuring that there are at least as many aluminum pulses as titanium pulses in each ALD cycle, the first work function layer has a higher aluminum concentration. In some embodiments, the atomic percentage (at%) of aluminum in the first work function adjustment layer 114A is in the range of 3% to 80%, such as in the range of 20% to 40%. In some embodiments, the first work function adjustment layer 114A has a gradient metal concentration, with a higher aluminum concentration near the inner portion of the second nanostructure 66 and a lower concentration in the outer portion away from the second nanostructure 66. In some embodiments, the disclosed method for forming the first work function adjustment layer 114A increases the effective work function by 10% to 15%.

[0081] In some embodiments, the ALD process for forming the first work function adjustment layer 114A includes allowing a carrier gas to flow out from a port at the bottom of the deposition chamber (e.g., below or on the back side of the substrate 50), while the aforementioned titanium and aluminum precursors flow into one or more ports at the top of the deposition chamber (e.g., above or on the front side of the substrate 50). In some embodiments, the carrier gas flowing into the bottom of the deposition chamber is N2 or the like, and the flow rate is in the range of 2 sccm to 100 sccm. In some embodiments, the current carrying is a pulse executed at the end of each ALD cycle. In some embodiments, the current carrying is a pulse executed after each titanium or aluminum precursor pulse in each ALD cycle. By including this back-side current carrying in the ALD process, the uniformity of the deposition thickness of the first work function adjustment layer 114A is improved by 23% compared to not including the back-side current carrying.

[0082] In addition, Figure 20A and Figure 20B And in step 214 of method 200, adhesive layer 114B is formed on the first work function adjustment layer 114A in a first region (e.g., n-type region 50N) and a second region (e.g., p-type region 50P). Figure 20A As shown, the adhesive layer 114B is merged between adjacent second nanostructures 66 in the first region 50N of the illustrated cross-section. In some embodiments, the adhesive layer 114B is formed to a thickness in the range of 10 nm to 50 nm. The adhesive layer 114B comprises any acceptable material to promote adhesion and prevent diffusion. For example, the adhesive layer 114B can be formed of a metal or metal nitride, such as titanium nitride, aluminum titanium carbide, aluminum tantalum carbide, silicon-doped tantalum aluminum, etc., which can be deposited by ALD, CVD, PVD, etc.

[0083] In some embodiments, adhesive layer 114B is produced using a similar ALD process with a titanium precursor (such as TiCl4) or a tantalum precursor (such as penta(dimethylamide)tantalum (PDMAT)). 10 H 30 Titanium or tantalum precursors (such as N5Ta, tantalum chloride (TaCl5), etc.) and / or nitrogen precursors (such as NH3) are formed. The titanium or tantalum precursor can flow into the deposition chamber at a rate ranging from 50 sccm to 100 sccm. The nitrogen precursor can flow into the deposition chamber at a rate ranging from 50 sccm to 50,000 sccm. Performing the ALD process at flow rates above these ranges may negatively impact the uniformity of the deposition and result in precursor waste. Performing the ALD process at flow rates below these ranges may negatively impact the yield and / or productivity of the manufacturing process and may result in lower material concentrations in the deposited layer. In some embodiments, the ALD process can be performed at temperatures ranging from 100°C to 600°C and pressures ranging from 0.0001 torr to 1 torr. Performing the ALD process at temperatures above 600°C may negatively impact the uniformity of the deposition and result in inconsistent material concentrations in the deposited layer. Performing the ALD process at temperatures below 100°C may negatively impact the yield and / or productivity of the manufacturing process and may result in higher manufacturing costs.

[0084] exist Figure 21A and Figure 21B In step 216 of method 200, a second mask layer 118B is formed in a second groove 110 above the adhesive layer 114B in the first and second regions 50N and 50P. The second mask layer 118B can be similar to the first mask layer 118A described above, and will not be described again here.

[0085] like Figure 21A and Figure 21BAs shown, the second mask layer 118B is patterned to remove the second mask layer 118B from the recess 110 in the second region 50P. The second mask layer 118B can be removed by plasma ashing, etching processes such as isotropic or anisotropic etching processes, etc. After patterning the second mask layer 118B, the remaining portions of the first work function adjustment layer 114A, the adhesive layer 114B, and the first sacrificial layer 116A are removed from the second region 50P using the second mask layer 118B as a mask. Removing the remaining portions of the first work function adjustment layer 114A, the adhesive layer 114B, and the first sacrificial layer 116A from the second region (e.g., p-type region 50P) enlarges the recess 110 in the second region to re-expose the gate dielectric layer 112 in the second region (e.g., p-type region 50P). Removal can be performed by acceptable photolithography and etching techniques. Etching can include any acceptable etching process, such as RIE, NBE, wet etching using, for example, ammonium hydroxide (NH4OH), dilute hydrofluoric acid (dHF), or a combination thereof. Etching can be isotropic.

[0086] In some embodiments, a single etch is performed to remove the remainder of the first work function adjustment layer 114A, the adhesive layer 114B, and the first sacrificial layer 116A. The single etch can be selective in its application to the materials of the remainder of the first work function adjustment layer 114A, the adhesive layer 114B, and the first sacrificial layer 116A (e.g., selectively etching the materials of the first work function adjustment layer 114A, the adhesive layer 114B, and the first sacrificial layer 116A at a faster rate than the material of the gate dielectric layer 112). In some embodiments, multiple etch steps / processes are performed to remove the remainder of the first work function adjustment layer 114A, the adhesive layer 114B, and the first sacrificial layer 116A. As previously described, the remainder of the first sacrificial layer 116A is more easily removed from between the second nanostructures 66 compared to the work function adjustment layer; therefore, the disclosed method provides better control over the threshold voltage of the adjusted device.

[0087] exist Figure 22A and Figure 22B In this process, the second mask layer 118B is patterned to remove the second mask layer 118B from the groove 110 in the first region 50N. The second mask layer 118B can be removed by plasma ashing, etching processes such as isotropic or anisotropic etching processes, etc.

[0088] After removing the second mask layer 118B from the groove 110 in the second region 50N, Figure 22A and Figure 22BIn step 218 of method 200, second work function adjustment layers 114C and 114D are deposited on the adhesive layer 114B in the first region (e.g., n-type region 50N) and on the gate dielectric layer 112 in the second region (e.g., p-type region 50P). As will be described in more detail later, a p-type device having the second work function adjustment layers 114C and 114D will be formed in the second region (e.g., p-type region 50P), and an n-type device having a first work function adjustment layer 114A, an adhesive layer 114B, and second work function adjustment layers 114C and 114D will be formed in the first region (e.g., n-type region 50N). When the second work function adjustment layers 114C and 114D are the only work function adjustment layers in the second region (e.g., p-type region 50P), they can be referred to as "p-type work function adjustment layers". The second work function adjustment layers 114C and 114D comprise any acceptable material to adjust the work function of the device to an ideal amount according to the application of the device to be formed, and can be deposited using acceptable deposition processes. For example, when the second work function adjustment layers 114C and 114D are p-type work function adjustment layers, they can be formed from p-type work function metals (PWFM), such as titanium nitride (TiN), tantalum nitride (TaN), or combinations thereof, which can be deposited by ALD, CVD, PVD, etc. The second work function adjustment layers 114C and 114D can be formed by an ALD process using the parameters described above for adhesive layer 114B, and will not be repeated here. Although the second work function adjustment layers 114C and 114D are shown as two layers, the second work function adjustment layers can be single-layered or have more than two layers. In some embodiments, the second work function adjustment layers 114C and 114D comprise a titanium nitride (TiN) layer and a tantalum nitride (TaN) layer.

[0089] The thickness of the second work function adjustment layers 114C and 114D is sufficient to allow portions of the second work function adjustment layers 114C or 114D to merge between the second nanostructures 66 in the second region (e.g., the p-type region 50P). In some embodiments, the second work function adjustment layers 114C and 114D are formed as follows: to Thickness within a range, such as in to Within the range. The second work function adjustment layer 114C is formed to be less than The thickness may not lead to the merging of portions of the second work function adjustment layers 114C and 114D. Forming a layer larger than... The thickness of the second work function adjustment layers 114C and 114D may have a negative impact on the threshold voltage of the resulting device.

[0090] The material of the first work function adjustment layer 114A is different from the material of the second work function adjustment layers 114C and 114D. As described above, the first work function adjustment layer 114A can be formed of an n-type work function metal (NWFM), and the second work function adjustment layers 114C and 114D can be formed of a p-type work function metal (PWFM). NWFM is different from PWFM.

[0091] exist Figure 23A and Figure 23B In step 220 of method 200, the filler layer 114E is deposited on the second work function adjustment layer 114D. After formation, the gate electrode layer 114 includes a first work function adjustment layer 114A, a binder layer 114B, second work function adjustment layers 114C and 114D, and a filler layer 114E.

[0092] The filler layer 114E comprises any acceptable low-resistivity material. For example, the filler layer 114E can be formed of metals such as tungsten, aluminum, cobalt, ruthenium, and combinations thereof, which can be deposited by ALD, CVD, PVD, etc. The filler layer 114E fills the remaining portion of the groove 110. Figure 23A and Figure 23B As shown in the cross section, the filling layer 114E does not extend between adjacent second nanostructures 66 in the first region 50N or the second region 50P, because the region between adjacent second nanostructures 66 in the two regions has been filled by other layers.

[0093] Although adhesive layer 114B is used to promote adhesion of the first work function adjustment layer 114A during processing and prevent its diffusion, it may not significantly affect the electrical characteristics of the resulting device and may remain in portions of the gate electrode layer 114 in the first region (e.g., n-type region 50N). Adhesive layer 114B is disposed between portions of the first work function adjustment layer 114A and the second work function adjustment layer 114C in the first region (e.g., n-type region 50N) and physically separates them. Conversely, the second region (e.g., p-type region 50P) lacks the first work function adjustment layer 114A and adhesive layer 114B, such that the second work function adjustment layer 114C and the gate dielectric layer 112 in the second region (e.g., p-type region 50P) are not separated by the adhesive layer and can be in physical contact.

[0094] Figure 24A and Figure 24B An embodiment is shown including a protective layer 114F between a first work function adjustment layer 114A and an adhesive layer 114B. The protective layer 114F is formed of a material that is antioxidant and prevents the diffusion of the first work function adjustment layer 114A, thereby inhibiting the first work function adjustment layer 114A from being modified by subsequent processing.

[0095] In some embodiments, the protective layer 114F is formed of amorphous silicon, tantalum nitride, titanium nitride, or a combination thereof, which can be deposited by CVD, ALD, etc. Although the protective layer 114F is shown as a single layer, it can be multilayered. For example, the protective layer 114F may include a layer of amorphous silicon and a layer of titanium nitride. In some embodiments, the protective layer 114F is formed to a thickness in the range of 0.1 nm to 10 nm.

[0096] exist Figure 25A and Figure 25B In this process, a removal process is performed to remove excess material from the gate dielectric layer 112 and the gate electrode layer 114, which lies above the top surface of the first ILD 104 and the gate spacer 90, thereby forming the gate dielectric 122 and the gate electrode 124. In some embodiments, planarization processes such as chemical mechanical polishing (CMP), etch-back processes, or combinations thereof may be utilized. The gate dielectric layer 112 has a portion remaining in the recess 110 during planarization (thus forming the gate dielectric layer 122). The gate electrode layer 114 has a portion remaining in the recess 110 during planarization (thus forming the gate electrode 124). Gate spacer 90, CESL 102, first ILD 104, gate dielectric 122 (e.g., interface layer 112A and high-k dielectric layer 112B, see...) Figures 23A-24B ) and gate electrode 124 (e.g., first work function adjustment layer 114A, adhesive layer 114B, second work function adjustment layers 114C and 114D, optional protective layer 114F and filler layer 114E, see Figures 23A-24B The top surfaces of the gate dielectric 122 and gate electrode 124 are coplanar (within the range of process variations). The gate dielectric 122 and gate electrode 124 form the alternative gate of the resulting nanoFET. Each pair of corresponding gate dielectric 122 and gate electrode 124 may be collectively referred to as a "gate structure". Each gate structure extends along the top surface, sidewalls and bottom surface of the channel region 68 of the second nanostructure 66.

[0097] exist Figure 26A and Figure 26B In this configuration, the second ILD 134 is deposited over the gate spacer 90, CESL 102, the first ILD 104, the gate dielectric 122, and the gate electrode 124. In some embodiments, the second ILD 134 is a flowable film formed by a flowable CVD method. In some embodiments, the second ILD 134 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., which can be deposited by any suitable method such as CVD, PECVD, etc.

[0098] In some embodiments, an etch stop layer (ESL) 132 is formed between the second ILD 134 and the gate spacer 90, ESL 102, the first ILD 104, the gate dielectric 122, and the gate electrode 124. The ESL 132 may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, etc., having high etch selectivity for etching the second ILD 134.

[0099] exist Figure 27A and Figure 27B In this configuration, a gate contact 142 and a source / drain contact 144 are formed to contact the gate electrode 124 and the epitaxial source / drain region 98, respectively. The gate contact 142 is physically and electrically coupled to the gate electrode 124. The source / drain contact 144 is physically and electrically coupled to the epitaxial source / drain region 98.

[0100] As an example of forming the gate contact 142 and the source / drain contact 144, the opening of the gate contact 142 is formed through the second ILD 134 and ESL 132, and the opening of the source / drain contact 144 is formed through the second ILD 134, ESL 132, the first ILD 104, and CESL 102. The openings can be formed using acceptable photolithography and etching techniques. A liner (not shown separately), such as a diffusion barrier layer or an adhesive layer, and a conductive material are formed within the openings. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, copper alloys, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP can be performed to remove excess material from the surface of the second ILD 134. The remaining liner and conductive material form the gate contact 142 and the source / drain contact 144 within the openings. The gate contact 142 and the source / drain contact 144 can be formed in different processes or in the same process. Although shown as being formed in the same cross section, it should be understood that each of the gate contact 142 and the source / drain contact 144 can be formed in a different cross section, which can avoid short circuits in the contacts.

[0101] Optionally, a metal-semiconductor alloy region 146 is formed at the interface between the epitaxial source / drain region 98 and the source / drain contact 144. The metal-semiconductor alloy region 146 can be a silicide region formed from metal silicides (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.), a germanide region formed from metal germanides (e.g., titanium germanide, cobalt germanide, nickel germanide, etc.), or a silicon germanide region formed from both metal silicides and metal germanides. The metal-semiconductor alloy region 146 can be formed before the material of the source / drain contact 144 by depositing metal in the opening of the source / drain contact 144 and then performing a thermal annealing process. The metal can be any metal capable of reacting with the semiconductor material of the epitaxial source / drain region 98 (e.g., silicon, silicon germanium, germanium, etc.) to form a low-resistance metal-semiconductor alloy, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof. Metals can be deposited using deposition processes such as ALD, CVD, PVD, etc. After the thermal annealing process, a cleaning process, such as wet cleaning, can be performed to remove any residual metal from the openings of the source / drain contacts 144, such as from the surface of the metal-semiconductor alloy region 146. The material for the source / drain contacts 144 can then be formed on the metal-semiconductor alloy region 146.

[0102] The embodiments offer advantages. In some embodiments, the work function adjustment layer of the n-type device is formed before the work function adjustment layer of the p-type device to allow for greater control over the threshold voltage of the resulting device. A method of forming the work function adjustment layer of the n-type device before the work function adjustment layer of the p-type device includes forming and patterning a sacrificial layer to prevent the work function adjustment layer of the n-type device from forming between the nanostructures of the p-type device. This helps prevent the work function adjustment layer from remaining on the p-type device, which would degrade the performance of the p-type device. In some embodiments, a protective layer is formed between the work function adjustment layer and the adhesive layer to suppress (e.g., substantially prevent or at least reduce) the diffusion of the work function adjustment layer. Therefore, the threshold voltage of the resulting device can be adjusted more precisely.

[0103] The embodiment includes a device having a first set of nanostructures on a substrate, the first set of nanostructures including a first channel region. The device also includes a second set of nanostructures on the substrate, the second set of nanostructures including a second channel region. The device further includes a gate dielectric layer surrounding each of the first and second sets of nanostructures. The device also includes a first work function adjustment layer on the gate dielectric layer of the first set of nanostructures, the first work function adjustment layer surrounding each of the first set of nanostructures, the first work function adjustment layer including an n-type work function metal. The device also includes a adhesive layer on the first work function adjustment layer, the adhesive layer surrounding each of the first set of nanostructures. The device further includes a second work function adjustment layer on the adhesive layer of the first set of nanostructures and on the gate dielectric layer of the second set of nanostructures, the second work function adjustment layer including a p-type work function metal, the p-type work function metal being different from the n-type work function metal. The device also includes a fill layer on the second work function adjustment layer.

[0104] The embodiments may include one or more of the following features. In this device, the adhesive layer comprises titanium nitride, aluminum titanium carbide, aluminum tantalum carbide, or silicon-doped tantalum aluminum. The device also includes a protective layer located between the first work function adjustment layer and the adhesive layer of the first set of nanostructures, the protective layer surrounding each of the first set of nanostructures. The protective layer comprises amorphous silicon. The adhesive layer separates and fills regions between corresponding portions of the protective layer on adjacent nanostructures of the first set of nanostructures. The adhesive layer separates and fills regions between corresponding portions of the first work function adjustment layer on adjacent nanostructures of the first set of nanostructures. A second work function adjustment layer separates and fills regions between corresponding portions of the gate dielectric layer on adjacent nanostructures of the second set of nanostructures. The filling layer does not extend between adjacent nanostructures of the second set of nanostructures.

[0105] The embodiment includes a method comprising forming a first set of nanostructures and a second set of nanostructures on a substrate, the first set of nanostructures including a first channel region and the second set of nanostructures including a second channel region. The method further includes forming a gate dielectric layer having a first portion and a second portion, the first portion being deposited on the first channel region and the second portion being deposited on the second channel region. The method further includes forming a first work function adjustment layer on the first portion and the second portion of the gate dielectric layer. The method further includes forming a binder layer on the first work function adjustment layer. The method further includes removing the binder layer and the first work function adjustment layer from the second portion of the gate dielectric layer. The method further includes forming a second work function adjustment layer on the remaining binder layer and the second portion of the gate dielectric layer. The method further includes forming a filler layer on the second work function adjustment layer.

[0106] The embodiments may include one or more of the following features. In the method, the first work function adjustment layer comprises an n-type work function metal, and wherein the second work function adjustment layer comprises a p-type work function metal. The method further includes forming a sacrificial layer on a second portion of a gate dielectric layer between adjacent nanostructures of a second set of nanostructures before forming the first work function adjustment layer, the first work function layer being formed on the sacrificial layer and the second portion of the gate dielectric layer. Forming the sacrificial layer on the second portion of the gate dielectric layer between adjacent nanostructures of the second set of nanostructures further includes: forming the first sacrificial layer on a first portion and a second portion of the gate dielectric layer; trimming the first sacrificial layer to expose a portion of the first portion and the second portion of the gate dielectric layer, wherein after trimming, a portion of the first sacrificial layer remains between adjacent nanostructures of both the first and second sets of nanostructures; forming a second sacrificial layer on the exposed portions of the first and second portions of the gate dielectric layer and the remaining portion of the first sacrificial layer; removing the first and second sacrificial layers from the first set of nanostructures to expose the first portion of the gate dielectric layer; and trimming the second sacrificial layer to expose a portion of the second portion of the gate dielectric layer, wherein after trimming, a portion of the first sacrificial layer remains between adjacent nanostructures of the second set of nanostructures. Forming the first work function adjustment layer involves depositing titanium aluminum carbide via an ALD process, performing the ALD process using titanium chloride and triethylaluminum, executing the ALD process at a temperature ranging from 100°C to 600°C, and at a pressure ranging from 1 to 100 torr. The ALD process includes the same number of titanium chloride and triethylaluminum pulses in each ALD cycle. The ALD process also includes more triethylaluminum pulses in each ALD cycle than titanium chloride. The method further includes forming a protective layer on the first work function adjustment layer on the first set of nanostructures, with an adhesive layer formed on the protective layer of the first set of nanostructures. The protective layer comprises amorphous silicon.

[0107] The embodiment includes a method comprising forming a first set of nanostructures and a second set of nanostructures on a substrate, the first set of nanostructures including a first channel region and the second set of nanostructures including a second channel region. The method further includes forming a first gate dielectric layer on the first channel region. The method further includes forming a second gate dielectric layer on the second channel region. The method further includes forming a sacrificial layer between the second set of nanostructures. The method further includes forming an n-type work function adjustment layer on the first gate dielectric layer, the second gate dielectric layer, and the sacrificial layer, the n-type work function adjustment layer surrounding each of the first set of nanostructures. The method further includes forming a binder layer on the n-type work function adjustment layer, the binder layer surrounding each of the first set of nanostructures. The method further includes removing the binder layer, the n-type work function adjustment layer, and the sacrificial layer from the second gate dielectric layer. The method further includes forming a p-type work function adjustment layer on the binder layer and the second gate dielectric layer of the first set of nanostructures. The method further includes forming a filler layer on the p-type work function adjustment layer.

[0108] The embodiments may include one or more of the following features. In this method, forming a sacrificial layer between the second set of nanostructures further includes: forming a first sacrificial layer on the first and second gate dielectric layers; trimming the first sacrificial layer to expose a portion of the first and second gate dielectric layers, wherein after trimming, a portion of the first sacrificial layer remains between adjacent nanostructures of both the first and second sets of nanostructures; forming a second sacrificial layer on the exposed portions of the first and second gate dielectric layers and the remaining portions of the first sacrificial layer; removing the first and second sacrificial layers from the first set of nanostructures to expose the first gate dielectric layer; and trimming the second sacrificial layer to expose a portion of the second gate dielectric layer, wherein after trimming, a portion of the first sacrificial layer remains between adjacent nanostructures of the second set of nanostructures. Forming an n-type work function adjustment layer includes depositing titanium aluminum carbide via an ALD process, the ALD process including performing multiple ALD cycles, wherein each ALD cycle includes pulses of titanium chloride and triethylaluminum, the ALD process being performed at a temperature ranging from 100°C to 600°C, and at a pressure ranging from 1 to 100 torr, wherein the ALD process includes more triethylaluminum pulses than titanium chloride in each ALD cycle.

[0109] The foregoing has described components of several embodiments, enabling those skilled in the art to better understand the various embodiments of the present invention. Those skilled in the art should understand that other processes and structures can be readily designed or modified based on the present invention to achieve the same objectives and / or realize the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent structures do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device, comprising: A first set of nanostructures is located on a substrate, and the first set of nanostructures includes a first channel region; A second set of nanostructures is located on the substrate, and the second set of nanostructures includes a second channel region; A gate dielectric layer surrounds each of the first set of nanostructures and the second set of nanostructures; A first work function adjustment layer is located on and in direct contact with the gate dielectric layer of the first group of nanostructures. The first work function adjustment layer surrounds each of the first group of nanostructures. The first work function adjustment layer includes an n-type work function metal. A glue layer is located on the first work function adjustment layer, the glue layer surrounding each of the first set of nanostructures; A protective layer is located between the first work function adjustment layer and the adhesive layer of the first group of nanostructures, the protective layer surrounding each of the first group of nanostructures; The second work function adjustment layer is located on the adhesive layer of the first group of nanostructures and the gate dielectric layer of the second group of nanostructures. The second work function adjustment layer includes a p-type work function metal, which is different from the n-type work function metal. as well as The filling layer is located on top of the second work function adjustment layer. The protective layer directly contacts the first work function adjustment layer, and the second work function adjustment layer directly contacts the gate dielectric layer on the second set of nanostructures.

2. The semiconductor device of claim 1, wherein, The adhesive layer includes titanium nitride, titanium aluminum carbide, tantalum aluminum carbide, and silicon-doped tantalum aluminum.

3. The semiconductor device of claim 1, wherein, The protective layer has a thickness ranging from 0.1 nm to 10 nm.

4. The semiconductor device of claim 3, wherein, The protective layer comprises amorphous silicon.

5. The semiconductor device according to claim 4, wherein, The adhesive layer separates from and fills the region between corresponding portions of the protective layer on adjacent nanostructures of the first set of nanostructures.

6. The semiconductor device according to claim 1, wherein, The adhesive layer separates from and fills the region between corresponding portions of the first work function adjustment layer on adjacent nanostructures of the first group of nanostructures.

7. The semiconductor device according to claim 1, wherein, The second work function adjustment layer separates and fills the region between corresponding portions of the gate dielectric layer on adjacent nanostructures of the second set of nanostructures.

8. The semiconductor device according to claim 1, wherein, The filling layer does not extend between adjacent nanostructures of the second group of nanostructures.

9. A method for forming a semiconductor device, comprising: A first set of nanostructures and a second set of nanostructures are formed on a substrate, the first set of nanostructures including a first channel region and the second set of nanostructures including a second channel region. Remove the pseudo-gate structure from the first channel region of the first group of nanostructures and the second channel region of the second group of nanostructures; After removing the dummy gate structure, a gate dielectric layer with a first portion and a second portion is formed, the first portion being deposited on the first channel region and the second portion being deposited on the second channel region; A first sacrificial layer is formed on the first and second portions of the gate dielectric layer; The first sacrificial layer is trimmed to expose a first portion and a portion of the second portion of the gate dielectric layer, wherein, after trimming, a portion of the first sacrificial layer remains between adjacent nanostructures of both the first set of nanostructures and the second set of nanostructures. After trimming the first sacrificial layer, a first work function adjustment layer is formed on the first portion of the gate dielectric layer and the second portion of the gate dielectric layer; An adhesive layer is formed on the first work function adjustment layer; Remove the adhesive layer and the first work function adjustment layer from the second portion of the gate dielectric layer; A second work function adjustment layer is formed on the remaining adhesive layer and the second portion of the gate dielectric layer; and A filling layer is formed on the second work function adjustment layer.

10. The method for forming a semiconductor device according to claim 9, wherein, The first work function adjustment layer comprises an n-type work function metal, and the second work function adjustment layer comprises a p-type work function metal.

11. The method for forming a semiconductor device according to claim 9, wherein, Also includes: A second sacrificial layer is formed on the exposed portions of the first and second portions of the gate dielectric layer and on the remaining portions of the first sacrificial layer; Remove the first sacrificial layer and the second sacrificial layer from the first set of nanostructures to expose a first portion of the gate dielectric layer; as well as The second sacrificial layer is trimmed to expose a portion of the second portion of the gate dielectric layer, wherein, after trimming, a portion of the first sacrificial layer remains between adjacent nanostructures of the second set of nanostructures.

12. The method for forming a semiconductor device according to claim 9, wherein, Forming the first work function adjustment layer includes depositing titanium aluminum carbide by an ALD process, wherein the ALD process is performed using titanium chloride and triethylaluminum, the ALD process is performed at a temperature ranging from 100°C to 600°C, and the ALD process is performed at a pressure ranging from 1 to 100 torr.

13. The method for forming a semiconductor device according to claim 12, wherein, The ALD process includes the same number of pulses of titanium chloride and triethylaluminum in each ALD cycle.

14. The method according to claim 12, wherein, The ALD process includes more pulses of triethylaluminum than titanium chloride in each ALD cycle.

15. The method for forming a semiconductor device according to claim 9, further comprising: A protective layer is formed on the first work function adjustment layer on the first group of nanostructures, and the adhesive layer is formed on the protective layer on the first group of nanostructures.

16. The method of forming a semiconductor device according to claim 15, wherein, The protective layer comprises amorphous silicon.

17. A method of forming a semiconductor device, comprising: A first set of nanostructures and a second set of nanostructures are formed on a substrate, the first set of nanostructures including a first channel region and the second set of nanostructures including a second channel region. Remove the pseudo-gate structure from the first channel region of the first group of nanostructures and the second channel region of the second group of nanostructures; After removing the dummy gate structure, a first gate dielectric layer is formed on the first channel region; After removing the dummy gate structure, a second gate dielectric layer is formed on the second channel region; A sacrificial layer is formed between the second group of nanostructures, and the sacrificial layer is merged between adjacent nanostructures of the second group of nanostructures; An n-type work function adjustment layer is formed on the first gate dielectric layer, the second gate dielectric layer and the sacrificial layer, the n-type work function adjustment layer surrounding each of the first group of nanostructures; A glue layer is formed on the n-type work function adjustment layer, the glue layer surrounding each of the first group of nanostructures; Remove the adhesive layer, the n-type work function adjustment layer, and the sacrificial layer from the second gate dielectric layer; A p-type work function adjustment layer is formed on the adhesive layer of the first group of nanostructures and the second gate dielectric layer; as well as A filling layer is formed on the p-type work function adjustment layer.

18. The method of forming a semiconductor device according to claim 17, wherein, Forming a sacrificial layer between the second group of nanostructures also includes: A first sacrificial layer is formed on the first gate dielectric layer and the second gate dielectric layer; The first sacrificial layer is trimmed to expose a portion of the first gate dielectric layer and the second gate dielectric layer, wherein after trimming, a portion of the first sacrificial layer remains between adjacent nanostructures of both the first set of nanostructures and the second set of nanostructures. A second sacrificial layer is formed on the exposed portions of the first gate dielectric layer and the second gate dielectric layer, as well as on the remaining portion of the first sacrificial layer; Remove the first sacrificial layer and the second sacrificial layer from the first set of nanostructures to expose the first gate dielectric layer; and The second sacrificial layer is trimmed to expose a portion of the second gate dielectric layer, wherein, after trimming, a portion of the first sacrificial layer remains between adjacent nanostructures of the second set of nanostructures.

19. The method of forming a semiconductor device according to claim 17, wherein, Forming the n-type work function adjustment layer includes depositing titanium aluminum carbide via an ALD process, the ALD process comprising performing multiple ALD cycles, wherein each ALD cycle includes pulses of titanium chloride and triethylaluminum, the ALD process being performed at a temperature ranging from 100°C to 600°C, the ALD process being performed at a pressure ranging from 1 to 100 torr, wherein each ALD cycle includes more pulses of triethylaluminum than titanium chloride.

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