Semiconductor device and method of manufacturing the same

Abstract

Embodiments of the present application provide a semiconductor device capable of suppressing adverse effects of pads of a bonded object on surrounding insulating films and a manufacturing method thereof. The semiconductor device of the embodiments includes a lower wiring layer including a plurality of lower wirings and a plurality of lower pads provided on the lower wirings. The device further includes a plurality of upper pads provided on the lower pads and connected to the lower pads, and an upper wiring layer including a plurality of upper wirings provided on the upper pads. Furthermore, the lower pads include a plurality of first pads and a plurality of second pads. Furthermore, the upper pads include a plurality of third pads having lower surfaces larger in area than upper surfaces of the second pads and provided on the second pads, and a plurality of fourth pads having lower surfaces smaller in area than upper surfaces of the first pads and provided on the first pads.

Description

[0001] Related applications

[0002] This application enjoys priority based on Japanese Patent Application No. 2021-029074 (filed on February 25, 2021). This application incorporates the entire contents of the said basic application by reference. Technical Field

[0003] The embodiments disclosed herein relate to a semiconductor device and a method for manufacturing the same. Background Technology

[0004] In the process of manufacturing semiconductor devices by bonding metal pads in one wafer to metal pads in other wafers, there are concerns that the metal pads may have an adverse effect on the surrounding interlayer insulating film. Summary of the Invention

[0005] The problem to be solved by the present invention is to provide a semiconductor device and a method thereof that can suppress the adverse effects of the bonding pads of the bonding object on the surrounding insulating film.

[0006] The semiconductor device of the embodiment includes: a lower wiring layer comprising a plurality of lower wirings; and a plurality of lower pads disposed on the lower wirings. The device further includes: a plurality of upper pads disposed on the lower pads and connected to the lower pads; and an upper wiring layer comprising a plurality of upper wirings disposed on the upper pads. Furthermore, the lower pads include a plurality of first pads and a plurality of second pads. Furthermore, the upper pads include: a plurality of third pads having a lower surface area larger than the upper surface of the second pads and disposed on the second pads; and a plurality of fourth pads having a lower surface area smaller than the upper surface of the first pads and disposed on the first pads. Attached Figure Description

[0007] Figure 1 This is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0008] Figure 2 This is a cross-sectional view showing the structure of a semiconductor device of a comparative example of the first embodiment.

[0009] Figure 3 This is another cross-sectional view showing the structure of the semiconductor device of the comparative example of the first embodiment.

[0010] Figure 4 This is another cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0011] Figure 5 (a) and (b) are top views showing the structure of the lower substrate and the upper substrate in the first embodiment.

[0012] Figure 6 This is a graph showing the relationship between the pad spacing and occupancy rate of the semiconductor device in the first embodiment.

[0013] Figure 7 (a) and (b) are top views showing the structure of the lower substrate and the upper substrate in the first variation of the first embodiment.

[0014] Figure 8 (a) and (b) are top views showing the structure of the lower substrate and the upper substrate in the second variation of the first embodiment.

[0015] Figure 9 (a) and (b) are top views showing the structure of the lower substrate and the upper substrate in the third variation of the first embodiment.

[0016] Figure 10 This is a graph showing the relationship between the pad spacing and occupancy rate of the semiconductor device in the third variation of the first embodiment.

[0017] Figure 11 (a) and (b) are cross-sectional views (1 / 5) showing the manufacturing method of the semiconductor device according to the second embodiment.

[0018] Figure 12 (a) and (b) are cross-sectional views (2 / 5) showing the manufacturing method of the semiconductor device according to the second embodiment.

[0019] Figure 13 (a) and (b) are cross-sectional views (3 / 5) showing the manufacturing method of the semiconductor device according to the second embodiment.

[0020] Figure 14 (a) and (b) are cross-sectional views (4 / 5) showing the manufacturing method of the semiconductor device according to the second embodiment.

[0021] Figure 15 This is a cross-sectional view (5 / 5) showing the manufacturing method of the semiconductor device according to the second embodiment. Detailed Implementation

[0022] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. Figures 1-15 In the text, identical symbols are used to annotate identical elements, and repeated explanations are omitted.

[0023] (First Embodiment)

[0024] Figure 1 This is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0025] The semiconductor device of this embodiment includes a lower substrate 1 and an upper substrate 2 disposed on the lower substrate 1. The semiconductor device of this embodiment is manufactured, for example, by bonding the lower substrate 1 and the upper substrate 2 together. Figure 1 This indicates the bonding surface (boundary surface) S between the lower substrate 1 and the upper substrate 2. The semiconductor device in this embodiment is, for example, a 3D memory or an image sensor.

[0026] Figure 1 The X, Y, and Z directions represent mutually perpendicular directions. In this specification, the +Z direction is treated as the upward direction, and the -Z direction as the downward direction. The -Z direction may or may not align with the direction of gravity.

[0027] The lower substrate 1 includes a semiconductor substrate 11, an interlayer insulating film 12, multiple interlayer plugs 13, a wiring layer 14, an insulating film 15, an interlayer insulating film 16, and multiple metal pads 17. Each wiring in the wiring layer 14 includes a barrier metal layer 14a and a wiring material layer 14b. Each metal pad 17 includes a barrier metal layer 17a and a pad material layer 17b. The wiring layer 14 is an example of a lower wiring layer, each wiring in the wiring layer 14 is an example of a lower wiring layer, and each metal pad 17 is an example of a lower pad. Figure 1 As an example, this represents 5 interlayer plugs 13, 5 wirings within the wiring layer 14, and 5 metal pads 17.

[0028] The upper substrate 2 includes a semiconductor substrate 21, an interlayer insulating film 22, multiple interlayer plugs 23, a wiring layer 24, an insulating film 25, an interlayer insulating film 26, and multiple metal pads 27. Each wiring in the wiring layer 24 includes a barrier metal layer 24a and a wiring material layer 24b. Each metal pad 27 includes a barrier metal layer 27a and a pad material layer 27b. The wiring layer 24 is an example of an upper wiring layer, each wiring in the wiring layer 24 is an example of upper wiring, and each metal pad 27 is an example of an upper pad. Figure 1 As an example, this section shows five interlayer plugs 23, five wirings within the wiring layer 24, and five metal pads 27. Alternatively, the upper substrate 2 may not include a semiconductor substrate 21.

[0029] Semiconductor substrate 11 is, for example, a silicon substrate. An interlayer insulating film 12 is formed above semiconductor substrate 11. A dielectric plug 13 is formed above semiconductor substrate 11 within interlayer insulating film 12. A wiring layer 14 is formed within interlayer insulating film 12 on dielectric plug 13. Figure 1 In this configuration, five wirings within the wiring layer 14 are respectively disposed on five interlayer plugs 13 and connected to the interlayer plugs 13. The wiring material layer 14b is, for example, an Al (aluminum) layer, a W (tungsten) layer, or a Cu (copper) layer.

[0030] An insulating film 15 is formed on the interlayer insulating film 12 and the wiring layer 14. An interlayer insulating film 16 is formed on the insulating film 15. Metal pads 17 are formed on the wiring layer 14 within the insulating film 15 and the interlayer insulating film 16. Figure 1 In this configuration, five metal pads 17 are respectively disposed on five wirings within the wiring layer 14 and connected to the wirings. The pad material layer 17b is, for example, a Cu layer. An adhesion surface S is formed on the upper surface of the metal pads 17 or the upper surface of the interlayer insulating film 16. When the insulating film 15 forms an opening for the metal pads 17 within the interlayer insulating film 16 and the insulating film 15, it is used as an etching stop layer.

[0031] Interlayer insulating film 26 is formed on interlayer insulating film 16 and metal pad 17. Insulating film 25 is formed on interlayer insulating film 26. Metal pad 27 is formed on metal pad 17 within interlayer insulating film 26 and insulating film 25. Figure 1 In this configuration, five metal pads 27 are respectively disposed on five metal pads 17 and are connected to the metal pads 17. As a result, the upper substrate 2 is electrically connected to the lower substrate 1. The pad material layer 27b is, for example, a Cu layer. A bonding surface S is formed on the lower surface of the metal pads 27 or the lower surface of the interlayer insulating film 26. When the insulating film 25 forms an opening for the metal pads 27 within the interlayer insulating film 26 and the insulating film 25, it is used as an etching stop layer.

[0032] An interlayer insulating film 22 is formed on the insulating film 25. A wiring layer 24 is formed within the interlayer insulating film 22 on the metal pads 27. An interlayer plug 23 is formed within the interlayer insulating film 22 on the wiring layer 24. A semiconductor substrate 21 is formed above the interlayer insulating film 22 and the interlayer plug 23. The semiconductor substrate 21 is, for example, a silicon substrate. Figure 1 In the wiring layer 24, five wirings are respectively disposed on five metal pads 27 and connected to the metal pads 27. The wiring material layer 24b is, for example, an Al layer, a W layer, or a Cu layer. Figure 1 The five interlayer plugs 23 are further disposed on the five wirings in the wiring layer 24 and connected to the wirings.

[0033] In this embodiment, the metal pads 17 and 27 have a hole-free structure. Therefore, the metal pad 17 is disposed on the wiring layer 14 without passing through an interlayer plug and is connected to the wiring layer 14. Furthermore, the metal pad 27 is disposed under the wiring layer 24 without passing through an interlayer plug and is connected to the wiring layer 24.

[0034] Furthermore, the metal pads 17 and 27 in this embodiment do not include dummy pads. Dummy pads are metal pads that are not electrically connected to the routing layer or the interposer. Therefore, the metal pads 17 and 27 in this embodiment do not include metal pad 17 that is not electrically connected to the routing layer 14, or metal pad 27 that is not electrically connected to the routing layer 24.

[0035] When metal pads 17 and 27 are constructed using an interlayer plug, if they contain dummy pads, these dummy pads could potentially become an obstacle when determining the routing layout within routing layers 14 and 24. Therefore, when metal pads 17 and 27 are constructed using an interlayer plug, it is ideal that they do not contain dummy pads. Therefore, as described above, the metal pads 17 and 27 of this embodiment do not contain dummy pads.

[0036] Alternatively, one or both of the metal pads 17 and 27 may not employ a hole-free construction. In this case, one or both of the metal pads 17 and 27 may also include dummy pads. Furthermore, each wiring in the wiring layer 14 or each wiring in the wiring layer 24 may have any planar shape, for example, it may have a straight line shape extending along the X direction, Y direction, or other directions, or it may have a curved shape extending along various directions.

[0037] Next, continue to refer to Figure 1 This section provides more detailed information about the metal pads 17 and 27 in this embodiment.

[0038] The metal pads 17 in this embodiment include a plurality of large pads 17L and a plurality of small pads 17S. The area of ​​the upper surface of each small pad 17S is set to be smaller than the area of ​​the upper surface of each large pad 17L. In other words, the planar shape of each small pad 17S is set to be smaller than the planar shape of each large pad 17L. The large pads 17L are an example of the first pad, and the small pads 17S are an example of the second pad.

[0039] Furthermore, the metal pads 27 in this embodiment include a plurality of large pads 27L and a plurality of small pads 27S. The area of ​​the lower surface of each small pad 27S is set to be smaller than the area of ​​the lower surface of each large pad 27L. In other words, the planar shape of each small pad 27S is set to be smaller than the planar shape of each large pad 27L. The large pad 27L is an example of the third pad, and the small pad 27S is an example of the fourth pad.

[0040] In this embodiment, the area of ​​the lower surface of each large pad 27L is set to be equal to the area of ​​the upper surface of each large pad 17L, and is set to be larger than the area of ​​the upper surface of each small pad 17S. In this embodiment, the area of ​​the lower surface of each small pad 27S is further set to be smaller than the area of ​​the upper surface of each large pad 17L, and is set to be equal to the area of ​​the upper surface of each small pad 17S. For example, when the planar shape of the metal pads 17 and 27 is square, the length of one side of the upper surface of the small pad 17S or the length of one side of the lower surface of the small pad 27S is set to be shorter than the length of one side of the upper surface of the large pad 17L or the length of one side of the lower surface of the large pad 27L.

[0041] In this embodiment, large pads 27L and small pads 17S are paired, and small pads 27S and large pads 17L are paired. Therefore, each large pad 27L is disposed on one small pad 17S, and each small pad 27S is disposed on one large pad 17L. These pairs are referred to as pad pairs. The semiconductor device of this embodiment includes multiple pad pairs in which one large pad 27L is disposed on one small pad 17S, and also multiple pad pairs in which one small pad 27S is disposed on one large pad 17L. Figure 1 This indicates that 3 pad pairs are the first type of pad pair, and 2 pad pairs are the second type of pad pair. On the other hand, the semiconductor device of this embodiment does not have pad pairs in which a large pad 27L is arranged on a large pad 17L, or pad pairs in which a small pad 27S is arranged on a small pad 17S.

[0042] As described above, in this embodiment, large pads 27L and small pads 17S are paired, and small pads 27S and large pads 17L are paired. If large pads 27L and 27S are paired, or small pads 27S and 27S are paired, then positional misalignment between metal pads 17 and 27 becomes a problem. For example, if positional misalignment occurs when large pads 27L are positioned on large pads 17L, the contact area between the upper and lower surfaces of large pads 17L and 27L becomes smaller, and the contact resistance between large pads 17L and 27L increases. On the other hand, even if positional misalignment occurs when large pads 27L are positioned on small pads 17S, if the misalignment is small, the contact area will not change, and therefore the contact resistance will not change. Therefore, according to this embodiment, even if positional misalignment occurs between metal pads 17 and 27, the problem accompanying positional misalignment can be suppressed.

[0043] Furthermore, the semiconductor device of this embodiment includes multiple pad pairs on which large pads 27L are disposed, and multiple pad pairs on which small pads 27S are disposed, respectively. For advantages of this configuration, please refer to [reference needed]. Figures 2-4 Please provide an explanation.

[0044] Figure 2 This is a cross-sectional view showing the structure of a semiconductor device of a comparative example of the first embodiment.

[0045] The semiconductor device of this comparative example has the same constituent components as the semiconductor device of this embodiment. However, the semiconductor device of this comparative example has a pad pair on which a large pad 27L is disposed on a small pad 17S, but does not have a pad pair on which a small pad 27S is disposed on a large pad 17L.

[0046] Figure 3 This is another cross-sectional view showing the structure of the semiconductor device of the comparative example of the first embodiment.

[0047] Figure 3 The sectional view is equivalent to Figure 2 A scaled-down view of the cross-section. Figure 3 Region R1, which includes metal pads 17 and 27, and region R2, which does not include metal pads 17 and 27, are represented as regions within the semiconductor device of this comparative example.

[0048] Here, the percentage of the metal pad 17 on the upper surface of the lower substrate 1 or the percentage of the metal pad 27 on the lower surface of the upper substrate 2 will be explained. The upper surface of the lower substrate 1 or the lower surface of the upper substrate 2 forms the bonding surface S between the lower substrate 1 and the upper substrate 2.

[0049] The occupancy of the metal pads 17 on the upper surface of the lower substrate 1 differs in regions R1 and R2. The occupancy in region R1 is given by dividing the area of ​​the upper surface of all metal pads 17 within region R1 by the area of ​​the upper surface of the lower substrate 1 within region R1. Conversely, the occupancy in region R2 is given by dividing the area of ​​the upper surface of all metal pads 17 within region R2 by the area of ​​the upper surface of the lower substrate 1 within region R2. Since region R2 does not contain metal pads 17, the occupancy of the metal pads 17 in region R2 is zero.

[0050] Similarly, the occupancy of the metal pads 27 on the lower surface of the upper substrate 2 differs in regions R1 and R2. The occupancy in region R1 is given by dividing the area of ​​the lower surface of all metal pads 27 within region R1 by the area of ​​the lower surface of the upper substrate 2 within region R1. On the other hand, the occupancy in region R2 is given by dividing the area of ​​the lower surface of all metal pads 27 within region R2 by the area of ​​the lower surface of the upper substrate 2 within region R2. Since region R2 does not contain metal pads 27, the occupancy of the metal pads 27 in region R2 is zero.

[0051] In this comparative example, the occupancy rate of metal pads 27 in region R1 is greater than that of metal pads 17 in region R1. This is because the metal pads 27 of the upper substrate 2 only contain large pads 27L, while the metal pads 17 of the lower substrate 1 only contain small pads 17S.

[0052] As a result, within the upper substrate 2, the difference between the occupancy rate of the metal pads 27 in region R1 and the occupancy rate of the metal pads 27 in region R2 becomes larger; that is, the difference in the density of the metal pads 27 between regions R1 and R2 becomes larger. This difference in pad density adversely affects the CMP (Chemical Mechanical Polishing) used to planarize the lower surface of the upper substrate 2. Generally, before bonding the lower substrate 1 to the upper substrate 2, CMP is used to planarize the upper surface of the lower substrate 1 or the lower surface of the upper substrate 2. At this time, if the difference in the density of the metal pads 27 between regions R1 and R2 is large, then the lower surface of the upper substrate 2 in region R2 is cut more than the lower surface of the upper substrate 2 in region R1, resulting in a step difference between the lower surfaces. As a result, when bonding the lower substrate 1 to the upper substrate 2, there is a concern that a gap V may be generated on the lower surface of the upper substrate 2 in region R1, or that poor bonding of the metal pads 17 and 27 in region R2 may occur.

[0053] This problem may also occur when there is a large difference in the occupancy rate of metal pads 17 in region R1 and region R2 within the lower substrate 1. Therefore, ideally, the difference in pad density between region R1 and region R2 should be reduced in both the upper substrate 2 and the lower substrate 1.

[0054] Figure 4 This is another cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0055] Figure 4 The sectional view is equivalent to Figure 1 A scaled-down view of the cross-section. Figure 4 and Figure 3Similarly, the regions R1 containing metal pads 17 and 27 and the region R2 not containing metal pads 17 and 27 are represented as regions within the semiconductor device of this embodiment.

[0056] In this embodiment, the metal pads 27 of the upper substrate 2 include large pads 27L and small pads 27S, and the metal pads 17 of the lower substrate 1 also include large pads 17L and small pads 17S. Therefore, according to this embodiment, the occupancy rate of the metal pads 27 in region R1 and the occupancy rate of the metal pads 17 in region R1 can both be set to relatively small values. In other words, according to this embodiment, the difference in pad density between region R1 and region R2 can be reduced in both the upper substrate 2 and the lower substrate 1. This helps to suppress the voids V or poor bonding.

[0057] Furthermore, the difference in pad coarseness and density can be reduced, for example, by configuring dummy pads within region R2. However, as mentioned above, when the metal pads 17 and 27 employ a via-less structure, it can be difficult to configure dummy pads. According to this embodiment, the metal pads 27 of the upper substrate 2 include large pads 27L and small pads 27S, and the metal pads 17 of the lower substrate 1 also include large pads 17L and small pads 17S, thereby reducing the difference in pad coarseness and density without using dummy pads. In addition, the metal pads 17 and 27 of this embodiment can be applied to semiconductor devices that use dummy pads and semiconductor devices that do not use dummy pads.

[0058] Here, the proportions of the large pad 17L or the large pad 27L in the upper surface of the lower substrate 1 or the lower surface of the upper substrate 2 within region R1 are explained.

[0059] The proportion of large pads 17L within region R1 is given by dividing the total number of large pads 17L within region R1 by the total number of metal pads 17 within region R1. In other words, the proportion represents the ratio of the number of large pads 17L within region R1 to the total number of metal pads 17 within region R1. Similarly, the proportion of large pads 27L within region R1 is given by dividing the total number of large pads 27L within region R1 by the total number of metal pads 27 within region R1. In other words, the proportion represents the ratio of the number of large pads 27L within region R1 to the total number of metal pads 27 within region R1. It should be noted that the term "occupancy" is given by dividing one area by another, whereas the "proportion" described here is given by dividing one number by another.

[0060] In this embodiment, it is desirable to set the proportion of large pads 27L within region R1 to 40-60% (e.g., approximately 50%). Similarly, in this embodiment, it is desirable to set the proportion of large pads 17L within region R1 to 40-60% (e.g., approximately 50%). This, for example, can reduce pad density differences in both the lower substrate 1 and the upper substrate 2, or suppress voids V or poor bonding in both the lower substrate 1 and the upper substrate 2. Region R1 is an example of a specific region.

[0061] Figure 5 This is a top view showing the structure of the lower substrate 1 and the upper substrate 2 in the first embodiment.

[0062] Figure 5 (a) shows the view from above of the metal pads 17 in the lower substrate 1. In this embodiment, the metal pads 17 are arranged at the intersection of multiple straight lines extending in the Y direction and multiple straight lines extending in the X direction, resulting in a square grid pattern. Figure 5 (a) represents line A-A' as an example of the former type of straight line, and line B-B' as an example of the latter type of straight line.

[0063] Along line A-A', multiple large pads 17L and multiple small pads 17S are alternately arranged. Similarly, along line B-B', multiple large pads 17L and multiple small pads 17S are alternately arranged. This is also true on straight lines other than line A-A' extending in the Y direction, or on straight lines other than line B-B' extending in the X direction. According to this arrangement, the proportion of large pads 17L can be made approximately uniform across the upper surface of the lower substrate 1 within region R1, that is, the uniformity of the proportion of large pads 17L can be improved.

[0064] Figure 5 (a) Further, the width W1 in the Y direction of the upper surface of the large pad 17L and the width W2 in the Y direction of the upper surface of the small pad 17S are shown. In this embodiment, the upper surfaces of the large pad 17L and the small pad 17S are, for example, squares. Therefore, width W1 represents the length of one side of the planar shape of the large pad 17L, which is a square, and width W2 represents the length of one side of the planar shape of the small pad 17S, which is a square. Width W1 is set to be longer than width W2 (W1 > W2), ideally set to, for example, more than 1.1 times the width W2 (W1 ≥ 1.1 × W2). Width W1 is, for example, 400 nm. Width W2 is, for example, 200 nm.

[0065] Figure 5(b) shows the view from above of the metal pads 27 within the upper substrate 2. In this embodiment, the metal pads 27 are also arranged at the intersection of multiple straight lines extending along the Y direction and multiple straight lines extending along the X direction, resulting in a square grid pattern. Figure 5 (b) and Figure 5 (a) Similarly, A-A' is shown as an example of the former type of straight line, and B-B' is shown as an example of the latter type of straight line.

[0066] Figure 5 (b) The shape or arrangement of the metal pad 27 shown is similar to Figure 5 The shape or configuration of the metal pads 17 shown in (a) is the same. However, Figure 5 (b) shows the location of the large solder pad 27L and Figure 5 (a) corresponds to the position of the small pad 17S. On the other hand, Figure 5 (b) shows the location of the small pad 27S and Figure 5 (a) shows the corresponding positions of the large pad 17L. As a result, the large pad 27L is paired with the small pad 17S, and the small pad 27S is paired with the large pad 17L.

[0067] Figure 6 This is a graph showing the relationship between the pad spacing and occupancy rate of the semiconductor device in the first embodiment.

[0068] exist Figure 6 In the diagram, curve A represents the relationship between the pad spacing and occupancy of the lower substrate 1 or the upper substrate 2 in this embodiment. Curve B1 represents the relationship between the pad spacing and occupancy of the lower substrate 1 in the comparative example. Curve B2 represents the relationship between the pad spacing and occupancy of the upper substrate 2 in the comparative example.

[0069] Figure 6 The horizontal axis represents the spacing between metal pads 17 and 27. Figure 6 The occupancy of the vertical axis represents the occupancy of the metal pads 17 and 27 within region R1. The upper substrate 2 of the comparative example contains only large pads 27L, and the lower substrate 1 of the comparative example contains only small pads 17S. Therefore, with the same pad spacing, the occupancy (B2) of the upper substrate 2 of the comparative example is greater than the occupancy (B1) of the lower substrate 1 of the comparative example.

[0070] In the upper substrate 2 of the comparative example, the occupancy (B2) of the metal pads 27 in region R1 is increased, and the difference between the occupancy in region R1 and the occupancy (=0%) in region R2 is increased. This causes voids V or poor contact in the comparative example. On the other hand, in the upper substrate 2 of this embodiment, the occupancy (A) of the metal pads 27 in region R1 is smaller than that in the comparative example, and the difference between the occupancy in region R1 and the occupancy (=0%) in region R2 is smaller. Therefore, according to this embodiment, voids V or poor contact can be suppressed.

[0071] Figure 7 This is a top view showing the structure of the lower substrate 1 and the upper substrate 2 in the first variation of the first embodiment.

[0072] Figure 7 (a) shows the view from above of the metal pads 17 in the lower substrate 1. In this variation, the metal pads 17 are arranged at the intersection of multiple straight lines extending in the Y direction and multiple straight lines extending in the X direction, resulting in a square grid pattern. Figure 7 (a) represents lines A-A' and C-C' as examples of the former type of straight line, and line B-B' as an example of the latter type of straight line.

[0073] exist Figure 7 In (a), the straight lines extending along the Y direction alternately include multiple straight lines, such as line C-C', which only contain large pads 17L, and multiple straight lines, such as line A-A', which only contain small pads 17S. The former type of straight line is an example of the first straight line, and the latter type of straight line is an example of the second straight line, with the Y direction being an example of a specific direction. On the other hand, along line B-B', multiple large pads 17L and multiple small pads 17S are alternately arranged. This is also the case on straight lines other than line B-B' extending along the X direction. According to this square lattice configuration, the proportion of large pads 17L can be made approximately uniform throughout the upper surface of the lower substrate 1 within region R1, that is, the uniformity of the proportion of large pads 17L can be improved.

[0074] Figure 7 (b) shows the view from above of the metal pads 27 within the upper substrate 2. In this variation, the metal pads 27 are also arranged at the intersection of multiple straight lines extending along the Y direction and multiple straight lines extending along the X direction, resulting in a square grid pattern. Figure 7 (b) and Figure 7 (a) Similarly, A-A' and C-C' are examples of the former type of straight line, and B-B' is an example of the latter type of straight line.

[0075] Figure 7 (b) The shape or arrangement of the metal pad 27 shown is similar to Figure 7The shape or configuration of the metal pads 17 shown in (a) is the same. However, Figure 7 (b) shows the location of the large solder pad 27L and Figure 7 (a) corresponds to the position of the small pad 17S. On the other hand, Figure 7 (b) shows the location of the small pad 27S and Figure 7 (a) shows the corresponding positions of the large pad 17L. As a result, the large pad 27L is paired with the small pad 17S, and the small pad 27S is paired with the large pad 17L.

[0076] Figure 8 This is a top view showing the structure of the lower substrate 1 and the upper substrate 2 in the second variation of the first embodiment.

[0077] Figure 8 (a) shows the view from above of the metal pads 17 in the lower substrate 1. In this variation, the metal pads 17 are arranged at the intersection of multiple straight lines extending in the inclined direction and multiple straight lines extending in the X direction, resulting in a square grid pattern. Figure 8 (a) shows line D-D' as an example of the first type of straight line, and lines E-E' and F-F' as examples of the second type of straight line. The first type of straight line and the second type of straight line are the same, extending parallel to each other.

[0078] exist Figure 8 In (a), the straight lines extending along the X direction alternately include multiple straight lines, such as line F-F', which only contain large pads 17L, and multiple straight lines, such as line E-E', which only contain small pads 17S. The former type of straight line is an example of the first straight line, and the latter type of straight line is an example of the second straight line, with the X direction being an example of a specific direction. On the other hand, along line D-D', multiple large pads 17L and multiple small pads 17S are alternately arranged. This is also the case on straight lines other than line D-D', which extends along the inclined direction. According to this triangular lattice configuration, the proportion of large pads 17L can be made approximately uniform across the upper surface of the lower substrate 1 within region R1, that is, the uniformity of the proportion of large pads 17L can be improved.

[0079] Figure 8 (b) shows the view from above of the metal pads 27 within the upper substrate 2. In this variation, the metal pads 27 are also positioned at the intersection of multiple straight lines extending in the inclined direction and multiple straight lines extending in the X direction, resulting in a triangular lattice configuration. Figure 8 (b) and Figure 8 (a) Similarly, D-D' is shown as an example of the first type of straight line, and E-E' and F-F' are shown as examples of the second type of straight line. The first and second types of straight lines extend parallel to each other.

[0080] Figure 8 (b) The shape or arrangement of the metal pad 27 shown is similar to Figure 8 The shape or configuration of the metal pads 17 shown in (a) is the same. However, Figure 8 (b) shows the location of the large solder pad 27L and Figure 8 (a) corresponds to the position of the small pad 17S. On the other hand, Figure 8 (b) shows the location of the small pad 27S and Figure 8 (a) shows the corresponding positions of the large pad 17L. As a result, the large pad 27L is paired with the small pad 17S, and the small pad 27S is paired with the large pad 17L.

[0081] Figure 9 This is a top view showing the structure of the lower substrate 1 and the upper substrate 2 in the third variation of the first embodiment.

[0082] Figure 9 (a) shows the metal pads 17 within the lower substrate 1 as viewed from above. In this variation, the metal pads 17 are arranged at the intersections of multiple straight lines extending in the Y direction and multiple straight lines extending in the X direction, resulting in a square grid pattern. However, in this variation, the metal pads 17 are arranged in a square grid pattern with large pads 17L and small pads 17S randomly arranged at the intersections. This arrangement increases the freedom of routing layout, for example, within the wiring layer 14. For example, by arranging more small pads 17S in areas with higher wiring density and more large pads 17L in areas with lower wiring density, the metal pads 17 can be prevented from obstructing routing.

[0083] Figure 9 (b) shows the view from above of the metal pads 27 within the upper substrate 2. In this variation, the metal pads 27 are also arranged at the intersection of multiple straight lines extending along the Y direction and multiple straight lines extending along the X direction, resulting in a square grid pattern.

[0084] Figure 9 (b) The shape or arrangement of the metal pad 27 shown is similar to Figure 9 The shape or configuration of the metal pads 17 shown in (a) is the same. However, Figure 9 (b) shows the location of the large solder pad 27L and Figure 9 (a) corresponds to the position of the small pad 17S. On the other hand, Figure 9 (b) shows the location of the small pad 27S and Figure 9 (a) shows the corresponding positions of the large pad 17L. As a result, the large pad 27L is paired with the small pad 17S, and the small pad 27S is paired with the large pad 17L.

[0085] In the upper substrate 2 of this variation, the proportion of large pads 27L in region R1 is set to approximately 60%. As a result, in the lower substrate 1 of this variation, the proportion of large pads 17L in region R1 is set to approximately 40%. This increases the freedom of routing layout within routing layer 14. This occupancy setting is used, for example, when it is desirable to prioritize increasing the freedom of routing layout within routing layer 14 over increasing the freedom of routing layout within routing layer 24.

[0086] Figure 10 This is a graph showing the relationship between the pad spacing and occupancy rate of the semiconductor device in the third variation of the first embodiment.

[0087] exist Figure 10 In the diagram, curve A1 represents the relationship between the pad spacing and occupancy of the lower substrate 1 in this variation example, and curve A2 represents the relationship between the pad spacing and occupancy of the upper substrate 2 in this variation example. Furthermore, curve B1 represents the relationship between the pad spacing and occupancy of the lower substrate 1 in the comparative example, and curve B2 represents the relationship between the pad spacing and occupancy of the upper substrate 2 in the comparative example. Figure 10 The horizontal axis represents the spacing between metal pads 17 and 27. Figure 10 The occupancy rate on the vertical axis represents the occupancy rate of metal pads 17 and 27 within region R1.

[0088] In this variation, the proportion of large pads 27L in region R1 is set to approximately 60%, and the proportion of large pads 17L in region R1 is set to approximately 40%. Therefore, with the same pad spacing, the occupancy rate (A2) of the large pads 27L on the upper substrate 2 in this variation is greater than the occupancy rate (A1) of the large pads 17L on the lower substrate 1 in this variation. However, the difference between the occupancy rate in region R1 and the occupancy rate in region R2 of the upper substrate 2 in this variation has been suppressed to be smaller than the difference in occupancy rate in the comparative example. Therefore, according to this variation, voids V or poor contact can be suppressed.

[0089] As described above, in the semiconductor device of this embodiment, large pads 27L and small pads 17S are paired, and small pads 27S and large pads 17L are paired. Therefore, according to this embodiment, the adverse effects of metal pads 17 and 27 on interlayer insulating films 16 and 26 can be suppressed; for example, the generation of voids V in interlayer insulating films 16 and 26 can be suppressed. Furthermore, according to this embodiment, poor bonding in metal pads 17 and 27 can be suppressed.

[0090] Furthermore, in this embodiment, the lower substrate 1 has two sizes of metal pads 17 (large pad 17L and small pad 17S), but it may also have three or more sizes of metal pads 17. Similarly, in this embodiment, the upper substrate 2 has two sizes of metal pads 27 (large pad 27L and small pad 27S), but it may also have three or more sizes of metal pads 27. In addition, the size of the large pad 27L may be different from the size of the large pad 17L, and the size of the small pad 27S may be different from the size of the small pad 17S.

[0091] Furthermore, the planar shape of the metal pads 17 and 27 is square in this embodiment, but it can also be other shapes (e.g., rectangle or circle).

[0092] (Second Implementation)

[0093] Figures 11-15 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to the second embodiment. The method of this embodiment is performed for manufacturing the semiconductor device of the first embodiment.

[0094] First, manufacturing Figure 11 (a) lower substrate 1', and Figure 11 (b) The upper substrate 2'. The lower substrate 1' is a wafer-like substrate used to manufacture the lower substrate 1 of the first embodiment. Similarly, the upper substrate 2' is a wafer-like substrate used to manufacture the upper substrate 2 of the first embodiment.

[0095] Figure 11 The lower substrate 1' of (a) is fabricated by forming an interlayer insulating film 12, a dielectric plug 13, a wiring layer 14, an insulating film 15, and an interlayer insulating film 16 on a semiconductor substrate 11. The wiring layer 14 is formed within the interlayer insulating film 12 in a manner that includes multiple wirings. The wiring layer 14 is electrically connected, for example, to a CMOS (Complementary Metal Oxide Semiconductor) circuit (not shown) of a 3D memory via the dielectric plug 13 beneath the wiring layer 14. The insulating film 15 and the interlayer insulating film 16 are sequentially formed on the interlayer insulating film 12 and the wiring layer 14. The insulating film 15 is, for example, a silicon nitride film with a thickness of 50 nm. The interlayer insulating film 16 is, for example, a silicon oxide film with a thickness of 250 nm.

[0096] Figure 11(b) The upper substrate 2' is fabricated by forming an interlayer insulating film 22, a dielectric plug 23, a wiring layer 24, an insulating film 25, and an interlayer insulating film 26 on a semiconductor substrate 21. The wiring layer 24 is formed within the interlayer insulating film 22 in a manner that includes multiple wirings. The wiring layer 24 is electrically connected to a memory cell array (not shown) of a 3D memory, for example, via the dielectric plug 23 beneath the wiring layer 24. The insulating film 25 and the interlayer insulating film 26 are sequentially formed on the interlayer insulating film 22 and the wiring layer 24. The insulating film 25 is, for example, a silicon nitride film with a thickness of 50 nm. The interlayer insulating film 26 is, for example, a silicon oxide film with a thickness of 250 nm.

[0097] Next, a plurality of openings 18 are formed through the interlayer insulating film 16 and the insulating film 15 using dry etching, and a plurality of openings 28 are formed through the interlayer insulating film 26 and the insulating film 25 using dry etching. Figure 12 (a) and Figure 12 (b)). As a result, the upper surface of one wiring of wiring layer 14 is exposed in each opening 18, and the upper surface of one wiring of wiring layer 24 is exposed in each opening 28. At this time, insulating films 15 and 25 are used as etch stop layers. Opening 18 is an example of a lower opening, and opening 28 is an example of an upper opening.

[0098] The opening 18 is formed in a manner comprising a plurality of large openings 18L and a plurality of small openings 18S. The large openings 18L are used to embed large pads 17L, and the small openings 18S are used to embed small pads 17S. Therefore, the opening 18 in this embodiment is formed in a planar shape having a square shape. Alternatively, the opening 18 may also be formed in a planar shape having a circular shape. For example, the planar shape of the large openings 18L is set to a circle with a diameter of 600 nm, and the planar shape of the small openings 18S is set to a circle with a diameter of 200 nm. In this embodiment, the large openings 18L and the small openings 18S are respectively formed as... Figure 5 (a) shows the large pad 17L and the small pad 17S arranged in the same layout.

[0099] The opening 28 is formed in a manner comprising a plurality of large openings 28L and a plurality of small openings 28S. The large openings 28L are used to embed large pads 27L, and the small openings 28S are used to embed small pads 27S. Therefore, the opening 28 in this embodiment is formed in a planar shape having a square shape. On the other hand, the opening 28 may also be formed in a planar shape having a circular shape. For example, the planar shape of the large openings 28L is set to a circle with a diameter of 600 nm, and the planar shape of the small openings 28S is set to a circle with a diameter of 200 nm. In this embodiment, the large openings 28L and the small openings 28S are respectively formed as... Figure 5(b) shows that the large pad 27L and the small pad 27S are configured in the same layout.

[0100] Next, a barrier metal layer 17a and a pad material layer 17b are sequentially formed on the interlayer insulating film 16, the insulating film 15, and the wiring layer 14. Similarly, a barrier metal layer 27a and a pad material layer 27b are sequentially formed on the interlayer insulating film 26, the insulating film 25, and the wiring layer 24. Figure 13 (a) and Figure 13 (b)). As a result, barrier metal layer 17a and pad material layer 17b are embedded in opening 18, and barrier metal layer 27a and pad material layer 27b are embedded in opening 28. Barrier metal layer 17a and pad material layer 17b are examples of materials for the lower pad, and barrier metal layer 27a and pad material layer 27b are examples of materials for the upper pad.

[0101] A barrier metal layer 17a is formed on the side or bottom surface of each opening 18. The barrier metal layer 17a is, for example, a Ta (tantalum) layer with a film thickness of 10 nm. A pad material layer 17b is formed inside each opening 18 to separate the barrier metal layer 17a. The pad material layer 17b is, for example, a Cu layer with a film thickness of 500 nm.

[0102] A barrier metal layer 27a is formed on the side or bottom surface of each opening 28. The barrier metal layer 27a is, for example, a Ta layer with a film thickness of 10 nm. A pad material layer 27b is formed inside each opening 28 to separate the barrier metal layer 27a. The pad material layer 27b is, for example, a Cu layer with a film thickness of 500 nm.

[0103] Next, CMP is used to planarize the surfaces of pad material layer 17b and barrier metal layer 17a, and CMP is used to planarize the surfaces of pad material layer 27b and barrier metal layer 27a. Figure 14 (a) and Figure 14 (b) The CMP is performed, for example, using a slurry containing silica particles as grinding stones and hydrogen peroxide as an oxidant.

[0104] CMP on the lower substrate 1' is performed by removing the remaining pad material layer 17b and barrier metal layer 17a outside the opening 18. As a result, the pad material layer 17b and barrier metal layer 17a are retained within the opening 18, forming metal pads 17 within the opening 18. The metal pads 17 are formed within the opening 18 in a manner that connects to the wiring layer 14. The metal pads 17 include large pads 17L and small pads 17S to form... Figure 5 The layout shown in (a) is configured such that CMP can be used to suppress the step difference that would cause voids V in the lower substrate 1'.

[0105] The CMP of the upper substrate 2' is performed by removing the remaining pad material layer 17b and barrier metal layer 27a outside the opening 28. As a result, the pad material layer 27b and barrier metal layer 27a are retained within the opening 28, forming metal pads 27 within the opening 28. The metal pads 27 are formed within the opening 28 in a manner that connects to the wiring layer 24. The large pads 27L and small pads 27S included in the metal pads 27 are formed... Figure 5 (b) shows the layout configuration. As a result, CMP can be used to suppress the step difference that would cause voids V in the upper substrate 2'.

[0106] Next, the upper substrate 2' is flipped upside down and attached to the lower substrate 1'. Figure 15 The bonding is performed as follows: a large pad 27L is disposed on a small pad 17S, the small pad 27S is disposed on the large pad 17L, and an interlayer insulating film 26 is disposed on an interlayer insulating film 16. Then, by annealing the lower substrate 1' and the upper substrate 2', the large pad 27L is bonded to the small pad 17S, the small pad 27S is bonded to the large pad 17L, and the interlayer insulating film 26 is bonded to the interlayer insulating film 16. According to this embodiment, by employing... Figure 5 (a) and Figure 5 The layout shown in (b) can suppress the formation of gaps V or poor bonding after bonding.

[0107] Then, the lower substrate 1' and the upper substrate 2' are cut into individual semiconductor devices using a dicing process. In this way, the semiconductor device of this embodiment, comprising the lower substrate 1 and the upper substrate 2, is manufactured. Alternatively, the semiconductor substrate 21 can be removed from the upper substrate 2' before dicing.

[0108] In this embodiment, the semiconductor device of the first embodiment is manufactured by bonding the lower substrate 1' to the upper substrate 2'. Therefore, according to this embodiment, the adverse effects of the metal pads 17, 27 on the interlayer insulating films 16, 26 can be suppressed; for example, the generation of voids V in the interlayer insulating films 16, 26 can be suppressed. Furthermore, according to this embodiment, poor bonding in the metal pads 17, 27 can be suppressed.

[0109] Furthermore, the method of this embodiment can also be used to manufacture semiconductor devices of the first, second, or third variation. In such cases, the large opening 18L and the small opening 18S are respectively positioned to... Figure 7 (a) Figure 8 (a) or Figure 9 (a) The large pad 17L and the small pad 17S shown are configured in the same layout. Furthermore, the large opening 28L and the small opening 28S are respectively positioned to be... Figure 7 (b) Figure 8(b) or Figure 9 (b) shows that the large pad 27L and the small pad 27S are configured in the same layout.

[0110] While several embodiments have been described above, these embodiments are merely illustrative and not intended to limit the scope of the invention. The novel apparatus and method described herein can be implemented in various other ways. Furthermore, various omissions, substitutions, and modifications can be made to the apparatus and method described herein without departing from the spirit of the invention. The appended claims and their equivalents are intended to encompass such embodiments or variations as implied in the scope or spirit of the invention.

[0111] [Explanation of Symbols]

[0112] 1: Lower substrate

[0113] 1A': Lower substrate

[0114] 2: Upper substrate

[0115] 2A': Upper substrate

[0116] 11: Semiconductor substrate

[0117] 12: Interlayer insulating film

[0118] 13: Interlayer plug

[0119] 14: Wiring Layer

[0120] 14a: Barrier metal layer

[0121] 14b: Wiring material layer

[0122] 15: Insulating film

[0123] 16: Interlayer insulating film

[0124] 17: Metal pads

[0125] 17a: Barrier metal layer

[0126] 17b: Pad material layer

[0127] 17L: Large solder pad

[0128] 17S: Small solder pad

[0129] 18: Opening

[0130] 18L: Large opening

[0131] 18S: Small opening

[0132] 21: Semiconductor substrate

[0133] 22: Interlayer insulating film

[0134] 23: Interlayer plug

[0135] 24: Wiring Layer

[0136] 24a: Barrier metal layer

[0137] 24b: Wiring material layer

[0138] 25: Insulating film

[0139] 26: Interlayer insulating film

[0140] 27: Metal pads

[0141] 27a: Barrier metal layer

[0142] 27b: Pad material layer

[0143] 27L: Large solder pad

[0144] 27S: Small solder pad

[0145] 28: Opening

[0146] 28L: Large opening

[0147] 28S: Small opening.

Claims

1. A semiconductor device comprising: The lower wiring layer contains multiple lower wirings; Multiple lower pads are provided on the lower wiring; Multiple upper pads are disposed on the lower pads and connected to the lower pads; and The upper wiring layer includes multiple upper wirings disposed on the upper pads; and The lower pads include a plurality of first pads and a plurality of second pads; The upper pad includes: a plurality of third pads having a lower surface with an area larger than the upper surface of the second pad, disposed on the second pad; and a plurality of fourth pads having a lower surface with an area smaller than the upper surface of the first pad, disposed on the first pad; The area of ​​the upper surface of the second pad is smaller than the area of ​​the upper surface of the first pad; The area of ​​the lower surface of the fourth pad is smaller than the area of ​​the lower surface of the third pad; The first pad and the fourth pad are in a one-to-one correspondence. The second pad and the third pad are in a one-to-one correspondence.

2. The semiconductor device according to claim 1, wherein The area of ​​the lower surface of the third pad is equal to the area of ​​the upper surface of the first pad. The area of ​​the lower surface of the fourth pad is equal to the area of ​​the upper surface of the second pad.

3. The semiconductor device according to claim 1, wherein the upper pad does not include the third pad disposed on the first pad, and does not include the fourth pad disposed on the second pad.

4. The semiconductor device of claim 1, wherein the lower pad and the upper pad do not include the lower pad that is not electrically connected to the lower wiring, and / or do not include the upper pad that is not electrically connected to the upper wiring.

5. The semiconductor device of claim 1, wherein the lower pad comprises the first and second pads alternately arranged on the same straight line.

6. The semiconductor device of claim 5, wherein the lower pad is configured as a square grid or a triangular grid.

7. The semiconductor device of claim 1, wherein the lower pad comprises: the first pad disposed on a plurality of first straight lines extending in a specific direction; and the second pad disposed on a plurality of second straight lines extending alternately with the first straight lines in the specific direction.

8. The semiconductor device of claim 7, wherein the lower pad is configured as a square grid or a triangular grid.

9. The semiconductor device according to claim 1, further comprising: The lower substrate includes the lower wiring layer and the lower pads; and The upper substrate includes the upper wiring layer and the upper pads; and In a specific region within the boundary surface between the lower substrate and the upper substrate, the number of the first pads is 40-60% of the number of the lower pads in the specific region, and / or the number of the third pads is 40-60% of the number of the upper pads in the specific region.

10. The semiconductor device of claim 1, wherein The lower pad is connected to the lower wiring, and / or The upper pad is connected to the upper wiring.

11. The semiconductor device of claim 1, wherein The width of the upper surface of the first pad is at least 1.1 times the width of the upper surface of the second pad. The width of the lower surface of the third pad is more than 1.1 times the width of the lower surface of the fourth pad.

12. The semiconductor device according to claim 1, wherein The width of the upper surface of the first pad is at least 1.1 times the width of the lower surface of the fourth pad. The width of the lower surface of the third pad is more than 1.1 times the width of the upper surface of the second pad.

13. A method for manufacturing a semiconductor device, comprising: A lower substrate is formed, the lower substrate comprising: a lower wiring layer including multiple lower wirings, and multiple lower pads disposed on the lower wirings. An upper substrate is formed, the upper substrate comprising: an upper wiring layer including multiple upper wirings, and multiple upper pads disposed on the upper wirings; and The upper substrate and the lower substrate are bonded together such that the upper pad is disposed on and connected to the lower pad; and The lower pad is formed to include a plurality of first pads and a plurality of second pads; The upper pad is formed to include, after bonding: a plurality of third pads having a lower surface with an area larger than the upper surface of the second pad, disposed on the second pad; and a plurality of fourth pads having a lower surface with an area smaller than the upper surface of the first pad, disposed on the first pad; The area of ​​the upper surface of the second pad is larger than the area of ​​the upper surface of the first pad; The area of ​​the lower surface of the fourth pad is larger than the area of ​​the lower surface of the third pad. The first pad and the fourth pad are formed in a one-to-one correspondence; The second pad and the third pad form a one-to-one correspondence.

14. The method of manufacturing a semiconductor device according to claim 13, wherein The lower pads are formed by creating multiple lower openings within the lower insulating film on the lower wiring, embedding the material of the lower pads within the lower openings, and planarizing the surface of the material within the lower openings. The upper pad is formed by forming multiple upper openings in the upper insulating film on the upper wiring, embedding the material of the upper pad in the upper openings, and planarizing the surface of the material in the upper openings.

15. The method of manufacturing a semiconductor device according to claim 13, wherein The lower pad is formed in a manner that connects to the lower wiring, and / or The upper pad is formed in a manner that connects to the upper wiring.

16. The method of manufacturing a semiconductor device according to claim 13, wherein The area of ​​the upper surface of the second pad after bonding is smaller than the area of ​​the upper surface of the first pad. The area of ​​the lower surface of the fourth pad after bonding is smaller than the area of ​​the lower surface of the third pad.

17. The method of manufacturing a semiconductor device according to claim 13, wherein The area of ​​the lower surface of the third pad after bonding is equal to the area of ​​the upper surface of the first pad. The area of ​​the lower surface of the fourth pad after bonding is equal to the area of ​​the upper surface of the third pad.

18. The method of manufacturing a semiconductor device according to claim 13, wherein the lower pad comprises the first and second pads alternately arranged on the same straight line.

19. The method of manufacturing a semiconductor device according to claim 13, wherein the lower pad comprises: the first pad disposed on a plurality of first straight lines extending in a specific direction; and the second pad disposed on a plurality of second straight lines extending alternately with the first straight lines in the specific direction.

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