Wafer level package device and fan-out package device
By forming bridging connections on the side of the redistribution layer away from the chip, the problem of high dielectric material costs in wafer-level packaging is solved, thus reducing packaging costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NANTONG FUJITSU MICROELECTRONICS
- Filing Date
- 2022-04-24
- Publication Date
- 2026-06-16
Smart Images
Figure CN114975328B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of chip packaging technology, and in particular to a wafer-level packaging device and a fan-out packaging device. Background Technology
[0002] In wafer-level packaging, redistribution layers are used to interconnect chips with other devices. Each redistribution layer is surrounded by a dielectric layer, and when the redistribution layer structure is multi-layered, multiple layers of dielectric material need to be coated. Since dielectric materials are expensive, accounting for the highest proportion of material costs in wafer-level packaging, the more redistribution layers there are, the higher the packaging cost. Summary of the Invention
[0003] The main technical problem addressed by this application is to provide a wafer-level packaging device and a fan-out packaging device that can reduce the use of dielectric materials and lower the cost of chip packaging.
[0004] To solve the above-mentioned technical problems, one technical solution adopted in this application is: to provide a wafer-level packaging device, including: a wafer containing multiple chips, wherein pads are provided on the functional surface of the chips;
[0005] A first dielectric layer is located on one side of the functional surface, and a first opening is provided on the first dielectric layer corresponding to the pad position; a redistribution layer is located on the side of the first dielectric layer away from the chip, and includes multiple redistributions, and one redistribution is connected to one pad through one of the first openings; wherein, at least one redistribution includes a first part and a second part arranged at intervals; at least one connecting line is located on the side of the redistribution layer away from the chip, and the connecting line is arranged across the first part and the second part of the same redistribution, so that the first part of the same redistribution is electrically connected to the second part through the connecting line.
[0006] The wafer-level packaging device further includes a second dielectric layer located on the side of the first dielectric layer away from the chip, wherein the second dielectric layer at least covers the side surface and part of the upper surface of the redistribution layer and part of the interconnection lines.
[0007] The second dielectric layer has a second opening at the position corresponding to the first part and the second part respectively; some of the connecting lines are located on the side of the second dielectric layer away from the chip, and the connecting lines are electrically connected to the first part and the second part through the second opening.
[0008] The wafer-level packaging device further includes a protective layer that covers the portion of the interconnect exposed from the second dielectric layer.
[0009] The second dielectric layer has a third opening, through which a portion of the redistribution wiring is exposed. The wafer-level packaging device further includes: a ball under metal layer located on the side of the second dielectric layer away from the chip, the ball under metal layer being electrically connected to a portion of the redistribution wiring through the third opening; and solder balls located on the side of the ball under metal layer away from the redistribution wiring.
[0010] The connecting lines and the redistribution layer are made of different materials.
[0011] To solve the above-mentioned technical problems, another technical solution adopted in this application is: providing a fan-out package device, including: a molding layer covering the side and non-functional surface of the chip; a first dielectric layer located on one side of the functional surface, wherein the first dielectric layer has a first opening corresponding to the pad position; a redistribution layer located on the side of the first dielectric layer away from the chip, including a plurality of redistributions, and one redistribution is connected to one pad through one of the first openings; wherein at least one redistribution includes a first part and a second part spaced apart; at least one connecting line located on the side of the redistribution layer away from the chip, and the connecting line is connected across the first part and the second part of the same redistribution, so that the first part of the same redistribution is electrically connected to the second part through the connecting line.
[0012] The fan-out packaged device further includes: a second dielectric layer located on the side of the first dielectric layer away from the chip, wherein the second dielectric layer has second openings at positions corresponding to the first part and the second part; a portion of the connecting wires located on the side of the second dielectric layer away from the chip, wherein the connecting wires are electrically connected to the first part and the second part through the second openings; and a protective layer covering the portion of the connecting wires exposed in the second dielectric layer.
[0013] The second dielectric layer has a third opening, through which a portion of the redistribution wiring is exposed. The fan-out package further includes a ball under metal layer located on the side of the second dielectric layer away from the chip. The ball under metal layer is electrically connected to a portion of the redistribution wiring through the third opening. The material of the connecting wire is the same as that of the ball under metal layer.
[0014] The beneficial effects of this application are as follows: Unlike the prior art, in the wafer-level packaging device and fan-out packaging device proposed in this application, the redistribution layer includes multiple redistributions, and at least one redistribution includes a first part and a second part spaced apart; at least one connection line is formed on the side of the redistribution layer away from the chip, and the connection line is connected across the first part and the second part of the same redistribution to make the first part and the second part of the same redistribution electrically connected. This structure does not require the setting of multiple interconnected redistribution structures, thus effectively saving the use of dielectric materials and reducing the cost of chip packaging. Attached Figure Description
[0015] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:
[0016] Figure 1 This is a schematic diagram of one embodiment of the wafer-level packaging device proposed in this application;
[0017] Figure 2 This is a schematic diagram of one embodiment of the fan-out packaged device proposed in this application;
[0018] Figure 3 This is a schematic flowchart of one embodiment of the method for fabricating a wafer-level packaged device proposed in this application;
[0019] Figure 4 yes Figure 3 A flowchart of an embodiment preceding step S101;
[0020] Figure 5 yes Figure 4 The middle step S201 corresponds to a cross-sectional structural schematic diagram of one embodiment;
[0021] Figure 6 yes Figure 4 The cross-sectional structural diagram corresponding to step S202 in one embodiment;
[0022] Figure 7 yes Figure 3 A cross-sectional structural diagram corresponding to an embodiment prior to step S101;
[0023] Figure 8 yes Figure 3 The middle step S101 corresponds to a cross-sectional structural schematic diagram of one embodiment;
[0024] Figure 9 yes Figure 3The cross-sectional structural diagram corresponding to step S102 in one embodiment;
[0025] Figure 10 yes Figure 3 The flowchart of step S103 corresponds to one embodiment;
[0026] Figure 11 yes Figure 10 The cross-sectional structural diagram corresponding to step S301 in one embodiment;
[0027] Figure 12 yes Figure 10 The cross-sectional structural diagram corresponding to step S302 in one embodiment;
[0028] Figure 13 yes Figure 10 A flowchart of an embodiment following step S302;
[0029] Figure 14 yes Figure 13 The middle step S401 corresponds to a cross-sectional structural schematic diagram of one embodiment;
[0030] Figure 15 yes Figure 13 The cross-sectional structural diagram corresponding to step S402 in one embodiment;
[0031] Figure 16 yes Figure 13 The cross-sectional structural diagram corresponding to step S403 in one embodiment;
[0032] Figure 17 yes Figure 10 The flowchart of another embodiment corresponds to step S302;
[0033] Figure 18 yes Figure 17 The cross-sectional structural diagram corresponding to step S501 in one embodiment;
[0034] Figure 19 yes Figure 17 Step S502 corresponds to a cross-sectional structural diagram of one embodiment.
[0035] Figure 20 yes Figure 17 The cross-sectional structural diagram corresponding to step S503 in one embodiment;
[0036] Figure 21 yes Figure 3 A cross-sectional structural schematic diagram corresponding to one embodiment after step S103;
[0037] Figure 22 yes Figure 3A cross-sectional structural schematic diagram corresponding to one embodiment after step S103;
[0038] Figure 23 yes Figure 3 A cross-sectional structural diagram corresponding to another embodiment after step S103;
[0039] Figure 24 yes Figure 3 A cross-sectional structural diagram corresponding to another embodiment after step S103;
[0040] Figure 25 This is a cross-sectional structural schematic diagram of another embodiment of the wafer-level packaging method proposed in this application;
[0041] Figure 26 This is a flowchart illustrating another embodiment of the wafer-level packaging method of this application;
[0042] Figure 27 yes Figure 26 The cross-sectional structural diagram corresponding to step S603 in one embodiment;
[0043] Figure 28 yes Figure 26 The cross-sectional structural diagram corresponding to step S604 in one embodiment;
[0044] Figure 29 This is a cross-sectional structural schematic diagram of another embodiment of the wafer-level packaging method proposed in this application;
[0045] Figure 30 This is a cross-sectional structural schematic diagram of another embodiment of the wafer-level packaging method proposed in this application;
[0046] Figure 31 This is a cross-sectional structural schematic diagram of another embodiment of the wafer-level packaging method proposed in this application;
[0047] Figure 32 This is a cross-sectional structural schematic diagram of another embodiment of the wafer-level packaging method proposed in this application. Detailed Implementation
[0048] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.
[0049] Please see Figure 1 , Figure 1This is a schematic diagram of an embodiment of the wafer-level packaging device proposed in this application. The wafer-level packaging device provided in this application includes: a wafer 500, a first dielectric layer 10, a redistribution layer 30, and at least one interconnect line 40.
[0050] Specifically, wafer 500 includes multiple chips 100, and pads 103 are provided on the functional surface 101 of chip 100. Figure 1 Only two pads 103 are drawn on the functional surface 101 of the chip 100. However, in actual applications, the functional surface 101 of the chip 100 may include multiple pads 103. In addition, in this embodiment, the number of chips 100 can be multiple, and the types of chips 100 can be the same or different, without limitation.
[0051] The first dielectric layer 10 is located on one side of the functional surface 101. The first dielectric layer 10 has a first opening (not shown) corresponding to the position of the pad 103, and at least part of the pad 103 is exposed through the first opening. Specifically, the first opening can be formed on the first dielectric layer 10 by a polishing process.
[0052] The redistribution layer 30 is located on the side of the first dielectric layer 10 opposite to the chip 100, and includes multiple redistributions, with one redistribution connected to a pad 103 through a first opening; wherein at least one redistribution includes a first portion 31 and a second portion 32 spaced apart. The redistribution layer 30 is made of copper or other metals.
[0053] At least one connecting line 40 is located on the side of the redistribution layer 30 away from the chip 100, and the connecting line 40 is bridging the first part 31 and the second part 32 of the same redistribution, so that the first part 31 and the second part 32 of the same redistribution are electrically connected through the connecting line 40. The connected first part 31, second part 32 and connecting line 40 constitute a complete redistribution structure. The material of the connecting line 40 can be one or more of titanium, tantalum, chromium, tungsten, copper, aluminum, nickel, gold, etc., preferably titanium, nickel or copper.
[0054] It should be noted that, in Figure 1 The diagram only schematically shows a rerouting structure including a first part 31 and a second part 32 with spacing, and the first part 31 and the second part 32 are connected by a connecting line 40. However, in actual applications, multiple rerouting structures can be configured to include a first part 31 and a second part 32 with spacing and connected by a connecting line 40.
[0055] In a wafer-level packaging device proposed in this application, the redistribution layer 30 includes a plurality of redistributions, and at least one redistribution includes a first portion 31 and a second portion 32 spaced apart; at least one connection line 40 is provided on the side of the redistribution layer 30 away from the chip 100, and the connection line 40 is provided above the first portion 31 and the second portion 32 of the same redistribution to electrically connect the first portion 31 and the second portion 32 of the same redistribution. This structure eliminates the need for multiple interconnected redistribution structures, thus effectively saving the use of dielectric materials and reducing the cost of chip packaging.
[0056] In one implementation, please refer to [link / reference needed]. Figure 1 The connecting line 40 and the rewiring layer 30 are made of different materials. Among them, a low-cost conductive metal can be used to form the connecting line 40 to save costs.
[0057] In one implementation, please refer to [link / reference needed]. Figure 1 The wafer-level packaging device provided in this application further includes a second dielectric layer 20. The second dielectric layer 20 is located on the side of the first dielectric layer 10 facing away from the chip 100, and at least covers the side surface and part of the upper surface of the redistribution layer 30, as well as part of the interconnect lines 40. The second dielectric layer 20 can provide a certain degree of fixation and protection for the redistribution layer 30 and part of the interconnect lines 40. The second dielectric layer 20 has second openings (not shown) corresponding to the positions of the first part 31 and the second part 32, so that at least part of the first part 31 and at least part of the second part 32 are exposed through the second openings. Part of the interconnect lines 40 are located on the side of the second dielectric layer 20 facing away from the chip 100, and the interconnect lines 40 are electrically connected to the first part 31 and the second part 32 through the second openings. By using the interconnect lines 40 to connect the first part 31 and the second part 32, a multi-layer redistribution layer structure can be avoided. Therefore, there is no need to additionally set multiple dielectric layers to cover the redistribution layer, which can effectively save the manufacturing cost of the wafer-level packaging device.
[0058] In addition, a third opening (not shown) is provided on the second dielectric layer 20, through which some of the rewiring is exposed. The wafer-level packaging device proposed in this application also includes an under-ball metal layer 50, located on the side of the second dielectric layer 20 facing away from the chip. The under-ball metal layer 50 is electrically connected to some of the rewiring through the third opening. Optionally, the material of the under-ball metal layer 50 can be one or more of titanium, tantalum, chromium, tungsten, copper, aluminum, nickel, and gold, preferably titanium, nickel, or copper. By providing the under-ball metal layer 50, the exposed rewiring from the third opening can be protected to a certain extent, and it facilitates the placement of devices connected to the rewiring.
[0059] In this embodiment, the wafer-level packaging device proposed in this application further includes solder balls 60 located on the side of the under-ball metal layer 50 away from the redistribution, to facilitate the connection of the wafer-level packaging device proposed in this application to a substrate or other devices. Specifically, a solder ball 60 is located within a third opening, and a solder ball 60 is electrically connected to a redistribution through a corresponding under-ball metal layer 50.
[0060] In one embodiment, the wafer-level packaging device proposed in this application further includes a protective layer 70, which covers the portion of the interconnect 40 exposed in the second dielectric layer 20 to provide some protection for the interconnect 40. The protective layer 70 can be made of one of the following materials: polyimide, polymer fiber, photoresist, or PSR foam.
[0061] In one embodiment, the material of the connecting line 40 is the same as the material of the under-ball metal layer 50. It can be one or more of titanium, tantalum, chromium, tungsten, copper, aluminum, nickel, gold, etc., preferably titanium, nickel, or copper. When the connecting line 40 and the under-ball metal layer 50 are made of the same material, the connecting line 40 and the under-ball metal layer 50 can be formed simultaneously, simplifying the packaging process. Of course, in other embodiments, the material of the connecting line 40 and the under-ball metal layer 50 can also be different.
[0062] Please see Figure 2 , Figure 2 This is a schematic diagram of an embodiment of the fan-out packaging device proposed in this application. In this embodiment, the wafer-level packaging device provided by this application includes: a chip 100, a molding layer 80, a first dielectric layer 10, a redistribution layer 30, and at least one interconnect line 40.
[0063] Specifically, chip 100 includes a functional surface 101 and a non-functional surface 102 arranged opposite to each other, and the functional surface 101 is provided with multiple pads 103. It should be noted that Figure 2 Only one chip 100 is shown in the figure, but in this embodiment, there can be multiple chips 100.
[0064] The molding compound 80 covers the side surface and non-functional surface 102 of the chip 100 to provide a certain degree of fixation and protection for the chip 100. The functional surface 101 of the chip 100 is flush with one side surface of the molding compound 80. The molding compound 80 can be made of epoxy resin or the like.
[0065] The first dielectric layer 10 is located on one side of the functional surface 101, and a first opening is provided on the first dielectric layer 10 corresponding to the pad 103. In this embodiment, the first dielectric layer 10 covers the functional surface 101 of the chip 100 and at least a portion of the surface of the molding compound 80 away from the non-functional surface 102. The first dielectric layer 10 can provide a certain degree of protection for the functional surface 101 of the chip 100.
[0066] The redistribution layer 30 is located on the side of the first dielectric layer 10 opposite to the chip 100, and includes multiple redistributions. Each redistribution is connected to a pad 103 through a first opening for information transmission with the pad 103. At least one redistribution includes a first portion 31 and a second portion 32 spaced apart. In this embodiment, the structure of the redistribution layer 30 can be referred to... Figure 1 The structure of the redistribution layer 30 is not described in detail here.
[0067] At least one connection line 40 is located on the side of the redistribution layer 30 away from the chip 100, and the connection line 40 is bridging the first part 31 and the second part 32 of the same redistribution, so that the first part 31 and the second part 32 of the same redistribution are electrically connected through the connection line 40. Specifically, the structure of the connection line 40 can be referred to Figure 1 The structure of the connecting line 40 will not be described in detail here.
[0068] In one implementation, please refer to [link / reference needed]. Figure 2 The wafer-level packaging device provided in this application also includes a second dielectric layer 20. The second dielectric layer 20 is located on the side of the first dielectric layer 10 away from the chip 100. The second dielectric layer 20 has second openings (not shown) corresponding to the positions of the first part 31 and the second part 32. A portion of the connecting wires 40 are located on the side of the second dielectric layer 20 away from the chip 100, and the connecting wires 40 are electrically connected to the first part 31 and the second part 32 through the second openings. A protective layer 70 is provided on the side of the second dielectric layer 20 away from the chip 100, which covers the portion of the connecting wires 40 exposed in the second dielectric layer 20, providing a certain degree of fixation and protection for the connecting wires 40. The structures of the second dielectric layer 20 and the protective layer 70 can be referred to... Figure 1 The structure of the second dielectric layer 20 and the protective layer 70 will not be described in detail here.
[0069] In addition, a third opening (not shown) is provided on the second dielectric layer 20, through which some redistribution wiring is exposed. The wafer-level packaging device proposed in this application also includes a ball-under-metal layer 50, located on the side of the second dielectric layer 20 away from the chip. The ball-under-metal layer 50 is electrically connected to some redistribution wiring through the third opening. The material of the connecting line 40 is the same as that of the ball-under-metal layer 50. In this embodiment, the wafer-level packaging device proposed in this application also includes solder balls 60 and a protective layer 70, the specific structures of which can be referred to... Figure 1 This will not be elaborated upon here.
[0070] Please see Figure 3 , Figure 3 This is a schematic flowchart of one embodiment of the method for fabricating a wafer-level packaged device proposed in this application. The method includes:
[0071] S101: A first dielectric layer is formed on one side of the functional surface of the chip.
[0072] In one implementation, please refer to Figure 4 , Figure 4 for Figure 3 The flowchart before step S101 corresponds to one embodiment. The steps before step S101 include:
[0073] S201: Place the chip on the carrier board.
[0074] Specifically, please refer to Figure 5 , Figure 5 for Figure 4 Step S201 corresponds to a cross-sectional structural diagram of one embodiment. Figure 5 This is merely illustrative and intended for ease of understanding. Figure 5 Only one chip 100 is shown above, and the chip 100 includes two pads 103. However, in actual applications, multiple chips 100 can be placed on the carrier board 90. Each chip 100's functional surface 101 can also include multiple pads 103 for receiving and / or transmitting signals. Specifically, step S201 includes: placing the chip 100 on the carrier board 90. The chip 100 includes oppositely arranged functional surfaces 101 and non-functional surfaces 102, with the functional surfaces 101 facing the carrier board 90. The functional surfaces 101 of the chip 100 include multiple pads 103. The functional surfaces 101 of the chip 100 can be fixed to the carrier board 90 by bonding adhesive. The pads 103 are embedded in the bonding adhesive and spaced apart from the carrier board 90 so that the carrier board 90 does not directly contact the pads 103. The carrier 90 can be made of one of the following materials: silicon, glass, metal, or organic composite materials. The carrier 90 can provide some protection for the functional surface 101 of the chip 100, preventing the functional surface 101 of the chip 100 from being exposed. Alternatively, at least one chip 100 can be adhered to the carrier 90 by attaching double-sided tape, with the functional surface 101 of the chip 100 facing the carrier 90.
[0075] S202: A molding layer is formed on the surface of the carrier board on the side where the chip is located.
[0076] Specifically, please refer to Figure 6 , Figure 6 for Figure 4Step S202 corresponds to a cross-sectional view of one embodiment. In one application, step S202 specifically includes: forming a molding compound 80 on the surface of the carrier 90 on which the chip 100 is disposed, the molding compound 80 covering the side surface and non-functional surface 102 of the chip 100. The molding compound 80 can fix the chip 100 and protect the side surface and non-functional surface 102 of the chip 100. The molding compound 80 can be made of epoxy resin or the like, and can be formed by a lamination process. Further, after forming the molding compound 80, the carrier 90 is removed so that the functional surface 101 of the chip 100 is exposed from the molding compound 80.
[0077] Optionally, please refer to Figure 7 , Figure 7 for Figure 3 The cross-sectional structural diagram corresponding to step S101 may include the following before step S101: providing a wafer 500 including a plurality of chips 100, wherein a plurality of pads 103 are provided on the functional surface 101 of the chips 100.
[0078] In one embodiment, when the sides and non-functional surfaces 102 of the chip 100 are covered by the molding compound 80, please refer to... Figure 8 , Figure 8 for Figure 3 Step S101 corresponds to a cross-sectional view of one embodiment. Specifically, step S101 includes forming a first dielectric layer 10 on one side of the functional surface 101 of the chip 100. The first dielectric layer 10 has a first opening 11 at the location corresponding to the pad 103, and at least a portion of the pad 103 is exposed through the first opening 11. The first opening 11 can be formed on the first dielectric layer 10 by methods such as polishing. Forming the first dielectric layer 10 facilitates the execution of step S102.
[0079] S102: A redistribution layer is formed on the side of the first dielectric layer away from the chip.
[0080] When the sides and non-functional surfaces 102 of chip 100 are covered by molding compound 80, please refer to Figure 9 , Figure 9 for Figure 3 Step S102 corresponds to a cross-sectional view of one embodiment. Step S102 specifically includes: forming a redistribution layer 30 on the side of the first dielectric layer 10 away from the chip 100. The redistribution layer 30 includes multiple redistributions, and each redistribution is electrically connected to a pad 103 through a first opening 11. At least one redistribution includes a first portion 31 and a second portion 32 spaced apart. The first portion 31 is electrically connected to the pad 103 at a corresponding position through the first opening 11. The redistribution layer 30 can be made of copper or other metals. Furthermore, in... Figure 9The diagram only schematically illustrates a rerouting structure including a first part 31 and a second part 32 with spacing. However, in practical applications, multiple rerouting structures can be configured to include a first part 31 and a second part 32 with spacing.
[0081] S103: At least one interconnect line is formed on the side of the redistribution layer away from the chip.
[0082] When the sides and non-functional surfaces 102 of chip 100 are covered by molding compound 80, please refer to Figure 10 , Figure 10 for Figure 3 Step S103 corresponds to a flowchart of one embodiment. Step S103 includes:
[0083] S301: A second dielectric layer is formed on the side of the redistribution layer away from the chip.
[0084] Please see Figure 11 , Figure 11 for Figure 10 Step S301 corresponds to a cross-sectional view of one embodiment. Step S301 includes forming a second dielectric layer 20 on the side of the redistribution layer 30 away from the chip 100. The second dielectric layer 20 covers the side surface of the redistribution layer 30 and the surface away from the chip 100. Further, second openings 21 are formed in the second dielectric layer 20 at positions corresponding to the first portion 31 and the second portion 32, respectively, with at least a portion of the first portion 31 and at least a portion of the second portion 32 exposed through the second openings 21. The second dielectric layer 20 and the first dielectric layer 10 are formed of the same material, and the second openings 21 can be formed on the second dielectric layer 20 by means of grinding or the like. Forming the second dielectric layer 20 provides some protection for the redistribution layer 30. Forming the second openings 21 facilitates the execution of step S302.
[0085] S302: At least one interconnect line is formed on the side of the second dielectric layer away from the chip.
[0086] Please see Figure 12 , Figure 12 for Figure 10 Step S302 corresponds to a cross-sectional view of one embodiment. Step S302 includes forming at least one connection line 40 on the side of the second dielectric layer 20 away from the chip 100. One connection line 40 is electrically connected to the first part 31 and the second part 32 of the same redistribution structure through a second opening 21, such that the first part 31, the second part 32, and the connection line 40 constitute a complete redistribution structure. The material of the connection line 40 can be one or more of titanium, tantalum, chromium, tungsten, copper, aluminum, nickel, gold, etc., preferably titanium, nickel, or copper.
[0087] In one implementation, please refer to Figure 13 , Figure 13 for Figure 10 The flowchart following step S302 corresponds to one embodiment. Specifically, after step S302, the following steps are also included:
[0088] S401: A third opening is formed on the second dielectric layer.
[0089] Please see Figure 14 , Figure 14 for Figure 13 Step S401 corresponds to a cross-sectional view of one embodiment. Specifically, step S401 includes forming a third opening 35 on the second dielectric layer 20, through which a portion of the redistribution wiring is exposed. When the redistribution wiring has a first portion 31 and a second portion 32, the projection of the third opening 35 onto the redistribution wiring is located within the second portion 32. The third opening 35 can be formed on the second dielectric layer 20 by means of polishing or the like. Forming the third opening 35 facilitates the execution of step S402.
[0090] S402: A subsurface metal layer is formed within the third opening.
[0091] Please see Figure 15 , Figure 15 for Figure 13 Step S402 corresponds to a cross-sectional view of one embodiment. Specifically, step S402 includes: forming a subsphere metal layer 50 within the third opening 35, wherein the subsphere metal layer 50 is electrically connected to the rewiring portion exposed from the third opening 35. The subsphere metal layer 50 can be made of one or more of titanium, tantalum, chromium, tungsten, copper, aluminum, nickel, and gold, preferably titanium, nickel, or copper. Forming the subsphere metal layer 50 provides some protection for the rewiring portion exposed from the third opening 35 and facilitates the execution of step S403.
[0092] S403: Form solder balls on the metal layer under the ball.
[0093] Please see Figure 16 , Figure 16 for Figure 13 Step S403 corresponds to a cross-sectional view of one embodiment. Specifically, step S403 includes forming solder balls 60 on the under-ball metal layer 50. Each solder ball 60 is connected to a rewiring line through the under-ball metal layer 50. The formation of solder balls 60 facilitates the connection of the wafer-level packaged device proposed in this application to a substrate or other devices.
[0094] In another embodiment, when the material of the under-sphere metal layer 50 and the connecting line 40 is the same, the under-sphere metal layer 50 can be formed simultaneously with the connecting line 40. Please refer to [link / reference] for details. Figure 17 , Figure 17 for Figure 10The flowchart for step S302 corresponds to another embodiment. In this embodiment, step S302 includes:
[0095] S501: A third opening is formed on the second dielectric layer.
[0096] Please see Figure 18 , Figure 18 for Figure 17 Step S501 corresponds to a cross-sectional view of one embodiment. Step S501 includes forming a third opening 35 on the second dielectric layer 20, through which a portion of the rewiring is exposed. The third opening 35 can be formed by methods such as polishing. Forming the third opening 35 facilitates the execution of step S502.
[0097] S502: Connectors and a ball under metal layer are formed simultaneously on the side of the second dielectric layer away from the chip.
[0098] Please see Figure 19 , Figure 19 for Figure 17 Step S502 corresponds to a cross-sectional view of one embodiment. Step S502 includes simultaneously forming a connecting line 40 and a sub-sphere metal layer 50 on the side of the second dielectric layer 20 away from the chip 100. The sub-sphere metal layer 50 and the connecting line 40 are formed of the same material, such as titanium, tantalum, chromium, tungsten, copper, aluminum, nickel, gold, etc., preferably titanium, nickel, or copper. One connecting line 40 is electrically connected to the first part 31 and the second part 32 of the same redistribution wiring through the second opening 21, and the sub-sphere metal layer 50 is electrically connected to the portion of redistribution wiring exposed through the third opening 35 through the third opening 35. Simultaneously forming the connecting line 40 and the sub-sphere metal layer 50 on the side of the second dielectric layer 20 away from the chip 100 simplifies the packaging process and improves packaging efficiency.
[0099] S503: Form solder balls on the metal layer under the ball.
[0100] Please see Figure 20 , Figure 20 for Figure 17 Step S503 corresponds to a cross-sectional view of one embodiment. Specifically, step S503 includes forming solder balls 60 on the under-ball metal layer 50. Each solder ball 60 is connected to a rewiring line through the under-ball metal layer 50. The formation of solder balls 60 facilitates the connection of the wafer-level packaged device proposed in this application to a substrate or other devices.
[0101] In a wafer-level packaging method proposed in this application, the redistribution layer 30 includes multiple redistributions, and at least one redistribution includes a first part 31 and a second part 32 spaced apart. At least one connection line 40 is provided on the side of the redistribution layer 30 away from the chip 100. The connection line 40 is connected across the first part 31 and the second part 32 of the same redistribution to electrically connect the first part 31 and the second part 32 of the same redistribution. This structure eliminates the need for multiple interconnected redistribution structures, thus effectively saving the use of dielectric materials and reducing the cost of chip packaging.
[0102] In one implementation, please refer to Figure 21 , Figure 21 for Figure 3 The cross-sectional view following step S103 corresponds to one embodiment. Specifically, after step S103, a protective layer 70 is provided on the side of the second dielectric layer 20 away from the chip 100. The protective layer 70 covers the portion of the connection line 40 exposed in the second dielectric layer 20. The protective layer 70 can be made of polyimide, poly(p-phenylenebenzobisoxazole) fiber, benzocyclobutene, or PSR material, etc., and the protective layer 70 can provide a certain degree of protection for the portion of the connection line 40 exposed in the second dielectric layer 20.
[0103] Specifically, please refer to Figure 22 , Figure 22 for Figure 3 The following step S103 corresponds to a cross-sectional structural schematic diagram of one embodiment. The step of forming a protective layer 70 on the side of the second dielectric layer 20 away from the chip 100 includes: forming a mesh plate 200 on the side of the second dielectric layer 20 away from the chip 100; the mesh plate 200 having a fourth opening 201 at a position corresponding to the connection line 40, through which the connection line 40 is exposed. Further, a protective layer 70 is formed within the fourth opening 201, covering the portion of the connection line 40 exposed from the second dielectric layer 20. When forming the protective layer 70 within the fourth opening 201, excess protective layer 70 on the side of the mesh plate 200 away from the chip 100 can be removed using a scraper or other cleaning device to make the surface of the formed protective layer 70 smooth. Further, the mesh plate 200 is removed after forming the protective layer 70.
[0104] It should be noted that in this embodiment, the protective layer 70 can be formed first using the mesh plate 200, and then an opening can be formed on the second dielectric layer 20 to form the under-sphere metal layer 50; alternatively, an opening can be formed on the second dielectric layer 20 first to form the under-sphere metal layer 50, and then the protective layer 70 can be formed using the mesh plate 200. This application does not limit this approach. A cross-sectional view of the packaged device after the protective layer 70 is formed is shown below. Figure 21As shown. The step of setting the metal layer 50 under the sphere can be referred to the above embodiment, and will not be repeated here.
[0105] Alternatively, in another implementation, please refer to Figure 23 , Figure 23 for Figure 3 The cross-sectional view following step S103 corresponds to another embodiment. The step of forming a protective layer 70 on the side of the second dielectric layer 20 away from the chip 100 may also include: providing a protective layer 70, which includes a first surface 71 and a second surface 72 disposed opposite to each other, the second surface 72 being adhesive. An adsorption device 300 is used to adsorb the first surface 71 of the protective layer 70, and the second surface 72 of the protective layer 70 is oriented towards the connection line 40, so that the protective layer 70 adheres to the connection line 40 and the second surface 72 covers the portion of the connection line 40 exposed from the second dielectric layer 20. Finally, the adsorption device 300 is removed. A cross-sectional view of the packaged device after the protective layer 70 is formed is shown below. Figure 21 As shown. This method involves first setting up the protective layer 70 and then using an adsorption device to cover part of the connecting line 40 with the protective layer 70, avoiding the direct placement of the protective layer 70 on the packaged device and reducing the complexity of the process.
[0106] Alternatively, in yet another embodiment, please refer to Figure 24 , Figure 24 for Figure 3 The cross-sectional view following step S103 corresponds to another embodiment. The step of providing a protective layer 70 on the side of the second dielectric layer 20 away from the chip 100 may further include: providing a carrier film 400 on which the protective layer 70 is provided. The protective layer 70 is positioned corresponding to the position of the connection line 40. The protective layer 70 includes a first surface 71 and a second surface 72 disposed opposite to each other. The first surface 71 is removably connected to the carrier film 400, and the second surface 72 is adhesive. Further, the side of the carrier film 400 on which the protective layer 70 is provided is positioned towards the second dielectric layer 20, so that the protective layer 70 adheres to the connection line 40 and the second surface 72 covers the portion of the connection line 40 exposed from the second dielectric layer 20. Further, the carrier film 400 is removed. The cross-sectional view of the packaged device after the protective layer 70 is formed is shown below. Figure 21 As shown. This method avoids directly placing the protective layer 70 on the packaged device, reducing the complexity of the manufacturing process.
[0107] In one implementation, when step S101 includes providing a wafer 500 comprising a plurality of chips 100, please refer to [reference needed]. Figure 25 , Figure 25 This is a cross-sectional structural schematic diagram of another embodiment of the wafer-level packaging method proposed in this application. The specific process for packaging a wafer 500 containing multiple chips 100 can be referred to... Figure 3Steps S101-S103 are not described in detail here. In addition, in this embodiment, after the packaging is completed, a portion of the first dielectric layer 10, the second dielectric layer 20, and the wafer 500 between adjacent chips 100 are cut off to obtain a chip package containing a single chip 100.
[0108] In yet another implementation, please refer to Figure 26 , Figure 26 This is a flowchart illustrating another embodiment of the wafer-level packaging method of this application. In this embodiment, the wafer-level packaging method proposed in this application includes the following steps:
[0109] S601: A redistribution layer is formed on one side of the functional plane of the chip.
[0110] Prior to step S601, a chip 100 is disposed on a carrier board 90. The chip 100 includes a functional surface 101 and a non-functional surface 102 disposed opposite each other, with the functional surface 101 facing the carrier board 90. Further, a molding compound layer 80 is formed on the surface of the carrier board 90 on which the chip 100 is disposed, as shown in the schematic diagram below. Figure 6 As shown, the molding compound 80 covers the side surface and non-functional surface 102 of the chip 100. For detailed procedures, please refer to [reference needed]. Figure 4 Steps S201-S202 will not be described in detail here.
[0111] Optionally, before step S601, a wafer 500 comprising multiple chips 100 may be provided, wherein multiple pads 103 are provided on the functional surface 101 of the chips 100, and a schematic diagram thereof can be referred to. Figure 7 .
[0112] In one embodiment, when the side surface and non-functional surface 102 of the chip 100 are covered by the molding compound 80, before step S601, a first dielectric layer 10 is formed on one side of the functional surface 101 of the chip 100. The first dielectric layer 10 has a first opening 11 at the location corresponding to the pad, and at least a portion of the pads 103 are exposed through the first opening 11. Specific implementation steps can be found in [reference needed]. Figure 3 Step S101 will not be described in detail here.
[0113] In this embodiment, step S601 includes forming a redistribution layer 30 on one side of the functional surface 101 of the chip 100. The redistribution layer 30 includes a plurality of redistributions, and one redistribution is electrically connected to a pad 103 on the functional surface 101 of the chip 100. At least one redistribution includes a first portion 31 and a second portion 32 spaced apart. The redistribution layer 30 is located on the side of the first dielectric layer 10 away from the chip 100, and one redistribution is electrically connected to a pad 103 through a first opening 11. Specific implementation steps can be found in [reference needed]. Figure 3 Step S102 will not be described in detail here.
[0114] S602: At least one interconnect line is formed on the side of the redistribution layer away from the chip.
[0115] Step S602 includes forming at least one connection line 40 on the side of the redistribution layer 30 away from the chip 100. The connection line 40 is bridging the first portion 31 and the second portion 32 of the same redistribution layer 30, so that the first portion 31 and the second portion 32 of the same redistribution are electrically connected through the connection line 40. Specifically, a second dielectric layer 20 is formed on the side of the redistribution layer 30 away from the chip 100, and second openings 21 are formed on the second dielectric layer 20 at positions corresponding to the first portion 31 and the second portion 32. Further, at least one connection line 40 is formed on the side of the second dielectric layer 20 away from the chip 100, and one connection line 40 is electrically connected to the first portion 31 and the second portion 32 of the same redistribution through the second opening 21. For specific implementation steps, please refer to [link to relevant documentation]. Figure 3 Step S103.
[0116] S603: A photoresist layer is formed on the side of the redistribution layer away from the chip.
[0117] Please see Figure 27 , Figure 27 for Figure 26 Step S603 corresponds to a cross-sectional view of one embodiment. Step S603 includes: forming a photoresist layer 600 on the side of the redistribution layer 30 away from the chip 100, the photoresist layer 600 covering a portion of the interconnect line 40 exposed from the second dielectric layer 20.
[0118] S604: Remove the photoresist layer at the corresponding position of the connection line to form a first groove, and set a baffle in the first groove.
[0119] Please see Figure 28 , Figure 28 for Figure 26 Step S604 corresponds to a cross-sectional view of one embodiment. Step S604 includes: removing the photoresist layer 600 at the location corresponding to the connection line 40 to form a first groove 601, and setting a baffle 610 within the first groove 601. The photoresist layer 600 at the location corresponding to the connection line 40 can be removed by exposure and development. Setting the baffle 610 within the first groove 601 includes covering the connection line 40 with the baffle 610. The baffle 610 has a second groove 611, and a portion of the connection line 40 is located within the second groove 611. The baffle 610 can be made of metal, silicon, plastic, etc. By setting the baffle 610, a certain degree of protection can be provided for the portion of the connection line 40 exposed from the second dielectric layer 20.
[0120] In a wafer-level packaging method proposed in this application, the redistribution layer 30 includes multiple redistributions, and at least one redistribution includes a first part 31 and a second part 32 spaced apart. At least one connection line 40 is provided on the side of the redistribution layer 30 away from the chip 100. The connection line 40 is connected across the first part 31 and the second part 32 of the same redistribution to electrically connect the first part 31 and the second part 32 of the same redistribution. This structure eliminates the need for multiple interconnected redistribution structures, thus effectively saving the use of dielectric materials and reducing the cost of chip packaging.
[0121] In one implementation, please refer to Figure 29 , Figure 29 This is a cross-sectional view of another embodiment of the wafer-level packaging method proposed in this application. The wafer-level packaging method further includes forming a fifth opening 605 on the photoresist layer 600, removing the second dielectric layer 20 at the corresponding position of the fifth opening 605, and exposing a portion of the redistribution layer 30 through the fifth opening 605. Specifically, a portion of the photoresist layer 600 can be removed first by exposure and development, and then the second dielectric layer 20 at the corresponding position can be removed by methods such as polishing to form the fifth opening 605. Further, a subsphere metal layer 50 is formed within the fifth opening 605, and the subsphere metal layer 50 is electrically connected to the portion of the redistribution layer through the fifth opening 605. The material of the subsphere metal layer 50 can be one or more of titanium, tantalum, chromium, tungsten, copper, aluminum, nickel, and gold, preferably titanium, nickel, or copper. Forming the subsphere metal layer 50 can provide some protection for the portion of the redistribution layer 30 exposed from the fifth opening 605 and facilitates the subsequent formation of interconnect devices on the subsphere metal layer 50.
[0122] In one implementation, please refer to Figure 30 , Figure 30 This is a cross-sectional view of another embodiment of the wafer-level packaging method proposed in this application. The wafer-level packaging method also includes forming solder balls 60 within the fifth opening 605, with the solder balls 60 electrically connected to the underlying metal layer 50. The solder balls 60 facilitate the connection of the wafer-level packaged device proposed in this application to a substrate or other devices.
[0123] In another embodiment, when the material of the under-sphere metal layer 50 and the interconnect 40 is the same, the under-sphere metal layer 50 can be formed simultaneously with the interconnect 40. In this embodiment, before the step of forming at least one interconnect 40 on the side of the redistribution layer 30 away from the chip 100, the method includes: forming a third opening 35 on the second dielectric layer 20, through which a portion of the redistribution layer 30 is exposed. A schematic diagram can be found [link to schematic diagram]. Figure 18Further, the step of forming at least one interconnect line 40 on the side of the second dielectric layer away from the chip 100 includes: simultaneously forming the interconnect line 40 and the under-ball metal layer 50 on the side of the second dielectric layer 20 away from the chip 100. The under-ball metal layer 50 and the interconnect line 40 are formed of the same material. One interconnect line 40 is electrically connected to the first portion 31 and the second portion 32 of the same rewiring through the second opening 21. The under-ball metal layer 50 is electrically connected to the portion of the rewiring exposed from the third opening 35 through the third opening 35. Solder balls 60 are formed on the under-ball metal layer 50, and one solder ball 60 is connected to one rewiring through the under-ball metal layer 50. A detailed structural diagram can be found [link to diagram]. Figure 20 The process of simultaneously forming the under-sphere metal layer 50 and the connecting line 40 in this embodiment can be referred to [reference needed]. Figure 17 Steps S501-S503 will not be described in detail here.
[0124] Additionally, please see Figure 31 , Figure 31 This is a cross-sectional view of another embodiment of the wafer-level packaging method proposed in this application. In this embodiment, after forming the under-ball metal layer 50, the interconnect line 40, and the solder ball 60, a photoresist layer 600 is formed on the side of the redistribution layer 30 away from the chip 100, with a portion of the solder ball 60 exposed from the photoresist layer 600. Further, the photoresist layer 600 at the corresponding position of the interconnect line 40 is removed to form a first groove, and a baffle 610 is disposed within the first groove. Specific steps can be found in [reference needed]. Figure 26 Steps S603-S604 will not be described in detail here.
[0125] In another embodiment, when step S601 includes providing a wafer 500 comprising a plurality of chips 100, please refer to [reference needed]. Figure 32 , Figure 32 This is a cross-sectional structural schematic diagram of another embodiment of the wafer-level packaging method proposed in this application. The specific process for packaging a wafer 500 containing multiple chips 100 can be referred to... Figure 26 Steps S601-S604 are not described in detail here. In addition, in this embodiment, after the packaging is completed, a portion of the first dielectric layer 10, the second dielectric layer 20, the photoresist layer 600, and the wafer 500 between adjacent chips 100 are cut off to obtain a chip package containing a single chip 100.
[0126] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.
Claims
1. A wafer-level packaged device, characterized in that, include: A wafer contains multiple chips, and pads are provided on the functional surfaces of the chips. A first dielectric layer is located on one side of the functional surface, and the first dielectric layer has a first opening corresponding to the pad position; A redistribution layer, located on the side of the first dielectric layer opposite to the chip, includes multiple redistributions, and one of the redistributions is connected to a pad through a first opening; wherein at least one of the redistributions includes a first part and a second part spaced apart. At least one connection line is located on the side of the redistribution layer away from the chip, and the connection line is bridging the first and second portions of the same redistribution layer, so that the first portion of the same redistribution layer is electrically connected to the second portion through the connection line; wherein the connection line and the redistribution layer are formed of different materials; The second dielectric layer is located on the side of the first dielectric layer away from the chip, and the second dielectric layer at least covers the side and part of the upper surface of the redistribution layer and part of the interconnection line; The second dielectric layer has a third opening, through which a portion of the redistribution wiring is exposed. The wafer-level packaging device further includes: a ball under metal layer located on the side of the second dielectric layer away from the chip, the ball under metal layer being electrically connected to a portion of the redistribution wiring through the third opening; and solder balls located on the side of the ball under metal layer away from the redistribution wiring. The wafer-level packaging device further includes a photoresist layer located on the side of the redistribution layer away from the chip, and the photoresist layer covers a portion of the interconnect exposed from the second dielectric layer; wherein, a first groove is formed in the photoresist layer at the position corresponding to the interconnect, and a baffle is disposed in the first groove, the baffle covering the interconnect around the interconnect.
2. The wafer-level packaged device according to claim 1, characterized in that, The second dielectric layer has a second opening at the position corresponding to the first part and the second part, respectively; Some of the connecting lines are located on the side of the second dielectric layer away from the chip, and the connecting lines are electrically connected to the first part and the second part through the second opening.
3. The wafer-level packaging device according to claim 1, characterized in that, The material of the connecting wire is the same as the material of the metal layer under the ball.
4. A fan-out packaged device, characterized in that, include: The chip includes functional and non-functional surfaces arranged opposite to each other, and the functional surfaces are provided with multiple pads; A molding compound covering the sides and non-functional surfaces of the chip; A first dielectric layer is located on one side of the functional surface, and the first dielectric layer has a first opening corresponding to the pad position; A redistribution layer, located on the side of the first dielectric layer opposite to the chip, includes multiple redistributions, and one of the redistributions is connected to a pad through a first opening; wherein at least one of the redistributions includes a first part and a second part spaced apart. At least one connection line is located on the side of the redistribution layer away from the chip, and the connection line is bridging the first and second portions of the same redistribution layer, so that the first portion of the same redistribution layer is electrically connected to the second portion through the connection line; wherein the connection line and the redistribution layer are formed of different materials; The fan-out packaged device further includes a second dielectric layer located on the side of the first dielectric layer away from the chip. The second dielectric layer has second openings at positions corresponding to the first part and the second part, respectively. Some of the connecting lines are located on the side of the second dielectric layer away from the chip, and the connecting lines are electrically connected to the first part and the second part through the second openings. The fan-out packaged device further includes a photoresist layer located on the side of the redistribution layer away from the chip, and the photoresist layer covers a portion of the interconnect exposed from the second dielectric layer; wherein, a first groove is formed in the photoresist layer at the position corresponding to the interconnect, and a baffle is disposed in the first groove, and the baffle covers the interconnect around the connection. A third opening is provided on the second dielectric layer, and part of the rewiring is exposed through the third opening; The under-sphere metal layer is located on the side of the second dielectric layer opposite to the chip, and the under-sphere metal layer is electrically connected to a portion of the redistribution through the third opening.
5. The fan-out packaged device according to claim 4, characterized in that, The material of the connecting wire is the same as the material of the metal layer under the ball.