Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device includes a substrate having a first power supply region, a second power supply region, and a cell region. The cell region extends between the first power supply region and the second power supply region. A first active region and a second active region are disposed within the cell region and extend side by side. A first power supply line is disposed within the first power supply region and extends in a first direction. A first source / drain contact is disposed connecting the first active region and the second active region. A second source / drain contact is disposed connecting the first active region and the first power supply line. The first source / drain contact includes a first recess disposed within an intermediate region between the first active region and the second active region.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0021795, filed on February 18, 2021, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to semiconductor devices and methods of manufacturing the same, and more specifically to semiconductor devices and methods of manufacturing the same having source / drain contacts. Background Technology

[0004] Semiconductor devices are generally considered an important element in the electronics industry due to their typical characteristics, such as miniaturization, versatility, and / or low manufacturing cost. Semiconductor devices can be classified into semiconductor memory devices that store logic data, semiconductor logic devices that perform computational processing of logic data, and hybrid semiconductor devices that include both storage and logic elements.

[0005] With the rapid development of the electronics industry, the requirements for the characteristics of semiconductor devices are gradually increasing. For example, there is a growing demand for high reliability, high speed, and / or multifunctionality in semiconductor devices. To meet these required characteristics, the internal structure of semiconductor devices is becoming more complex and their integration density is higher. Summary of the Invention

[0006] Various aspects of this disclosure provide a semiconductor device in which parasitic capacitance is reduced to improve device performance.

[0007] This disclosure also provides a method for manufacturing a semiconductor device in which parasitic capacitance is reduced to improve device performance.

[0008] According to some aspects of the present invention, a semiconductor device is provided, the semiconductor device comprising: a first power region and a second power region extending side-by-side in a first direction. A cell region is also disposed between the first power region and the second power region. The semiconductor device further comprises: a substrate having a first active region and a second active region therein, the first active region and the second active region extending side-by-side in the first direction and within the cell region. A first power line is disposed, the first power line extending in the first power region in the first direction. A first source / drain contact is disposed connecting the first active region and the second active region. A second source / drain contact is disposed connecting the first active region and the first power line. The first source / drain contact may include: a first recess disposed in an intermediate region between the first active region and the second active region. The second source / drain contact may include: a second recess disposed within the first power region. Furthermore, the lowermost surface of the first recess may be disposed higher than the lowermost surface of the second recess relative to the upper surface of the substrate.

[0009] According to some aspects of the present invention, a semiconductor device is provided, the semiconductor device comprising: a first cell region and a second cell region extending side-by-side in a first direction; and a power supply region between the first cell region and the second cell region. The semiconductor device includes: a substrate having a first active region and a second active region therein, the first active region and the second active region extending side-by-side in the first cell region in the first direction. A gate electrode is provided, the gate electrode extending on the substrate in a second direction intersecting the first direction. A power supply line is provided, the power supply line extending in the power supply region in the first direction. A first source / drain contact is provided, the first source / drain contact being connected to the first active region on one side of the gate electrode. A second source / drain contact is provided, the second source / drain contact being connected to the first active region and the power supply line on the other side of the gate electrode. The first source / drain contact may include: a first recess in an intermediate region between the first active region and the second active region, and the second source / drain contact may include: a second recess in the power supply region. The lowermost surface of the first recess may be higher than the lowermost surface of the second recess relative to the upper surface of the substrate.

[0010] According to an additional aspect of the present invention, a semiconductor device is provided, the semiconductor device comprising: a first power region and a second power region extending side-by-side in a first direction. A cell region is disposed between the first power region and the second power region. The semiconductor device includes: a substrate having a first active region and a second active region therein, the first active region and the second active region extending side-by-side in the first direction within the cell region. A first active pattern is disposed, the first active pattern extending in the first direction over the first active region. A second active pattern is disposed, the second active pattern extending in the first direction over the second active region. A gate electrode is disposed, the gate electrode extending in the second direction intersecting the first direction and on the first active pattern and the second active pattern. An insulating film is disposed, the insulating film covering the first active pattern, the second active pattern and the gate electrode. A first power line is disposed, the first power line extending in the first direction within the first power region and providing a first power supply voltage. A second power line is disposed, the second power line extending in the first direction within the second power region and providing a second power supply voltage (different from the first power supply voltage). A first source / drain contact is provided, which connects the source / drain region of the first active pattern and the source / drain region of the second active pattern within the insulating film. A second source / drain contact is provided, which connects the source / drain region of the first active pattern and the first power line within the insulating film. Furthermore, the insulating film may include: a first recess extending between the first active region and the second active region and having a first depth; a second recess disposed in the first power region and having a second depth greater than the first depth; the first source / drain contact may further include a first recess portion filling the first recess; the second source / drain contact may further include a second recess portion filling the second recess.

[0011] According to some aspects of the present invention, a method for manufacturing a semiconductor device is provided, the semiconductor device comprising: a first power region and a second power region extending side-by-side in a first direction; and a cell region extending between the first power region and the second power region. The method includes: setting a substrate having a first active region and a second active region extending side-by-side in the cell region in the first direction. The method further includes: forming a gate electrode on the substrate extending in a second direction intersecting the first direction; and forming an insulating film on the substrate covering the gate electrode. A mask pattern is formed, the mask pattern including: a first source / drain contact opening overlapping the first active region and the second active region; and a second source / drain contact opening overlapping the first active region and the first power region. A protective pattern is formed, the protective pattern overlapping an intermediate region between the first active region and the second active region, and not overlapping the first power region. The mask pattern and the protective pattern are also used as an etching mask to etch the insulating film.

[0012] However, the aspects of this disclosure are not limited to those set forth herein. These and other aspects of this disclosure will become more apparent to those skilled in the art upon reference to the detailed description of this disclosure given below. Attached Figure Description

[0013] The above and other aspects and features of this disclosure will become clearer from the following detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0014] Figure 1 It is a schematic layout diagram used to illustrate a semiconductor device according to some embodiments.

[0015] Figure 2 It is along Figure 1 The cross-sectional view taken from line AA.

[0016] Figure 3 It is along Figure 1 The cross-sectional view of line BB.

[0017] Figure 4 It is along Figure 1 The cross-sectional view taken from line CC.

[0018] Figure 5A and Figure 5B It is used for explanation Figure 4 An enlarged view of the prominent central region S1.

[0019] Figure 6 It is along Figure 1 The cross-sectional view of line DD.

[0020] Figure 7 It is used for explanation Figure 6 A magnified view of the prominent area S2.

[0021] Figure 8 and Figure 9 This is a cross-sectional view used to illustrate a semiconductor device according to some embodiments.

[0022] Figure 10 It is a schematic layout diagram used to illustrate a semiconductor device according to some embodiments.

[0023] Figure 11 It is along Figure 10 The cross-sectional view of line EE.

[0024] Figure 12 It is a schematic layout diagram used to illustrate a semiconductor device according to some embodiments.

[0025] Figure 13 It is along Figure 12 The cross-sectional view taken from the line FF.

[0026] Figure 14 It is a schematic layout diagram used to illustrate a semiconductor device according to some embodiments.

[0027] Figures 15 to 34 This is a cross-sectional view illustrating an intermediate structure of a method for manufacturing a semiconductor device according to some embodiments.

[0028] Figure 35 This is a plan view illustrating the structure of a method for manufacturing a semiconductor device according to some embodiments. Detailed Implementation

[0029] In the following text, reference will be made to Figures 1 to 14 A semiconductor device is described according to an exemplary embodiment.

[0030] Figure 1 It is a schematic layout diagram used to illustrate a semiconductor device according to some embodiments. Figure 2 It is along Figure 1 The cross-sectional view taken from line AA. Figure 3 It is along Figure 1 The cross-sectional view of line BB. Figure 4 It is along Figure 1 The cross-sectional view taken from line CC. Figure 5A and Figure 5B It is prominent Figure 4 An enlarged view of region S1 in the image. Figure 6 It is along Figure 1 The cross-sectional view of line DD. Figure 7 It is prominent Figure 6 A magnified view of region S2.

[0031] refer to Figures 1 to 7 A semiconductor device according to some embodiments includes a first power region PW1, a second power region PW2, a first cell region CR1, and a second cell region CR2. The first power region PW1 and the second power region PW2 may be spaced apart from each other and extend side-by-side. For example, each of the first power region PW1 and the second power region PW2 may extend in a first direction X. Furthermore, the first power region PW1 and the second power region PW2 may be spaced apart from each other in a second direction Y that intersects (e.g., is perpendicular to) the first direction X.

[0032] The first unit region CR1 can be inserted between the first power region PW1 and the second power region PW2. The second unit region CR2 and the first unit region CR1 can be separated by the first power region PW1 inserted between them. That is, the first power region PW1 can be inserted between the first unit region CR1 and the second unit region CR2, as shown below. Figure 1 As shown.

[0033] In some embodiments, the first unit region CR1 and the second unit region CR2 may be defined between a first unit separation pattern IB1 and a second unit separation pattern IB2 that are spaced apart from each other along a first direction X. For example, the first unit separation pattern IB1 and the second unit separation pattern IB2 may extend side by side longitudinally in a second direction Y. The first unit region CR1 and the second unit region CR2 may be defined between the first unit separation pattern IB1 and the second unit separation pattern IB2.

[0034] The first power supply region PW1 can provide a first power supply voltage to the first unit region CR1 and the second unit region CR2, and the second power supply region PW2 can provide a second power supply voltage different from the first power supply voltage to the first unit region CR1. For example, the first power line V extending in the first direction X DD A second power line V can be set within the first power area PW1 and extended in the first direction X. SS It can be set within the second power supply area PW2. First power supply line V DD It can provide leakage voltage, and the second power supply line V SS A source voltage can be provided. As an example, the first supply voltage can be a positive (+) voltage, and the second supply voltage can be ground (GND) voltage or a negative (-) voltage.

[0035] Semiconductor elements (e.g., transistors) may be disposed in each of the first cell region CR1 and the second cell region CR2. The semiconductor elements disposed in the first cell region CR1 and the second cell region CR2 may be different, but are not limited to, for example, NAND cells, NOR cells and XOR cells.

[0036] A semiconductor device according to some embodiments may include: a substrate 100, active patterns / fins F1 to F5, gate electrodes G1 to G3, source / drain contacts CA11 to CA22, gate contact CB, wiring path VA, and wiring lines RW1 and RW2. The number, arrangement, etc., of the active patterns F1 to F5, gate electrodes G1 to G3, source / drain contacts CA11 to CA22, gate contact CB, wiring path VA, and wiring lines RW1 and RW2 are merely examples and are not limited to those shown.

[0037] Substrate 100 may be bulk silicon or silicon-on-insulator (SOI). Alternatively, substrate 100 may be a silicon substrate, or may include other semiconductor materials, but not limited to, silicon germanium, silicon germanium-on-insulator (SGOI), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

[0038] The substrate 100 may include a first active region AR1, a second active region AR2, and a third active region AR3. The first active region AR1 and the second active region AR2 may be disposed within a first cell region CR1, and the third active region AR3 may be disposed within the second cell region CR2. The first active region AR1, the second active region AR2, and the third active region AR3 may be spaced apart from each other and extend side-by-side in a first direction X. An intermediate region MR may be defined between the first active region AR1 and the second active region AR2.

[0039] In some embodiments, semiconductor elements (e.g., transistors) with different conductivity types may be formed on the first active region AR1 and the second active region AR2. Furthermore, in some embodiments, semiconductor elements (e.g., transistors) with different conductivity types may be formed on the first active region AR1 and the third active region AR3. Hereinafter, the first active region AR1 will be described as a PFET region, and the second active region AR2 and the third active region AR3 will be described as NFET regions. However, this is merely an example, and naturally, the first active region AR1 can be an NFET region, and the second active region AR2 and the third active region AR3 can be PFET regions.

[0040] In some embodiments, the first active region AR1, the second active region AR2, and the third active region AR3 may be defined by a substrate trench DT. The substrate trench DT may be a deep trench formed within the substrate 100. The substrate trench DT extends in the second direction Y and can separate the first active region AR1, the second active region AR2, and the third active region AR3 from each other.

[0041] Active patterns F1 to F5 can be formed on substrate 100. For example, first active pattern F1 and second active pattern F2 can be formed on first active region AR1, third active pattern F3 and fourth active pattern F4 can be formed on second active region AR2, and fifth active pattern F5 can be formed on third active region AR3. Active patterns F1 to F5 can be spaced apart from each other and extend side by side in a first direction X. In some embodiments, each of active patterns F1 to F5 may include a fin-shaped pattern protruding from the upper surface of substrate 100.

[0042] In some embodiments, a field insulating film 105 may be formed on a substrate 100. The field insulating film 105 may surround at least a portion of the side surfaces of the active patterns F1 to F5. For example, as Figure 3 As shown, a portion of the active patterns F1 to F5 can protrude upward from the field insulating film 105.

[0043] In some embodiments, the field insulating film 105 may fill the substrate trench DT. That is, the first active region AR1, the second active region AR2, and the third active region AR3 may be spaced apart from each other by the field insulating film 105.

[0044] The field insulating film 105 may include, but is not limited to, at least one of silicon oxide (SiO2), silicon oxynitride (SiON), silicon carbonitride (SiOCN), or combinations thereof.

[0045] Gate electrodes G1 to G3 can be formed on active patterns F1 to F5. Gate electrodes G1 to G3 can intersect active patterns F1 to F5 respectively. For example, a first gate electrode G1, a second gate electrode G2, and a third gate electrode G3, which are spaced apart from each other and extend side by side in the second direction Y, can be formed between the first unit separation pattern IB1 and the second unit separation pattern IB2.

[0046] In some embodiments, a first gate dicing pattern CT1 and a second gate dicing pattern CT2 may be formed to dice gate electrodes G1 to G3. The first gate dicing pattern CT1 may extend in a first direction X within a first power region PW1 to dice gate electrodes G1 to G3. The second gate dicing pattern CT2 may extend in the first direction X within a second power region PW2 to dice gate electrodes G1 to G3. Each of the first gate dicing pattern CT1 and the second gate dicing pattern CT2 may include, but is not limited to, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiOCN), or combinations thereof.

[0047] Each of the gate electrodes G1 to G3 may include a gate conductive film 130. The gate conductive film 130 may include, but is not limited to, at least one of Ti, Ta, W, Al, Co, and combinations thereof. The gate conductive film 130 may also include, for example, a semiconductor (e.g., silicon or silicon germanium) instead of a metal.

[0048] Although the gate conductive film 130 is shown as a single film, the technical concept of this disclosure is not limited thereto. Unlike the illustrated case, the gate conductive film 130 can also be formed by stacking multiple conductive materials as a gate stack. For example, the gate conductive film 130 may include: a work function adjustment film for adjusting the work function; and a filled conductive film for filling the space formed by the work function adjustment film. The work function adjustment film may include at least one of, for example, TiN, TaN, TiC, TaC, TiAlC, and combinations thereof. The filled conductive film may include, for example, W or Al. The gate conductive film 130 may be formed using, but is not limited to, alternative processes.

[0049] The gate dielectric film 120 can be inserted between the active patterns F1 to F5 and the gate conductive film 130. For example, the gate dielectric film 120 can extend along the side and lower surfaces of the gate conductive film 130. However, the technical concept of this disclosure is not limited thereto, and the gate dielectric film 120 can extend only along the lower surface of the gate conductive film 130.

[0050] In some embodiments, a portion of the gate dielectric film 120 may be inserted between the field insulating film 105 and the gate conductive film 130. For example, as Figure 3 As shown, the gate dielectric film 120 may also extend along the upper surface of the field insulating film 105. In other embodiments, a portion of the gate dielectric film 120 may be inserted between the gate conductive film 130 and the first gate dicing pattern CT1, and between the gate conductive film 130 and the second gate dicing pattern CT2. For example, as Figure 3 As shown, the gate dielectric film 120 can also extend along the side surface of the first gate cutting pattern CT1 and the side surface of the second gate cutting pattern CT2.

[0051] The gate dielectric film 120 may include at least one of, for example, silicon oxide, silicon oxynitride, silicon nitride, and a high dielectric constant (high k) material having a higher dielectric constant than silicon oxide. The high dielectric constant material may include, but is not limited to, hafnium oxide.

[0052] Gate spacers 140 may be formed on substrate 100 and field insulating film 105. Gate spacers 140 may extend along both side surfaces of gate conductive film 130. For example, gate spacers 140 may extend along a second direction Y to intersect active patterns F1 to F5.

[0053] The gate spacer 140 may include, but is not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof. The gate capping pattern 150 may extend along the upper surface of the gate conductive film 130. For example, the gate capping pattern 150 may extend in the second direction Y to cover the upper surface of the gate conductive film 130. The gate capping pattern 150 may include, but is not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof.

[0054] In some embodiments, a first dummy gate electrode DG1 may be formed on a first cell separation pattern IB1, and a second dummy gate electrode DG2 may be formed on a second cell separation pattern IB2. The first dummy gate electrode DG1 and the second dummy gate electrode DG2 may be dummy electrodes that are not used as gate electrodes. The first dummy gate electrode DG1 and the second dummy gate electrode DG2 may be formed at the same height as the gate electrodes G1 to G3. As used herein, the expression "formed at the same height" means that they may be formed by the same manufacturing process. For example, each of the first dummy gate electrode DG1 and the second dummy gate electrode DG2 may include a gate conductive film 130, a gate dielectric film 120, a gate spacer 140, and a gate capping pattern 150.

[0055] The first source / drain region 160 can be formed on the first active region AR1. For example, the first source / drain region 160 can be formed on both sides of the gate conductive film 130 within the first active pattern F1 and the second active pattern F2. The first source / drain region 160 can be spaced apart from the gate conductive film 130 by the gate spacer 140.

[0056] In some embodiments, the first source / drain region 160 may include an epitaxial layer formed within a first active pattern F1 and a second active pattern F2. In some embodiments, the first active pattern F1 and the second active pattern F2 may share the first source / drain region 160. For example, the first source / drain region 160 may be a merged epitaxial layer.

[0057] When the semiconductor device formed in the first active region AR1 is a PFET, the first source / drain region 160 may include p-type impurities or impurities used to prevent the diffusion of p-type impurities. For example, the first source / drain region 160 may include at least one of B, C, In, Ga, and Al or combinations thereof.

[0058] The second source / drain region 260 can be formed on the second active region AR2. For example, the second source / drain region 260 can be formed on both sides of the gate conductive film 130 within the third active pattern F3 and the fourth active pattern F4. The second source / drain region 260 can be spaced apart from the gate conductive film 130 by the gate spacer 140.

[0059] In some embodiments, the second source / drain region 260 may include an epitaxial layer formed within the third active pattern F3 and the fourth active pattern F4. In some embodiments, the third active pattern F3 and the fourth active pattern F4 may share the second source / drain region 260. For example, the second source / drain region 260 may be a merged epitaxial layer.

[0060] When the semiconductor device formed within the second active region AR2 is an NFET, the second source / drain region 260 may include n-type impurities or impurities used to prevent the diffusion of n-type impurities. For example, the second source / drain region 260 may include at least one of P, Sb, As, or combinations thereof.

[0061] The third source / drain region 360 can be formed on the third active region AR3. For example, the third source / drain region 360 can be formed on both sides of the gate conductive film 130 within the fifth active pattern F5. The third source / drain region 360 can be spaced apart from the gate conductive film 130 by the gate spacer 140.

[0062] In some embodiments, the third source / drain region 360 may include an epitaxial layer formed within the fifth active pattern F5. In some embodiments, the third source / drain region 360 may be a merged epitaxial layer.

[0063] When the semiconductor device formed in the third active region AR3 is an NFET, the third source / drain region 360 may include n-type impurities or impurities used to prevent the diffusion of n-type impurities. For example, the third source / drain region 360 may include at least one of P, Sb, As, or combinations thereof.

[0064] Although each of the first source / drain region 160, the second source / drain region 260, and the third source / drain region 360 is shown as a single membrane, the technical concept of this disclosure is not limited thereto. For example, the first source / drain region 160, the second source / drain region 260, and the third source / drain region 360 may be formed from multiple membranes, each containing impurities with different concentrations from each other.

[0065] Multiple interlayer insulating films 110, 210, 220 and 230 may be formed on substrate 100. For example, interlayer insulating films 110, 210, 220 and 230 may be formed from at least one of the following: silicon oxide, silicon oxynitride and a low dielectric constant (low k) material having a dielectric constant lower than that of silicon oxide.

[0066] The first interlayer insulating film 110 and the second interlayer insulating film 210 can be formed to cover the field insulating film 105, the first source / drain region 160, the second source / drain region 260, the third source / drain region 360, the gate spacer 140, and the gate cap pattern 150. For example, the first interlayer insulating film 110 can be formed on the field insulating film 105 to cover the side surface of the gate spacer 140. The second interlayer insulating film 210 can be formed on the first interlayer insulating film 110 to cover the upper surface of the gate cap pattern 150.

[0067] Source / drain contacts CA11 to CA22 can be disposed on both sides of gate electrodes G1 to G3. Furthermore, source / drain contacts CA11 to CA22 can be connected to the first active region AR1, the second active region AR2, or the third active region AR3. For example, first source / drain contacts CA11, second source / drain contacts CA12, third source / drain contacts CA13, fourth source / drain contacts CA21, and fifth source / drain contacts CA22 can be formed, penetrating the first interlayer insulating film 110 and the second interlayer insulating film 210 and connected to the first source / drain region 160, the second source / drain region 260, or the third source / drain region 360.

[0068] The first source / drain contact CA11 may be disposed on at least one side of the gate electrodes G1 to G3. For example, the first source / drain contact CA11 may be formed on the first active region AR1 and / or the second active region AR2 between the first cell separation pattern IB1 and the first gate electrode G1. The first source / drain contact CA11 may be formed within an insulating film (e.g., field insulating film 105 and first interlayer insulating film 110) covering the first active region AR1 and / or the second active region AR2, and may be connected to the first active region AR1 and / or the second active region AR2.

[0069] In some embodiments, the first source / drain contact CA11 may connect to the first active region AR1 and the second active region AR2. For example, the first source / drain contact CA11 extends along the second direction Y over the first active region AR1, the intermediate region MR, and the second active region AR2, and may connect the first source / drain region 160 and the second source / drain region 260.

[0070] The first source / drain contact CA11 may be recessed downwards from the first source / drain region 160 and / or the second source / drain region 260 toward the upper surface of the substrate 100. For example, the first source / drain contact CA11 may include a first extension EP1 that extends in the second direction Y and connects the first source / drain region 160 and the second source / drain region 260. In this case, as... Figure 4 , Figure 5A and Figure 5BAs shown, the lower surface of the first extension EP1 can be closer to the upper surface of the substrate 100 than the uppermost part 160T of the first source / drain region 160.

[0071] The first source / drain contact CA11 may include a first recess RP1, which is further recessed from the first extension EP1 within the intermediate region MR. For example, an insulating film (e.g., the first interlayer insulating film 110) disposed within the intermediate region MR may include a first recess 110r1, which is closer to the upper surface of the substrate 100 than the lower surface of the first extension EP1. The first recess RP1 may fill the first recess 110r1. That is, the first recess RP1 may be in the form of protruding from the lower surface of the first extension EP1 disposed in the intermediate region MR.

[0072] In some embodiments, the side surface of the first recess RP1 may contact the side surface of the first source / drain region 160 and the side surface of the second source / drain region 260. For example, the first recess RP1 may expose the side surfaces of the first source / drain region 160 and the second source / drain region 260. In this case, the contact area between the first source / drain contact CA11, the first source / drain region 160, and the second source / drain region 260 is increased, and the resistance may be improved.

[0073] In some embodiments, such as Figure 5A As shown, with the upper surface of the substrate 100 as a reference, the lowermost surface of the first recess RP1 can be formed higher than the upper surface of the field insulating film 105. In some embodiments, such as Figure 5B As shown, with the upper surface of the substrate 100 as a reference, the lowermost surface of the first recess RP1 can be formed to be lower than the upper surface of the field insulating film 105.

[0074] In some embodiments, the first source / drain contact CA11 may further include a first contact CP1. The first contact CP1 may be in the form of protruding from the upper surface of the first extension EP1. The first source / drain contact CA11 may make contact with at least a portion of the wiring lines RW1 and RW2 to be described below through the first contact CP1.

[0075] The second source / drain contact CA12 may be disposed on at least one side of the gate electrodes G1 to G3. For example, the second source / drain contact CA12 may be formed on the first active region AR1 between the first gate electrode G1 and the second gate electrode G2. The second source / drain contact CA12 is formed in an insulating film (e.g., field insulating film 105 and first interlayer insulating film 110) covering the first active region AR1, and may be connected to the first active region AR1.

[0076] In some embodiments, the second source / drain contact CA12 can connect the first active region AR1 and the first power line V.DD For example, connecting the second source / drain contact CA12 and the first power line V. DD The wiring path VA can be formed within the third interlayer insulating film 220. The second source / drain contact CA12 extends along the second direction Y on the first power region PW1 and the first active region AR1, and can connect the first source / drain region 160 and the wiring path VA.

[0077] The second source / drain contact CA12 may be recessed downwards from the first source / drain region 160 toward the upper surface of the substrate 100. For example, the second source / drain contact CA12 may include a second extension EP2 that extends in the second direction Y and is connected to the first source / drain region 160. In this case, as... Figure 6 and Figure 7 As shown, the lower surface of the second extension EP2 can be closer to the upper surface of the substrate 100 than the uppermost part 160T of the first source / drain region 160.

[0078] The second source / drain contact CA12 may include a second recess RP2, which is further recessed from the second extension EP2 within the first power region PW1. For example, the insulating film (e.g., field insulating film 105 and first interlayer insulating film 110) disposed in the first power region PW1 may include a second recess 110r2, which is closer to the upper surface of the substrate 100 than the lower surface of the second extension EP2. The second recess RP2 may fill the second recess 110r2. That is, the second recess RP2 may be in the form of protruding from the lower surface of the second extension EP2 disposed within the first power region PW1. In some embodiments, such as Figure 7 As shown, with the upper surface of the substrate 100 as a reference, the lowermost surface of the second recess RP2 is formed to be lower than the upper surface of the field insulating film 105.

[0079] The first recess RP1 of the first source / drain contact CA11 can be formed to be shallower than the second recess RP2 of the second source / drain contact CA12. For example, as Figure 5A , Figure 5B and Figure 7 As shown, with the uppermost part 160T of the first source / drain region 160 as a reference, the first depth D1 of forming the first depression 110r1 can be shallower than the second depth D2 of forming the second depression 110r2. Therefore, as Figures 4 to 7 As shown, with the upper surface of the substrate 100 as a reference, the first height H1 of the lowest surface of the first recess RP1 can be higher than the second height H2 of the lowest surface of the second recess RP2.

[0080] For example, the first depth D1 can range from about 10 nm to about 50 nm, and the second depth D2 can range from about 40 nm to about 80 nm. Preferably, the first depth D1 can range from about 20 nm to about 40 nm, and the second depth D2 can range from about 50 nm to about 70 nm.

[0081] In some embodiments, the side surface of the second recess RP2 may contact the side surface of the first source / drain region 160. For example, the second recess RP2 may expose the side surface of the first source / drain region 160. In this case, the contact area between the second source / drain contact CA12 and the first source / drain region 160 can be increased to improve resistance. In other embodiments, the contact area between the second source / drain contact CA12 and the first source / drain region 160 may be greater than the contact area between the first source / drain contact CA11 and the first source / drain region 160. As described above, this may be because the second recess RP2 of the second source / drain contact CA12 is formed to be deeper than the first recess RP1 of the first source / drain contact CA11.

[0082] In some other embodiments, the second source / drain contact CA12 may further include a second contact CP2. The second contact CP2 may protrude from the upper surface of the second extension EP2. The second source / drain contact CA12 can connect to the first power line V via the second contact CP2. DD touch.

[0083] The third source / drain contact CA13 can be disposed on at least one side of the gate electrodes G1 to G3. For example, the third source / drain contact CA13 can be formed on the second active region AR2 between the first gate electrode G1 and the second gate electrode G2. The third source / drain contact CA13 is formed within an insulating film (e.g., field insulating film 105 and first interlayer insulating film 110) covering the second active region AR2, and can be connected to the second active region AR2.

[0084] In other embodiments, the third source / drain contact CA13 can connect the second active region AR2 to the second power line V. SS For example, connecting the third source / drain contact CA13 and the second power line V. SS The wiring path VA can be formed within the third interlayer insulating film 220. The third source / drain contact CA13 extends along the second direction Y on the second power region PW2 and the second active region AR2, and can connect the second source / drain region 260 and the wiring path VA.

[0085] The third source / drain contact CA13 may be recessed downwards from the second source / drain region 260 toward the upper surface of the substrate 100. Since the shape of the third source / drain contact CA13 may be similar to that of the second source / drain contact CA12, a detailed description thereof will not be provided below.

[0086] The fourth source / drain contact CA21 may be disposed on at least one side of the gate electrodes G1 to G3. For example, the fourth source / drain contact CA21 may be formed on the third active region AR3 between the first cell separation pattern IB1 and the first gate electrode G1. The fourth source / drain contact CA21 is formed within an insulating film (e.g., field insulating film 105 and first interlayer insulating film 110) covering the third active region AR3, and may be connected to the third active region AR3.

[0087] The fifth source / drain contact CA22 can be disposed on at least one side of the gate electrodes G1 to G3. For example, the fifth source / drain contact CA22 can be formed on the third active region AR3 between the first gate electrode G1 and the second gate electrode G2. The fifth source / drain contact CA22 is formed within an insulating film (e.g., field insulating film 105 and first interlayer insulating film 110) covering the third active region AR3, and can be connected to the third active region AR3.

[0088] The gate contact CB can be configured to correspond to the respective gate electrodes G1 to G3. Furthermore, the gate contact CB can be connected to each of the gate electrodes G1 to G3. For example, as... Figure 3 As shown, each gate contact CB sequentially penetrates the second interlayer insulating film 210, the first interlayer insulating film 110, and the gate cover pattern 150, and can be connected to the gate conductive film 130.

[0089] Wiring lines RW1 and RW2 can be disposed within the first unit area CR1. Wiring lines RW1 and RW2 can be spaced apart from each other and extend side-by-side in the first direction X. In some embodiments, wiring lines RW1 and RW2 can be disposed adjacent to the first power line V. DD Second power line V SS At the same height. For example, the first power line V. DD Second power supply line V SS And wiring lines RW1 and RW2 can be set inside the fourth interlayer insulating film 230.

[0090] The gate contact CB can connect at least some of the gate electrodes G1 to G3 to the wiring lines RW1 and RW2. For example, as Figure 3 As shown, the gate contact portion CB penetrates the second interlayer insulating film 210, the first interlayer insulating film 110 and the gate cover pattern 150, and can connect the gate conductive film 130 and the first wiring line RW1.

[0091] The first source / drain contact CA11 can connect the first active area AR1 and / or the second active area AR2 to at least a portion of the wiring lines RW1 and RW2. For example, as Figure 4 As shown, the wiring path VA connecting the first source / drain contact CA11 and the second wiring line RW2 can be formed within the third interlayer insulating film 220. The first source / drain contact CA11 can connect the first source / drain region 160 and / or the second source / drain region 260 to the second wiring line RW2 through the wiring path VA. In some embodiments, the wiring path VA can contact the first contact portion CP1 of the first source / drain contact CA11.

[0092] In some embodiments, the source / drain contacts CA11 to CA22, the gate contact CB, the wiring path VA, the wiring lines RW1 and RW2, and the first power line V DD Second power line V SS Each of these can include barrier films 212, 216, and 222 and filler films 214, 218, and 224. As shown, these barrier films 212, 216, and 222 can be inserted between interlayer insulating films 110, 210, 220, and 230 and filler films 214, 218, and 224. Barrier films 212, 216, and 222 can include metals or metal nitrides for preventing diffusion of filler films 214, 218, and 224. For example, barrier films 212, 216, and 222 can include, but are not limited to, at least one of the following: titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), cobalt (Co), platinum (Pt), alloys thereof, and nitrides thereof.

[0093] Filler films 214, 218, and 224 can fill the remaining space within the interlayer insulating films 110, 210, 220, and 230 after the formation of barrier films 212, 216, and 222. Filler films 214, 218, and 224 can be, but are not limited to, at least one of aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), cobalt (Co), and their alloys.

[0094] Although only wiring path VA, wiring lines RW1 and RW2, and the first power line V are shown. DD Second power line V SS Cases formed by dual damascene process, but this is just an example, and they can certainly be formed by single damascene process or other wiring processes.

[0095] As semiconductor devices become increasingly integrated, the performance degradation caused by parasitic capacitance becomes more severe. For example, the parasitic capacitance between the source / drain contacts and the gate electrode is a cause of reduced AC performance in semiconductor devices. In particular, because the source / drain contacts can be further recessed in regions where no source / drain region (or epitaxial layer) is formed (e.g., intermediate region MR), the problem of parasitic capacitance between the source / drain contacts and the gate electrode becomes even more serious.

[0096] However, the semiconductor device according to some embodiments may include a first source / drain contact CA11 that is formed relatively shallow, even if a portion of it is disposed in the intermediate region MR. Specifically, as described above, the first source / drain contact CA11 may include a first recess RP1 that is formed relatively shallower than a second recess RP2 of the second source / drain contact CA12. Therefore, since the parasitic capacitance generated between the first source / drain contact CA11 and the adjacent gate electrode (e.g., the first gate electrode G1) is reduced, a semiconductor device with improved performance can be provided.

[0097] Furthermore, the semiconductor device according to some embodiments may include a second source / drain contact CA12 (or a third source / drain contact CA13) formed relatively deep within the first power supply region PW1 (or the second power supply region PW2). Specifically, as described above, the second source / drain contact CA12 may include a second recess RP2 formed relatively deeper than the first recess RP1 of the first source / drain contact CA11. Therefore, the resistance between the second source / drain contact CA12 (or the third source / drain contact CA13) supplied with the power supply voltage and the first source / drain region 160 (or the second source / drain region 260) is increased, and a semiconductor device with improved performance can be provided.

[0098] Figure 8 and Figure 9 This is a cross-sectional view used to illustrate a semiconductor device according to some embodiments. For reference, Figure 8 It is along Figure 1 Another cross-sectional view taken from line AA, and Figure 9 It is along Figure 1 Another cross-sectional view taken from line BB. For ease of explanation, the use of lines will be briefly described or omitted. Figures 1 to 7 The repeated parts of the above description.

[0099] refer to Figure 8 and Figure 9In a semiconductor device according to some embodiments, each of the active patterns F1 to F5 includes a plurality of wire patterns 114, 116, and 118. For example, each of the active patterns F1 to F5 may include: first wire patterns to third wire patterns 114, 116, and 118, which are sequentially stacked on the upper surface of the substrate 100 and spaced apart from each other. As an example, the first wire pattern 114 may be spaced apart from the substrate 100 in a third direction Z, the second wire pattern 116 may be spaced apart from the first wire pattern 114 in a third direction Z, and the third wire pattern 118 may be spaced apart from the second wire pattern 116 in a third direction Z.

[0100] Each of the first to third conductor patterns 114, 116, and 118 can extend in the first direction X. Furthermore, each of the first to third conductor patterns 114, 116, and 118 can penetrate the gate electrodes G1 to G3. Therefore, as... Figure 9 As shown, the gate electrodes G1 to G3 can have shapes surrounding the outer peripheral surfaces of the first to third conductor patterns 114, 116, and 118. Although each of the cross-sections of the first to third conductor patterns 114, 116, and 118... Figure 9 The diagram is shown as a rectangular shape, but this is merely an example. For example, the cross-sections of the first to third conductor patterns 114, 116, and 118 may be configured as polygons or circles, for example, other shapes. In some embodiments, unlike the case shown, the widths of the first to third conductor patterns 114, 116, and 118 may also decrease as they move away from the upper surface of the substrate 100.

[0101] In some embodiments, each of the active patterns F1 to F5 may further include a fin pattern 112 that protrudes from the upper surface of the substrate 100 and extends in a first direction X. A first conductor pattern 114 may be spaced apart from, for example, the fin pattern 112 in a third direction Z. While only fin transistors (FinFETs) including channel regions with fin patterns and transistors including channel regions with conductor patterns (nanowires or nanosheets) are described as semiconductor devices according to some embodiments, these are merely examples. As another example, semiconductor devices according to some embodiments may of course include tunneling transistors (tunneling FETs), vertical FETs (VFETs), complementary FETs (CFETs), or three-dimensional (3D) transistors. Alternatively, semiconductor devices according to some embodiments may also include bipolar junction transistors, laterally diffused metal-oxide semiconductors (LDMOS), etc.

[0102] Figure 10 It is a schematic layout diagram used to illustrate a semiconductor device according to some embodiments. Figure 11 It is along Figure 10The cross-sectional view taken from line EE. For ease of explanation, the use of [the term] will be briefly described or omitted. Figures 1 to 9 The repeated parts of the above description.

[0103] refer to Figure 10 and Figure 11 In a semiconductor device according to some embodiments, a second source / drain contact CA12 connects a first active region AR1 and a third active region AR3. For example, the second source / drain contact CA12 extends along a second direction Y over the first active region AR1, the first power region PW1, and the third active region AR3, and can connect the first source / drain region 160 and the third source / drain region 360.

[0104] In some embodiments, the side surface of the second recess RP2 may contact the side surface of the third source / drain region 360. In this case, the contact area between the second source / drain contact CA12 and the third source / drain region 360 can be increased to improve resistance.

[0105] In some embodiments, the contact area between the second source / drain contact CA12 and the third source / drain region 360 can be larger than that between the first source / drain contact ( Figure 4 The contact area between CA11 and the first source / drain region 160. As described above, this is because the second recess RP2 of the second source / drain contact CA12 is formed to be deeper than the first recess RP1 of the first source / drain contact CA11.

[0106] Figure 12 It is a schematic layout diagram used to illustrate a semiconductor device according to some embodiments. Figure 13 It is along Figure 12 The cross-sectional view is taken from line FF. For ease of explanation, the use of lines will be briefly described or omitted. Figures 1 to 9 The repeated parts of the above description.

[0107] refer to Figure 12 and Figure 13 In a semiconductor device according to some embodiments, a portion of the second source / drain contact CA12 is disposed in the intermediate region MR. For example, the second source / drain contact CA12 may extend along a second direction Y over the first power region PW1, the first active region AR1, and the intermediate region MR. The second source / drain contact CA12 may include a third recess RP3, which is further recessed from the second extension EP2 in the intermediate region MR. For example, the third recess RP3 may be in the form of protruding from the lower surface of the second extension EP2 disposed in the intermediate region MR.

[0108] In some embodiments, the side surface of the third recess RP3 may contact the side surface of the first source / drain region 160. In this case, the contact area between the second source / drain contact CA12 and the first source / drain region 160 can be increased to improve resistance.

[0109] The third recess RP3 of the second source / drain contact CA12 can be formed to be shallower than the second recess RP2 of the second source / drain contact CA12. For example, with reference to the upper surface of the substrate 100, the third height H3 of the lowest surface of the third recess RP3 can be higher than the second height H2 of the lowest surface of the second recess RP2. In some embodiments, with reference to the upper surface of the substrate 100, the third height H3 of the lowest surface of the third recess RP3 can be equal to the first height H2 of the lowest surface of the first recess RP1. Figure 4 The H1) are the same. As used herein, the term “same” means not only completely identical cases, but also includes minor differences that may arise due to process allowances, etc.

[0110] Figure 14 This is a schematic layout diagram used to illustrate semiconductor devices according to some embodiments. For ease of explanation, the use of words will be briefly described or omitted. Figures 1 to 13 The repeated parts of the above description. (See reference.) Figure 14 In a semiconductor device according to some embodiments, a first cell region CR1 includes a first active pattern group F11 to F13 and a second active pattern group F14 to F16, and a second cell region CR2 includes a third active pattern group F21 and F22. The first active pattern groups F11 to F13, the second active pattern groups F14 to F16, and the third active pattern groups F21 and F22 are spaced apart from each other and can extend side by side in a first direction X.

[0111] The first source / drain contact CA11 can connect the first active pattern group F11 to F13 to the second active pattern group F14 to F16. The second source / drain contact CA12 can connect the first active pattern group F11 to F13 to the first power line V. DD Connection. The third source / drain contact CA13 can connect the second active pattern group F14 to F16 to the second power line V. SS connect.

[0112] In some embodiments, at least a portion of the second source / drain contact CA12 can connect the first active pattern groups F11 to F13 to the third active pattern groups F21 and F22. In some embodiments, at least a portion of the third source / drain contact CA13 can connect the second active pattern groups F14 to F16 to the third active pattern groups F21 and F22.

[0113] In some embodiments, semiconductor elements (e.g., transistors) with different conductivity types may also be formed on the first active pattern groups F11 to F13 and the second active pattern groups F14 to F16. Furthermore, in some embodiments, semiconductor elements (e.g., transistors) with different conductivity types may be formed on the first active pattern groups F11 to F13 and the third active pattern groups F21 and F22. In some embodiments, the first region I to the fourth region IV, arranged along the first direction X, may be defined within the first unit region CR1. In the first region I to the fourth region IV, the first unit region CR1 may have a different number of active patterns.

[0114] As an example, as shown in the figure, the first active pattern group F11 to F13 may include: a sixth active pattern F11 extending over the first region I to the fourth region IV; a seventh active pattern F12 extending over the first region I to the third region III; and an eighth active pattern F13 extending over the first region I. Furthermore, for example, as shown in the figure, the second active pattern group F14 to F16 may include: a ninth active pattern F14 extending over the first region I and the second region II; a tenth active pattern F15 extending over the first region I to the third region III; and an eleventh active pattern F16 extending over the first region I to the fourth region IV.

[0115] In the following text, reference will be made to Figures 1 to 35 A method for manufacturing a semiconductor device according to an exemplary embodiment is described. Figures 15 to 34 This is a diagram illustrating intermediate stages of a method for manufacturing a semiconductor device according to some embodiments. For ease of explanation, the use of [specific terms] will be briefly described or omitted. Figures 1 to 7 The repeated parts of the above description.

[0116] refer to Figures 15 to 19 Active patterns F1 to F5 and gate electrodes G1 to G3 are formed on substrate 100. For example, substrate 100 may include a first power region PW1, a second power region PW2, a first cell region CR1, and a second cell region CR2. Active patterns F1 to F5 may be formed on substrate 100. In some embodiments, a substrate trench DT defining a first active region AR1, a second active region AR2, and a third active region AR3 may be formed within substrate 100.

[0117] Subsequently, a field insulating film 105 can be formed on the substrate 100. The field insulating film 105 can be formed to surround at least a portion of the side surfaces of the active patterns F1 to F5. Gate electrodes G1 to G3 can then be formed on the active patterns F1 to F5 and the field insulating film 105. The gate electrodes G1 to G3 can each include a gate conductive film 130, a gate dielectric film 120, a gate spacer 140, and a gate capping pattern 150. The gate conductive film 130 can be formed using, but is not limited to, alternative processes.

[0118] Then, first source / drain regions to third source / drain regions 160, 260, and 360 can be formed on the active patterns F1 to F5. The first source / drain regions to third source / drain regions 160, 260, and 360 can be formed on any side of the gate electrodes G1 to G3 within the active patterns F1 to F5. Next, a field insulating film 105, a first interlayer insulating film 110 and a second interlayer insulating film 210 covering the first source / drain regions to third source / drain regions 160, 260, and 360, and the gate electrodes G1 to G3 can be formed.

[0119] In some embodiments, a first gate dicing pattern CT1 and a second gate dicing pattern CT2 may be formed for dicing gate electrodes G1 to G3. Although the first gate dicing pattern CT1 and the second gate dicing pattern CT2 may be formed, for example, before performing a replacement process, the embodiments are not limited thereto.

[0120] refer to Figures 20 to 22 A first mask pattern 510 and a second mask pattern 520 are formed on the second interlayer insulating film 210. The second mask pattern 520 may include source / drain contact openings OA11 to OA22. Each of the source / drain contact openings OA11 to OA22 may be connected to... Figures 1 to 7 The source / drain contacts CA11 to CA22 correspond to each other. For example, first source / drain contact openings OA11, second source / drain contact openings OA12, third source / drain contact openings OA13, fourth source / drain contact openings OA21 and fifth source / drain contact openings OA22 may be formed to overlap with the first source / drain region 160, the second source / drain region 260 or the third source / drain region 360. The second mask pattern 520 may include, but is not limited to, photoresist.

[0121] The first mask pattern 510 can be patterned by the second mask pattern 520. The first mask pattern 510 can have etch selectivity for the first interlayer insulating film 110 and the second interlayer insulating film 210 covering the first source / drain regions to the third source / drain regions 160, 260 and 360. Therefore, the first mask pattern 510 can be used as an etching mask in a process of etching the first interlayer insulating film 110 and the second interlayer insulating film 210 to expose the first source / drain regions to the third source / drain regions 160, 260 and 360. The first mask pattern 510 can include, but is not limited to, a hard mask.

[0122] refer to Figures 23 to 25A protective pattern 530 is formed on the second interlayer insulating film 210. At least a portion of the protective pattern 530 may be disposed within the intermediate region MR. For example, the protective pattern 530 may extend within the intermediate region MR in the first direction X. At least a portion of the protective pattern 530 may correspondingly overlap with the source / drain contact openings OA11 to OA22 disposed within the intermediate region MR. For example, the protective pattern 530 may overlap with the portion of the first source / drain contact opening OA11 disposed within the intermediate region MR.

[0123] The protective pattern 530 may not be located within the first power region PW1 and the second power region PW2. Therefore, the protective pattern 530 may not overlap with the source / drain contact openings OA11 to OA22 located within the first power region PW1 and the second power region PW2. For example, the protective pattern 530 may not overlap with the portion of the second source / drain contact opening OA12 located within the first power region PW1. The protective pattern 530 may include, but is not limited to, a spin-on hard mask (SOH).

[0124] Now for reference Figure 23 , Figure 26 and Figure 27 A first etching process is performed using a first mask pattern 510, a second mask pattern 520, and a protective pattern 530. The first etching process can etch the portions of the second interlayer insulating film 210 that overlap with the source / drain contact openings OA11 to OA22. For example, a third recess 210r can be formed in the second interlayer insulating film 210 that overlaps with the source / drain contact openings OA11 to OA22.

[0125] The protective pattern 530 can protect the second interlayer insulating film 210 during the first etching process. For example, as... Figure 26 As shown, the region of the second interlayer insulating film 210 that overlaps with the protective pattern 530 may have the following step H11: it has a region of the second interlayer insulating film 210 that overlaps with the source / drain contact openings OA11 to OA22 but does not overlap with the protective pattern 530. Due to the performance of the first etching process, the second mask pattern 520 and the protective pattern 530 can be removed.

[0126] refer to Figure 23 , Figure 28 and Figure 29A second etching process is performed to expose the first source / drain regions to the third source / drain regions 160, 260, and 360. The second etching process may etch a first interlayer insulating film 110 and a second interlayer insulating film 210 that overlap with the source / drain contact openings OA11 to OA22. The source / drain contact openings OA11 to OA22 may accordingly expose the first source / drain regions to the third source / drain regions 160, 260, and 360. In some embodiments, the second etching process may etch a portion of the first source / drain regions to the third source / drain regions 160, 260, and 360.

[0127] Through a second etching process, the regions of the source / drain contact openings OA11 to OA22 that do not overlap with the first to third source / drain regions 160, 260, and 360 can have a form that is recessed downwards from the first to third source / drain regions 160, 260, and 360 toward the upper surface of the substrate 100. For example, the first source / drain contact opening OA11 may include a first recess 110r1 disposed within the intermediate region MR, and the second source / drain contact opening OA12 may include a second recess 110r2 disposed within the first power region PW1.

[0128] Before performing the second etching process, because the area of ​​the second interlayer insulating film 210 overlapping with the protective pattern 530 can have a step H11, the first recess 110r1 can be formed to be shallower than the second recess 110r2. For example, with the upper surface of the substrate 100 as a reference, the first height H1 of the lowermost surface of the first recess 110r1 can be higher than the second height H2 of the lowermost surface of the second recess 110r2. The second etching process can be performed after the first etching process, or it can be performed in situ together with the first etching process.

[0129] refer to Figures 30 to 32 Source / drain contacts CA11 to CA22 are formed in the first interlayer insulating film 110 and the second interlayer insulating film 210. Source / drain contacts CA11 to CA22 can be formed to fill the source / drain contact openings ( Figure 23 (OA11 to OA22). Therefore, source / drain contacts CA11 to CA22 connected to the first active region AR1, the second active region AR2, or the third active region AR3 can be formed.

[0130] Furthermore, the source / drain contacts CA11 to CA22 can be formed to fill the first recess ( Figure 28 110r1) and the second depression ( Figure 29 (110r2). Therefore, a first source / drain contact CA11 including a first recess RP1 can be formed, and a second source / drain contact CA12 including a second recess RP2 can be formed.

[0131] refer to Figure 30 , Figure 33 and Figure 34 This causes a portion of the source / drain contacts CA11 to CA22 to be recessed. The source / drain contacts CA11 to CA22 are connected to the wiring path ( Figure 1 The area overlapping with the VA (va) can be left unrecessed. That is, the source / drain contacts CA11 to CA22 do not overlap with the wiring path ( Figure 1 At least a portion of the overlapping area of ​​the VA can be recessed. Therefore, a first source / drain contact CA11 including a first contact CP1 can be formed, and a second source / drain contact CA12 including a second contact CP2 can be formed.

[0132] Next, refer to Figures 1 to 7 This forms the gate contact CB, wiring path VA, wiring lines RW1 and RW2, and first power line V. DD Second power line V SS Therefore, methods can be provided for manufacturing semiconductor devices with reduced parasitic capacitance and improved performance.

[0133] Figure 35 This is a diagram illustrating intermediate stages of a method for manufacturing a semiconductor device according to some embodiments. For ease of explanation, the above descriptions will be brief or omitted. Figures 14 to 34 The repeated parts of the description. (See reference) Figure 35 In a method of manufacturing a semiconductor device according to some embodiments, a protective pattern 530 is inserted between a first active pattern group F11 to F13 and a second active pattern group F14 to F16.

[0134] The protective pattern 530 may not be provided within the first power region PW1 and the second power region PW2. Therefore, a relatively shallow first source / drain contact CA11 can be formed even if a portion of it is located within the intermediate region MR. Furthermore, a relatively deep second source / drain contact CA12 (or a third source / drain contact CA13) can be formed within the first power region PW1 (or the second power region PW2).

[0135] In some embodiments, the protective pattern 530 may have different widths in the first region I to the fourth region IV. Here, the width of the protective pattern 530 refers to its width in the second direction Y. As an example, as shown, the width of the protective pattern 530 may increase from the first region I to the fourth region IV.

[0136] In concluding with the detailed description, those skilled in the art will understand that many variations and modifications can be made to the preferred embodiments without departing substantially from the principles of the invention. Therefore, the preferred embodiments disclosed herein are for general and descriptive purposes and not for limiting purposes.

Claims

1. A semiconductor device, comprising: The substrate includes a first power region and a second power region, and a cell region extending between the first power region and the second power region. The first active region and the second active region extend side by side in a first direction within the unit region; A first power line extends in the first power area in the first direction; The first source / drain contact portion connects the first active region and the second active region; as well as The second source / drain contact connects the first active area and the first power line. The first source / drain contact portion includes a first recess, which is disposed in the intermediate region between the first active region and the second active region. The second source / drain contact includes a second recess, which is disposed within the first power supply area, and Wherein, relative to the upper surface of the substrate, the lowermost surface of the first recess is higher than the lowermost surface of the second recess.

2. The semiconductor device according to claim 1, in, The first source / drain contact portion further includes: a first extension portion extending over the first active region, the intermediate region, and the second active region. The first recessed portion protrudes from the lower surface of the first extension portion. The second source / drain contact further includes a second extension extending over the first power region and the first active region. The second recessed portion protrudes from the lower surface of the second extension portion.

3. The semiconductor device according to claim 2, further comprising: The wiring lines extend within the unit area and in the first direction. The first source / drain contact portion further includes: a first contact portion protruding from the upper surface of the first extension portion and connected to the wiring line, and The second source / drain contact portion further includes a second contact portion that protrudes from the upper surface of the second extension portion and is connected to the first power line.

4. The semiconductor device according to claim 1, further comprising: The gate electrode extends on the substrate in a second direction intersecting the first direction, and The first source / drain contact is disposed on one side of the gate electrode, and the second source / drain contact is disposed on the other side of the gate electrode.

5. The semiconductor device according to claim 1, further comprising: The first active pattern extends in the first direction over the first active region; The second active pattern extends in the first direction over the second active region; as well as A field insulating film is provided on the substrate surrounding the side surfaces of the first active pattern and the second active pattern.

6. The semiconductor device according to claim 5, wherein, The lowest surface of the first recess is higher than the upper surface of the field insulating film relative to the upper surface of the substrate.

7. The semiconductor device according to claim 5, wherein, The lowest surface of the second recess is lower than the upper surface of the field insulating film relative to the upper surface of the substrate.

8. The semiconductor device according to claim 5, wherein, The substrate further includes: a substrate trench extending in the first direction, the substrate trench separating the first active region from the second active region, and wherein the field insulating film at least partially fills the substrate trench.

9. The semiconductor device according to claim 1, further comprising: The second power line extends in the first direction within the second power area; as well as The third source / drain contact connects the second active area and the second power line. The third source / drain contact includes a third recess disposed within the second power supply area, and Wherein, relative to the upper surface of the substrate, the lowermost surface of the first recess is higher than the lowermost surface of the third recess.

10. A semiconductor device, comprising: The substrate includes a first cell region and a second cell region extending side-by-side in a first direction, and a power supply region extending between the first cell region and the second cell region. The first active region and the second active region extend side by side in the first direction within the first unit region; A gate electrode extends on the substrate in a second direction intersecting the first direction; A power line extends in the first direction within the power area; The first source / drain contact on one side of the gate electrode is connected to the first active region; as well as On the other side of the gate electrode, a second source / drain contact connects the first active region and the power supply line. The first source / drain contact portion includes a first recess, which is disposed in the intermediate region between the first active region and the second active region. The second source / drain contact includes a second recess extending within the power supply area, and Wherein, relative to the upper surface of the substrate, the lowermost surface of the first recess is higher than the lowermost surface of the second recess.

11. The semiconductor device according to claim 10, in, The first source / drain contact portion further includes: a first extension portion extending over the first active region, the intermediate region, and the second active region. The first recessed portion protrudes from the lower surface of the first extension portion. The second source / drain contact further includes a second extension that extends in the second direction over the power supply region and the first active region. The second recessed portion protrudes from the lower surface of the second extension portion.

12. The semiconductor device according to claim 10, wherein, The first source / drain contact connects the first active region to the second active region.

13. The semiconductor device according to claim 10, further comprising: The wiring extends in the first direction within the first unit area, and wherein the first source / drain contact connects the first active area to the wiring.

14. The semiconductor device according to claim 10, wherein, The substrate further includes: a third active region extending in the first direction within the second cell region, wherein the second source / drain contact connects the first active region to the third active region.

15. The semiconductor device of claim 10, further comprising: The gate cutting pattern extends in the first direction and cuts the gate electrode, and extends within the power supply region.

16. A semiconductor device, comprising: A substrate having a cell region extending between a first power region and a second power region extending side-by-side along a first direction, and the cell region including a first active region and a second active region at side-by-side positions within the cell region. The first active pattern extends in the first direction over the first active region; The second active pattern extends in the first direction over the second active region; The gate electrode extends in a second direction intersecting the first direction on the first active pattern and the second active pattern; An insulating film covering the first active pattern, the second active pattern, and the gate electrode on the substrate; A first power supply line extends in the first power area in the first direction and provides a first power supply voltage; The second power supply line extends in the second power supply area in the first direction and provides a second power supply voltage that is different from the first power supply voltage. The first source / drain contact portion connects the source / drain region of the first active pattern and the source / drain region of the second active pattern within the insulating film; as well as The second source / drain contact connects the source / drain region of the first active pattern and the first power line within the insulating film. The insulating film includes: a first recess disposed between the first active region and the second active region and having a first depth; and a second recess disposed within the first power region and having a second depth greater than the first depth. Wherein, the first source / drain contact portion includes a first recess portion that fills the first depression, and The second source / drain contact portion includes a second recess portion that fills the second depression.

17. The semiconductor device of claim 16, further comprising: A field insulating film is provided on the substrate surrounding the side surfaces of the first active pattern and the second active pattern. as well as An interlayer insulating film covers the gate electrode, the source / drain region of the first active pattern, and the source / drain region of the second active pattern on the field insulating film.

18. The semiconductor device of claim 16, further comprising: The wiring extends in the first direction within the unit area. The first source / drain contact portion connects the source / drain area of ​​the first active pattern and the wiring line.

19. The semiconductor device according to claim 16, wherein, The first depth is 20 nm to 40 nm relative to the uppermost part of the source / drain region of the first active pattern, and the second depth is 50 nm to 70 nm.

20. The semiconductor device according to claim 16, wherein, The first active region and the second active region have different conductivity types.

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