Packaging components, packages and their manufacturing methods

Abstract

A packaging structure and manufacturing method are provided, thereby providing a bonding dielectric material layer on the back side of a wafer and a bonding dielectric material layer on the front side of an adjacent wafer, wherein the bonding dielectric material layers are fused together with each other. Embodiments of this application also relate to packaging components, packages, and methods of manufacturing the same.

Description

Technical Field

[0001] Embodiments of this application relate to packaging components, packages, and methods of manufacturing the same. Background Technology

[0002] Semiconductor devices are used in a wide range of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and then using photolithography to pattern the individual material layers to form circuit components and elements. Tens or hundreds of integrated circuits are typically fabricated on a single semiconductor wafer. The individual dies are separated by scribe-cutting the integrated circuits. The individual dies are then packaged separately in multi-chip modules or other types of packages.

[0003] The semiconductor industry has experienced rapid growth due to the ever-increasing integration density of various electronic components, such as transistors, diodes, resistors, capacitors, etc. In most cases, this increase in integration density stems from the repeated reduction in the size of the smallest components (e.g., shrinking semiconductor process nodes to below 20nm), which allows more components to be integrated into a given area. With the recent growth in demand for miniaturization, higher speeds and greater bandwidth, as well as lower power consumption and latency, there is a growing need for smaller and more innovative packaging technologies for semiconductor dies.

[0004] With the further development of semiconductor technology, stacked semiconductor devices, such as three-dimensional integrated circuits (3DICs), have emerged as an effective option for further reducing the physical size of semiconductor devices. In stacked semiconductor devices, active circuits, such as logic, memory, and processor circuits, are fabricated on different semiconductor wafers. Two or more semiconductor wafers can be mounted or stacked on top of each other to further reduce the form factor of the semiconductor device. A stacked package (POP) device is a type of 3DIC in which a die is packaged and then combined with one or more other packaged dies. Summary of the Invention

[0005] Some embodiments of this application provide a method of manufacturing a package, comprising: thinning a first wafer to expose a metal via; forming a bonding layer over the metal via, the metal via extending through the bonding layer; positioning a second wafer onto the first wafer, wherein bonding pads of the second wafer are aligned with the metal via of the first wafer; bonding the bonding pads of the second wafer to the metal via of the first wafer without using bonding material between the bonding pads and the metal via; and fusing the bonding layer of the first wafer to the bonding layer of the second wafer.

[0006] Other embodiments of this application provide a package comprising: a first device, the first device including a first set of vias, a first active device, and a first interconnect structure, the first set of vias passing through the first interconnect structure from the front side of the first device to the back side of the first device, the first active device being adjacent to the first interconnect structure; a second device, the second device including a second set of vias, a second active device, a second interconnect structure, a second front bonding layer, and a second reverse bonding layer, the second reverse bonding layer being located on the back side of the second device, the second reverse bonding layer including a first dielectric material, the second front bonding layer being bonded to the first device, wherein the second set of vias passes through the second reverse bonding layer from the second front bonding layer; and a third device, the third device including a third set of vias, a third active device, a third interconnect structure, and a third front bonding layer, the third front bonding layer including a dielectric material identical to the first dielectric material, wherein the third set of vias passes through the third front bonding layer from the third device to the back side of the third device, wherein the second reverse bonding layer is bonded to the third front bonding layer.

[0007] Some embodiments of this application provide a packaging assembly including: a first wafer bonded to a second wafer, wherein, at the bonding interface, a metal via of the first wafer is directly bonded to a bonding pad of the second wafer, and a first bonding layer of the first wafer is fused to a second bonding layer of the second wafer, the first bonding layer being disposed on the back side of the first wafer, and the metal via of the first wafer passing through the first bonding layer, through a semiconductor substrate, and through a first interconnect of the first wafer. Attached Figure Description

[0008] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0009] Figures 1 to 2 , Figures 3a to 3d and Figures 4 to 10 Intermediate steps in the process of forming a first wafer of a package according to some embodiments are shown.

[0010] Figures 11 to 19 Intermediate steps in the process of forming a second wafer of a package according to some embodiments are shown.

[0011] Figure 20a , Figure 20b and Figures 21 to 26 A wafer stacking configuration according to some embodiments is shown.

[0012] Figures 27 to 30A process for forming a two-layer wafer stack is shown according to some embodiments.

[0013] Figures 31 to 32 A process using a two-layer wafer stack is illustrated according to some embodiments.

[0014] Figures 33 to 34 A process for forming a four-layer wafer stack is shown according to some embodiments.

[0015] Figures 35 to 36 A process using a four-layer wafer stack is shown according to some embodiments.

[0016] Figures 37a to 37d Processes using one, two, and / or four-layer stacks are illustrated according to some embodiments.

[0017] Figures 38a to 38b The process of forming a package using one, two, and / or four stacked components according to some embodiments is illustrated. Detailed Implementation

[0018] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0019] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used to describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientation shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0020] The embodiments provide multi-die stacked structures. In some embodiments, combinations of one-, two-, and four-layer wafer structures can be attached to device wafers, such as controller wafers. Each of the multilayer structures may include an active device and a via through the substrate of the wafer. Before bonding one wafer to another, the substrate may be thinned to expose the vias. A bonding layer can then be formed such that the vias pass through the bonding layer. The vias can be bonded to bonding pads on the next wafer. The multi-die structure can be prefabricated and then subsequently bonded to another wafer, such as a controller wafer.

[0021] Figures 1 to 7 Intermediate steps in the process of forming and preparing die 112 are shown. One or more of dies 112 can be formed as logic dies, such as central processing unit (CPU) dies, microcontroller unit (MCU) dies, input / output (I / O) dies, baseband (BB) dies, application processor (AP) dies, system-on-chip (SoC), integrated system-on-chip (SoIC), etc. One or more of dies 112 can also be memory dies, such as dynamic random access memory (DRAM) dies or static random access memory (SRAM) dies. In the illustrated embodiment, one or more dies or die stacks can be bonded to die 112.

[0022] refer to Figure 1 According to some embodiments, a top view of a wafer 100 having a plurality of dies 112 is shown. The dies 112 may be configured to each include the same die function or different die functions. Between each die 112 are cleaving channels 111 designated for dividing the dies 112 in subsequent processes. Dies 112 can be understood as packaged regions, while cleaving channels 111 can be understood as unpackaged regions. In some embodiments, no active or passive devices are formed in the cleaving channels 111; therefore, in such embodiments, the cleaving channels 111 do not contain active or passive devices.

[0023] exist Figure 2 The diagram shows a cross-sectional view of a portion of wafer 100. Within the shown portion, a first die 112 and a second die 112 separated by a dicing track 111 are depicted. Details have been omitted for simplicity. It should be understood that the illustration of die 112 is for informational purposes and should not be construed as limiting to a particular configuration.

[0024] Die 112 may include a substrate 115 having one or more active or passive devices formed therein. Substrate 115 may be formed of silicon, but it may also be formed of other Group III, IV, and / or V elements, such as silicon, germanium, gallium, arsenic, and combinations thereof. The substrate may also be in the form of silicon-on-insulator (SOI). An SOI substrate may include a layer of semiconductor material (e.g., silicon, germanium, etc.) formed over an insulating layer (e.g., a buried oxide layer, etc.) formed on the silicon substrate. Other substrates that may be used include multilayer substrates, gradient substrates, mixed-orientation substrates, any combination thereof, etc.

[0025] In the illustrated embodiment, wafer 100 includes a device region 110 for each die 112. Device region 110 may include embedded devices such as transistor 118 or other active devices such as diodes, as well as possible passive devices such as capacitors, inductors, and resistors. Above device region 110 is interconnecting devices and interconnecting structures 130 that route input / output signals to the devices.

[0026] Interconnect structure 130 may include a dielectric layer and metal lines and vias formed in the dielectric layer, details of which are not shown for simplicity. The dielectric layer of interconnect structure 130 may also be referred to as an inter-metal dielectric (IMD) layer. Some or all of the dielectric layer may be formed of a low-k dielectric material having a dielectric constant (k value) of less than about 3.0 or about 2.5. The dielectric layer of interconnect structure 130 may be formed of Black Diamond (a registered trademark of Applied Materials), carbon-containing low-k dielectric materials, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), etc. According to other embodiments of the invention, some or all of the dielectric layer may be formed of a non-low-k dielectric material, such as silicon oxide, silicon carbide (SiC), silicon carbonitride (SiCN), silicon carbonitride oxynitride (SiOCN), etc. According to some embodiments of the invention, forming the dielectric layer of interconnect structure 130 includes: depositing a dielectric material containing a pore-forming agent; and then performing a curing process to remove the pore-forming agent, and thus the remaining dielectric layer becomes porous. An etch stop layer, which can be formed from silicon carbide, silicon nitride, etc., can be formed between the IMD layers.

[0027] Metal lines and vias of the interconnect structure 130 are formed in the dielectric layer of the interconnect structure 130. Therefore, the interconnect structure 130 may include multiple metal layers (metal lines located in the same layer) interconnected through the vias of the interconnect structure 130. The metal lines and vias may be formed of copper or a copper alloy, and they may also be formed of other metals. The formation process may include single damascene and double damascene processes. In a single damascene process, a trench is first formed in one of the dielectric layers of the interconnect structure 130, and then the trench is filled with a conductive material. A planarization process, such as CMP, is then performed to remove excess conductive material above the top surface of the IMD layer, leaving metal lines in the trench. In a double damascene process, trenches and via openings are formed in the IMD layer, with the via openings located below and connected to the trench. Conductive material is then filled into the trenches and via openings to form metal lines and vias, respectively. The conductive material may include a diffusion barrier and a copper-containing metal material above the diffusion barrier. The diffusion barrier may include titanium, titanium nitride, tantalum, tantalum nitride, etc.

[0028] According to some embodiments of the present invention, a dielectric layer 132 is formed over the interconnect structure 130. The dielectric layer 132 may be formed of multiple layers. In some embodiments, the dielectric layer 132 may be formed of silicon oxide, silicon oxynitride, silicon oxycarbide, etc.

[0029] Via openings corresponding to vias 120 can be formed through the dielectric layer 132 and into the substrate 115. In some embodiments, the via openings may expose metal components of the interconnect structure 130 for coupling to active and / or passive devices in the device region 110. One or more via openings corresponding to vias 120 may not expose metal components of the interconnect structure 130, such that via materials subsequently formed in the via openings are not coupled to any device in the device region 110 and can be considered pseudo-vias. The via openings can be formed using a photolithography process that uses, for example, photoresist formed and patterned over the dielectric layer 132 and / or a hard mask. Anisotropic etching can be used to form the via openings through photoresist and / or a hard mask.

[0030] Vias 120 and contact pads 125 can be formed above dielectric layer 132. Vias 120 and contact pads 125 can be formed using a process similar to that used to form vias and metal lines of the interconnect structure 130 described above, but other suitable processes can be used. For example, a seed layer can be deposited in the via opening, and the via can be formed, for example, by electroplating or electroless plating, by depositing a conductive material in the via opening on the seed layer. Contact pads 125 can be formed simultaneously or in a subsequent similar process. Vias 120 and contact pads 125 can be formed of copper or a copper alloy, and they can also be formed of other metals.

[0031] In some embodiments, die 112 includes one or more known good dies (KGDs) that have undergone functional testing. In some embodiments, dies 112 that fail testing may not undergo further processing and may be recycled or discarded. In other embodiments, dies 112 that fail testing may be retained in wafer 100 along with the KGDs through further processing and may be recycled or discarded in subsequent steps. For example, in embodiments using wafer-to-wafer bonding processes, the entire undrilled wafer is bonded to wafer 100, while in embodiments using chip-to-wafer bonding processes or chip-to-chip bonding processes, diced chips are bonded to wafer 100 or diced chips are bonded to diced chips of wafer 100. Therefore, in some embodiments, only the KGD dies 112 undergo subsequent packaging processing, and dies that fail CP testing are not packaged.

[0032] Figure 3a , Figure 3b , Figure 3c and Figure 3d Various embodiments using wafer 100 and die 112 in a packaging process are illustrated. Figure 3a and Figure 3b In the process, wafer 100 remains intact and is attached to carrier substrate 190, and... Figure 3c and Figure 3d In the process, wafer 100 is diced to release die 112. KGD can then be attached to carrier substrate 190. Figure 3a and Figure 3c In this configuration, wafer 100 and / or die 112 are rotated (i.e., flipped) and attached face down to carrier substrate 190. Figure 3b and Figure 3d In the process, wafer 100 and / or die 112 are kept facing upwards, and the back side (non-active side) of wafer 100 and / or die 112 is attached to carrier substrate 190.

[0033] Typically, the carrier substrate 190 provides temporary mechanical and structural support for the various components (e.g., wafer 100) during subsequent processing steps. In this way, damage to the die 112 is reduced or prevented. The carrier substrate 190 may include, for example, glass, ceramic, bulk silicon, etc. The release layer 150 may be used to attach the wafer 100 and / or die 112 to the carrier substrate 190. In some embodiments, the carrier substrate 190 may be substantially free of any active devices and / or functional circuitry. In some embodiments, the carrier substrate 190 may include bulk silicon, and the wafer 100 and / or die 112 may be attached to the carrier substrate 190 via the dielectric release layer 150. In some embodiments, the carrier substrate 190 may include a support strip.

[0034] Release layer 150 can be any die attachment film or any suitable adhesive, epoxy resin, UV adhesive (which loses its adhesiveness when exposed to UV radiation), etc. Release layer 150 can be formed over the surface of carrier substrate 190 or the surface of wafer 100 and / or die 112 using deposition processes, spin coating, printing processes, lamination processes, etc. In other embodiments, release layer 150 can be thermally applied, wherein the adhesive strength of release layer 150 is significantly reduced after exposure to a suitable heat source.

[0035] In some embodiments, wafer 100 and / or die 112 are attached to carrier substrate 190 using a fusion bonding process, wherein the insulating layer of wafer 100 is directly bonded to dielectric release layer 150 to form an insulator-to-insulator bond. The following description, in conjunction with the information below... Figure 20a The description of wafer-to-wafer bonding is used to discuss further details regarding fusion bonding.

[0036] In some embodiments, for example, Figure 3c and Figure 3d For example, wafer 100 is diced into individual dies 112 by sawing, laser ablation, etc. The dies can then be positioned on carrier substrate 190 using pick-and-place processes. A gap-filling material 155 can then be deposited to seal the dies 112, and then ground back so that the upper surface of the gap-filling material 155 is flush with the upper surface of the die 112. The gap-filling material 155 can include molding compounds such as epoxy resins, resins, moldable polymers, polyamides, etc. The molding compound can be applied while substantially liquid and then cured by a chemical reaction, such as in epoxy resins or resins. In other embodiments, the molding compound can be a UV (UV) adhesive or a thermosetting polymer applied as a gel or stretchable solid. In some embodiments, the gap-filling material 155 can include non-polymers such as silicon dioxide, silicon nitride, etc., such as another oxide or nitride, which are deposited using any suitable process. For example, the gap-filling material 155 can be formed by CVD, PECVD, or ALD deposition processes, FCVD, or spin-coating glass processes. For ease of reference, the resulting structure may be referred to as wafer 100'; however, it should be recognized that this is not actually a wafer, but can be used in the continued description as an alternative to wafer 100.

[0037] exist Figures 4 to 7 In some embodiments, wafer 100 or wafer 100' faces downwards, for example, as shown in... Figure 3a and Figure 3c As shown. In such an embodiment, the back side of wafer 100 or wafer 100' can be thinned. Although shown is from... Figure 3a The structure, but it should be understood that it can be replaced. Figure 3cThe structure within (called wafer 100'). It can also be replaced. Figure 3b and Figure 3d The structure is as described, but because these surfaces are oriented upwards, they are omitted in this embodiment. Figures 4 to 7 The process is shown. In Figure 4 In this process, wafer 100 is thinned to reduce its thickness. Thinning can be performed using CMP processes, grinding, etching, or other suitable processes. Thinning exposes the vias 120 in wafer 100 and / or die 112, and also reduces the thickness of wafer 100 and / or die 112 to provide better heat dissipation and occupy less vertical spacing. After thinning, the thickness of wafer 100 and / or die 112 can be from about 2 to 100 μm, such as between about 10 and 50 μm. In some embodiments, the top surface of the gap filler 155 and the upper surface (back side) of wafer 100 and / or die 112 are substantially coplanar within the process variations.

[0038] In other embodiments, the via 120 may be formed after thinning the wafer 100 and / or die 112, rather than before thinning. In such embodiments, the via 120 may be formed using processes and materials similar to those described above for forming vias, such as interconnect structures 130.

[0039] According to some embodiments, Figures 5 to 7 This includes adding a bonding layer to Figure 4 The process of thinning the back side of substrate 115. Figure 5 In this process, the substrate 115 can be recessed using any suitable process, such as an etch-back process using a suitable wet or dry etching process. Therefore, the upper sidewall of the via 120 can be exposed. In some embodiments, the substrate 115 can be recessed to a depth between 0.8 μm and about 3 μm, but other dimensions are conceivable and can be used.

[0040] exist Figure 6 In this process, a bonding layer 160 can be deposited over the exposed portion of the via 120. The bonding layer 160 can be any suitable insulating material, such as an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), or polyimide. Any suitable process can be used to deposit the bonding layer 160. For example, the bonding layer 160 can be formed by CVD, PECVD, or ALD deposition processes, FCVD, or spin-coating glass processes.

[0041] exist Figure 7 In this process, the bonding layer 160 can be planarized, for example, by a CMP process, so that the upper surface of the via 120 is flush with the bonding layer 160. The thickness of the bonding layer 160 can be between about 0.8 μm and 3 μm, but other sizes can be considered and used.

[0042] According to some embodiments, Figures 8 to 10 This includes adding a bonding layer to Figure 4 The process of thinning the back side of substrate 115. Figure 8 In this process, a bonding layer 160 is deposited over the substrate 115 and the via 120. The bonding layer 160 can be similar to that described above. Figure 6 The processes and materials discussed are used to form those layers. The thickness of the bonding layer 160 can be between approximately 0.8 μm and 3 μm, but other sizes can be considered and used.

[0043] exist Figure 9 In this process, an opening corresponding to the via 120 is formed in the bonding layer 160. The opening can be formed using any suitable technique, such as mechanical or laser drilling or photolithography. In some embodiments, the opening may have a width larger than the via 120.

[0044] exist Figure 10 In this process, a via extension 165 is deposited in the opening of the bonding layer 160. The via extension 165 may be made of the same or different material as the via 120. The via extension 165 can be formed by any suitable technique, such as by using PVD, CVD, electroplating, electroless plating, etc. In some embodiments, a seed layer and / or a barrier layer may be deposited in the opening and over the bonding layer 160 before depositing the via extension 165. The material of the via extension 165 may protrude over the opening and over the bonding layer 160. After depositing the material of the via extension 165, a planarization technique such as CMP may be used to flush the via extension 165 with the bonding layer 160. In some embodiments, the via extension 165 may be wider than the via 120, forming a pad area.

[0045] In embodiments, wafer 100 and / or die 112 may have wafers or wafer stacks bonded thereto in a multilayer wafer or chip-on-a-chip wafer bonding process. In embodiments using wafer stacks, wafer stacks may be formed separately to be bonded to wafers 100 and / or die 112 in a pre-formed wafer stack. These embodiments are described below.

[0046] exist Figure 11According to some embodiments, a top view of a wafer 200 having a plurality of dies 212 is shown. Dies 212 may be configured to each include the same die function or different die functions. In some embodiments, dies 212 may be formed as logic dies, such as CPU dies, MCU dies, I / O dies, BB dies, AP dies, SoC, SoIC, etc. In other embodiments, one or more of the dies 212 may be memory dies, such as DRAM dies or SRAM dies. In the illustrated embodiments, multiple wafers 200 may be stacked to form a memory device stack. Between each die 212 is a cleaving track 211 designated for dividing the die 212 in subsequent processes. Dies 212 can be understood as packaged regions, while cleaving tracks 211 can be understood as unpackaged regions. Typically, no active or passive devices are formed in cleaving tracks 211, and therefore, cleaving tracks 211 have no active or passive devices.

[0047] exist Figure 12 The diagram shows a cross-sectional view of a portion of wafer 200. Within the shown portion, a first die 212 and a second die 212 separated by a dicing 211 are illustrated. Details have been omitted for simplicity. It should be understood that the illustration of die 212 is for informational purposes and should not be considered as limiting to a particular configuration.

[0048] Die 212 may include a substrate 215 having one or more passive devices formed therein. Substrate 215 may be formed of a material similar to those discussed above with respect to substrate 115, and will not be repeated here.

[0049] Wafer 200 includes device regions 210 for each die 212. Device regions 210 may be similar to device regions 110, as they may include embedded devices such as transistors or other active devices such as diodes, as well as possible passive devices such as capacitors, inductors, resistors, etc. Above device regions 210 are interconnecting devices and interconnecting structures 230 that route input / output signals to the devices. Interconnecting structures 230 may be formed using materials and processes similar to those used for interconnecting structures 130 described above. In particular, interconnecting structures 230 may include several ILD layers, including an uppermost ILD layer, which itself may include multiple layers, such as dielectric layer 132 described above.

[0050] exist Figure 13Via openings 219 can be formed through interconnect structure 230 and into substrate 215. In some embodiments, via openings may expose metal components of interconnect structure 230 for coupling to active and / or passive devices in device region 210. One or more via openings 219 may not expose metal components of interconnect structure 230, such that via material subsequently formed in via opening 219 is not coupled to any device in device region 210 and can be considered pseudo-vias. Via openings 219 can be formed using a photolithography process that uses, for example, a photoresist and / or a hard mask formed and patterned over an upper dielectric layer of interconnect structure 230. Anisotropic etching can be used to form via openings through photoresist and / or a hard mask. Via openings 219 can be formed in substrate 215 in any suitable pattern.

[0051] exist Figure 14 In some embodiments, material for via 220 can be formed over interconnect structure 230. Via 220 can be formed using a process similar to that used to form vias in interconnect structure 130 described above, but other suitable processes can be used. For example, a seed layer can be deposited in via opening 219, and via 220 can be formed by depositing conductive material in via opening 219 on the seed layer, for example by electroplating, electroless plating, PVD, CVD, etc. In some embodiments, contact pads 225 (see...) can be formed simultaneously. Figure 16 The vias 220 can be formed of copper or a copper alloy, or they can be formed of other metals. The material used for the vias 220 can protrude above the via opening 219 and cover a portion of the interconnect structure 230.

[0052] exist Figure 15 In this process, planarization or grinding processes can be used to make the upper surface of the via 220 flush with the upper surface of the interconnect structure 230. Figure 16 In this process, contact pads 225 are formed. Contact pads 225a are physically and electrically coupled to vias 220, while contact pads 225b are not physically coupled to vias 220, but can be physically and electrically coupled to metal lines in interconnect structure 230. Therefore, they can also be electrically coupled to vias 220 through interconnect structure 230. Contact pads 225 can be formed using any suitable process. For example, a resist layer can be deposited and patterned to form openings corresponding to contact pads 225. A seed layer can be deposited in the openings and over the resist layer. Next, contact pads 225 can be deposited using any suitable process and then flush-mounted as needed. Finally, the resist layer can be removed, which also removes the seed layer and any metal deposited on the seed layer over the resist layer. In another embodiment, contact pads 225 can also be deposited by forming a blanket layer of conductive material and etching to remove unwanted portions of the conductive material.

[0053] In another embodiment, a dielectric layer may be deposited over the interconnect structure 230, the openings formed in the dielectric layer corresponding to the contact pads 225, the seed layer deposited in the openings, and the material of the contact pads 225 in the openings deposited on the seed layer. A planarization process can then provide a flat upper surface.

[0054] exist Figure 17 In this process, a dielectric layer 235 is deposited over the contact pad 225. In some embodiments, the dielectric layer 235 (or a sublayer thereof) may correspond to the dielectric layer used to help form the contact pad 225. The thickness of the dielectric layer 235 may be between 0 nm and 50 nm greater than the thickness of the contact pad 225. In other words, in some embodiments, the dielectric layer 235 may be thicker than the contact pad 225, while in other embodiments, the dielectric layer 235 may have an upper surface flush with the upper surface of the contact pad 225.

[0055] Also in Figure 17 In this process, a dielectric layer 240 can be deposited over the contact pad 225 as part of the bonding structure 260 (see...). Figure 19 Dielectric layers 235 and 240 may comprise any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, silicon carbonitride, etc., and may be formed using any suitable process. For example, dielectric layers 235 and 240 may be formed by CVD, PECVD or ALD deposition processes, FCVD or spin-coating glass processes.

[0056] exist Figure 18 In this process, a bonding pad via 245 is formed. The bonding pad via 245 can be formed using processes and materials similar to those used for via 220 described above. In another embodiment, the bonding pad via 245 can be connected to a bonding pad 255 (see...). Figure 19 They are formed simultaneously.

[0057] exist Figure 19In this process, a bonding layer 250 is deposited over the dielectric layer 240. Bonding pads 255 are formed in the bonding layer 250. The bonding pads can be formed using any of the materials and processes described above with respect to contact pads 225. In some embodiments, the bonding layer 250 is formed prior to forming the bonding pad via 245. The bonding pad via 245 and the bonding pad 255 can then be formed simultaneously by forming an opening in the bonding layer 250 corresponding to the bonding pad 255, and then forming an opening in the dielectric layer 240 corresponding to the bonding pad via 245. Next, a barrier layer can be deposited simultaneously in the openings for the bonding pad via 245 and the bonding pad 255, followed by the conductive material of the bonding pad 255. Finally, any excess conductive material can be removed by a planarization or grinding process that flushes the upper surfaces of the bonding pad 255 and the bonding layer 250.

[0058] In some embodiments, bonding layer 250 can be formed of any suitable material and can be between about 0.8 μm and about 3 μm, but other sizes can be used. In some embodiments, bonding layer 250 can be formed of an oxide such as silicon oxide or a nitride such as silicon nitride or polyimide. In some embodiments, bonding layer 250 can be formed of the same material used to form bonding layer 160. Bonding layer 250 is used to form a fusion bond with another bonding layer 250 in a wafer-to-wafer bonding process. Similar processes can also be used to form a fusion bond between bonding layer 250 and bonding layer 160 (see...). Figure 7 and Figure 9 ).

[0059] exist Figure 20a In the process, wafer 200 is flipped and bonded to, for example... Figure 7 or Figure 10 The wafer 100. The bonding technology can be a hybrid bonding technology, wherein the bonding layer 160 of wafer 100 and the bonding layer 250 of wafer 200 are fused together by fusion bonding, and the bonding pad 255 is directly bonded to the via 120 by direct metal-to-metal bonding, without using interface bonding materials, such as solder or other eutectic materials. Hybrid bonding has the advantage of not requiring solder material between the connectors of the two bonding devices. Hybrid bonding creates a bonding interface between two devices, which includes direct metal-to-metal bonding from metal parts in the first device to metal parts in the second device, and fusion bonding (or dielectric-to-dielectric bonding) from insulating material in the first device to insulating material in the second device. Any suitable hybrid bonding process can be used.

[0060] In the hybrid bonding process, bonding pads 255 and bonding layer 250 are aligned and contact vias 120 and bonding layer 160 of wafer 100. Annealing can then be performed to directly bond the conductive materials and fuse the insulating materials together. Annealing causes the metals in bonding pads 255 and vias 120 to diffuse into each other, resulting in a direct metal-to-metal bond. Annealing also causes bonding layer 250 to fuse to bonding layer 160, where they are in direct contact by forming chemical bonds between the two layers. For example, atoms (such as oxygen atoms) in one of the insulating materials of bonding layers 160 and 250 can form chemical bonds or covalent bonds (such as OH bonds) with atoms (such as hydrogen atoms) in the other of bonding layers 160 and 250. The resulting bond between bonding layers 160 and 250 is an insulator-to-insulator bond. Minor variations in the surface of the bonded structure can be overcome by the annealing process, while pressure holds the structure together. In some embodiments, a pressure of about 1 Newton to 10 Newtons may be applied to press the bonding pad 255 and the via 120 together, and to press the bonding layer 250 and the bonding layer 160 together. Other embodiments may not utilize pressure. Hybrid bonding processes can be performed in environments ranging from about 1 atm to about 100 atm (such as about 5 atm). The expansion of the material at the annealing temperature can complete the bonding and substantially eliminate voids.

[0061] The annealing temperature in the hybrid bonding process can be between about 150°C and about 400°C, depending on the strength of the materials of bonding layers 160 and 250. In embodiments where bonding layers 160 and 250 are formed of inorganic dielectric materials such as oxides or oxynitrides, the annealing temperature can be between about 150°C and about 400°C. The annealing time for the hybrid bonding process can be between about 0.5 hours and 5 hours.

[0062] A better fusion bond can be formed by forming bonding layers 160 and 250 specifically for bonding wafer 200 to wafer 100. Specifically, the thickness of bonding layers 160 and 250 is between approximately 0.8 μm and 3 μm or greater, providing sufficient bonding layer thickness to allow chemical bonding to occur. The minimum target thickness of 0.8 μm is important for several reasons. This thickness provides some margin for variations in the layer thicknesses of the two bonding layers 160 and 250. Due to variations in layer thickness, some voids can be observed between the two bonding layers when they are mated together. With a minimum thickness of approximately 0.8 μm, bonding layers 160 and 250 can each expand vertically during annealing, helping to fill these voids. The minimum thickness of 0.8 μm also provides sufficient opportunity for bonding to form between bonding layers 160 and 250. In other words, chemical or covalent bonds can form between the materials in bonding layer 160 and bonding layer 250 during the annealing process. A minimum thickness of approximately 0.8 μm provides sufficient bonding material so that localized bonds in each of bonding layers 160 and 250 can break and reform cross-bonded to the localized bonds of opposing bonding layers 160 and 250. The minimum thickness of 0.8 μm also provides sufficient material to withstand several annealing cycles. As noted above and discussed later, after the different structures are bonded together in the annealing process, subsequent structures (e.g., wafer 200, wafer stack 300, or wafer stack 400) can also be bonded in subsequent annealing processes. As discussed above, each annealing process can be between 0.5 hours and 5 hours. Therefore, bonding layers 160 and 250 must undergo several annealing processes. The minimum thickness of approximately 0.8 μm for bonding layers 160 and 250 provides suitable robustness to withstand these annealing cycles. It should be noted that some embodiments consider other thicknesses, including less than 0.8 μm, depending on the materials of bonding layers 160 and 250. It should also be understood that variations in total thickness can result in the thickness of the bonding layers 160 and 250 being less than 0.8 μm in some regions.

[0063] The conductive materials bonding the bonding pads 255 and the via 120 can have a distinguishable interface. That is, even after bonding, the interface can be observed and it can be determined that the bonding pads 255 and the via 120 were formed separately and bonded together. Similarly, the insulating materials bonding the bonding layers 250 and 160 can also have a distinguishable interface.

[0064] Figure 20a This includes an enlarged (enlarged) portion of the bonding interface. In this enlarged portion, barrier layer 221 is shown surrounding via 220. Similarly, barrier layer 121 is shown surrounding via 120, and barrier layer 246 is shown surrounding bonding pad via 245.

[0065] Figure 20b The hybrid bonding process is illustrated, in which the bottom structure faces upwards instead of downwards, such as... Figure 3b and Figure 3d Provided. In particular, Figure 20b include Figure 3d The structure shown is the bottom structure. Figure 20b The enlarged portion shows the metal-to-metal bonding from bonding pad to bonding pad after the hybrid bonding process, as well as the fusion bonding of bonding layer 250 and dielectric layer 132. The enlarged portion also shows metal components 131 including metal lines and vias in interconnect structure 130, some vias 120 being electrically and physically coupled to the metal components 131 in interconnect structure 130, while other vias 120 may not be electrically and physically coupled to the metal components 131 in interconnect structure 130. Although shown... Figure 3d The structure in the text, but the amplified portion will be applicable. Figure 3b or Figure 3d The structure in.

[0066] exist Figure 21 In this process, any suitable process is used to thin the wafer 200. Thinning can be achieved through CMP, grinding, etching, or other suitable processes. Thinning exposes the via 220 in the die 212 and also reduces the thickness of the die 212 to provide better heat dissipation and occupy less space. After thinning, the thickness of the wafer 200 and the die 212 can be from about 2 μm to 500 μm, for example, between about 10 μm and 50 μm. In some embodiments, the top surfaces of the wafer 200, substrate 215, and via 220 are flush with each other.

[0067] exist Figures 22 to 24 In the embodiment, by adding a reverse bonding layer 265 ( Figure 24 ), wafer 200 is prepared to receive another wafer bonded to it. In some embodiments, such as Figure 22 As shown, the substrate 215 of wafer 200 can be recessed to expose the upper sidewall of via 220. This process can be similar to that described above regarding the use of... Figure 5 The substrate 115 is recessed using a process. Specifically, the substrate can be recessed to a depth of approximately 0.8 μm to 3 μm, or in other words, the via 220 can protrude from the substrate 215 by approximately 0.8 μm to 3 μm. Figure 23 In this process, a reverse bonding layer 265 can be deposited over the exposed via 220. A similar layer to the one described above can be used. Figure 6 The bonding layer 160 describes the processes and materials used to deposit the reverse bonding layer 265. Figure 24In this process, the reverse bonding layer 265 can be planarized using CMP or grinding processes so that the upper surface of the reverse bonding layer 265 is flush with the upper surface of the via 220. This process can be similar to the one described above. Figure 7 The process described is illustrated by the bonding layer 160 and the through-hole 120.

[0068] In other embodiments, the substrate 215 may not be recessed, and a reverse bonding layer 265 may be deposited over the substrate 215 and the exposed via 220, similar to the above description. Figure 8 The described bonding layer 160. Next, an opening can be formed in the reverse bonding layer 265, similar to the one described above. Figure 9 The process described. Then, a through-hole extension can be formed in the opening, and the upper surface of the through-hole extension is flush with the upper surface of the reverse bonding layer 265, similar to the above description. Figure 10 The described process.

[0069] exist Figure 25 In some embodiments, wafer 200 becomes wafer 200a, and another wafer 200b is bonded to wafer 200a. Wafer 200b can use methods such as those described above. Figure 20a The described hybrid bonding technique is used to bond to wafer 200a. For each subsequent hybrid bonding technique, the structure bonded using the hybrid bonding technique may have its increased bond strength when bond annealing is performed. Therefore, in some embodiments, the bond strength between different structures may be different.

[0070] exist Figure 26 In this process, the above-mentioned steps can be repeated on wafer 200b. Figures 21 to 24 The described thinning process and formation of the reverse bonding layer 265 can be used as described above. Figure 20a The described hybrid bonding technique is used to stack and bond additional wafers 200 up to wafer 200n. The total number of wafers 200 can be between about 1 and 16 or more. In some embodiments, each wafer 200 can be bonded using a minimum bonding annealing time (e.g., between 30 and 60 minutes) up to the bonding of the final wafer 200n, where the increased bonding annealing time increases the bonding strength of the already bonded structures while reducing the overall processing time. In some embodiments, the bonding strength between the first bonded wafers will be greater than that of subsequently bonded wafers. For example, the bonding strength between wafers 200a and 200b may be the greatest, followed by the bonding strength between wafers 200b and 200c, and so on.

[0071] Figures 27 to 30 The diagram illustrates a process for attaching a two-layer wafer stack 300 to wafer 100, according to some embodiments. Figure 27 middle, Figure 19The wafer 200 is attached to the carrier substrate 305 via the release layer 310 as wafer 200a. The carrier substrate 305 and the release layer 310 can be made similar to those described above. Figure 3a , Figure 3b , Figure 3c and Figure 3d The material formation of the carrier substrate 190 and the release layer 150 is described. Figure 28 In this way, the above-mentioned matters can be implemented. Figures 21 to 24 The described process is to thin the wafer 200a and form a reverse bonding layer 265 on the wafer 200a.

[0072] exist Figure 29 In the process, the second wafer 200b is bonded to the first wafer 200a using a hybrid bonding process, as described above. Figure 20a As described. In Figure 30 In the process, the carrier substrate 305 can be removed to form a two-layer wafer stack 300. The carrier substrate 305 can be removed by applying UV radiation to the release layer 310, mechanical polishing, etching back, heating, or combinations thereof.

[0073] exist Figure 31 In the middle, two layers of wafer stack 300 are bonded to, for example Figure 10 Wafer 100. Two wafer stacks 300 can be bonded to wafer 100 using hybrid bonding processes, such as those described above. Figure 20a As described.

[0074] exist Figure 32 In this process, two wafer stacks 300 become wafer stack 300a, and the process of bonding the two wafer stacks 300 can be repeated a desired number of times to bond a total of n two wafer stacks 300 to wafer 100. The total number of wafers 200 is twice n. Before bonding each additional two wafer stack 300, the previous two wafer stacks 300 can be processed to thin the top wafer 200 of the two wafer stacks 300 and form a reverse bonding layer 265, as described above. Figures 21 to 24As described. In some embodiments, each wafer stack 300 may be bonded using a minimum bonding annealing time (e.g., between 30 and 60 minutes) until the final wafer stack 300n is bonded, where the bonding annealing time is increased, thereby increasing the bonding strength of the already bonded structures while reducing the overall processing time. In some embodiments, the bonding strength between each pair of wafer stacks 300 will be greater than that of subsequently bonded wafer stacks. For example, the bonding strength between wafer stacks 300a and 300b may be the greatest, followed by the bonding strength between wafer stacks 300b and 300c, and so on. Moreover, in some embodiments, the bonding strength between the individual wafers 200 within a wafer stack 300 is greater than the bonding strength between wafer stacks 300.

[0075] exist Figure 33 In some embodiments, the four-layer wafer stack 400 is formed from individual wafers 200 including wafers 200a, 200b, 200c, and 200d. The four-layer wafer stack 400 can be formed by continuously adding additional wafers 200, for example to... Figure 29 The structure is formed using a process. Before bonding each additional wafer 200, the previous wafer 200 can be processed to thin the wafer 200 and form a reverse bonding layer 265, as described above. Figures 21 to 24 As described. In some embodiments, each wafer 200 can be bonded using a minimum bonding annealing time (such as between 30 and 60 minutes) until the last wafer 200d is bonded, wherein the bonding annealing time is increased, thereby increasing the bonding strength of the already bonded structures while reducing the total processing time.

[0076] exist Figure 34 In some embodiments, the four-layer wafer stack 400 is formed from two-layer wafer stack 300. For example, Figure 34 The four-layer wafer stack 400 can be made possible by adding two additional wafer stacks 300 (see...) Figure 30 Add, for example, to Figure 29 The structure is formed by this. In another embodiment, for example, Figure 30 The two-layer wafer stack 300 can be attached to a carrier substrate, followed by another two-layer wafer stack 300 or two wafers 200 bonded to the first two-layer wafer stack 300. In another embodiment, the two-layer wafer stack 300 can be bonded to the wafer 200, for example, Figure 28 The structure and subsequent another wafer 200. Before bonding each additional wafer 200 or the two-layer wafer stack 300, the previous wafer 200 or the upper wafer 200 of the two-layer wafer stack 300 can be processed to thin the wafer 200 and form a reverse bonding layer 265, as described above. Figures 21 to 24As described.

[0077] exist Figure 35 In this process, the carrier substrate 405 can be removed to form a four-layer wafer stack 400. The four-layer wafer stack 400 is bonded to, for example... Figure 10 Wafer 100. A four-layer wafer stack 400 can be bonded to wafer 100 using hybrid bonding processes, such as those described above. Figure 20a As described.

[0078] exist Figure 36 In this process, the four-layer wafer stack 400 becomes wafer stack 400a, and the process of bonding the four-layer wafer stack 400 can be repeated a desired number of times to bond a total of n four-layer wafer stacks 400 to wafer 100. The total number of wafers 200 is four times n. Before bonding each additional four-layer wafer stack 400, the previous four-layer wafer stack 400 can be processed to thin the top wafer 200 of the four-layer wafer stack 400 and form a reverse bonding layer 265, as described above. Figures 21 to 24 As described. In some embodiments, each wafer stack 400 can be bonded using a minimum bonding annealing time (e.g., between 30 and 60 minutes) until the final wafer stack 400n is bonded, where the bonding annealing time is increased, thereby increasing the bonding strength of the already bonded structures while reducing the overall processing time. In some embodiments, the bonding strength between each four-layer wafer stack 400 will be greater than that of subsequently bonded wafer stacks 400. For example, the bonding strength between wafer stacks 400a and 400b may be the greatest, followed by the bonding strength between wafer stacks 400b and 400c, and so on. Moreover, in some embodiments, the bonding strength between the individual wafers 200 within each wafer stack 400 is greater than the bonding strength between wafer stacks 400.

[0079] exist Figure 37a , Figure 37b , Figure 37c and Figure 37d In this process, any combination of any number and any order of wafers 200, two-layer wafer stacks 300, and / or four-layer wafer stacks 400 can be bonded to... Figure 3a and Figure 3b 100 wafers flowed out or from Figure 3c and Figure 3d The outgoing wafer is 100'. It should be noted that... Figure 37b and Figure 37dIn this context, dielectric layer 132 can be synonymous with bonding layer 160. In some embodiments, wafer 100' can be modified to add bonding layer 160 over gap filler 155 by recessing gap filler 155 and depositing bonding layer 160 at locations where gap filler 155 is removed. In other embodiments, wafer 100' can be modified to add bonding layer 160 over gap filler 155 by depositing bonding layer 160 over gap filler 155 and over die 112, forming openings in bonding layer 160 to expose contact pads 125, and extending contact pads 125 through the openings in bonding layer 160, as described above. Figures 5 to 6 and Figures 8 to 10 These processes are described, and modifications can be made from those embodiments as needed.

[0080] In some embodiments, each wafer 200, two-layer wafer stack 300, or four-layer wafer stack 400 can be bonded using a minimum bonding annealing time (such as between 30 and 60 minutes) until the last wafer 200 or wafer stack 300 or 400 is bonded, wherein the bonding annealing time is increased, thereby increasing the bonding strength of the already bonded structures while reducing the total processing time.

[0081] The total number of wafers 200 can be determined by a combination of a single wafer 200, a two-layer wafer stack 300, and a four-layer wafer stack 400. For example, the total number of wafers 200 can be between one wafer 200 and approximately twenty wafers 200. Before bonding each additional wafer 200, two-layer wafer stack 300, or four-layer wafer stack 400, the previous wafer 200, two-layer wafer stack 300, or four-layer wafer stack 400 can be processed to thin the uppermost wafer 200 and form a reverse bonding layer 265, as described above. Figures 21 to 24 As described.

[0082] In an embodiment, each wafer 200 may be a memory wafer, and a stack of wafers 200 may constitute a memory dataset. A memory dataset may include, for example, eight wafers 200. In some embodiments, one or more additional wafers 200 may be included above a designed number of wafers 200 to provide spare capacity in the event that one or more wafers 200 fail a test. For example, in an embodiment, nine wafers 200 may be bonded to wafer 100 or wafer 100', which may be a memory controller. When it is determined that one of the nine wafers 200 is defective, the memory controller may be programmed to bypass the defective wafer 200 without losing the functionality of the entire memory / controller combination.

[0083] In some embodiments, one or more of the different layers of wafer 200 may have different functions.

[0084] exist Figure 38a In this process, after thinning the uppermost wafer 200 (i.e., wafer 200n), the carrier substrate 190 is removed, the packages 500 are segmented, and connectors 515 are formed on the front side of wafers 100 / 100'. These processes can be performed in any suitable order. In some embodiments, the carrier substrate 190 is removed, the connectors 515 are formed, and then the packages 500 are segmented. In other embodiments, the packages 500 are segmented with the carrier substrate 190 on it, then the carrier substrate 190 is removed, and the connectors 515 are formed. These processes will be described in more detail below.

[0085] Figure 38a The optional thermal interface material (TIM) 540 and heat dissipation structure 550 are also shown, which will be described in more detail below. Figure 38a It also includes an optional redistribution structure 530, which can be formed using materials and processes similar to those described above with respect to interconnect structure 130, which will not be repeated here.

[0086] Package 500 can be divided using any suitable cutting technique 560. Cutting technique 560 may include dry etching, wet etching, anisotropic etching, or plasma etching using a suitable etchant. Cutting technique 560 may include laser cutting in multiple passes to laser-cut package 500 into pieces. Cutting technique 560 may include mechanical processes, such as saws configured to cut to a desired depth. Combinations of the cutting techniques 560 described above may also be used. Through non-packaged areas (outside the package 500 area, see, for example...) Figure 1 Cutting channel 111 and Figure 11 The dicing occurs at dicing channel 211. The dicing cuts through the processed wafer stack up to release layer 150. In some embodiments, the dicing may continue through release layer 150 and may continue into or through carrier substrate 190.

[0087] A connector 515 is formed on the front side of wafer 100. Connector 515 can be formed using any suitable process and includes various configurations. In some embodiments, connector 515 may be a controlled-collapse chip connection (C4) bump, microbump, solder ball, etc. For example, an opening (not shown) may be formed in a passivation layer deposited on the front side of wafer 100, exposing metal components such as contact pads 125 of wafer 100 or metal lines of optional redistribution structure 530. Connector 515 is formed in the opening. In some embodiments, an under-bump metal (UBM) layer may be formed in the opening prior to forming connector 515. In the illustrated embodiment, connector 515 has a lower portion 505 (closer to wafer 100) comprising conductive material and an upper portion 510 (remote from wafer 100) comprising solder material. The lower portion 505 and the upper portion 510 may also be referred to as conductive pillar 505 and solder cap 510, respectively.

[0088] The connector 515 can be coupled to the conductive components of wafer 100 through through-holes 120 / 220, bonding pad through-holes 245, and interconnect structures 130, 230 and / or 530, and also coupled to the individual wafers of wafers 200a to 200n.

[0089] An optional thermal interface material (TIM) 540 is formed over the package 500. TIM 540 is a material with good thermal conductivity, which can be greater than about 5 W / m*K and can be equal to or greater than about 50 W / m*K or 100 W / m*K. An optional heat dissipation structure 550 can be attached via TIM 540, which can also be adhesive. The heat dissipation structure 550 has high thermal conductivity and can be formed using metals, metal alloys, etc. For example, the heat dissipation structure 550 can include metals such as Al, Cu, Ni, Co, etc., or alloys thereof. The heat dissipation structure 550 can also be formed from a composite material selected from the group consisting of silicon carbide, aluminum nitride, graphite, etc. The heat dissipation structure 550 can be used to dissipate heat through each of the bonded wafers 100 / 100' and 200. The vias 120 of wafers 100 / 100' and 220 of wafer 200 can effectively dissipate heat from device region 110 (see...). Figure 2 ) and / or device region 210 (see Figure 12 The heat generated can be reduced. If vias 120 and 220 are aligned (as shown), heat dissipation efficiency can be improved. However, the embodiments also contemplate that vias 120 and 220 may not be aligned, or may be omitted as needed, depending on the design of device regions 110 and 210 and the wiring of metal lines and vias in interconnect structures 130 and 230.

[0090] Figure 38b Similar to Figure 38aIn addition to the 100 / 100' side of the wafer facing upwards, the back side of the wafer faces downwards (such as...). Figure 37b and Figure 37d (As shown). In such an embodiment, the carrier substrate 190 can be removed, and the substrate 115 of the wafer 100 can be thinned to expose the via 120. A redistribution structure 530 can then be formed to route the via 120 on the back side of the wafer 100 / 100' or the front side of the package 500 as needed. The redistribution structure 530 can use a method similar to that described above. Figure 2 The interconnect structure 130 is formed using the processes and materials described above. The package 500 can then be segmented to form the connector 515, forming the TIM 540, and so on, similar to the above description. Figure 38a The heat dissipation structure 550 is applied in the manner described.

[0091] Figure 38a and Figure 38b A combination diagram of wafers 100 / 100' is also provided, which shows the results from... Figure 37a , Figure 37b , Figure 37c and Figure 37d Wafer 100 and wafer 100'. Specifically, following... Figure 37c and Figure 37d After that, Figure 38a and Figure 38b The left half shows the gap-filling material 155, and then... Figure 37a and Figure 37b after, Figure 38a and Figure 38b No gap filler material 155 is used on the right half.

[0092] Examples include wafer-to-wafer hybrid bonding stacking processes to provide great flexibility in forming devices in multifunctional packages. To achieve high-quality wafer-to-wafer bonding, bonding layers can be formed on adjacent components to provide a fusion bond between the layers, which is less prone to failure than other bonding processes. Wafer metal components can be flexibly aligned by providing a larger target contact area (e.g., contact pad) than adjacent metal components, which may be, for example, portions of vias. Furthermore, metal components such as vias can be used to route signals and / or dissipate heat throughout the package structure.

[0093] One embodiment includes a method of thinning a first wafer to expose a via-metal. A bonding layer is formed over the via-metal, with the via extending through the bonding layer. A second wafer is pressed onto the first wafer, wherein bonding pads of the second wafer are aligned with the via-metal of the first wafer, and the bonding pads of the second wafer are bonded to the via-metal of the first wafer without using bonding material between the bonding pads and the via-metal. The bonding layer of the first wafer is fused to the bonding layer of the second wafer. In an embodiment, forming the bonding layer includes: recessing a first material around the via-metal; depositing a second material corresponding to the bonding layer; and planarizing the second material so that the upper surface of the second material is flush with the upper surface of the via-metal. In an embodiment, forming the bonding layer includes: depositing a bonding layer over the via-metal; forming an opening in the bonding layer corresponding to the via-metal; depositing a via extension in the opening, the via extension being physically coupled to the via-metal; and planarizing the via extension so that the upper surface of the bonding layer is flush with the upper surface of the via extension. In one embodiment, a first wafer and a second wafer together form a first wafer stack, and may further include: pressing the first wafer stack onto a third wafer, wherein bonding pads of the first wafer are aligned with metal components of the third wafer; bonding the bonding pads of the first wafer to the metal components of the third wafer without using bonding material between the bonding pads and the metal components; and fusing a bonding layer of the first wafer to a bonding layer of the third wafer. In one embodiment, the first wafer includes a controller for controlling devices in the first wafer stack. In one embodiment, the first wafer face down and the third wafer face up, with the face of the third wafer bonded to the face of the first wafer. In one embodiment, the method may include: dicing the stacked device package from the first wafer and the second wafer. In one embodiment, a first wafer and a second wafer together form a first wafer stack, and the method further includes: forming a second wafer stack that may include two wafer stacks; thinning the second wafer to expose a second metal via of the first wafer stack; forming a second bonding layer over the second metal via, the second metal via extending through the second bonding layer; pressing the second wafer stack onto the first wafer stack, wherein bonding pads of the second wafer stack are aligned with the second metal via; bonding the bonding pads of the second wafer stack to the second metal via of the first wafer stack, without using bonding material between the bonding pads of the second wafer stack and the second metal via; and fusing the second bonding layer to the bonding layer of the second wafer stack to form a first four-layer wafer stack. In another embodiment, the method includes: bonding the bonding pads of the first four-layer wafer stack to a metal part of a third wafer, without using bonding material between the bonding pads and the metal part; and fusing the bonding layer of the first four-layer wafer stack to the bonding layer of the third wafer. In one embodiment, each side of the wafer in the first four-layer wafer stack faces downwards. In another embodiment, the thickness of the bonding layer of the first wafer is between 0.8 μm and 3 μm.

[0094] Another embodiment is a package including a first device, a second device, and a third device. The first device includes a first set of vias, a first active device, and a first interconnect structure. The first set of vias extends from the front side of the first device through the first interconnect structure to the back side of the first device, and the first active device is adjacent to the first interconnect structure. The second device includes a second set of vias, a second active device, a second interconnect structure, a second front bonding layer, and a second reverse bonding layer. The second reverse bonding layer is located on the back side of the second device and includes a first dielectric material. The second front bonding layer is bonded to the first device, wherein the second set of vias extends from the second front bonding layer through the second reverse bonding layer. The third device includes a third set of vias, a third active device, a third interconnect structure, and a third front bonding layer. The third front bonding layer includes the same dielectric material as the first dielectric material, wherein the third set of vias extends from the third front bonding layer through the third device to the back side of the third device, and wherein the second reverse bonding layer is bonded to the third front bonding layer. In an embodiment, the third front bonding layer may include a set of bonding pad vias and a set of bonding pads, wherein each bonding pad has an interface with a corresponding via of the second set of vias. In one embodiment, the package may include: a thermal interface material disposed on the third device, the thermal interface material contacting the third set of vias; and a heat dissipation component disposed above the thermal interface material. In another embodiment, the first device is laterally surrounded by a gap-filling material, wherein the second front bonding layer overlaps with the gap-filling material. In yet another embodiment, the first device further includes a first set of bonding pads electrically coupled to the first set of vias, wherein the first set of bonding pads is directly bonded to a second bonding pad disposed on the second front bonding layer. In yet another embodiment, the thickness of each of the second front bonding layer and the second reverse bonding layer is between 0.8 μm and 3 μm.

[0095] Another embodiment is a packaging assembly, including: a first wafer bonded to a second wafer, wherein, at the bonding interface, a metal via of the first wafer is directly bonded to a bonding pad of the second wafer, and a first bonding layer of the first wafer is fused to a second bonding layer of the second wafer, the first bonding layer being disposed on the back side of the first wafer, and the metal via of the first wafer passing through the first bonding layer, through a semiconductor substrate, and through a first interconnect of the first wafer. In an embodiment, the packaging assembly may include: a third wafer, a fourth bonding layer of the third wafer bonded to a third bonding layer of the second wafer; and a fourth wafer, a sixth bonding layer of the fourth wafer bonded to a fifth bonding layer of the third wafer. In an embodiment, each face of the first, second, third, and fourth wafers faces downward. In an embodiment, the bonding pads of the second wafer are coupled to a second interconnect of the second wafer through bonding pad vias passing through the second bonding layer. In an embodiment, a first dielectric material of the first bonding layer is the same as a second dielectric material of the second bonding layer, and the thickness of each of the first and second bonding layers is between 0.8 μm and 3 μm.

[0096] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the invention.

Claims

1. A method for manufacturing a package, comprising: Thin the first wafer to expose the metal vias; A bonding layer is formed above the metal via, the metal via extending through the bonding layer; The second wafer is positioned on top of the first wafer, wherein the bonding pads of the second wafer are aligned with the metal vias of the first wafer; The bonding pads of the second wafer are bonded to the metal vias of the first wafer, without using bonding material between the bonding pads and the metal vias; and The bonding layer of the first wafer is fused to the bonding layer of the second wafer to form a first wafer stack. The first wafer stack is positioned on the third wafer, wherein the bonding pads of the first wafer are aligned with the metal components of the third wafer; The bonding pads of the first wafer are bonded to the metal components of the third wafer without using bonding material between the bonding pads and the metal components; and The bonding layer of the first wafer is fused to the bonding layer of the third wafer.

2. The method of claim 1, wherein, Forming the bonding layer includes: The first material surrounding the metal through-hole is recessed; Deposition of a second material corresponding to the bonding layer; and The second material is planarized so that the upper surface of the second material is flush with the upper surface of the metal through hole.

3. The method according to claim 1, wherein, Forming the bonding layer includes: The bonding layer is deposited over the metal via; An opening is formed in the bonding layer, the opening corresponding to the metal through-hole; A metal via extension is deposited in the opening, the metal via extension being physically coupled to the metal via; and The metal via extension is planarized so that the upper surface of the bonding layer is flush with the upper surface of the metal via extension.

4. The method according to claim 1, wherein, The metal through-hole is formed of copper or a copper alloy.

5. The method according to claim 1, wherein, The first wafer includes a controller for controlling devices in the first wafer stack.

6. The method according to claim 1, wherein, The first wafer face is facing down and the third wafer face is facing up, with the face of the third wafer bonded to the face of the first wafer.

7. The method according to claim 1, wherein, The thickness of the bonding layer on the first wafer is between 0.8 μm and 3 μm.

8. The method according to claim 1, wherein, The first wafer and the second wafer together form a first wafer stack, which also includes: Forming a second wafer stack comprising two layers of wafer stacks; Thin the second wafer to expose a second metal via in the first wafer stack; A second bonding layer is formed above the second metal via, the second metal via extending through the second bonding layer; The second wafer stack is positioned on top of the first wafer stack, wherein the bonding pads of the second wafer stack are aligned with the second metal via. The bonding pads of the second wafer stack are bonded to the second metal vias of the first wafer stack, without using bonding material between the bonding pads of the second wafer stack and the second metal vias; and The second bonding layer is fused to the bonding layer of the second wafer stack to form a first four-layer wafer stack.

9. The method according to claim 8, further comprising: The first four-layer wafer stack is positioned on the third wafer, wherein the bonding pads of the first four-layer wafer stack are aligned with the metal components of the third wafer. The bonding pads of the first four-layer wafer stack are bonded to the metal components of the third wafer, without using bonding material between the bonding pads and the metal components; and The bonding layer of the first four-layer wafer stack is fused to the bonding layer of the third wafer.

10. The method according to claim 8, wherein, Each face of the wafer in the first four-layer wafer stack is facing down.

11. A package comprising: The first device includes a first set of vias, a first active device, and a first interconnect structure. The first set of vias extends from the front of the first device through the first interconnect structure to the back of the first device. The first active device is adjacent to the first interconnect structure. A second device, comprising a second set of vias, a second active device, a second interconnect structure, a second front bonding layer, and a second reverse bonding layer, wherein the second reverse bonding layer is located on the back side of the second device and comprises a first dielectric material; the second front bonding layer is bonded to the first device, wherein the second set of vias passes through the second reverse bonding layer from the second front bonding layer; and The third device includes a third set of vias, a third active device, a third interconnect structure, and a third front bonding layer. The third front bonding layer includes the same dielectric material as the first dielectric material. The third set of vias extends from the third front bonding layer through the third device to the back side of the third device. The second reverse bonding layer is bonded to the third front bonding layer.

12. The package according to claim 11, wherein, The thickness of each of the second front bonding layer and the second reverse bonding layer is between 0.8 μm and 3 μm.

13. The package according to claim 11, further comprising: A thermal interface material is disposed on the third device, and the thermal interface material is in contact with the third set of through holes; And a heat dissipation component, disposed above the thermal interface material.

14. The package according to claim 11, wherein, The first device is laterally surrounded by a gap-filling material, wherein the second front bonding layer overlaps with the gap-filling material.

15. The package according to claim 11, wherein, The first device further includes a first set of bonding pads electrically coupled to the first set of vias, wherein the first set of bonding pads is directly bonded to a second bonding pad disposed on the second front bonding layer.

16. An encapsulation component, comprising: A first wafer is bonded to a second wafer, wherein the first wafer includes a semiconductor substrate; a first insulating bonding layer located on a first surface of the semiconductor substrate; a first interconnect located on a second surface of the semiconductor substrate; and a metal via extending through the semiconductor substrate, the first insulating bonding layer, and the first interconnect; wherein the second wafer includes a second insulating bonding layer and bonding pads located in the second insulating bonding layer; wherein at the bonding interface between the first wafer and the second wafer, the metal via of the first wafer is directly bonded to the bonding pad of the second wafer, and the first insulating bonding layer of the first wafer is fused to the second insulating bonding layer of the second wafer, the first insulating bonding layer being disposed on the back side of the first wafer.

17. The packaging component of claim 16, further comprising: The third wafer, wherein the fourth insulating bonding layer of the third wafer is bonded to the third insulating bonding layer of the second wafer; as well as The fourth wafer, wherein the sixth insulating bonding layer of the fourth wafer is bonded to the fifth insulating bonding layer of the third wafer.

18. The encapsulation component of claim 17, wherein, Each face of the first, second, third, and fourth wafers is facing down.

19. The packaging component of claim 16, wherein, The bonding pads of the second wafer are coupled to the second interconnect of the second wafer through the bonding pad vias through the second insulating bonding layer.

20. The packaging component of claim 16, wherein, The first dielectric material of the first insulating bonding layer is the same as the second dielectric material of the second insulating bonding layer; and wherein the thickness of each of the first insulating bonding layer and the second insulating bonding layer is between 0.8 μm and 3 μm.

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