Package structure and method of forming the same

Abstract

The application provides a packaging structure and a forming method thereof. The packaging structure comprises a substrate, an electric integrated circuit above the substrate, and an interposer between the substrate and the electric integrated circuit. The electric integrated circuit is electrically connected with the substrate through the interposer with a through hole. The above technical scheme of the application can shorten the electric connection path between the EIC and the substrate, and improve the RC delay problem of the signal.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to a packaging structure and a method for forming the same. Background Technology

[0002] like Figure 1 As shown, the package structure includes a PIC (Optical Integrated Circuit) 12, which is, for example, a silicon photonics (Si-Ph) chip. In existing 100Gb / s silicon photonics chip structures, the EIC 14 and PIC 12 are electrically connected via FCB (Flip Chip Bonding), and then electrically connected to the substrate 16 via wire bonding (WB) using leads 13. However, this electrical connection method may result in a longer transmission path and higher impedance due to the wire bonding method (the lead diameter is in the range of 18μm to 25μm, and the length is approximately 2000μm), leading to RC delay issues in the signal and failing to meet the future 400Gb / s transmission rate requirements. Summary of the Invention

[0003] In view of the above-mentioned problems in related technologies, the present invention proposes a packaging structure and its forming method, which can shorten the electrical connection path between EIC and substrate.

[0004] Embodiments of the present invention provide a packaging structure, including: a substrate; an electrical integrated circuit located above the substrate; and an interposer located between the substrate and the electrical integrated circuit. The electrical integrated circuit is electrically connected to the substrate through the interposer having through-holes.

[0005] In some embodiments, the lower surface of the electrical integrated circuit has pads, and the upper end of the through-hole adjacent to the electrical integrated circuit has conductive pillars, with the pads of the electrical integrated circuit in contact with the conductive pillars.

[0006] In some embodiments, the lower end of the through hole has a solder bump, and the upper surface of the substrate has a pad, wherein the solder bump of the through hole is directly engaged with the pad of the substrate.

[0007] In some embodiments, the package structure further includes an optical integrated circuit located above the substrate and below the electrical integrated circuit, and electrically connected to the electrical integrated circuit. In some embodiments, the lower surface of the electrical integrated circuit has pads, and the upper surface of the optical integrated circuit has pads, wherein the pads of the electrical integrated circuit and the pads of the optical integrated circuit are directly bonded. In some embodiments, the pads of the electrical integrated circuit and the pads of the optical integrated circuit are surrounded by a dielectric layer.

[0008] In some embodiments, the packaging structure further includes an insulating material located between the optical integrated circuit and the substrate.

[0009] In some embodiments, the packaging structure further includes: a fiber array unit, which is laterally spaced from the electrical integrated circuit and located on the optical integrated circuit.

[0010] In some embodiments, the fiber array unit has a sidewall facing the electrical integrated circuit, at least a portion of which is tilted away from the electrical integrated circuit.

[0011] In some embodiments, the package structure further includes: another integrated circuit located above the substrate and below the electrical integrated circuit and electrically connected to the electrical integrated circuit, and the other integrated circuit and the optical integrated circuit are located on opposite sides of the interposer.

[0012] In some embodiments, the pads on the lower surface of the electrical integrated circuit are directly bonded to the pads on the upper surface of another integrated circuit. In some embodiments, a multilayer redistribution line layer is provided between the electrical integrated circuit and the other integrated circuit, and the other integrated circuit is electrically connected to the electrical integrated circuit through the multilayer redistribution line layer. In some embodiments, the other integrated circuit is a power management integrated circuit.

[0013] Embodiments of the present invention also provide a method for forming a package structure, comprising: placing an electrical integrated circuit on a carrier; bonding an interposer layer on the electrical integrated circuit; inverting the carrier and bonding the electrical integrated circuit to a substrate through the interposer layer; and removing the carrier.

[0014] In some embodiments, after bonding the interposer, other integrated circuits, including optical integrated circuits, are bonded to the electrical integrated circuit, and the optical integrated circuit is also bonded to the substrate when the electrical integrated circuit is electrically connected to the substrate.

[0015] In some embodiments, after the carrier is removed, the optical integrated circuit has a portion of its upper surface that is not covered by the electrical integrated circuit, and fiber array units are formed on the portion of the upper surface.

[0016] In some embodiments, the other integrated circuits also include a power management integrated circuit, and the power management integrated circuit is placed on the side of the interposer opposite to the optical integrated circuit.

[0017] In some embodiments, after removing the carrier, the method further includes covering the surface of the electrical integrated circuit away from the substrate with a heat dissipation structure, wherein the heat dissipation structure also extends vertically to the surface of the substrate.

[0018] Embodiments of the present invention also provide a method for forming a package structure, comprising: bonding a pad above a substrate to a lower portion of a through-hole in an interposer; and bonding an upper portion of the interposer to a pad of an electrical integrated circuit.

[0019] In some embodiments, prior to bonding with the electrical integrated circuit, the method further includes: forming an optical integrated circuit and a power management integrated circuit on a substrate, and bonding the optical integrated circuit and the power management integrated circuit with the electrical integrated circuit when bonding the electrical integrated circuit. Attached Figure Description

[0020] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to standard industrial practice, the components are not drawn to scale. In fact, the dimensions of the components may be arbitrarily increased or decreased for clarity of discussion.

[0021] Figure 1 This is a cross-sectional schematic diagram of an existing PIC packaging structure.

[0022] Figure 2 This is a cross-sectional schematic diagram of the packaging structure according to an embodiment of the present invention.

[0023] Figures 3A to 3G A cross-sectional schematic diagram of each stage of forming the encapsulation structure according to an embodiment of the present invention is shown.

[0024] Figures 4A to 4F A cross-sectional schematic diagram of the various stages of forming the encapsulation structure according to another embodiment of the present invention is shown.

[0025] Figures 5 to 6 This is a cross-sectional schematic diagram of the packaging structure according to other embodiments of the present invention. Specific Implementation

[0026] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of elements and arrangements will be described below to simplify the invention. These are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated throughout the various instances. This repetition is for brevity and clarity only and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0027] Figure 2 This is a cross-sectional schematic diagram of the packaging structure according to an embodiment of the present invention. Figure 2As shown, the package structure includes a substrate 210, with an EIC 220 located above the substrate 210. An interposer 250 is disposed between the substrate 210 and the EIC 220. The interposer 250 includes a dielectric layer 251 and a through-hole 252 located in the dielectric layer 251, the through-hole 252 passing through the dielectric layer. In some embodiments, the material of the dielectric layer 251 may include an organic photosensitive liquid, an organic non-photosensitive liquid, or / and a dry film material. In other embodiments, the material of the dielectric layer 251 may be an inorganic oxide (e.g., SiO2). x SiN x TaO x Materials may include glass, silicon, and ceramics. In other embodiments, the dielectric layer 251 may be an organic material, such as PI (Polyimide), epoxy resin, ABF (Ajinomoto buildup film), or a molded material.

[0028] The EIC 220 is electrically connected to the substrate 210 via an interposer 250. The packaging structure provided by this invention, which uses an interposer 250 with through-holes 252 for electrical connection, avoids the use of existing wire-based methods, shortening the electrical connection path between the EIC 220 and the substrate 210, improving the RC delay problem of the signal, and thus meeting the transmission rate requirements of future integrated circuits.

[0029] The lower surface of EIC 220 has pads 222 located in dielectric layer 221. A dielectric layer 253 is located above the upper end of via 252 adjacent to the upper end of EIC 220. Conductive posts 254 connected to via 252 are located in dielectric layer 253, and the pads 222 of EIC 220 are in contact with and electrically connected to the conductive posts 254. In some embodiments, the dielectric layer 253 may be made of an oxide material. EIC 220 is electrically connected to the interposer 250 using this hybrid bonding method. In some embodiments, the material of dielectric layer 253 may include organic photosensitive liquid, organic non-photosensitive liquid, and / or dry film material.

[0030] A solder bump 259 is provided at the lower end of the through-hole 252. A pad 212 is provided on the upper surface of the substrate 210. The solder bump 259 of the through-hole 252 is bonded to the pad 212 of the substrate 210. An insulating material 262 is formed on the upper surface of the substrate 210, and the insulating material 262 is located between the PIC 230 and the substrate 210. The solder bump 259 and the pad 212 may be surrounded by the insulating material 262. The insulating material 262 may be, for example, non-conductive paste (NCP).

[0031] Continue to refer to Figure 2As shown, a PIC 230 is also disposed above the substrate 210. The PIC 230 is partially located below the EIC 220 and electrically connected to the EIC 220. The EIC 220 can be electrically connected to the PIC 230 via a hybrid bonding method. In this embodiment, a dielectric layer 231 is also disposed between the EIC 220 and the PIC 230, and the upper surface of the PIC 230 has pads 232 located in the dielectric layer 231. The pads 222 of the EIC 220 and the pads 232 of the PIC 230 are bonded to each other.

[0032] Furthermore, another integrated circuit 240 may be disposed above the substrate 210, with the other integrated circuit 240 and the PIC 230 located laterally on opposite sides of the interposer 250. The other integrated circuit 240 is at least partially located below the EIC 220 and electrically connected to the EIC 220. In some embodiments, the other integrated circuit 240 may be a power management integrated circuit (PMIC). Similarly, the EIC 220 may be electrically connected to the other integrated circuit 240 via a hybrid bonding method. In this embodiment, a dielectric layer 241 is disposed between the EIC 220 and the other integrated circuit 240, and the upper surface of the other integrated circuit 240 has pads 242 located in the dielectric layer 241. The pads 222 of the EIC 220 are bonded to the pads 242 of the other integrated circuit 240. In some embodiments, the material of the dielectric layer 241 may be an inorganic oxide (e.g., SiO2). x SiN x TaO x Materials may include glass, silicon, and ceramics. In other embodiments, the dielectric layer 241 may be an organic material, such as PI (Polyimide), epoxy resin, ABF (Ajinomoto buildup film), or a molded material.

[0033] In other embodiments, a multi-layered redistribution line (RDL) layer may be provided between EIC 220 and another integrated circuit 240, through which EIC 220 and another integrated circuit 240 are electrically connected.

[0034] Above the PIC 230 is a FAU (fiber optic array unit) 270, which is laterally spaced from the EIC 220. The FAU 270 has a sidewall facing the EIC 220, at least a portion of which is inclined away from the EIC 220.

[0035] Figures 3A to 3G A cross-sectional schematic diagram of each stage of forming the encapsulation structure according to an embodiment of the present invention is shown. Figure 3AAs shown, an EIC 220 is placed on top of a carrier 301. The upper surface of the EIC 220 has a dielectric layer 221 and pads 222 located in the dielectric layer 221 for subsequent hybrid bonding with other devices, such as a PIC 230, an interposer 250 and another integrated circuit 240.

[0036] like Figure 3B As shown, the interposer layer 250 is bonded above the upper surface of the EIC 220. Figure 3C In this process, PIC 230 and another integrated circuit 240 are bonded above the upper surface of EIC 220. Interchange layer 250 includes dielectric layer 251 and through-hole 252 located in dielectric layer 251, through-hole 252 passing through dielectric layer 251. Dielectric layer 253 is disposed at one end of through-hole 252 adjacent to EIC 220, and conductive pillar 254 is provided in dielectric layer 253 to connect to through-hole 252. Pad 222 of EIC 220 contacts and is electrically connected to conductive pillar 254. Another integrated circuit 240 and PIC 230 are located on opposite sides of interchange layer 250 in the lateral direction. Dielectric layer 231 is disposed between EIC 220 and PIC 230, and dielectric layer 241 is disposed between another integrated circuit 240 and EIC 220. The surface of PIC 230 has pads 232 located in dielectric layer 231, and the surface of another integrated circuit 240 has pads 242 located in dielectric layer 241. An annealing process can be performed to make the pads 222 of EIC 220 bond to the pads 242 of the other integrated circuit 240 and the pads 232 of PIC 230.

[0037] Then, as Figure 3D The structure after bonding another integrated circuit 240 and PIC 230 is flipped, and the flipped structure is bonded to the surface of substrate 210, such as to pads 212 on the upper surface of substrate 210. After bonding to substrate 210, an insulating material 262 is formed, which surrounds the interposer 250, PIC 230, and portions of the other integrated circuit 240 adjacent to substrate 210. The insulating material 262 can be, for example, non-conductive paste (NCP). The carrier 301 is removed. Figure 3E In this case, FAU 270 is bonded to the surface of PIC 230 that is not bonded to EIC 220.

[0038] like Figure 3F An underfill 280 is formed above the insulating material 262. The underfill 280 surrounds the portion of the interposer 250, PIC 230, and another integrated circuit 240 that is not surrounded by the insulating material 262.

[0039] like Figure 3G ,Will Figure 3FThe structure is flipped, and solder 289 is formed on pads 212 on the exposed surface of substrate 210. The resulting structure is flipped again, and an adhesive layer 287 is formed above EIC 220, and a heat sink 288 is bonded above the adhesive layer 287. The heat sink 288 covers the upper surface of EIC 220 and extends vertically to the upper surface of substrate 210. Finally, a dicing process can be performed to form the final package structure (e.g., Figure 2 ).

[0040] exist Figures 3A to 3G In the method shown, an EIC 220 is first formed, followed by a PIC 230, an interposer 250, and another integrated circuit 240. This creates a gap between the PIC 230 and the other integrated circuit 240 and the substrate 210, and an insulating material 262 fills the gap between the PIC 230 and the other integrated circuit 240 and the substrate 210.

[0041] Figures 4A to 4F A cross-sectional schematic diagram of the various stages of forming the encapsulation structure according to another embodiment of the present invention is shown. Figure 4A As shown, a substrate 210 is provided. The substrate 210 has pads 212 on both the upper and lower surfaces.

[0042] like Figure 4B On the first surface of substrate 210, PIC 230 and another integrated circuit 240 are bonded to pads 212 on the first surface of substrate 210 by adhesive layer 225, and interposer 250 is electrically bonded between PIC 230 and another integrated circuit 240.

[0043] exist Figure 4C In this process, an EIC 220 is placed above the interposer 250, the PIC 230, and another integrated circuit 240. Then, an annealing process can be performed so that the pads of the EIC 220 are aligned with the other integrated circuit 240, the PIC 230, and the interposer 250.

[0044] exist Figure 4D In this process, FAU 270 is bonded to the surface of PIC 230 that is not bonded to EIC 220. Figure 4E In this process, a bottom filler 280 is formed that surrounds another integrated circuit 240, PIC 230, and the interposer layer 250. Furthermore, the bottom filler 280 also surrounds the lower portions of EIC 220 and FAU 270. Figure 4E The resulting structure is flipped over, and solder 289 is formed on the pads 212 on the surface of the substrate 210.

[0045] exist Figure 4F In the middle, Figure 4EThe structure is flipped, and an adhesive layer 287 is formed above the EIC 220, and a heat sink 288 is bonded above the adhesive layer 287. The heat sink 288 covers the upper surface of the EIC 220 and extends vertically to the upper surface of the substrate 210. Subsequently, a dicing process can be performed to form the final package structure (e.g., Figure 2 ).

[0046] exist Figures 4A to 4F In the method shown, a PIC 230, an interposer 250, and another integrated circuit 240 are first formed, and then an EIC 220 is formed. There is no gap between the PIC 230 and the other integrated circuit 240 and the substrate 210.

[0047] Figure 5 This is a cross-sectional schematic diagram of a packaging structure according to another embodiment of the present invention. Figure 2 Compared to the simultaneous formation of bottom filler 280 and insulating material 262, in Figure 5 In one embodiment, a molded article 295 may be formed, and the molded article 295 covers the upper surface of the PIC 230 and the upper surface of the FAU 270. In this embodiment, an adhesive layer 287 and a heat sink 288 are formed on the top surface of the molded article 295.

[0048] Figure 6 This is a cross-sectional schematic diagram of a packaging structure according to another embodiment of the present invention. Figure 2 Compared to the heat sink 288 structure shown in the figure, in Figure 6 In one embodiment, the heat sink 288 has a structure that is a membrane structure covering the upper surface of the PIC 230.

[0049] It should be understood that Figures 5 to 6 Other aspects of the embodiments shown are related to... Figure 2 The description is similar and therefore will not be repeated.

[0050] The foregoing summary outlines features of several embodiments that enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that other processes and structures can be readily designed or modified based on this invention to achieve the same objectives and / or benefits as the embodiments described herein. Those skilled in the art should also recognize that these equivalent structures do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the invention.

Claims

1. A packaging structure, characterized in that, include: substrate; An electrical integrated circuit is located above the substrate; An interposer layer is located between the substrate and the electrical integrated circuit, wherein the electrical integrated circuit is electrically connected to the substrate through the interposer layer having through holes; An optical integrated circuit is located above the substrate and below the electrical integrated circuit, and is electrically connected to the electrical integrated circuit; Fiber optic array units are laterally spaced from the electrical integrated circuit and located on the optical integrated circuit; and Another integrated circuit is located above the substrate and below the electrical integrated circuit, and is electrically connected to the electrical integrated circuit. This other integrated circuit and the optical integrated circuit are located on opposite sides of the interposer layer, wherein the electrical integrated circuit extends across the interposer layer to the other integrated circuit. The fiber array unit has a sidewall facing the electrical integrated circuit, at least a portion of which is inclined away from the electrical integrated circuit. The lower surface of the electrical integrated circuit has pads, the upper surface of the optical integrated circuit has pads, the pads of the electrical integrated circuit and the pads of the optical integrated circuit are surrounded by a dielectric layer, and the pads on the lower surface of the electrical integrated circuit are directly bonded to the pads on the upper surface of the other integrated circuit.

2. The packaging structure according to claim 1, characterized in that, The lower surface of the electrical integrated circuit has pads, and a conductive post is located adjacent to the upper end of the electrical integrated circuit of the through hole, with the pads of the electrical integrated circuit in contact with the conductive post.

3. The packaging structure according to claim 1, characterized in that, The pads of the electrical integrated circuit are directly bonded to the pads of the optical integrated circuit.

4. The packaging structure according to claim 1, characterized in that, A multi-layer redistribution line is provided between the electrical integrated circuit and the other integrated circuit, and the other integrated circuit is electrically connected to the electrical integrated circuit through the multi-layer redistribution line.

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