Semiconductor device and method of manufacturing the same

Abstract

The present application relates to a semiconductor device and a manufacturing method thereof. The semiconductor device includes a first chip and a second chip which are attached via a plurality of attachment electrodes. The first chip includes a first substrate, a first semiconductor element, and a first attachment electrode which is one of the plurality of attachment electrodes and is electrically connected to the first semiconductor element. The second chip includes a second substrate, a second semiconductor element, and a second attachment electrode which is one of the plurality of attachment electrodes and is electrically connected to the second semiconductor element. The second substrate includes a pair of first regions which are provided at both end portions in a first direction and extend in a second direction which intersects the first direction, and a pair of second regions which are provided at both end portions in the second direction and extend in the first direction. When viewed from a third direction which intersects a surface of the second substrate, portions of the first regions and the second regions of the second substrate do not overlap the first substrate.

Description

[0001] Citation of relevant applications

[0002] This application is based on and seeks the priority interest of the prior Japanese Patent Application No. 2021-030397, filed on February 26, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This embodiment relates to a semiconductor device and a method for manufacturing the same. Background Technology

[0004] It is known that a technique exists in which multiple bonding electrodes are formed on two wafers, the two wafers are bonded together via the multiple bonding electrodes, and the two wafers are monolithically diced using a dicing tool or the like, thereby forming multiple bare dies. Summary of the Invention

[0005] One embodiment provides a semiconductor device that can be manufactured well and a method for manufacturing the same.

[0006] One embodiment of a semiconductor device includes a first chip and a second chip bonded together via a plurality of bonding electrodes. The first chip includes: a first substrate; a first semiconductor element; and a first bonding electrode, which is one of the plurality of bonding electrodes and electrically connected to the first semiconductor element. The second chip includes: a second substrate; a second semiconductor element; and a second bonding electrode, which is one of the plurality of bonding electrodes and electrically connected to the second semiconductor element. The second substrate includes: a pair of first regions disposed at both ends in a first direction and extending along a second direction intersecting the first direction; and a pair of second regions disposed at both ends in the second direction and extending along the first direction. Viewed from a third direction intersecting the surface of the second substrate, portions of the first and second regions disposed on the second substrate do not overlap with the first substrate.

[0007] A semiconductor device according to one embodiment includes a first chip and a second chip bonded together via a plurality of bonding electrodes. The first chip includes: a first substrate; a first semiconductor element; and a first bonding electrode, which is one of the plurality of bonding electrodes and electrically connected to the first semiconductor element. The second chip includes: a second substrate; a second semiconductor element; and a second bonding electrode, which is one of the plurality of bonding electrodes and electrically connected to the second semiconductor element. If the roughness of at least one end of at least one of a first direction and a second direction intersecting the first direction of the first substrate is defined as a first roughness, and the roughness of at least one end of at least one of the first direction and the second direction of the second substrate is defined as a second roughness, then the first roughness is less than the second roughness.

[0008] In a semiconductor device bonding method according to one embodiment, a first wafer having a first substrate and a second wafer having a second substrate are bonded together. Furthermore, portions of the first substrate disposed along dicing lines are removed, and the first substrate is divided into multiple portions corresponding to multiple dies. Additionally, the first and second wafers are cut along the dicing lines to form multiple dies.

[0009] Based on the aforementioned configuration, a semiconductor device that can be manufactured well and a method for manufacturing the same can be provided. Attached Figure Description

[0010] Figure 1 This is a schematic block diagram illustrating the configuration of the semiconductor memory device according to the first embodiment.

[0011] Figure 2 This is a schematic side view showing the configuration of the semiconductor memory device.

[0012] Figure 3 This is a schematic top view showing the configuration of the semiconductor memory device.

[0013] Figure 4 This is a schematic exploded perspective view showing the configuration of the semiconductor memory device.

[0014] Figure 5 This is a schematic bottom view showing the configuration of the semiconductor memory device.

[0015] Figure 6 This is a schematic bottom view showing the configuration of the semiconductor memory device.

[0016] Figure 7 This is a schematic cross-sectional view showing the configuration of the semiconductor memory device.

[0017] Figure 8 This is a schematic cross-sectional view showing the configuration of the semiconductor memory device.

[0018] Figure 9 This is a schematic bottom view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0019] Figure 10 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0020] Figure 11 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0021] Figure 12 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0022] Figure 13This is a schematic top view used to illustrate the manufacturing method.

[0023] Figure 14 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0024] Figure 15 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0025] Figure 16 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0026] Figure 17 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0027] Figure 18 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0028] Figure 19 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0029] Figure 20 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0030] Figure 21 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0031] Figure 22 This is a schematic cross-sectional view used to illustrate the manufacturing method of a comparative example semiconductor memory device.

[0032] Figure 23 This is a schematic cross-sectional view used to illustrate the manufacturing method of a comparative example semiconductor memory device.

[0033] Figure 24 This is a schematic cross-sectional view showing the configuration of the semiconductor memory device according to the second embodiment.

[0034] Figure 25 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the second embodiment.

[0035] Figure 26 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0036] Figure 27 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0037] Figure 28 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0038] Figure 29 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0039] Figure 30 This is a schematic cross-sectional view showing the configuration of the semiconductor memory device according to the third embodiment.

[0040] Figure 31 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0041] Figure 32 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0042] Figure 33 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0043] Figure 34 This is a schematic cross-sectional view used to illustrate other manufacturing methods of the semiconductor memory device of the third embodiment.

[0044] Figure 35 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0045] Figure 36 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0046] Figure 37 This is a schematic cross-sectional view used to illustrate a variation of the semiconductor memory device of the third embodiment.

[0047] Figure 38 This is a schematic cross-sectional view showing a variation of the configuration of the semiconductor memory device according to the first embodiment. Detailed Implementation

[0048] Next, the semiconductor device according to the embodiments will be described in detail with reference to the accompanying drawings. Furthermore, the following embodiments are merely examples and are not intended to limit the invention. Additionally, the following drawings are schematic, and for ease of explanation, some components may be omitted. Furthermore, common parts in multiple embodiments may be labeled with the same symbol, and descriptions may be omitted.

[0049] Furthermore, in this specification, when it is expressed as "electrically connected" to the second component, it can mean that the first component is directly connected to the second component, or that the first component is connected to the second component via wiring, semiconductor components, or transistors. For example, in the case of three transistors connected in series, even if the second transistor is in an OFF state, the first transistor is "electrically connected" to the third transistor.

[0050] Furthermore, in this specification, when the first component is expressed as "electrically connected" to the second and third components, it may mean that the first, second, and third components are connected in series, and the second component is connected to the third component via the first component.

[0051] Furthermore, in this specification, when it is expressed as a circuit or the like "conducting" two wirings, it may mean, for example, that the circuit or the like includes a transistor or the like, which is disposed in the current path between the two wirings, and that the transistor or the like is in an ON state.

[0052] In addition, in this specification, a specific direction parallel to the upper surface of the substrate is called the X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is called the Y direction, and a direction perpendicular to the upper surface of the substrate is called the Z direction.

[0053] In addition, in this specification, the direction along a specific surface is sometimes referred to as the first direction, the direction along the specific surface that intersects the first direction is referred to as the second direction, and the direction that intersects the specific surface is referred to as the third direction. The first, second, and third directions may correspond to any one of the X, Y, and Z directions, or they may not correspond to each other.

[0054] Furthermore, when using terms such as "upper" or "lower" in this specification, for example, one of the two semiconductor substrates included in the die may be designated as the upper semiconductor substrate, and the other without pad electrodes may be designated as the lower semiconductor substrate. Moreover, when referring to the configuration included in the die, for example, the orientation along the Z direction towards the upper semiconductor substrate may be referred to as "upper," and the orientation along the Z direction towards the lower semiconductor substrate may be referred to as "lower." Additionally, when referring to a configuration as a lower surface or lower end, it may refer to the surface or end point on the lower semiconductor substrate side of the configuration; when referring to an upper surface or upper end, it may refer to the surface or end point on the upper semiconductor substrate side of the configuration. Furthermore, a surface intersecting the X or Y direction may also be referred to as a side surface, etc.

[0055] In addition, in this specification, when referring to "width," "length," or "thickness" in a specific direction for components, parts, etc., it sometimes refers to the width, length, or thickness of a cross-section observed using SEM (Scanning electron microscopy) or TEM (Transmission electron microscopy).

[0056] [First Embodiment] [Memory System 10] Figure 1 This is a schematic block diagram showing the configuration of the memory system 10 in the first embodiment.

[0057] The memory system 10 reads, writes, deletes, etc. user data according to signals sent from the host 20. The memory system 10 is, for example, a memory chip, a memory card, an SSD (Solid State Disk), or other systems capable of storing user data. The memory system 10 includes: a plurality of memory dies MD that store user data; and a controller die CD that is connected to the plurality of memory dies MD and the host 20. The controller die CD, for example, includes a processor, a RAM (Random Access Memory), etc., and performs processes such as conversion between logical addresses and physical addresses, bit error detection / correction, garbage collection (compression), wear leveling, etc.

[0058] Figure 2 FIG. is a schematic side view showing a configuration example of the memory system 10 of the present embodiment. Figure 3 FIG. is a schematic top view showing the configuration example. For ease of explanation, in Figure 2 and Figure 3 a part of the configuration is omitted.

[0059] As Figure 2 shown, the memory system 10 of the present embodiment includes a mounting substrate MSB, a plurality of memory dies MD stacked on the mounting substrate MSB, and a controller die CD stacked on the memory dies MD. Pad electrodes P are provided in a region at an end in the Y direction on the upper surface of the mounting substrate MSB X , and a part of other regions is adhered to the lower surface of the memory die MD via an adhesive or the like. Pad electrodes P are provided in a region at an end in the Y direction on the upper surface of the memory die MD X , and other regions are adhered to the lower surface of other memory dies MD or the controller die CD via an adhesive or the like. Pad electrodes P are provided in a region at an end in the Y direction on the upper surface of the controller die CD X .

[0060] As Figure 3 shown, the mounting substrate MSB, the plurality of memory dies MD, and the controller die CD each include a plurality of pad electrodes P arranged in the X direction X . The plurality of pad electrodes P provided on the mounting substrate MSB, the plurality of memory dies MD, and the controller die CD X are respectively connected to each other via bonding wires B.

[0061] In addition, Figure 2 and Figure 3 shown configurations are only examples, and the specific configuration can be appropriately adjusted. For example, in Figure 2 and Figure 3In the example shown, a controller die CD is stacked on multiple memory dies MD, and the configuration is connected using solder lines B. In this configuration, the multiple memory dies MD and the controller die CD are contained within a single package. However, the controller die CD may also be contained in a different package than the memory dies MD. Alternatively, the multiple memory dies MD and the controller die CD may be interconnected via through electrodes or the like instead of solder lines B.

[0062] [Construction of Memory Die (MD)] Figure 4 This is a schematic exploded perspective view showing an example of the configuration of the semiconductor memory device according to this embodiment. Figure 4 As shown, the memory die MD has a chip C containing a memory cell array MCA. M , and chip C containing peripheral circuits P .

[0063] In chip C M The upper surface is provided with multiple solder pad electrodes P X Additionally, in chip C... M On the lower surface, multiple bonding electrodes P are provided. I1 Additionally, in chip C... P On the upper surface, multiple bonding electrodes P are set. I2 The following section concerns chip C. M Multiple bonding electrodes P will be set up I1 The surface is called the surface, and multiple pad electrodes P will be set there. X The side facing out is called the back side. Additionally, regarding chip C... P Multiple bonding electrodes P will be set up I2 The side facing out is called the front side, and the side opposite the front side is called the back side. In the example shown, chip C P The surface of the chip C is set P On the back, further up, chip C M The back is set on the chip C M Above the surface.

[0064] Chip C M and chip C P With chip C M Surface and chip C P The surfaces are arranged in an opposing manner. Multiple bonding electrodes P I1 Each with multiple bonding electrodes P I2 Corresponding settings, configured to be able to attach to multiple electrodes P I2 The bonding location. Bonding electrode P I1 With the attached electrode P I2 As for chip C M With chip C P The bonding electrodes, which are both in contact with the substrate and electrically conductive, perform their function.

[0065] In addition, Figure 4 In the example, chip C M The corners a1, a2, a3, and a4 correspond to chip C respectively. P The corners b1, b2, b3, b4.

[0066] Figure 5 This indicates that chip C M A schematic bottom view of the composition example. Figure 6 This indicates that chip C M A schematic bottom view of the configuration of the included semiconductor substrate 100. Figure 7 This is a schematic cross-sectional view showing the structure of a memory die (MD). Furthermore, Figure 7 Includes cutting along line AA′ Figure 5 The structure shown is a cross-section viewed in the direction of the arrow. Additionally, Figure 7 Includes cutting along BB' line Figure 5 The structure shown is a cross-section viewed in the direction of the arrow. Additionally, Figure 7 Includes cutting along the CC' line Figure 5 The structure shown is a cross-section viewed in the direction of the arrow. Figure 8 yes Figure 7 A schematic enlarged diagram consisting of a portion of it.

[0067] [Chip C] M [Chip Structure] M For example Figure 5 As shown, it has four memory cell array regions R arranged in the X and Y directions. MCA Additionally, chip C M Having relative to the four memory cell array regions R MCA Set on one side in the Y direction (e.g.) Figure 5 The surrounding area R (below) P Surrounding area R P It has multiple input / output circuit regions R arranged in the X direction IO Additionally, in chip C... M The four sides are marked with edge regions R. E In other words, the edge region R E It has: two regions located at both ends in the X direction and extending along the Y direction; and two regions located at both ends in the Y direction and extending along the X direction.

[0068] In addition, chip C M For example Figure 7 As shown, it has a matrix layer L SB Set in the substrate layer L SB The memory cell array layer L below MCAand set in the memory cell array layer L MCA Below this are multiple wiring layers 140, 150, and 160. Additionally, in the memory cell array layer L... MCA An insulating layer 103, such as silicon oxide (SiO2), is embedded between the components of wiring layers 140, 150, and 160.

[0069] [Chip C] M The base layer L SB [Construction] For example Figure 7 As shown, the matrix layer L SB It includes a semiconductor substrate 100, an insulating layer 101 disposed on the upper surface of the semiconductor substrate 100, and an insulating layer 102 disposed on the upper surface of the insulating layer 101. Additionally, in the input / output circuit region R... IO A pad electrode P is provided between the insulating layer 101 and the insulating layer 102. X .

[0070] The semiconductor substrate 100 is, for example, a semiconductor substrate such as silicon (Si) implanted with N-type impurities such as phosphorus (P) or P-type impurities such as boron (B).

[0071] For example Figure 6 As shown, the semiconductor substrate 100 has a region R with four memory cell arrays. MCA There are four corresponding regions R1 and a region R2 surrounding the four regions R1. The four regions R1 are, for example, electrically independent of each other.

[0072] The four regions R1 can be electrically independently constructed using a wafer fabrication process. For example, if the semiconductor substrate 100 is a P-type semiconductor substrate containing P-type impurities, region R2 can be an N-type wafer containing N-type impurities. Alternatively, region R1 can also be a P-type wafer containing P-type impurities.

[0073] Furthermore, the four regions R1 can be electrically independent of each other, for example, using insulating layers. For example, region R2 can also be an STI (Shallow Trench Isolation) containing an insulating layer such as silicon oxide (SiO2).

[0074] Furthermore, the four regions R1 can be physically separated from each other. For example, the semiconductor substrate 100 may have four portions corresponding to the four regions R1 and one portion corresponding to the other regions. Additionally, region R2 may be a groove that divides the five portions.

[0075] Additionally, in the semiconductor substrate 100, multiple input / output circuit regions R IO Multiple contact holes are correspondingly provided. Inside these multiple contact holes, for example... Figure 7 As shown, pad electrode P is set.X Part of it.

[0076] In addition, the semiconductor substrate 100 is not disposed in the edge region R E Therefore, for example Figure 6 As shown, when viewing the memory die MD from the Z direction, in the edge region, the insulating layer 103 and the chip C P The insulating layer 203 and the semiconductor substrate 200 do not overlap with the semiconductor substrate 100 (see reference). Figure 7 ).

[0077] Furthermore, the surface roughness of the semiconductor substrate 100 in the X and Y directions is smaller than that of the chip C. P The roughness of the sides of the semiconductor substrate 200 in the X and Y directions.

[0078] Furthermore, the semiconductor substrate 100 is manufactured from the back side using a method described later. Figure 7 The upper side of the semiconductor substrate 100 is thinned. Therefore, the thickness of the semiconductor substrate 100 in the Z direction is less than the thickness of the semiconductor substrate 200 in the Z direction. Consequently, the chip C... M The thickness in the Z direction is less than that of the chip C. P The thickness in the Z direction.

[0079] Insulation layer 101 ( Figure 7 This is, for example, an insulating layer containing an insulating material such as silicon dioxide (SiO2). Insulating layer 101, for example... Figure 7 As shown, the insulating layer 101 covers the upper surface of the semiconductor substrate 100, as well as the side surfaces in the X and Y directions. Furthermore, the insulating layer 101 extends to the edge region R... E The upper surface of the insulating layer 103 may or may not be covered.

[0080] Insulating layer 102 is, for example, a passivation layer containing an insulating material such as polyimide. Insulating layer 102, for example... Figure 7 As shown, the insulating layer 101 covers the upper surface of the semiconductor substrate 100, as well as its sides in the X and Y directions. Furthermore, the insulating layer 102 extends to the edge region R... E The upper surface of the insulating layer 103 may or may not be covered.

[0081] Pad electrode P X Contains conductive materials such as aluminum (Al). Pad electrode P X For example Figure 7 The device includes: an external connection region 104, with an insulating layer 101 disposed on the upper surface of the semiconductor substrate 100; and an internal connection region 105 disposed on the inner peripheral surface and bottom surface of the contact hole.

[0082] External connection area 104 is connected to welding line B ( Figure 2 , Figure 3 The area of ​​the external connection area 104 is provided with an opening in at least a portion of the portion of the insulating layer 102 corresponding to the external connection area 104. The external connection area 104 is exposed to the outer region of the memory die MD through the opening.

[0083] Internal connection region 105 is connected to memory cell array layer L MCA The area containing contact 112. The internal connection region 105 is located on the bottom surface of the contact holes disposed on the semiconductor substrate 100, covering the memory cell array layer L. MCA The upper surface of the insulating layer 103, including silicon oxide (SiO2).

[0084] In addition, such as Figure 7 As shown, a metal layer M is disposed on the side surfaces of the semiconductor substrate 100 in the X and Y directions of the dielectric insulating layer 101. E Metal layer M E Equipped with pad electrode P X Same material and same film thickness. Metal layer M E It can completely cover the sides of the semiconductor substrate 100 in the X and Y directions, or it can only cover a portion of the sides of the semiconductor substrate 100 in the X and Y directions.

[0085] [Chip C] M memory cell array layer L MCA [Construction] For example Figure 7 As shown, in the memory cell array layer L MCA memory cell array region R MCA The memory cell array (MCA) is provided. The MCA includes multiple memory blocks (BLK) arranged in the Y direction and inter-block insulating layers (106) such as silicon oxide (SiO2) disposed between the multiple memory blocks (BLK).

[0086] The memory block BLK includes: multiple conductive layers 110 arranged in the Z direction; multiple semiconductor layers 120 extending in the Z direction; and multiple gate insulating films 130. Figure 8 ), respectively disposed between multiple conductive layers 110 and multiple semiconductor layers 120.

[0087] The conductive layer 110 is a generally plate-shaped conductive layer extending along the X direction. The conductive layer 110 may comprise a laminated film containing a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). Alternatively, the conductive layer 110 may also comprise, for example, polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). An insulating layer such as silicon oxide (SiO2) is disposed between the plurality of conductive layers 110 arranged in the Z direction. The plurality of conductive layers 110 function, for example, as word lines and gate electrodes of a plurality of memory cells connected to the word lines.

[0088] The semiconductor layer 120 functions, for example, as a channel region for multiple memory cells. The semiconductor layer 120 is, for example, a polysilicon (Si) semiconductor layer. The semiconductor layer 120 has, for example, a generally cylindrical shape. Furthermore, the outer peripheral surfaces of the semiconductor layer 120 are each surrounded by a conductive layer 110, which faces the conductive layer 110.

[0089] An impurity region (not shown) containing N-type impurities such as phosphorus (P) is provided at the lower end of semiconductor layer 120. The impurity region is connected to bit line BL via contacts 121 and 122.

[0090] An impurity region (not shown) containing N-type impurities such as phosphorus (P) or P-type impurities such as boron (B) is provided at the upper end of the semiconductor layer 120. The impurity region is connected to the semiconductor substrate 100.

[0091] also, Figure 7 The illustrated semiconductor layer 120 includes: a portion 123 facing the upper half of the conductive layer 110; and a portion 124 facing the lower half of the conductive layer 110. The widths of the upper portion 123 in the X and Y directions are smaller than the widths of the lower portion 123 in the X and Y directions. Similarly, the widths of the upper portion 124 in the X and Y directions are smaller than the widths of the lower portion 124 in the X and Y directions. However, the semiconductor layer 120 may not have such a shape.

[0092] Gate insulating film 130 ( Figure 8The gate insulating film 130 has a generally cylindrical shape covering the outer peripheral surface of the semiconductor layer 120. The gate insulating film 130 includes a tunnel insulating film 131, a charge storage film 132, and a bulk insulating film 133 deposited between the semiconductor layer 120 and the conductive layer 110. The tunnel insulating film 131 and the bulk insulating film 133 are, for example, insulating films such as silicon oxide (SiO2). The charge storage film 132 is, for example, a film capable of storing charges such as silicon nitride (Si3N4). The tunnel insulating film 131, the charge storage film 132, and the bulk insulating film 133 have a generally cylindrical shape and extend in the Z direction along the outer peripheral surface of the semiconductor layer 120.

[0093] also, Figure 8 This example illustrates a gate insulating film 130 comprising a charge storage film 132 such as silicon nitride. However, the gate insulating film 130 may also comprise a floating gate, for example, polysilicon containing N-type or P-type impurities.

[0094] Additionally, the memory cell array layer L MCA Input / output circuit area R IO For example Figure 7 As shown, it has a plurality of contacts 112 that penetrate the insulating layer 103 and extend along the Z direction.

[0095] Contact 112 may be a multilayer film comprising, for example, a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). Contact 112 has, for example, a generally cylindrical shape. The upper ends of the plurality of contacts 112 are respectively connected to the pad electrode P. X The lower surface of the internal connection area 105. In addition, multiple contacts 112 are respectively connected to the wiring 141 at the lower end.

[0096] [Chip C] M [Construction of wiring layers 140, 150, 160] includes multiple wirings in wiring layers 140, 150, 160 electrically connected to, for example, a memory cell array layer L. MCA The composition and chip C in P At least one of the components in.

[0097] Wiring layer 140 includes multiple wirings 141. These wirings 141 may comprise, for example, a stacked film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as copper (Cu). Furthermore, a portion of the multiple wirings 141 functions as bit lines BL. The bit lines BL are arranged, for example, in the X direction and extend along the Y direction. Additionally, the multiple bit lines BL are respectively connected to multiple semiconductor layers 120.

[0098] The wiring layer 150 includes multiple wirings 151. The multiple wirings 151 may also include, for example, a stacked film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as copper (Cu).

[0099] Wiring layer 160 includes multiple bonding electrodes P I1 The plurality of bonding electrodes P I1 It may also include laminated films such as barrier conductive films such as titanium nitride (TiN) and metal films such as copper (Cu).

[0100] [Chip C] P [Chip Structure] P It includes, for example, a semiconductor substrate 200 and a transistor layer L disposed above the semiconductor substrate 200. TR and set in transistor layer L TR The upper wiring layers are 220, 230, 240, and 250. Additionally, on transistor layer L... TR An insulating layer 203, such as silicon oxide (SiO2), is embedded between the components of wiring layers 220, 230, 240, and 250. Furthermore, a material with a lower dielectric constant than the material of insulating layer 103 can also be used as the material of insulating layer 203.

[0101] [Chip C] P [Semiconductor substrate 200 structure] The semiconductor substrate 200 is, for example, a semiconductor substrate containing p-type silicon (Si) containing p-type impurities such as boron (B). On the surface of the semiconductor substrate 200, a semiconductor substrate region 200S and an insulating region 200I are provided.

[0102] Semiconductor substrate 200 includes edge region R E This applies to all area settings in the memory die MD.

[0103] [Chip C] P transistor layer L TR [Structure] On the upper surface of the semiconductor substrate 200, an electrode layer 210 is disposed on a dielectric insulating layer 200G. The electrode layer 210 includes a plurality of electrodes 211 facing the surface of the semiconductor substrate 200. In addition, each region of the semiconductor substrate 200 and the plurality of electrodes 211 included in the electrode layer 210 are respectively connected to a contact 201.

[0104] The semiconductor substrate region 200S of the semiconductor substrate 200 functions as the channel region of multiple transistors Tr that constitute the peripheral circuit.

[0105] The electrode layer 210 includes a plurality of electrodes 211 that function as gate electrodes of a plurality of transistors Tr constituting a peripheral circuit. The electrodes 211 have, for example, a semiconductor layer such as polysilicon (Si) containing N-type impurities such as phosphorus (P) or P-type impurities such as boron (B); and a metal layer such as tungsten (W) disposed on the upper surface of the semiconductor layer.

[0106] Contact 201 extends along the Z direction and is connected at its lower end to the upper surface of semiconductor substrate 200 or electrode 211. Contact 201 may also include, for example, a stacked film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0107] In addition, the multiple transistors Tr disposed on the semiconductor substrate 200 each constitute part of the peripheral circuit.

[0108] [Chip C] P [Construction of wiring layers 220, 230, 240, 250] The multiple wirings contained in wiring layers 220, 230, 240, 250 are, for example, electrically connected to transistor layer L. TR The composition and chip C in M At least one of the components in.

[0109] The wiring layer 220 includes multiple wirings 221. The multiple wirings 221 may also include, for example, stacked films of barrier conductive films such as titanium nitride (TiN) and metal films such as copper (Cu).

[0110] The wiring layer 230 includes multiple wirings 231. The multiple wirings 231 may also include, for example, stacked films of barrier conductive films such as titanium nitride (TiN) and metal films such as copper (Cu).

[0111] The wiring layer 240 includes multiple wirings 241. The multiple wirings 241 may also include, for example, stacked films of barrier conductive films such as titanium nitride (TiN) and metal films such as copper (Cu).

[0112] Wiring layer 250 includes multiple bonding electrodes P I2 The plurality of bonding electrodes P I2 It may also include laminated films such as barrier conductive films such as titanium nitride (TiN) and metal films such as copper (Cu).

[0113] [Manufacturing Method of Memory Die MD] Next, refer to Figures 9 to 21 The manufacturing method of memory die MD is explained. Figure 9 This is a schematic bottom view used to illustrate the manufacturing method. Figures 10-12 ,and Figures 14-21 This is a schematic cross-sectional view used to illustrate the manufacturing method. Furthermore, Figures 10-12 ,and Figures 14-19 Indicates corresponding to Figure 7 The part. Figure 13 This is a schematic top view used to illustrate the manufacturing method.

[0114] Figure 9 Example of manufacturing chip C M The wafer used W M In wafer WM The semiconductor substrate 100A has multiple dicing lines DL extending along the X or Y direction. Furthermore, each region divided by the multiple dicing lines DL becomes a memory die region R. MD .

[0115] In the manufacturing method, for example Figure 10 and Figure 11 As shown, chip C will be manufactured. M The wafer used W M , and chip manufacturing C P The wafer used W P Bonding. In the bonding step, for example by bonding the wafer W M Pressed onto wafer W P And make the wafer W M With wafer W P Close contact, heat treatment, etc. Thus, wafer W M via bonding electrode P I1 and bonding electrode P I2 bonded to wafer W P superior.

[0116] Next, for example Figure 12 As shown, after the semiconductor substrate 100A is thinned by back-side grinding, a portion of the semiconductor substrate 100A is removed to form the electrode corresponding to the pad P. X Contact holes. Additionally, for example... Figure 12 and Figure 13 As shown, in the cutting line DL and the edge region R E In the process, a portion of the semiconductor substrate 100A is removed. This results in defects on the bottom surface of the contact hole, the dicing line DL, and the edge region R. E In this process, the insulating layer 103 is exposed. Additionally, a semiconductor substrate 100 is formed. This step is performed, for example, by a method such as RIE (Reactive Ion Etching). Furthermore, through this step, the thickness of the semiconductor substrate 100A in the Z direction is less than the thickness of the semiconductor substrate 200A in the Z direction.

[0117] Next, for example Figure 14 As shown, in Figure 12 An insulating layer 101 is formed on the upper surface of the structure shown. This step is performed, for example, by a method such as CVD (Chemical Vapor Deposition).

[0118] Next, for example Figure 15 As shown, on the bottom surface of the contact hole, the cutting line DL, and the edge area R E In the middle, the insulating layer 101 is removed. This results in the removal of insulating layer 101 from the bottom surface of the contact hole, the cutting line DL, and the edge area R.E In this process, the insulating layer 103 is exposed. This step is performed, for example, by a method such as RIE (Reinforcing Interruption).

[0119] Next, for example Figure 16 As shown, a metal layer M is formed on the upper surface of the insulating layer 101, the side surfaces of the insulating layer 101 in the X and Y directions (including the inner peripheral surface of the contact hole), and the upper surface of the insulating layer 103. E The steps described are performed, for example, by methods such as CVD.

[0120] Next, for example Figure 17 As shown, remove metal layer M E Part of forming the pad electrode P X The steps described herein are performed, for example, by methods such as RIE. Furthermore, in these steps, as shown in the figure, the metal layer M may not need to be removed from the sides of the insulating layer 101 in the X and Y directions. E And thus it survived.

[0121] Next, for example Figure 18 As shown, on the upper surface of the insulating layer 101, the metal layer M E The upper surface, metal layer M E An insulating layer 102 is formed on the side surfaces in the X and Y directions (including the inner peripheral surface inside the contact hole) and the upper surface of the insulating layer 103. This step is performed, for example, by a method such as CVD.

[0122] Next, for example Figure 19 As shown, a portion of the insulating layer 102 is removed, exposing the pad electrode P. X A portion of the external connection region 104 is exposed. This step is performed, for example, by a method such as RIE. Furthermore, in this step, as shown in the figure, in the edge region R... E In the middle, the insulation layer 102 can be removed or left as is.

[0123] Next, for example Figure 20 and Figure 21 As shown, the wafer W is cut along the cutting line DL. M W P Therefore, settings are provided in each memory die region R. MD The components are respectively called memory dies (MD). Furthermore, Figure 20 and Figure 21 The example below illustrates cutting a wafer W using a dicing blade DB. M W P The situation.

[0124] In addition, for example, when referencing methods such as RIE. Figure 12 and Figure 13Under the described steps, the roughness of the inner peripheral surface of the contact hole and the side surfaces of the semiconductor substrate 100 in the X and Y directions is relatively small. On the other hand, when using a cutting tool DB as a reference... Figure 20 and Figure 21 In the described steps, the surface roughness of the sides of the semiconductor substrate 200 in the X and Y directions is relatively large. In such cases, there are cases where the surface roughness of the sides of the semiconductor substrate 100 in the X and Y directions is smaller than that of the sides of the semiconductor substrate 200 in the X and Y directions.

[0125] [Comparative Example] Next, refer to Figure 22 and Figure 23 The manufacturing method of the comparative example semiconductor memory device will be described. Figure 22 and Figure 23 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0126] In the method for manufacturing a semiconductor memory device according to the first embodiment, as referenced Figure 12 and Figure 13 Generally speaking, in the fabrication of the pad electrode P X In the corresponding contact hole step, a portion of the semiconductor substrate 100 is removed along the dicing line DL. On the other hand, in the manufacturing method of the comparative example, a portion of the semiconductor substrate 100 is not removed along the dicing line DL in this step.

[0127] In addition, such as Figure 22 and Figure 23 As shown, the wafer W is cut along the cutting line DL. M W P At that time, semiconductor substrates 100A and 200A remained on the dicing line DL.

[0128] In this method, stress can be easily applied to the structure between semiconductor substrates 100A and 200A by the cutting blade DB, such as Figure 23 As illustrated, there is a wafer W M W P The structure in the film may produce cracks d1 or film peeling d2.

[0129] [Effect] In the method for manufacturing a semiconductor memory device according to the first embodiment, as referred to Figure 12 and Figure 13 Generally speaking, when fabricating the electrode corresponding to the pad P... X In the contact hole step, a portion of the semiconductor substrate 100A is removed along the cutting line DL. Therefore, as... Figure 20 and Figure 21 As shown, the wafer W is cut along the cutting line DL. M W PAt that time, no semiconductor substrate 100A remained on the dicing line DL. Therefore, compared with the manufacturing method of the comparative example, it is possible to better suppress the generation of cracks or film peeling.

[0130] Furthermore, in the manufacturing method of the semiconductor memory device in the first embodiment, reference is made to... Figure 12 and Figure 13 The steps described herein include fabricating the pad electrode P together. X The corresponding contact holes are used to remove a portion of the semiconductor substrate 100A along the dicing line DL. This helps to suppress the increase in the number of manufacturing steps.

[0131] [Second Embodiment] Next, refer to Figure 24 The configuration of the semiconductor memory device according to the second embodiment will be described. Figure 24 This is a schematic cross-sectional view showing a portion of the semiconductor memory device according to the second embodiment.

[0132] The semiconductor memory device of the second embodiment is configured in essentially the same way as the semiconductor memory device of the first embodiment. (Refer to...) Figure 7 Generally speaking, in the first embodiment, the sides of the semiconductor substrate 100 in the X and Y directions are formed by an insulating layer 101 and a metal layer M. E Coverage. On the other hand, such as Figure 24 As shown, in the second embodiment, the sides of the semiconductor substrate 100 in the X and Y directions are not covered by the insulating layer 101 and the metal layer M. E cover.

[0133] Next, refer to Figures 25-29 The manufacturing method of the semiconductor memory device according to the second embodiment will be described. Figures 25-29 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0134] In the manufacturing method of the semiconductor memory device according to the second embodiment, the manufacturing method of the semiconductor memory device according to the first embodiment is performed to the reference. Figure 11 That concludes the explained steps.

[0135] Next, for example Figure 25 As shown, a portion of the semiconductor substrate 100A is removed to form an electrode P on the bonding pad. X The corresponding contact hole. Thus, the insulating layer 103 is exposed on the bottom surface of the contact hole. This step is performed, for example, by a method such as RIE (Residual Insulation).

[0136] Next, for example Figure 26 As shown, in Figure 25 An insulating layer 101 and a pad electrode P are formed on the upper surface of the structure shown. XThe steps described are performed, for example, by methods such as CVD and RIE.

[0137] Next, for example Figure 27 As shown, in the cutting line DL and the edge region R E In the process, a portion of the semiconductor substrate 100A is removed. As a result, the insulating layer 103 is removed along the dicing line DL and the edge region R. E The exposed portion. Additionally, a semiconductor substrate 100 is formed. This step is performed, for example, by a method such as RIE.

[0138] Next, for example Figure 28 As shown, on the upper surface of the insulating layer 101, the pad electrode P X The upper surface, pad electrode P X An insulating layer 102 is formed on the side surfaces in the X and Y directions (including the inner peripheral surface inside the contact hole) and the upper surface of the insulating layer 103. This step is performed, for example, by a method such as CVD.

[0139] Next, for example Figure 29 As shown, a portion of the insulating layer 102 is removed, exposing the pad electrode P. X A portion of the external connection region 104 is exposed. This step is performed, for example, by a method such as RIE. Furthermore, in this step, as shown in the figure, in the edge region R... E In the middle, the insulation layer 102 can be removed or left as is.

[0140] Next, for example, refer to Figure 20 and Figure 21 As explained, the wafer W is cut along the dicing line DL. M W P .

[0141] The semiconductor memory device manufacturing method according to the second embodiment, similar to the first embodiment, can better suppress the generation of cracks or film peeling compared to the manufacturing method of the comparative example.

[0142] Furthermore, in the semiconductor memory device manufacturing method of the second embodiment, the wafer W is cut along the dicing line DL. M W P At that time, no metal layer M remained on the sides of the semiconductor substrate 100 in the X and Y directions. E Therefore, it is possible to make the cutting line DL and the edge region R... E The size is relatively small. As a result, it is possible to increase the number of memory dies (MDs) that can be manufactured from a single wafer and reduce manufacturing costs.

[0143] [Third Embodiment] Next, refer to Figure 30 The configuration of the semiconductor memory device according to the third embodiment will be described. Figure 30This is a schematic cross-sectional view showing a portion of the semiconductor memory device according to the third embodiment.

[0144] The semiconductor memory device of the third embodiment is configured in essentially the same way as the semiconductor memory device of the second embodiment. (Referring to...) Figure 24 Generally speaking, in the second embodiment, the sides of the semiconductor substrate 100 in the X and Y directions are covered by the insulating layer 102. On the other hand, as... Figure 30 As shown, in the third embodiment, the sides of the semiconductor substrate 100 in the X and Y directions are not covered by the insulating layer 102.

[0145] Next, refer to Figures 31-33 The manufacturing method of the semiconductor memory device according to the third embodiment will be described. Figures 31-33 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0146] In the manufacturing method of the semiconductor memory device according to the third embodiment, the manufacturing method of the semiconductor memory device according to the second embodiment is performed to the reference. Figure 26 That concludes the explained steps.

[0147] Next, for example Figure 31 As shown, on the upper surface of the insulating layer 101, the pad electrode P X The upper surface, pad electrode P X An insulating layer 102 is formed on the side surfaces in the X and Y directions (including the inner peripheral surface inside the contact hole) and the upper surface of the insulating layer 103. This step is performed, for example, by a method such as CVD.

[0148] Next, for example Figure 32 As shown, a portion of the insulating layer 102 is removed, exposing the pad electrode P. X A portion of the external connection area 104 is exposed. This step is performed, for example, by a method such as RIE.

[0149] Next, for example Figure 33 As shown, in the cutting line DL and the edge region R E A portion of the semiconductor substrate 100A is removed. Consequently, the insulating layer 103 is applied along the dicing line DL and the edge region R. E The exposed portion. Additionally, a semiconductor substrate 100 is formed. This step is performed, for example, by a method such as RIE.

[0150] Next, for example, refer to Figure 20 and Figure 21 As explained, the wafer W is cut along the dicing line DL. M W P .

[0151] The semiconductor memory device manufacturing method according to the third embodiment, similar to the first embodiment, and compared with the comparative example manufacturing method, can better suppress the generation of cracks or film peeling.

[0152] Furthermore, the manufacturing method of the semiconductor memory device according to the third embodiment, like the second embodiment, can reduce manufacturing costs.

[0153] [Other Embodiments] The semiconductor memory devices and their manufacturing methods according to the first to third embodiments have been described above. However, the semiconductor memory devices described in these embodiments are merely examples, and the specific configurations and methods can be appropriately adjusted.

[0154] For example, in the manufacturing method of the third embodiment, as referenced Figure 32 and Figure 33 Generally speaking, a portion of the insulating layer 102 is removed to make the pad electrode P X The exposed steps, and the cutting line DL and edge area R E The step of removing a portion of the semiconductor substrate 100A is described. However, this method is merely illustrative, and the specific method can be appropriately adjusted. For example, in the manufacturing method of the third embodiment, the reference method is performed. Figure 31 After the explained steps, for example Figure 34 As shown, it can also be found in Figure 31 The upper surface of the structure shown is formed with a photoresist 301. In the photoresist 301, for example, with the pad electrode P... X An opening is provided at the position corresponding to the external connection area 104. Additionally, in the resist 301, for example, it is used with the cutting line DL and the edge area R. E An opening is provided at the corresponding location. In this state, a portion of the insulating layer 102 and a portion of the semiconductor substrate 100A can also be removed using methods such as RIE, forming a structure as shown in the reference diagram. Figure 33 The construction is described. In such a case, for example, on the semiconductor substrate 100A, the pad electrode P... X Methods such as RIE can be performed under conditions where removal is easier.

[0155] Furthermore, in cases where such a method is implemented, for example... Figure 35 As shown, the insulation layer 103 is removed from the cutting line DL and the edge region R. E In the case of at least a portion of the part. Thus, a surface 103b is formed on the upper surface of the insulating layer 103, located below the contact surface 103a with the semiconductor substrate 100. In such a case, for example... Figure 36 As shown, the wafer W is cut along the dicing line DL. M W PIn the case where surface 103b is not removed from the upper surface of the insulating layer 103, leaving a residue, the memory system 10 is manufactured in this way. Figure 2 , Figure 3 In the case of, for example Figure 37 As shown, surface 103a is in contact with semiconductor substrate 100, and surface 103b is in contact with molding resin 302.

[0156] Furthermore, there are cases where the roughness of the surfaces 103a and 103b of the insulating layer 103 is less than the roughness of the side surfaces 103c of the insulating layer 103 in the X and Y directions (e.g., the cutting surface of the cutting blade DB).

[0157] Additionally, the molding resin 302 can be an insulating layer such as polyimide or epoxy resin. Furthermore, fillers can be included in the molding resin 302. Also, although... Figure 7 , Figure 24 and Figure 30 The diagram is omitted, but the pad electrode P in the structure shown in the diagram is... X In, it can also be with Figure 37 Similarly, welding line B is connected. Additionally, the upper surface of the structure shown in the figure, as well as the side surfaces in the X and Y directions, can also be connected to the molding resin 302.

[0158] Furthermore, for example, in the manufacturing methods of the first to third embodiments, on the wafer W M W P When it is monolithic, for example, reference Figure 20 and Figure 21 As explained, the wafer W is cut using a dicing blade DB. M W P However, this method is only an example, and the specific method can be adjusted accordingly.

[0159] For example, also consider wafer W M W P In monolithization, the user is utilized. For example, consider the user removing wafer W along the dicing line DL. M W P It is part of the structure and is then cut using a dicing blade DB. Additionally, it is also considered that the user may cut the wafer W along the dicing line DL. M W P The structure within causes damage, and the wafer is broken by mechanical forces rather than a cutting blade. M W P Monolithic.

[0160] Here, when using this user-defined method, it is necessary to first remove one of the semiconductor substrates 100A and 200A along the dicing line DL. This step can also be performed using the same method as in the manufacturing methods of the first to third embodiments. In other words, in the manufacturing methods of the first to third embodiments, this step can be substituted... Figure 20 and Figure 21 The illustrated steps employ the user-defined method described above.

[0161] Furthermore, in the semiconductor memory devices of the first to third embodiments, for example... Figure 7 As shown, it can be done in the memory cell array layer L MCA Edge region R E Only the insulating layer 103 is provided. Additionally, for example... Figure 38 As shown, it can also be done in the memory cell array layer L. MCA Edge region R E The structure comprises multiple insulating layers 110A or multiple semiconductor layers and multiple structures 120′ that are connected to it.

[0162] Multiple insulating layers 110A or multiple semiconductor layers, for example, correspond to and are arranged in the Z direction with respect to multiple conductive layers 110. Furthermore, the multiple insulating layers 110A may comprise, for example, silicon nitride (Si3N4). Furthermore, the multiple semiconductor layers may comprise, for example, silicon (Si). Additionally, an insulating layer, such as silicon oxide (SiO2), is disposed between the multiple insulating layers 110A or the multiple semiconductor layers.

[0163] The structure 120' has, for example, a generally cylindrical shape. Furthermore, the outer peripheral surfaces of the semiconductor layer 120 are surrounded by a plurality of insulating layers 110A or a plurality of semiconductor layers, and face each other. The upper end of the structure 120' is connected to the semiconductor substrate 100. The structure 120' may contain, for example, silicon oxide (SiO2), silicon (Si), or other materials.

[0164] in addition, Figure 38 The illustrated structure 120' includes: a portion 123' facing approximately half of the upper insulating layer 110A or semiconductor layer; and a portion 124' facing approximately half of the lower insulating layer 110A or semiconductor layer. The widths of the upper portion 123' in the X and Y directions are smaller than the widths of the lower portion 123' in the X and Y directions. Similarly, the widths of the upper portion 124' in the X and Y directions are smaller than the widths of the lower portion 124' in the X and Y directions.

[0165] Furthermore, in the first to third embodiments, a semiconductor memory device is exemplified as a form of semiconductor device. However, the configuration and manufacturing method exemplified in the first to third embodiments can also be applied to semiconductor devices other than semiconductor memory devices. Examples of such semiconductor devices include, for example, image sensors, sound sensors or other sensors, CPUs (Central Processing Units), GPUs (Graphics Processing Units), FPGAs (Field Programmable Gate Arrays) or other computing devices, or communication circuits.

[0166] Furthermore, in the first to third embodiments, as two chips C M C P The included substrate is exemplified by a semiconductor substrate. However, the substrates included in the two laminated chips may also be substrates other than semiconductor substrates.

[0167] [Other] Although several embodiments of the present invention have been described, these embodiments are provided by way of example and are not intended to limit the scope of the invention. The novel embodiments may be implemented in various other ways, with various omissions, substitutions, and modifications made without departing from the spirit of the invention. The embodiments or their modifications are included within the scope or spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A semiconductor device comprising: The first chip and the second chip are bonded together via multiple bonding electrodes; and The first chip has the following features: First substrate; First semiconductor device; and The first bonding electrode is one of the plurality of bonding electrodes and is electrically connected to the first semiconductor element; and The second chip has the following features: Second substrate; The second semiconductor device; and The second bonding electrode is one of the plurality of bonding electrodes and is electrically connected to the second semiconductor element; and The second substrate comprises: A pair of first regions, located at both ends of a first direction, extending along a second direction intersecting the first direction; and A pair of second regions are disposed at both ends of the second direction and extend along the first direction; in Viewed from a third direction intersecting the surface of the second substrate, portions of the first region and the second region disposed on the second substrate do not overlap with the first substrate; If the roughness of at least one end of at least one of the first direction and the second direction of the first substrate is set as the first roughness, The roughness of at least one end of the pair of first regions and the pair of second regions of the second substrate is set as the second roughness. Then the first roughness is less than the second roughness, and The first chip and the second chip are the same size.

2. The semiconductor device according to claim 1, wherein The first semiconductor element is a memory unit capable of storing data.

3. The semiconductor device according to claim 1, wherein The first semiconductor element comprises: Multiple first conductive layers are arranged in the third direction; A first semiconductor layer extends along the third direction and is aligned with the plurality of first conductive layers; and A first gate insulating layer is disposed between the plurality of first conductive layers and the first semiconductor layer; and The first semiconductor layer comprises: The first end portion in the third direction; and The second end is farther from the first bonding electrode in the third direction than the first end; and The width of the first end in the first direction and the second direction is greater than the width of the second end in the first direction and the second direction.

4. The semiconductor device according to claim 3, wherein The first semiconductor element comprises: Multiple second conductive layers are separated from the first conductive layer in the third direction and arranged in the third direction; A second semiconductor layer extends along the third direction and is aligned with the plurality of second conductive layers; and A second gate insulating layer is disposed between the plurality of second conductive layers and the second semiconductor layer; and The second semiconductor layer comprises: The third end in the third direction; and The fourth end is farther from the first bonding electrode in the third direction than the third end; and The width of the third end in the first and second directions is greater than the width of the fourth end in the first and second directions.

5. The semiconductor device according to claim 1, wherein The width of the first chip in the third direction is smaller than the width of the second chip in the third direction.

6. The semiconductor device according to claim 1, wherein At least one end of the first substrate in the first direction and the second direction is provided with a laminated structure comprising at least one insulating layer and at least one metal layer.

7. A semiconductor device comprising: The first chip and the second chip are bonded together via multiple bonding electrodes; and The first chip has the following features: First substrate; First semiconductor device; and The first bonding electrode is one of the plurality of bonding electrodes and is electrically connected to the first semiconductor element; and The second chip has the following features: Second substrate; The second semiconductor device; and The second bonding electrode is one of the plurality of bonding electrodes and is electrically connected to the second semiconductor element; wherein If the roughness of at least one end of at least one of the first direction of the first substrate and the second direction intersecting the first direction is defined as the first roughness, The roughness of at least one end of at least one of the first direction and the second direction of the second substrate is defined as the second roughness. Then the first roughness is less than the second roughness, and The first chip and the second chip are the same size.

8. The semiconductor device according to claim 7, wherein The first semiconductor element is a memory unit capable of storing data.

9. The semiconductor device according to claim 7, wherein The first semiconductor element comprises: Multiple first conductive layers are arranged in a third direction that intersects the first direction and the second direction; A first semiconductor layer extends along the third direction and is aligned with the plurality of first conductive layers; and A first gate insulating layer is disposed between the plurality of first conductive layers and the first semiconductor layer; and The first semiconductor layer comprises: The first end portion in the third direction; and The second end is farther from the first bonding electrode in the third direction than the first end; and The width of the first end in the first direction and the second direction is greater than the width of the second end in the first direction and the second direction.

10. The semiconductor device of claim 9, wherein The first semiconductor element comprises: Multiple second conductive layers are separated from the first conductive layer in the third direction and arranged in the third direction; A second semiconductor layer extends along the third direction and is aligned with the plurality of second conductive layers; and A second gate insulating layer is disposed between the plurality of second conductive layers and the second semiconductor layer; and The second semiconductor layer comprises: The third end in the third direction; and The fourth end is farther from the first bonding electrode in the third direction than the third end; and The width of the third end in the first and second directions is greater than the width of the fourth end in the first and second directions.

11. The semiconductor device according to claim 7, wherein The width of the third direction of the first chip, which intersects the first direction and the second direction, is smaller than the width of the third direction of the second chip.

12. The semiconductor device according to claim 7, wherein At least one end of the first substrate in the first direction and the second direction is provided with a laminated structure comprising at least one insulating layer and at least one metal layer.

13. A method for manufacturing a semiconductor device, wherein... A first wafer having a first substrate and a second wafer having a second substrate are bonded together. The portion of the first substrate located on the dicing line is removed, and the first substrate is divided into multiple portions corresponding to multiple bare wafers. The first wafer and the second wafer are cut along the dicing line to form the plurality of bare wafers, wherein... Each of the plurality of bare dies includes a first chip and a second chip bonded together via a plurality of bonding electrodes, and The first chip has the following features: A portion of the first substrate; First semiconductor device; and The first bonding electrode is one of the plurality of bonding electrodes and is electrically connected to the first semiconductor element; and The second chip has the following features: A portion of the second substrate; The second semiconductor device; and The second bonding electrode is one of the plurality of bonding electrodes and is electrically connected to the second semiconductor element; If the roughness of at least one end of at least one of the first direction of the first substrate and the second direction intersecting the first direction is defined as the first roughness, The roughness of at least one end of at least one of the first direction and the second direction of the second substrate is defined as the second roughness. Then the first roughness is less than the second roughness, and The first chip and the second chip are the same size.

14. The manufacturing method according to claim 13, wherein When the first substrate is divided into multiple portions corresponding to multiple bare wafers, multiple contact holes are formed on the first substrate. After forming the plurality of contact holes and before forming the plurality of bare wafers, electrodes are formed inside the plurality of contact holes.

15. The manufacturing method according to claim 13, wherein The first substrate is divided into multiple portions corresponding to multiple bare wafers by reactive ion etching. The first wafer and the second wafer are separated along the cutting line by a cutting tool.

16. The manufacturing method according to claim 13, wherein The first substrate is divided into multiple portions corresponding to multiple bare wafers by reactive ion etching. The first wafer and the second wafer are separated along the cutting line by laser cutting.

17. The manufacturing method according to claim 13, wherein The second substrate comprises: A pair of first regions, disposed at both ends of the first direction, extending along the second direction; and A pair of second regions, located at both ends of the second direction, extending along the first direction; and Viewed from a third direction intersecting the surface of the second substrate, portions of the first region and the second region disposed on the second substrate do not overlap with the first substrate.

18. The manufacturing method according to claim 17, wherein The first semiconductor element is a memory unit capable of storing data.

19. The manufacturing method according to claim 17, wherein The first semiconductor element comprises: Multiple first conductive layers are arranged in the third direction; A first semiconductor layer extends along the third direction and is aligned with the plurality of first conductive layers; and A first gate insulating layer is disposed between the plurality of first conductive layers and the first semiconductor layer; and The first semiconductor layer comprises: The first end portion in the third direction; and The second end is farther from the first bonding electrode in the third direction than the first end; and The width of the first end in the first direction and the second direction is greater than the width of the second end in the first direction and the second direction.

20. The manufacturing method according to claim 17, wherein The width of the first chip in the third direction is smaller than the width of the second chip in the third direction.

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