Integrated circuit device and method of manufacturing the same

Abstract

An ESD protection device includes a PN diode formed in a semiconductor body. The PN diode has a first contact coupled to a metal structure on a front side of the semiconductor body and a second contact coupled to a metal structure on a back side of the semiconductor body. Metal coupled to the first contact is spaced from metal coupled to the second contact by a thickness of the semiconductor body. This spacing greatly reduces the capacitance associated with the metal structures, which can substantially reduce the total capacitance added to an I / O channel by the ESD protection device, thereby improving the performance of high speed circuits using the I / O channel. Embodiments of the present application provide integrated circuit devices and methods of manufacturing the same.

Description

Technical Field

[0001] Embodiments of this application relate to integrated circuit devices and methods for manufacturing the same. Background Technology

[0002] As integrated circuit density increases, the spacing between structures becomes smaller. Smaller spacing leads to higher capacitance. If the capacitance is too high relative to the desired operating speed, it can degrade performance. Therefore, there has long been a need for a low-capacitance device structure that can be used in high-speed circuits. Summary of the Invention

[0003] Embodiments of this application provide an integrated circuit device, including: a semiconductor body having a front side and a back side; a front metal structure formed on the front side; a back metal structure formed on the back side; and a PN diode including a PN junction, a first contact, and a second contact; wherein the PN junction is formed by an interface between a P-doped region of the semiconductor body and an N-doped region of the semiconductor body; one of the first contact and the second contact is a front contact on the front side, and the other of the first contact and the second contact is a back contact on the back side; the front contact is coupled to the front metal structure; and the back contact is coupled to the back metal structure.

[0004] Embodiments of this application provide an integrated circuit device, including: a first metal interconnect and a second metal interconnect, located on opposite sides of a semiconductor body; V SS Track and V DD A rail, configured to supply power to the circuit; I / O terminals for the circuit; ESD protection devices for the circuit, including: a first PN diode and a second PN diode, formed in the semiconductor body; wherein the first PN diode is coupled to the I / O terminal through a first I / O terminal, and through V DD Rail coupling to couple to the V DD Rail; the second PN diode is coupled to the I / O terminal through the second I / O terminal, and through V SS Rail coupling to couple to the V SS Rail; both the first metal interconnect and the second metal interconnect provide coupling only to the first I / O terminal and the V DD One of the rail couplings; and both the first metal interconnect and the second metal interconnect provide only the second I / O terminal coupling and the V SS One type of track coupling.

[0005] Embodiments of this application provide a method for manufacturing an integrated circuit device, the method comprising: forming a PN diode in a semiconductor substrate having a front side and a back side; forming a first metal interconnect on the front side, wherein the first metal interconnect is coupled to a first contact of the PN diode located on the front side; and forming a second metal interconnect on the back side, wherein the second metal interconnect is coupled to a second contact of the PN diode located on the back side.

[0006] Embodiments of this application provide dual-substrate-side ESD diodes for high-speed circuits. Attached Figure Description

[0007] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components can be arbitrarily increased or decreased.

[0008] Figure 1 A cross-sectional view is provided illustrating an ESD protection device in an integrated circuit device according to some aspects of this teaching.

[0009] Figure 2A The image shows the front edge portion of an integrated circuit device, including an ESD protection device, according to some aspects of this teaching.

[0010] Figure 2B Show Figure 2A The back side of the integrated circuit device.

[0011] Figure 3A The image shows the front edge portion of another integrated circuit device, including an ESD protection device, according to some aspects of this teaching.

[0012] Figure 3B Show Figure 3A The back side of the integrated circuit device.

[0013] Figure 4A A diagram of a circuit that may include a diode in accordance with this teaching is provided.

[0014] Figure 4B A diagram is provided of another circuit that may include a diode in accordance with this teaching.

[0015] Figure 5 A cross-sectional view of an ESD protection device in an integrated circuit device is shown, according to some other aspects of this teaching.

[0016] Figure 6 A cross-sectional view of an ESD protection device in an integrated circuit device is shown, according to some other aspects of this teaching.

[0017] Figure 6A Show Figure 6 A top view of the gate structure.

[0018] Figure 7 A cross-sectional view of an ESD protection device in an integrated circuit device is shown, according to some other aspects of this teaching.

[0019] Figure 8 A cross-sectional view of an ESD protection device in an integrated circuit device is shown, according to some other aspects of this teaching.

[0020] Figure 9 A cross-sectional view of an ESD protection device in an integrated circuit device is shown, according to some other aspects of this teaching.

[0021] Figures 10-19 These are a series of cross-sectional views illustrating methods for forming integrated circuit devices with ESD protection devices according to some aspects of this teaching.

[0022] Figure 20 Flowcharts are provided for example methods of forming integrated circuit devices based on some aspects of this teaching. Detailed Implementation

[0023] This invention provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements will be described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components are not in direct contact.

[0024] This disclosure teaches methods and device structures for improving the performance of high-speed circuits having I / O channels with ESD protection. According to some aspects of this teaching, the ESD protection device includes a PN diode formed in a semiconductor body. The PN diode has a first contact coupled to a metal structure on the front side of the semiconductor body and a second contact coupled to a metal structure on the back side of the semiconductor body. The metal coupled to the first contact and the metal coupled to the second contact space the thickness of the semiconductor body. This spacing significantly reduces the capacitance associated with the metal structure, which in turn has been found to greatly reduce the total capacitance associated with the I / O channel, thereby improving the performance of the high-speed circuit.

[0025] The diode can be a P+ / N-well diode and an N+ / P-well diode, an N-well / P-well diode, or a diode having any other type of junction. In some embodiments, the diode has a shallow trench isolation (STI) diode structure because it includes two heavily doped regions separated by an STI structure on the front side of the semiconductor body. The two heavily doped regions can have the same doping type compared to a conventional STI diode. In some embodiments, the diode has a gate-aligned diode structure including two heavily doped regions adjacent to the front side and having edges aligned with the opposite side of a gate structure disposed on the front side. In various embodiments, the two heavily doped regions adjacent to the front side have the same or opposite doping types. In some embodiments, the gate-aligned diode further includes two heavily doped regions adjacent to the back side of the semiconductor body and having edges aligned with the opposite side of a gate structure disposed on the front side. In some embodiments, the gate structure is a polysilicon or metal transistor gate structure. In some embodiments, the gate structure is a finFET (fin field-effect transistor) gate. In some embodiments, the gate structure includes nanosheets or nanowires. Therefore, many of the same process steps used in the formation of integrated circuit devices can be used to form the diode according to the present teachings.

[0026] Some aspects of this teaching relate to an ESD protection device having coupling between the I / O channel and V DD The first PN diode (pull-up diode) between the rails and coupled in the I / O channel and V SS The second PN diode (pull-down diode) between the rails. V DD Track and V SS The rail is the power rail of a circuit, which can be a high-speed circuit. The N-terminal of the pull-up diode is coupled to V. DD Rail. The P terminal of the pull-down diode is coupled to V. SS The pull-up diode's P-terminal and the pull-down diode's N-terminal are coupled to the I / O channel. This structure clamps the I / O channel to V. DD Above rail voltage and V SS Below rail voltage. According to this teaching, each of the first pull-down diode and the pull-up diode has a contact located on the opposite side of the semiconductor body, which is coupled to a metal structure located on the opposite side of the semiconductor body.

[0027] In some embodiments, the pull-up diode is a P+ / N-well diode. This structure can facilitate coupling to V... DD Isolation in N-well devices. In some embodiments, the pull-down diode is an N+ / P-well diode. This structure can facilitate isolation with coupling to V. SS Isolation in devices with P-substrate.

[0028] Some aspects of this teaching relate to a method of manufacturing an integrated circuit device having a diode according to this disclosure. The method includes: forming a PN junction diode in a semiconductor substrate; forming a first metal interconnect coupled to one side of the PN junction diode on a front side of the semiconductor substrate; and forming a second metal interconnect coupled to a second side of the PN junction diode on a side portion of the semiconductor substrate. In some embodiments, the semiconductor substrate is thinned before forming the second metal interconnect. In some embodiments, all doping of the semiconductor substrate is completed before forming the first or second metal interconnect.

[0029] Figure 1 A cross-sectional view 100 of an ESD protection device 105A in an integrated circuit device according to some aspects of this teaching is shown. The ESD protection device 105A includes a pull-down diode 167A formed in a first region 153 of a semiconductor substrate 159 and a pull-up diode 133A formed in a second region 149. A first top metal structure 171 couples the pull-down diode 167A to an I / O terminal. The I / O terminal may be a solder bump 101 or some other structure through which an electrical connection to an external device can be established. A first bottom metal structure 155 couples the pull-down diode 167A to a V... SS Track. V SS The rail can extend from the first bottom metal structure 155 and can be connected to the anode of the power supply via solder bump 151 or a similar structure.

[0030] The second top metal structure 107 couples the pull-up diode 133A to the I / O terminal. This connection can also be achieved via solder bump 101 or some other structure. The solder bump 101 is shown twice to illustrate that each of the pull-down diode 167A and the pull-up diode 133A has a connection to the I / O terminal. The second bottom metal structure 145 couples the pull-up diode 133A to V DD Track. V DD The rail can extend from the second bottom metal structure 145 and can be connected to the cathode of the power supply via solder bumps 147 or a similar structure.

[0031] The pull-down diode 167A includes a heavily N-doped region 165A adjacent to the front side 124 of the semiconductor body 159A. The heavily N-doped region 165A has an edge aligned with a gate structure 114A formed on the front side 124 and may have additional edges defined by a dielectric structure such as a shallow trench isolation (STI) region 129. The heavily N-doped region 165A provides an N-doped contact 166A on the front side 124. The N-terminus of the pull-down diode 167A is connected to a first top metal structure 171 via the N-doped contact 166A. A silicide pad 125A may be disposed on the N-doped contact 166A to reduce connection resistance. A metal plug 123 may also be part of the connection structure. The metal plug 123 may be tungsten (W), copper (Cu), cobalt (Co), titanium (Ti), titanium nitride (TiN), or any other suitable material for achieving this type of connection.

[0032] The pull-down diode 167A may include a heavily p-doped region 161A adjacent to the back side 138 of the semiconductor body 159A. The heavily p-doped region 161A also has an edge aligned with the gate structure 114A. The heavily p-doped region 161A provides a p-doped contact 158A on the back side 138. The p-terminal of the pull-down diode 167A is connected to the first bottom metal structure 155 via the p-doped contact 158A. A silicide pad 156A may be disposed on the p-doped contact 158A to reduce connection resistance. The silicide pads 125A, 137A, and 156A may include any suitable silicide. Suitable silicides may be, for example, titanium silicide (TiSi2), tungsten silicide (WSi2), tantalum silicide (TaSi2), nickel silicide (NiSi), cobalt silicide (CoSi2), platinum silicide (PtSi), etc.

[0033] Given the relatively large area for connection to the pull-down diode 167A on the back side 138, the ESD protection device 105A can operate without the heavily p-doped region 161A. In this case, a p-well can provide a p-doped contact 158A. Eliminating the heavily p-doped region 161A simplifies the fabrication of the ESD protection device 105A. Another option is to form a single heavily p-doped region 161A that extends across the entire back side 138 below the pull-down diode 167A.

[0034] P-well 163A extends from the heavily N-doped region 165A to the heavily P-doped region 161A adjacent to the back side 138. P-well 163A also extends from the front side 124 to the back side 138. P-well 163A is disposed between the heavily P-doped regions 161A and below the gate structure 114A. P-well 163A can be formed by doping the semiconductor body 159A, or it can be simply the semiconductor body 159A if the semiconductor body 159A is initially P-doped.

[0035] The pull-down diode 167A is an N+ / P-well diode because it includes a PN junction 164A, which is formed by the interface between a heavily N-doped region 165A and an undoped P-well 163A. The P-well 163A can be electrically coupled to V. SS The pull-down diode 167A is a gate-aligned diode. A gate-aligned diode is a diode that includes a PN junction whose edge is aligned with a gate structure. The PN junction 164A of the pull-down diode 167A has an edge aligned with the gate structure 114A.

[0036] The pull-up diode 133A includes a heavily p-doped region 127A adjacent to the front side 124 of the semiconductor body 159A. The heavily p-doped region 127A has an edge aligned with a gate structure 115A formed on the front side 124 and may have additional edges defined by a dielectric structure such as a shallow trench isolation (STI) region 129. The heavily p-doped region 127A provides a p-doped contact 116A on the front side 124. The p-terminal of the pull-up diode 133A is connected to a second top metal structure 107 via the p-doped contact 116A. A silicide pad 125A may be disposed on the p-doped contact 116A to reduce connection resistance. A metal plug 123 may also be part of the connection structure.

[0037] Pull-up diode 133A may include a heavily N-doped region 135A adjacent to the back side 138 of semiconductor body 159A. In this example, the heavily N-doped region 135A also has an edge aligned with one of the gate structures 115A. The heavily N-doped region 135A provides an N-doped contact 139A on the back side 138. The N-terminus of pull-up diode 133A is connected to a second bottom metal structure 145 via the N-doped contact 139A. A silicide pad 137A may be disposed on the N-doped contact 139A to reduce connection resistance. As described with respect to the heavily P-doped region 161A, ESD protection device 105A can operate without the heavily N-doped region 135A. In this case, N-well 131A may provide the N-doped contact 139A.

[0038] N-well 131A extends from the heavily p-doped region 127A to the heavily n-doped region 135A adjacent to the back side 138. N-well 131A also extends from the front side 124 to the back side 138. N-well 131A is disposed between the heavily n-doped regions 135A and below one of the gate structures 115A. N-well 131A can be formed by doping a semiconductor body 159A, or it can be simply a semiconductor body 159A if the semiconductor body 159A is initially n-doped.

[0039] The pull-up diode 133A is a P+ / N-well diode because it includes a PN junction 130A, which is formed by the interface between a heavily P-doped region 127A and an undoped N-well 131A. The N-well 131A can be electrically coupled to V. DD The pull-up diode 133A effectively maintains the voltage at the cathode of the power supply. It is also a gate-aligned diode. The PN junction 130A of the pull-up diode 133A has an edge aligned with the gate structure 115A.

[0040] Gate structures 114A and 115A can be dummy gates, polysilicon gates, metal gates, or any other type of gate. Gate structures 114A and 115A can include a gate electrode 117 and a gate dielectric 119 disposed between the gate electrode 117 and the semiconductor body 159A. Gate structures 114A and 115A also include spacers 121 on the side of the gate electrode 117. Spacers 121 can be silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), another dielectric, or any other material used as a mask when doping the semiconductor body 159A.

[0041] The alignment referred to herein with the gate structure or its edges is an alignment achieved by using all or part of the gate structure as a mask for dopant implantation. A gate-aligned diode is a diode with a PN junction, the location of which is determined by a dopant distribution having this type of alignment. The alignment is the same as the source-channel and drain-channel junction in a transistor with a self-aligned gate. In a self-aligned gate, source and drain implantation are formed using the gate electrode as a mask or the gate electrode plus sidewall spacers as a mask. In either case, a horizontal alignment is established between the gate electrode and the edges of the source and drain regions without the use of photolithography. Self-aligned doping can provide two PN junctions that are approximately symmetrical and located on two opposite sides of the gate structure.

[0042] like Figure 1 As shown, the heavily N-doped regions 165A and 127A near the front side 124 and the heavily P-doped regions 161A and 135A near the back side 138 have been formed by dopant implantation masked by gate structures 114A and 115A including spacers 121. This is emphasized by showing that these heavily doped regions have boundaries that are perfectly horizontally aligned with the edges of spacers 121. In reality, the alignment is only approximate. Due to effects including dopant diffusion, the edges of the heavily doped regions lie below spacers 121. The heavily doped regions typically terminate near the gate electrode 117 and do not extend below the gate electrode 117. As a result, PN junctions 164A and 130A typically extend below and terminate below spacers 121.

[0043] A heavily doped region is a degraded doped region of a semiconductor substrate. A degraded doped region of a semiconductor substrate is a region where the doping concentration is sufficiently high to make the semiconductor's conductivity similar to that of a metal. In some embodiments, the heavily doped region has a doping concentration of 10. 19 / cm 3 Or a higher dopant concentration. In some embodiments, the heavily doped region has 10 20 / cm 3 Or higher dopant concentrations. The N-wells and P-wells of this disclosure can have moderate doping levels that are relatively high but do not degrade. In some embodiments, these doping levels are in the range of 10... 13 / cm 3 Up to 10 18 / cm 3 In some embodiments, these doping levels are in the range of 10. 15 / cm 3 Up to 10 18 / cm 3 In some embodiments, these doping levels are in the range of 10. 16 / cm 3 Up to 10 18 / cm 3 Within a certain range. The relatively high doping concentration reduced the resistance of the pull-down diode 167A and the pull-up diode 133A.

[0044] The first top metal structure 171 and the second top metal structure 107 are both part of a metal interconnect structure 169 formed on the front side 124 of the semiconductor body 159A. The metal interconnect structure 169 includes multiple metallization layers 111 (e.g., M0, M1, M2...M...) located within the dielectric matrix 109. top ) and via 113. If both the first top metal structure 171 and the second top metal structure 107 are connected to the same terminal or rail, they can be a continuous metal structure. Both the first bottom metal structure 155 and the second bottom metal structure 145 are part of a bottom metal interconnect structure 157 formed on the back side 138 of the semiconductor body 159A. The bottom metal interconnect structure 157 includes a plurality of metallization layers 141 (e.g., BM0, BM1...BM) located in the dielectric matrix 143. top ) and through hole 140.

[0045] In some embodiments, P-well 163A is isolated from N-well 131A via STI region 129 or a similar dielectric structure. However, if P-well 163A is coupled to V... SS And N-well 131A is coupled to V DDThen the junction between P-well 163A and N-well 131A will be reverse biased. Therefore, although silicide pads 156A and 137A should still be isolated, P-well 163A and N-well 131A can be adjacent.

[0046] ESD protection device 105A has been described as using metal structures 107 and 171 on the front side 124 for I / O terminal connections, and metal structures 145 and 155 on the back side 138 for V SS Track and V DD Rail connection. In an alternative embodiment, metal structures 155 and 145 on the back side are used for I / O terminal connections, and metal structure 171 is used for V... DD Rail connection, and metal structure 107 for V SS Rail connection. In this configuration, P-well 163A and N-well 131A can be floated relative to the I / O terminals. If an alternative connection structure is to be used, the doping types of P-well 163A and N-well 131A can be reversed to avoid this floating.

[0047] Metallization layer 111, metallization layer 141, via 113, and via 140 can be formed of any suitable metal, such as copper (Cu), aluminum (Al), gold (Au), tungsten (W), titanium nitride (TiN), etc. Dielectric matrix 109 and dielectric matrix 143 can include low-k dielectrics or very low-k dielectrics. Low-k dielectrics are materials with a dielectric constant lower than that of SiO2. The dielectric constant of SiO2 is approximately 3.9. Examples of low-k dielectrics include organosilicon glasses (OSGs), such as carbon-doped silicon dioxide, fluorine-doped silicon dioxide (also known as fluorinated silica glass (FSG)), organic polymer low-k dielectrics, and porous silicate glasses. Very low-k dielectrics are materials with a dielectric constant of approximately 2.1 or less. Very low-k dielectric materials are typically low-k dielectric materials formed as porous structures. Porosity reduces the effective dielectric constant.

[0048] The semiconductor body 159A may be or include one or more layers of silicon (Si), germanium (Ge), silicon-germanium (SiGe), oxide semiconductors such as indium gallium zinc oxide (IGZO), III-V materials such as indium gallium arsenide (InGaAs), etc. Some layers of the semiconductor body 159A may be formed by epitaxial growth. The semiconductor body 159A may be part of a semiconductor substrate such as a wafer or die. In some embodiments, the semiconductor substrate is silicon-on-insulator (SOI). The semiconductor body 159A may support various devices, including devices forming circuitry protected by ESD protection device 105A.

[0049] The semiconductor body 159A can be very thin. In some embodiments, the thickness 136A of the semiconductor body 159A is 5 μm or less when measured from the front side 124 to the back side 138 via the pull-down diode 167A or the pull-up diode 133A. In some embodiments, the thickness 136A is 1 μm or less. In some embodiments, the thickness 136A is 400 nm or less. Keeping the thickness 136A small helps to keep the resistance of the pull-down diode 167A and the pull-up diode 133A low. Reducing the resistance of the pull-down diode 167A and the pull-up diode 133A extends the ESD protection provided by the ESD protection device 105A.

[0050] Another parameter more closely related to the resistance of pull-down diode 167A and pull-up diode 133A is the span 134A of the moderately doped portion of pull-down diode 167A or pull-up diode 133A. The span 134A of the moderately doped portion of pull-up diode 133A is the distance from the heavily P-doped region 127A to the heavily N-doped region 135A. If the heavily N-doped region 135A is removed, the span 134A is the distance from the heavily P-doped region 127A to the back side 138. Similarly, the span 134A of the moderately doped portion of pull-down diode 167A is the distance from the heavily N-doped region 165A to the heavily P-doped region 161A. If the heavily P-doped region 161A is removed, the span 134A of pull-down diode 167A is the distance from the heavily N-doped region 165A to the back side 138. In some embodiments, the span 134A is 1 μm or less. In some embodiments, the span 134A is less than 400 nm or less. In some embodiments, the span 134A is in the range of 30 nm to 150 nm.

[0051] Figure 2A and Figure 2B The front side 201 and back side 202 of an integrated circuit device 200, concentrated on an edge portion including an ESD protection device 105A, are shown. Figure 2A As shown, solder bump 101 can be located on the front side 124 above pull-down diode 167A. In this configuration, solder bump 101 is not required because the first top metal structure 171 and the second top metal structure 107 are combined. As shown, ESD protection device 105A can be one of an array of similar devices in integrated circuit device 200.

[0052] like Figure 2B As shown, V is provided SS The solder bump 151 can be offset from the pull-down diode 167A. The first bottom metal structure 155 can be part of a larger metal structure 203 extending from the solder bump 151 below the pull-down diode 167A. The larger metal structure 203 can be used as a V... SSThe rail provides V-band protection for multiple ESD protection devices 105A and potentially for other devices. SS Connection. Similarly, V is provided. DD The solder bump 147 can be offset from the pull-up diode 133A. The second bottom metal structure 145 can be part of a larger metal structure 205 extending from the solder bump 147 below the pull-up diode 133A. The larger metal structure 205 can be used as a V... DD The rail provides V-band protection for multiple ESD protection devices 105A and potentially for other devices. DD connect.

[0053] Figure 3A and Figure 3B The diagram shows a front side 301 and a back side 303 of an integrated circuit device 300 that may include an ESD protection device 105A, and all solder bumps on one side. (See diagram for reference.) Figure 3A and Figure 3B As shown, V is provided SS The solder bump 151 can be located on the front side 301 and can be connected to a larger metal structure 203 on the back side 303 via a silicon through-hole 305. Similarly, V... DD The solder bump 147 can be located on the front side 301 and can be connected to a larger metal structure 205 on the back side 303 via another silicon through-hole 307.

[0054] Figure 4A A diagram of a circuit 400, which may include an ESD protection device 105A, is provided. In circuit 400, a pull-down diode 167A is connected to I / O terminal 401 and V. SS Between rails 407. If the resistance of pull-down diode 167A is low enough, the negative voltage spike on I / O terminal 401 will discharge through pull-down diode 167A instead of through the protected circuit 405. Pull-up diode 133A is connected between I / O terminal 401 and V. DD Between rails 403. If the resistance of pull-up diode 133A is low enough, the positive voltage spike on I / O terminal 401 will discharge through pull-up diode 133A instead of through protected circuit 405. If the capacitance of pull-up diode 133A and pull-down diode 167A is low enough, the signal entering through I / O terminal 401 will be transmitted to protected circuit 405 as intended.

[0055] Figure 4B A diagram of circuit 420, which may also include ESD protection device 105A, is provided. In circuit 420, pull-down diode 167A and second pull-down diode 423 are connected in series at I / O terminals 401 and V. SSBetween rails 407. Pull-up diode 133A and second pull-up diode 421 are connected in series between I / O terminals 401 and V. DD Between rails 403. This configuration extends the voltage range that will not trigger ESD protection. Pull-down diode 167A and pull-up diode 133A can be used individually or in combination as diodes in any ESD protection circuit or any other device where low capacitance or low resistance characteristics are desired.

[0056] Figures 5-9 Cross-sectional views 500-900 show ESD protection device 105B-F, which has pull-down diodes 167B-F replacing pull-down diode 167A and pull-up diodes 133B-F replacing pull-up diode 133A, respectively. Comments regarding the structure in cross-sectional view 100 apply to the corresponding structures shown in cross-sectional views 500-900, except for the differences shown in the figures or indicated in the following description.

[0057] Figure 5 Cross-sectional view 500 shows an ESD protection device 105B, which includes a pull-down diode 167B and a pull-up diode 133B. The pull-down diode 167B includes a heavily N-doped region 165B and a heavily P-doped region 161B aligned to the opposite side of a gate structure 114A formed on the front side 124. The heavily N-doped region 165B provides a front-side contact 166B, and the heavily P-doped region 161B provides a back-side contact 158B. A P-well 163B, disposed below the gate structure 114A, extends from the heavily N-doped region 165B to the heavily P-doped region 161B. A PN junction 164B is formed at the interface between the heavily N-doped region 165B and the P-well 163B. Therefore, the pull-down diode 167B is a gate-aligned N+ / P-well junction diode.

[0058] The pull-up diode 133B includes a heavily P-doped region 127B and a heavily N-doped region 135B aligned to the opposite side of the gate structure 115A formed on the front side 124. The heavily P-doped region 127B provides a front-side contact 116B, and the heavily N-doped region 135B provides a back-side contact 139B. An N-well 131B disposed below the gate structure 115A extends from the heavily P-doped region 127B to the heavily N-doped region 135B. A PN junction 130B is formed at the interface between the heavily P-doped region 127B and the N-well 131B. Therefore, the pull-up diode 133B is a gate-aligned P+ / N-well junction diode.

[0059] The width 134B of the N-well 131B is approximately the same as the width of the gate structure 115A, and spans from the heavily P-doped region 127B to the heavily N-doped region 135B. Reducing the width 134B reduces the resistance of the pull-up diode 133B. In some embodiments, the width 134B is 400 nm or less. In some embodiments, the width 134B is less than 100 nm or less. In some embodiments, the width 134B is 28 nm or less. The resistance of the pull-up diode 133B can also be reduced by increasing the depth of the heavily P-doped region 127B to the heavily N-doped region 135B. In some embodiments, the heavily P-doped region 127B and the heavily N-doped region 135B extend from the front side 124 to the back side 138. Typically, the pull-up diode 133B has a smaller resistance within the body 159B compared to the pull-up diode 133A. The advantage can be offset by reducing the area available for connecting pull-up diode 133A to the second top metal structure 107 and the second bottom metal structure 145, compared to the area available for connecting pull-up diode 133B to these structures. For example, the area available for silicide pads 125B and 137B is smaller than the area available for silicide pads 125A and 137A. It will be understood that pull-down diodes 167B and 167A undergo a similar comparison.

[0060] Figure 6 Cross-sectional view 600 shows an ESD protection device 105C, which includes a pull-down diode 167C and a pull-up diode 133C. The pull-down diode 167C includes two heavily N-doped regions 165C aligned to the opposite side of the gate structure 115C. The two heavily N-doped regions 165C may include doped regions on a semiconductor fin 168C and / or epitaxial growth. The heavily N-doped regions 165C provide a front-side contact 166C. The semiconductor fin 168C is P-doped between the heavily N-doped regions 165C, but may alternatively be N-doped. A P-well 163C disposed below the semiconductor fin 168C extends to the back side 138 and provides a back-side contact 158C. A PN junction 164C is formed by the interface between the heavily N-doped regions 165C and the P-well 163C. Therefore, the pull-down diode 167C is a gate-aligned N+ / P-well junction diode.

[0061] The pull-up diode 133C includes two heavily P-doped regions 127C aligned to the opposite side of the gate structure 115C. The two heavily P-doped regions 127C may include doped regions on a semiconductor fin 126C and / or epitaxially grown regions. The heavily P-doped regions 127C provide a front-side contact 116C. The semiconductor fin 126C is N-doped between the heavily P-doped regions 127C, but may alternatively be P-doped. An N-well 131C disposed below the semiconductor fin 126C extends to the back side 138 and provides a back-side contact 139C. A PN junction 130C is formed by the interface between the heavily P-doped regions 127C and the N-well 131C. Therefore, the pull-up diode 133C is a gate-aligned P+ / N-well junction diode.

[0062] The thickness 134C of the semiconductor body 159C beneath fin 168C separates the heavily N-doped region 165C from the back contact 158C. The same thickness 134C separates the heavily P-doped region 127C from the back contact 139C. Reducing the thickness 134C decreases the resistance of the pull-down diode 167C and the pull-up diode 133C. In some embodiments, the thickness 134C is 5 μm or less. In some embodiments, the thickness 134C is 1 μm or less. In some embodiments, the thickness 134C is 400 nm or less.

[0063] Pull-down diode 167C and pull-up diode 133C have no heavily doped semiconductors near their back-side contacts 158C and 139C, but these contacts have relatively large areas. In some embodiments, the area of ​​back-side contact 158C is equal to the area of ​​P-well 163C. In some embodiments, the area of ​​back-side contact 139C is equal to the area of ​​N-well 131C. In an alternative embodiment, the doping of the heavily N-doped region 165C and the heavily P-doped region 127C is modified to correspond to... Figure 5 The pattern shown in the cross-sectional view 500 provides a short horizontal path on the heavily doped back-side contacts and the moderately doped portions of the pull-down diode 167C and the pull-up diode 133C.

[0064] Gate structures 114C and 115C can be single-fin or multi-fin gate structures. Figure 6A The diagram shows a top view of gate structure 115C in the example, where gate structures 114C and 115C are tri-fin gates. Epitaxial growth on semiconductor fin 126C increases the area available for the front contact 116C. Increasing the area of ​​the front contact 116C reduces the resistance of the pull-up diode 133C. The area can be further increased using a multi-fin gate structure, such as... Figure 6A As shown, growth on adjacent fins merges to form a relatively large heavily p-doped region 127C. The heavily p-doped region 127C and the heavily n-doped region 165C can be siliconized where they form front or back contacts.

[0065] Figure 7 Cross-sectional view 700 shows an ESD protection device 105D, which includes a pull-down diode 167D and a pull-up diode 133D formed in a semiconductor body 159D. The pull-down diode 167D includes a heavily N-doped region 165D and a heavily P-doped region 161D formed on the opposite side of the P-doped fin 163D. The heavily N-doped region 165D provides a front-side contact 166D, while the heavily P-doped region 161D provides a back-side contact 158D. A silicide pad 137D may be formed on the back-side contact 158D. The gate structure 114D includes a gate electrode 117D formed from a plurality of nanosheets. The nanosheets are separated from the P-doped fin 163D by a gate dielectric 119D. The P-doped fin 163D may cover the dielectric 129D, extending from the heavily N-doped region 165D to the heavily P-doped region 161D, and serve as a P-well for the pull-down diode 167D. The PN junction 164D is formed by the interface between the heavily N-doped region 165D and the P-doped fin 163D. Therefore, the pull-down diode 167D is an N+ / P-well junction diode. The span 134D of the moderately doped portion of the pull-down diode 167D can be limited to the width of the P-doped fin 163D.

[0066] The pull-up diode 133D includes a heavily P-doped region 127D and a heavily N-doped region 135D formed on the opposite side of an N-doped fin 131D. The heavily P-doped region 127D provides a front-side contact 116D, while the heavily N-doped region 135D provides a back-side contact 139D. The gate structure 115D includes a gate electrode 117D formed of multiple nanosheets. The nanosheets are separated from the N-doped fin 131D by a gate dielectric 119D. The N-doped fin 131D may cover the dielectric 129D and serve as the N-well of the pull-up diode 133D, extending from the heavily P-doped region 127D to the heavily N-doped region 135D. A PN junction 130D is formed at the interface between the heavily P-doped region 127D and the N-doped fin 131D. Therefore, the pull-up diode 133D is a P+ / N-well junction diode. Pull-down diode 167D and pull-up diode 133D can be formed on insulator using the same set of processes as those used to form transistors with gate structures 114D and 115D.

[0067] Figure 8Cross-sectional view 800 shows an ESD protection device 105E, which includes a pull-down diode 167E and a pull-up diode 133E formed in a semiconductor body 159E. The pull-down diode 167E includes a heavily N-doped region 165E defined on all sides by an STI region 112. The pull-down diode 167E includes two heavily N-doped regions 165E separated by the STI region 112, but removing the STI region 112 between the heavily N-doped regions 165E is also an option. The heavily N-doped region 165E provides a front-side contact 166E on which a silicide 125E can be formed. A P-well 163E disposed below the heavily N-doped region 165E extends to the back side 138 and provides a back-side contact 158E. Alternatively, a heavily doped deep P-well can be inserted between the P-well 163E and the back side 138 to provide heavy doping near the back-side contact 158E. The P-well 163E can extend below one or more STI regions 112 from one of the heavily N-doped regions 165E to another of the heavily N-doped regions 165E. The PN junction 164E is formed by the interface between the heavily N-doped region 165E and the P-well 163E. Therefore, the pull-down diode 167E is an N+ / P-well junction diode.

[0068] Pull-up diode 133E includes a heavily p-doped region 127E defined on all sides by STI region 112. Pull-up diode 133E includes two heavily p-doped regions 127E separated by STI region 112. The heavily p-doped region 127E provides a front-side contact 116E on which silicide 125E can be formed. An N-well 131E disposed below the heavily p-doped region 127E extends to the back side 138 and provides a back-side contact 139E. Alternatively, a heavily doped deep N-well can be inserted between the N-well 131E and the back side 138 to provide the back-side contact 139E. The N-well 131E can extend from one of the heavily p-doped regions 127E to another of the heavily p-doped regions 127E below one or more STI regions 112. PN junction 130E is formed by the interface between the heavily p-doped region 127E and the N-well 131E. Therefore, pull-up diode 133E is an STI P+ / N-well junction diode.

[0069] The resistance of the pull-up diode 133E is proportional to the distance 134E from the heavily P-doped region 127E to the back side 138. The distance 134E varies with the thickness 136E of the body 159E. The body 159E can be thinned in the first region 153 and the second region 149 to keep the resistance of the pull-down diode 167E and the pull-up diode 133E low.

[0070] Figure 9Cross-sectional view 900 shows an ESD protection device 105F, which includes a pull-down diode 167F and a pull-up diode 133F formed in a semiconductor body 159F. The pull-down diode 167F is similar to... Figure 8 The pull-down diode 167E differs from the pull-down diode 167F in that, in the pull-down diode 167F, an N-well 156 is inserted between a heavily N-doped region 165E and a P-well 163F. The pull-down diode 167F includes a PN junction 164F formed by the interface between the N-well 156 and the P-well 163F. Therefore, the pull-down diode 167E is an STI P-well / N-well junction diode.

[0071] The pull-up diode 133F is similar to Figure 8 The pull-up diode 133F differs from the pull-up diode 133E in that, in the pull-up diode 133F, a P-well 128 is inserted between a heavily P-doped region 127E and an N-well 131F. The pull-up diode 133F includes a PN junction 130F formed by the interface between the P-well 128 and the N-well 131F. Therefore, the pull-up diode 133F is an STI P-well / N-well junction diode. In some applications, the pull-down diode 167F and the pull-up diode 133F may offer better resistance or capacitance compared to the pull-down diode 167E and the pull-up diode 133F, respectively.

[0072] Figures 10-19 Cross-sectional views 1000-1900 are shown, illustrating methods for forming integrated circuit devices with diodes according to some embodiments of the present disclosure. Although described... Figures 10-19 It's related to the method, but it should be understood. Figures 10-19 The disclosed structure is not limited to this method, but can exist independently of this method. Furthermore, although... Figures 10-19 A specific structure and composition are shown, but the method can be readily extended to other structures and compositions within the scope of this disclosure.

[0073] like Figure 10 As shown in cross-sectional view 1000, the process can begin with the formation of a photoresist mask 1001, and the photoresist mask 1001 is used to mask the first region 153 of the body 159A while irradiating with plasma to form an N-well 131A in the second region 149. The body 159A can be p-doped first, thereby forming a P-well 163A in the substrate region not exposed to plasma. The photoresist mask 1001 is then stripped off.

[0074] like Figure 11As shown in cross-sectional view 1100, the STI region 129 can be formed in the body 159A. Forming the STI region 129 may include forming trenches, depositing dielectric, and planarizing to remove dielectric deposited outside the trenches. Other types of isolation structures may be used instead of the STI region 129. The STI region 129 may be formed earlier or later in the process.

[0075] like Figure 12 As shown in the cross-sectional diagram 1200, it can be seen that... Figure 11 A dummy gate structure 1201 is formed above the structure shown in cross-sectional view 1100. The dummy gate structure 1201 includes a dummy gate electrode 1203, which may be polysilicon or the like. The dummy gate structure 1201 may include a gate dielectric 119 or another material subsequently replaced by the gate dielectric 119. Sidewall spacers 121 are formed around the dummy gate electrode 1203 and are considered part of the dummy gate structure 1201. Forming the sidewall spacers 121 may involve depositing spacer material followed by anisotropic etching, leaving only the material forming the sidewall spacers 121.

[0076] like Figure 13 As shown in cross-sectional view 1300, the second region 149 can be covered by photoresist mask 1301, while a heavily p-doped region 161A is formed in the first region 153. A dummy gate structure 1201 masks a portion of the first region 153, thereby aligning the edge of the heavily p-doped region 161A with the edge of the dummy gate structure 1201. The heavily p-doped region 161A can be formed by a high-energy plasma injection process, the type of which is used to form a deep p-well, such as a p-well located below and spaced from the front side 124. The photoresist mask 1301 is then stripped off.

[0077] like Figure 14 As shown in cross-sectional view 1400, a first region 153 can be covered by a photoresist mask 1401, while a heavily N-doped region 135A is formed in a second region 149. A dummy gate structure 1201 masks a portion of the second region 149, thereby aligning the edge of the heavily N-doped region 135A with the edge of the dummy gate structure 1201. The heavily N-doped region 135A can be formed by a high-energy plasma implantation process, the type of which is used to form a deep N-well. This process may include irradiating the front side 124 with high-energy plasma. Alternatively, a buried layer can be formed using diffusion and / or epitaxial growth processes, which function similarly to the heavily P-doped region 161A and the heavily N-doped region 135A, but are not aligned with the dummy gate structure 1201. The heavily P-doped region 161A and the heavily N-doped region 135A without gate alignment can also be formed by high-energy plasma implantation prior to the formation of the dummy gate structure 1201.

[0078] like Figure 15As shown in cross-sectional view 1500, a heavily N-doped region 165A can be formed in the first region 153 adjacent to the front side 124, aligned with the dummy gate structure 1201, and a heavily P-doped region 127A can be formed in the second region 149 adjacent to the front side 124, aligned with the dummy gate structure 1201. They can be formed by two separate low-energy implantations using two separate masks. Figure 15 As further shown in cross-sectional view 1500, silicide pad 125A can be formed on heavily P-doped region 127A and heavily N-doped region 165A.

[0079] like Figure 16 As shown in cross-sectional view 1600, the dummy gate electrode 1203 can be replaced with a metal gate electrode 117 to form gate structures 114A and 115A. This illustrates a gate replacement process where the gate replacement is performed after annealing the previous implantation. By completing substrate doping and annealing before forming the metal gate electrode 117, undesirable interactions between the metal gate electrode 117 and the high-k gate dielectric 119 can be avoided.

[0080] like Figure 17 As shown in cross-sectional view 1700, metal plug 123 and metal interconnect structure 169 can be formed on front side 124. These structures can be formed by standard back-end process (BEOL) technology, which may include damascene or dual damascene processes.

[0081] like Figure 18 As shown in cross-sectional view 1800, the semiconductor body 159A can be thinned by removing material from the back side 138. Thinning can be achieved using any suitable process. This process can include one or more of wet etching, dry etching, and chemical mechanical polishing. The wafer including the semiconductor body 159A can be flipped for this process. The thinned surface can sometimes be leveled using methods such as spin coating. Thinning produces a pull-down diode 167A and a pull-up diode 133A, wherein the back side 138 has a heavily P-doped region 161A and a heavily N-doped region 135A. Silicide pads 156A and 137A can then be formed by reacting with the body 159A on the back side 138.

[0082] like Figure 19 As shown in the cross-sectional view 1900, a bottom metal interconnect structure 157 can then be formed on the back side 138. The bottom metal interconnect structure 157 can be formed using processes similar to those used to form the metal interconnect structure 169. A passivation layer, contact pads, solder balls, etc., can then be formed to provide a complete device, implanted... Figure 1 The device shown in cross-sectional view 100.

[0083] Figure 20Flowcharts of some embodiments of a method 2000 for forming an integrated circuit device having diodes according to this disclosure are provided. While method 2000 is shown and described herein as a series of steps or events, it should be understood that the order of these steps or events shown should not be construed as limiting. For example, some steps may occur in a different order and / or simultaneously with other actions or events besides those shown and / or described herein. Furthermore, it is not required that all shown steps be used to implement one or more aspects or embodiments described herein. Additionally, one or more of the steps described herein may be performed in one or more separate steps and / or stages.

[0084] Method 2000 can begin with action 2001, forming a P-well, and action 2003, forming an N-well. Figure 10 An example is provided. The processes for forming P-wells and N-wells can include one or more of plasma implantation, diffusion, or epitaxial growth, as well as providing some initial doping type to the semiconductor body.

[0085] Method 2000 can continue to Action 2005, forming an isolated region. These can be, for example... Figure 12 The STI region is shown. Other types of isolation regions, such as field oxides, can be used instead. The STI region can be formed before or after any doping operation in Method 2000.

[0086] Method 2000 can continue to Action 2007, forming as follows: Figure 14 The dummy gate structure is shown. In some embodiments, these may be polysilicon gates, metal gates, or dummy gates. In some embodiments, the diode is not gate-aligned, and this step is optional.

[0087] Method 2000 can continue to Action 2009, forming as follows: Figure 13 The deep P-trap shown, and action 2011, form as follows Figure 14 The deep N-wells are shown. These deep wells can be heavily doped regions, which are beneficial for back-side contacts. Heavily doped regions for back-side contacts can be formed or completely eliminated by other methods.

[0088] Action 2013 is to form an N-doped diffusion region, action 2015 is to form a P-doped diffusion region, and action 2017 is to... Figure 15 The entire area is silicided as shown. The diffusion region is a heavily doped region adjacent to the upper surface and can be gate-aligned. The silicide process can be a self-aligned silicide process for the gate structure.

[0089] Action 2019 involves high-temperature annealing of various injection processes. Action 2021 involves... Figure 16 The gate replacement process is shown. Action 2023 is as follows. Figure 17 As shown, a metal interconnect is formed on the front side.

[0090] Action 2025 is wafer flipping. Wafer flipping signifies the transition from processing applied to the front side 124 to processing applied to the back side 138. Wafer flipping may not be necessary, but typical wafer processing equipment is designed to operate on the top side of the wafer, thus allowing the use of a physical process to flip the wafer.

[0091] Action 2027 is like Figure 18 The wafer is thinned as shown. Action 2029 involves forming silicide on the back side, also as... Figure 18 As shown. Action 2031 is as follows. Figure 19 As shown, metal interconnects are formed on the back side. Action 2033 is a further process to complete the formation of the integrated circuit device.

[0092] Some aspects of this teaching relate to an integrated circuit device comprising a semiconductor body having a front side and a back side. A front metal structure is formed on the front side, and a back metal structure is formed on the back side. Within the semiconductor body is a PN diode having a PN junction, P-doped contacts, and N-doped contacts. The PN junction is formed by an interface between a P-doped region and an N-doped region of the semiconductor body. One of the P-doped and N-doped contacts is a front contact on the front side, and the other is a back contact on the back side. The front contact is coupled to the front metal structure. The back contact is coupled to the back metal structure.

[0093] Some aspects of this teaching relate to an integrated circuit device, including: a first metal interconnect and a second metal interconnect located on opposite sides of a semiconductor substrate; V SS Track and V DD The circuit includes a rail configured to supply power to the circuit; I / O terminals for the circuit; and ESD protection devices for the circuit. The ESD protection devices include a first PN diode and a second PN diode formed in a semiconductor substrate. The first PN diode is coupled to the I / O terminal via a first I / O terminal and via V... DD Rail coupling to couple to V DD The second PN diode is coupled to the I / O terminal through the second I / O terminal, and through V... SS Rail coupling to couple to V SS Rail. Both the first and second metal interconnects provide coupling only to the first I / O terminal and V. DD One of the rail couplings and only providing second I / O terminal coupling and V SS One type of track coupling.

[0094] Some aspects of this teaching relate to a method of providing an ESD protection device for an integrated circuit. The method includes: forming a PN diode in a semiconductor substrate having a front side and a back side; forming a first metal interconnect on the front side; and forming a second metal interconnect on the back side. The first metal interconnect is coupled to a first contact of the PN diode on the front side. The second metal interconnect is coupled to a second contact of the PN diode on the back side.

[0095] Embodiments of this application provide an integrated circuit device, including: a semiconductor body having a front side and a back side; a front metal structure formed on the front side; a back metal structure formed on the back side; and a PN diode including a PN junction, a first contact, and a second contact; wherein the PN junction is formed by an interface between a P-doped region of the semiconductor body and an N-doped region of the semiconductor body; one of the first contact and the second contact is a front contact on the front side, and the other of the first contact and the second contact is a back contact on the back side; the front contact is coupled to the front metal structure; and the back contact is coupled to the back metal structure. In some embodiments, both the first contact and the second contact have 10 19 / cm 3 Or a higher dopant concentration. In some embodiments, the back contact is siliconized and has a larger area than the front contact. In some embodiments, the PN junction extends and terminates below a spacer associated with a gate structure formed on the front side. In some embodiments, the PN diode further includes a second PN junction; and the first PN junction and the second PN junction are symmetrically disposed on opposite sides of the gate structure. In some embodiments, the back contact is doped with a semiconductor body concentration of 10. 19 / cm 3 Or a larger area is provided. In some embodiments, the back contact is provided by a heavily doped region of the semiconductor structure horizontally aligned with the edge of the gate structure formed on the front side; and the dopant concentration of the heavily doped region is 10. 19 / cm 3 Or higher. In some embodiments, the PN diode includes two heavily doped regions of the semiconductor on opposite sides of the gate structure formed on the semiconductor body; the two heavily doped regions have the same doping type; and the heavily doped regions are dopant concentrations of 10. 19 / cm 3Or a higher region. In some embodiments, the PN diode includes a heavily P-doped region and a heavily N-doped region on the opposite side of the gate structure formed on the semiconductor body; one of the heavily P-doped region and the heavily N-doped region provides the front contact; each of the heavily P-doped region and the heavily N-doped region has 10 19 / cm 3 Or a higher dopant concentration. In some embodiments, the second of the heavily P-doped region and the heavily N-doped region provides the back contact. In some embodiments, the PN diode includes two heavily doped regions of the semiconductor body on the opposite side of the shallow trench isolation region formed on the front side; the two heavily doped regions have the same doping type; and each of the two heavily doped regions has 10 19 / cm 3 Or a higher dopant concentration. In some embodiments, the back contact is made of a semiconductor body with a doping level of less than 10. 19 / cm 3 Partially provided.

[0096] Embodiments of this application provide an integrated circuit device, including: a first metal interconnect and a second metal interconnect, located on opposite sides of a semiconductor body; V SS Track and V DD A rail, configured to supply power to the circuit; I / O terminals for the circuit; ESD protection devices for the circuit, including: a first PN diode and a second PN diode, formed in the semiconductor body; wherein the first PN diode is coupled to the I / O terminal through a first I / O terminal, and through V DD Rail coupling to couple to the V DD Rail; the second PN diode is coupled to the I / O terminal through the second I / O terminal, and through V SS Rail coupling to couple to the V SS Rail; both the first metal interconnect and the second metal interconnect provide coupling only to the first I / O terminal and the V DD One of the rail couplings; and both the first metal interconnect and the second metal interconnect provide only the second I / O terminal coupling and the V SS One type of rail coupling. In some embodiments, the first PN diode includes a first PN junction formed by a heavily P-doped region and an N-doped region of the semiconductor body; the second PN diode includes a second PN junction formed by a heavily N-doped region and a P-doped region of the semiconductor body; and the heavily P-doped region and the heavily N-doped region have a 10... 19 / cm3 Or a higher dopant concentration. In some embodiments, the first PN diode includes a first PN junction that extends and terminates below a spacer associated with the first gate structure; and the second PN diode includes a second PN junction that extends and terminates below a spacer associated with the second gate structure.

[0097] Embodiments of this application provide a method for manufacturing an integrated circuit device, the method comprising: forming a PN diode in a semiconductor substrate having a front side and a back side; forming a first metal interconnect on the front side, wherein the first metal interconnect is coupled to a first contact of the PN diode located on the front side; and forming a second metal interconnect on the back side, wherein the second metal interconnect is coupled to a second contact of the PN diode located on the back side. In some embodiments, the method further comprises: thinning the semiconductor substrate after forming the PN diode but before forming the second metal interconnect. In some embodiments, the method further comprises: implanting a dopant into the substrate through the front side to form a dopant concentration of 10 in the semiconductor substrate. 19 / cm 3 Or higher, and provide a heavily doped region for the second contact. In some embodiments, a gate structure on the front side provides a mask for injecting the dopant into the substrate. In some embodiments, dopant injection includes irradiating the front side with high-energy injection and obtaining a well located near the second metal interconnect structure and far from the first metal interconnect structure.

[0098] The foregoing has described components of several embodiments, enabling those skilled in the art to better understand the various embodiments of the present invention. Those skilled in the art should understand that other processes and structures can be readily designed or modified based on the present invention to achieve the same objectives and / or realize the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made therein without departing from the spirit and scope of this disclosure.

Claims

1. An integrated circuit device, comprising: The semiconductor body has a front side and a back side; A front metal structure is formed on the front side; A back metal structure is formed on the back side; as well as A PN diode includes a first PN junction, a first contact, and a second contact. The first PN junction is formed by the interface between the heavily P-doped region of the semiconductor body and the N-doped region of the semiconductor body. One of the first contact and the second contact is a front contact on the front side, and the other of the first contact and the second contact is a back contact on the back side. The front contact element is coupled to the front metal structure; and The back contact is coupled to the back metal structure, and the back contact is siliconized and has a larger area than the front contact.

2. The integrated circuit device according to claim 1, wherein, Both the first contact and the second contact have 10 19 / cm 3 Or a higher dopant concentration.

3. The integrated circuit device according to claim 1, wherein, The thickness of the semiconductor substrate is 5 μm or less.

4. The integrated circuit device according to claim 1, wherein, The first PN junction extends and terminates below a spacer associated with the gate structure formed on the front side.

5. The integrated circuit device according to claim 4, wherein: The PN diode further includes a second PN junction; and The first PN junction and the second PN junction are symmetrically disposed on opposite sides of the gate structure.

6. The integrated circuit device according to claim 1, wherein, The back contact is made of semiconductor body with a doping concentration of 10. 19 / cm 3 Or available in a larger area.

7. The integrated circuit device according to claim 1, wherein: The back contact is provided by a heavily doped region of the semiconductor structure that is horizontally aligned with the edge of the gate structure formed on the front side; and The dopant concentration in the heavily doped region is 10. 19 / cm 3 Or higher.

8. The integrated circuit device according to claim 1, wherein: The PN diode includes two heavily doped regions of the semiconductor on the opposite side of the gate structure formed on the semiconductor body; The two heavily doped regions have the same doping type; and The heavily doped region is where the dopant concentration is 10. 19 / cm 3 Or a higher region.

9. The integrated circuit device according to claim 1, wherein: The PN diode includes a heavily P-doped region and a heavily N-doped region on the opposite side of the gate structure formed on the semiconductor body. One of the heavily P-doped region and the heavily N-doped region provides the front contact; Each of the heavily P-doped regions and the heavily N-doped regions has 10 19 / cm 3 Or a higher dopant concentration.

10. The integrated circuit device according to claim 9, wherein, The second of the heavily P-doped region and the heavily N-doped region provides the back contact.

11. The integrated circuit device according to claim 1, wherein: The PN diode includes two heavily doped regions of the semiconductor body on the opposite side of the shallow trench isolation region formed on the front side; The two heavily doped regions have the same doping type; and Each of the two heavily doped regions has 10 19 / cm 3 Or a higher dopant concentration.

12. The integrated circuit device according to claim 1, wherein, The back contact is made of semiconductor body with a doping level of less than 10. 19 / cm 3 Partially provided.

13. An integrated circuit device, comprising: The first metal interconnect and the second metal interconnect are located on opposite sides of the semiconductor body; V SS track and V DD The rail is configured to supply power to the circuit. I / O terminals are used in the circuit. ESD protection device for the circuit, comprising: A first PN diode and a second PN diode are formed in the semiconductor body, wherein each of the first PN diode and the second PN diode includes a PN junction, a front contact and a back contact, and the PN junction is formed by an interface between a P-doped region and an N-doped region of the semiconductor body. The first PN diode is coupled to the I / O terminal via the front contact of the first PN diode through the first I / O terminal, and is coupled to the I / O terminal via the back contact of the first PN diode through V DD Rail coupling to couple to the V DD rail; The second PN diode is coupled to the I / O terminal via the front contact of the second PN diode through the second I / O terminal, and is coupled to the I / O terminal via the back contact of the second PN diode through V SS Rail coupling to couple to the V SS The back contact of at least one of the first PN diode or the second PN diode is siliconized and has a larger area than the corresponding front contact. Both the first metal interconnect and the second metal interconnect provide coupling only to the first I / O terminal and the V DD One of the orbital couplings; and Both the first metal interconnect and the second metal interconnect provide only the second I / O terminal coupling and the V SS One type of track coupling.

14. The integrated circuit device according to claim 13, wherein: The first PN diode includes a first PN junction, which is formed by a heavily P-doped region of the semiconductor body and an N-doped region of the semiconductor body; The second PN diode includes a second PN junction, which is formed by a heavily N-doped region of the semiconductor body and a P-doped region of the semiconductor body; and The heavily P-doped region and the heavily N-doped region have 10 19 / cm 3 Or a higher dopant concentration.

15. The integrated circuit device according to claim 13, wherein: The first PN diode includes a first PN junction that extends and terminates below a spacer associated with the first gate structure; and The second PN diode includes a second PN junction that extends and terminates below a spacer associated with the second gate structure.

16. A method for manufacturing an integrated circuit device, the method comprising: A PN diode is formed in a semiconductor substrate having a front side and a back side. The PN diode includes a PN junction, a first contact, and a second contact. The PN junction is formed by an interface between a P-doped region of the semiconductor substrate and an N-doped region of the semiconductor substrate. A first metal interconnect is formed on the front side, wherein the first metal interconnect is coupled to the first contact of the PN diode located on the front side; and A second metal interconnect is formed on the back side, wherein the second metal interconnect is coupled to a second contact of the PN diode located on the back side, the second contact being siliconized and having a larger area than the first contact.

17. The method of claim 16, further comprising: The semiconductor substrate is thinned after the PN diode is formed but before the second metal interconnect is formed.

18. The method of claim 16, further comprising: The dopant concentration for forming the semiconductor substrate by injecting dopant into the substrate via the front side is 10. 19 / cm 3 Or higher, and provide a heavily doped region for the second contact.

19. The method of claim 16, wherein, The gate structure located on the front side provides a mask for injecting dopants into the substrate.

20. The method according to claim 18, wherein, The dopant injection includes: irradiating the front side with high-energy injection and obtaining a well located near the second metal interconnect and far from the first metal interconnect.

Images