Nanosheet field effect transistor devices and methods of forming the same

Abstract

This application relates to nanosheet field effect transistor devices and methods of forming the same. A semiconductor device includes a fin protruding above a substrate, source / drain regions located above the fin, nanosheets located between the source / drain regions, and a gate structure located above the fin and between the source / drain regions, the gate structure including a gate dielectric material located around each of the nanosheets, a work function material located around the gate dielectric material, a liner material located around the work function material, wherein the liner material has a non-uniform thickness and is thicker at a first location between the nanosheets than at a second location along a sidewall of the nanosheet, and a gate electrode material located around at least some portions of the liner material.

Description

Technical Field

[0001] This disclosure generally relates to nanosheet field-effect transistor devices and methods for forming the same. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and using photolithography to pattern the various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continuously improves the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that need to be addressed. Summary of the Invention

[0004] According to one aspect of the present invention, a semiconductor device is provided, comprising: a fin protruding above a substrate; source / drain regions located above the fin; nanosheets located between the source / drain regions; and a gate structure located above the fin and between the source / drain regions, the gate structure comprising: a gate dielectric material located around each nanosheet in the nanosheets; a work function material located around the gate dielectric material; a liner material located around the work function material, wherein the liner material has a non-uniform thickness and is thicker at a first location between the nanosheets than at a second location along the sidewalls of the nanosheets; and a gate electrode material located around at least some portions of the liner material.

[0005] According to another aspect of the present invention, a semiconductor device is provided, comprising: a fin protruding above a substrate; a gate structure located above the fin; a source / drain region located above the fin and on opposite sides of the gate structure; and a first channel layer and a second channel layer disposed between the source / drain regions and above the fin, wherein the first channel layer is located between the second channel layer and the fin, wherein the gate structure comprises: a gate dielectric material located around the first channel layer and around the second channel layer; a work function material located around the gate dielectric material; a liner material located around the work function material, wherein the liner material has a first thickness above the upper surface of the second channel layer away from the fin and a second thickness between the first channel layer and the second channel layer, wherein the first thickness is less than the second thickness; and a gate electrode. Attached Figure Description

[0006] The various aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the features may be arbitrarily enlarged or reduced.

[0007] Figure 1 An example of a nanosheet field-effect transistor (NSFET) device according to some embodiments is shown in a three-dimensional view.

[0008] Figure 2 , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figures 5A-5C , Figures 6A-6C , Figures 7A-7C , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figures 11-14 , Figure 15A and Figure 15B This is a cross-sectional view of a nanosheet field-effect transistor device at different stages of manufacturing according to one embodiment.

[0009] Figure 16 , Figure 17 , Figure 18A and Figure 18B This is a cross-sectional view of a nanosheet field-effect transistor device at various stages of manufacturing according to another embodiment.

[0010] Figure 19 This is a flowchart of a method for forming a semiconductor device in some embodiments. Detailed Implementation

[0011] The following disclosure provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature on or over a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact.

[0012] Furthermore, spatially related terms (e.g., "below," "below," "lower than," "higher than," "upper," etc.) may be used herein to readily describe the relationship of one element or feature shown in the figures relative to another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device in use or operation other than those shown in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein may be interpreted accordingly. Throughout the discussion herein, unless otherwise stated, the same reference numerals in different figures denote the same or similar components formed by the same or similar forming methods and using one or more of the same or similar materials. Furthermore, figures with the same reference numerals but different letters (e.g., Figure 5A , Figure 5B and Figure 5C (This shows different views of a semiconductor device at the same processing stage.)

[0013] According to some embodiments, a liner material is formed around the work function material of the nanosheet device. The liner material surrounds the work function material located around each nanosheet within the nanosheet, and prevents the work function material between adjacent nanosheets from coalescing and forming a thicker work function material than at other locations. Since a work function material with non-uniform thickness can lead to a decrease in the threshold voltage V of the formed device... TH The disclosed method avoids or reduces threshold voltage variations caused by non-uniform thickness of the work function material, thereby improving the performance of the formed device. Furthermore, the liner material prevents or reduces aluminum diffusion from the work function material to other layers.

[0014] Figure 1 An example of a nanosheet field-effect transistor (NSFET) device according to some embodiments is shown in a three-dimensional view. The NSFET device includes a semiconductor fin 90 (also referred to as a fin) protruding above a substrate 50. A gate electrode 122 (e.g., a metal gate) is disposed on the fin, and source / drain regions 112 are formed on opposite sides of the gate electrode 122. A plurality of nanosheets 54 are formed on the fin 90 and between the source / drain regions 112. An isolation region 96 is formed on opposite sides of the fin 90. A gate layer stack 120 (which may include, for example, a gate dielectric material, a work function material) is formed around the nanosheets 54. The gate electrode 122 is located on and around the gate layer stack 120.

[0015] Figure 1Reference cross sections used in the following figures are also shown. Cross section AA is along the longitudinal axis of the gate electrode 122 and in a direction, for example, perpendicular to the current flow direction between the source / drain regions 112 of the NSFET device. Cross section BB is perpendicular to cross section AA and along the longitudinal axis of the fin and in the direction of current flow between the source / drain regions 112 of the NSFET device. Cross section CC is parallel to cross section BB and is located between two adjacent fins. Cross section DD is parallel to cross section AA and extends through the source / drain regions 112 of the NSFET device. For clarity, the following figures refer to these reference cross sections.

[0016] Figure 2 , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figures 5A-5C , Figures 6A-6C , Figures 7A-7C , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figures 11-14 , Figure 15A and Figure 15B This is a cross-sectional view of a nanosheet field-effect transistor (NSFET) device 100 at various stages of manufacturing according to one embodiment.

[0017] exist Figure 2 A substrate 50 is provided. The substrate 50 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which can be doped (e.g., doped with p-type or n-type dopant) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide box layer, a silicon oxide layer, etc. The insulating layer is disposed on the substrate (typically a silicon substrate or a glass substrate). Other substrates, such as multilayer substrates or gradient substrates, can also be used. In some embodiments, the semiconductor material of the substrate 50 can include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0018] A multilayer stack 64 is formed on the substrate 50. The multilayer stack 64 includes alternating layers of first semiconductor material 52 and second semiconductor material 54. Figure 2 In this design, the layers formed of the first semiconductor material 52 are labeled 52A, 52B, and 52C, and the layers formed of the second semiconductor material 54 are labeled 54A, 54B, and 54C. Figure 2 The number of layers formed by the first and second semiconductor materials shown is merely a non-limiting example. Other numbers of layers are also possible and are fully intended to be included within the scope of this disclosure.

[0019] In some embodiments, the first semiconductor material 52 is an epitaxial material suitable for forming, for example, the channel region of a p-type FET, such as silicon germanium (Si). x Ge 1-x (where x can be in the range of 0 to 1), and the second semiconductor material 54 is an epitaxial material suitable for forming, for example, the channel region of an n-type FET, such as silicon. The multilayer stack 64 (also referred to as an epitaxial material stack) will be patterned to form the channel region of the NSFET in a subsequent process. Specifically, the multilayer stack 64 will be patterned to form horizontal nanosheets, and the resulting NSFET channel region comprises multiple horizontal nanosheets.

[0020] The multilayer stack 64 can be formed by an epitaxial growth process performed in a growth chamber. In one embodiment, during the epitaxial growth process, the growth chamber is cyclically exposed to a first set of precursors for selectively growing a first semiconductor material 52 and then to a second set of precursors for selectively growing a second semiconductor material 54. In some embodiments, the first set of precursors includes a precursor for the first semiconductor material (e.g., silicon-germanium), and the second set of precursors includes a precursor for the second semiconductor material (e.g., silicon). In some embodiments, the first set of precursors includes a silicon precursor (e.g., silane) and a germanium precursor (e.g., germanane), and the second set of precursors includes a silicon precursor but omits the germanium precursor. Thus, the epitaxial growth process can include continuously allowing silicon precursors to flow into the growth chamber and then cyclically: (1) allowing germanium precursors to flow into the growth chamber when growing the first semiconductor material 52; and (2) preventing germanium precursors from flowing into the growth chamber when growing the second semiconductor material 54. The cyclic exposure can be repeated until a target number of layers are formed.

[0021] Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figures 5A-5C , Figures 6A-6C , Figures 7A-7C , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figures 11-14 , Figure 15A and Figure 15B This is a cross-sectional view of an NSFET device 100 in a later stage of manufacturing according to one embodiment. Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A and Figure 15A It is along Figure 1 The cross-sectional view of section BB in the diagram. Figure 3B , Figure 4B , Figure 5C , Figure 6C , Figure 7C , Figure 8B , Figure 9B , Figure 10B and Figure 15B It is along Figure 1 The cross-sectional view of section AA in the diagram. Figure 5B , Figure 6B and Figure 7B It is along Figure 1 The cross-sectional view of section DD in the diagram. Figures 11-14 It is an NSFET device along Figure 1 The figure shows a cross-sectional view of section AA. Although two fins and two gate structures are shown in the figure as a non-limiting example, it should be understood that other numbers of fins and other numbers of gate structures may also be formed.

[0022] exist Figure 3A and Figure 3B In the substrate 50, the fin structure 91 is formed to protrude above the substrate 50. Each fin structure 91 includes a semiconductor fin 90 and a nanostructure 92 covering the semiconductor fin 90. The nanostructure 92 and the semiconductor fin 90 can be formed by etching trenches in the multilayer stack 64 and the substrate 50, respectively.

[0023] The fin structure 91 can be patterned using any suitable method. For example, one or more photolithography processes (including dual-patterning or multi-patterning processes) can be used to pattern the fin structure 91. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with, for example, a spacing smaller than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. A spacer is formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacer can then be used to pattern, for example, the fin structure 91.

[0024] In some embodiments, the remaining spacers are used to pattern the mask 94, which is then used to pattern the fin structure 91. The mask 94 can be a single-layer mask or a multi-layer mask, such as a multi-layer mask including a first mask layer 94A and a second mask layer 94B. The first mask layer 94A and the second mask layer 94B can each be formed of a dielectric material such as silicon oxide, silicon nitride, or combinations thereof, and can be deposited or thermally grown according to suitable techniques. The first mask layer 94A and the second mask layer 94B are different materials with high etch selectivity. For example, the first mask layer 94A can be silicon oxide, and the second mask layer 94B can be silicon nitride. The mask 94 can be formed by patterning the first mask layer 94A and the second mask layer 94B using any acceptable etch process. The mask 94 can then be used as an etch mask to etch the substrate 50 and the multilayer stack 64. The etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or a combination thereof. In some embodiments, the etching is an anisotropic etching process. Following this etching process, a patterned multilayer stack 64 forms a nanostructure 92, and a patterned substrate 50 forms semiconductor fins 90, such as... Figure 3A and Figure 3B As shown. Therefore, in the illustrated embodiment, the nanostructure 92 further includes alternating layers of a first semiconductor material 52 and a second semiconductor material 54, and the semiconductor fin 90 is formed of the same material as the substrate 50 (e.g., silicon).

[0025] Next, in Figure 4A and Figure 4B In this embodiment, a shallow trench isolation (STI) region 96 is formed on the substrate 50 and on the opposite side of the fin structure 91. As an example of forming the STI region 96, an insulating material can be formed on the substrate 50. The insulating material can be an oxide (e.g., silicon oxide), a nitride, or a combination thereof, and can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system followed by post-curing to transform it into another material, such as an oxide), or a combination thereof. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. After forming the insulating material, an annealing process can be performed.

[0026] In one embodiment, the insulating material is formed such that excess insulating material covers the fin structure 91. In some embodiments, a liner is first formed along the surfaces of the substrate 50 and the fin structure 91, and a filler material such as that discussed above is formed on the liner. In some embodiments, the liner is omitted.

[0027] Next, a removal process is applied to the insulating material to remove excess insulating material above the fin structure 91. In some embodiments, planarization processes, such as chemical mechanical polishing (CMP), etching back processes, or combinations thereof, can be used. The planarization process exposes the nanostructure 92 such that, after the planarization process is completed, the top surfaces of the nanostructure 92 and the insulating material are flush. Next, the insulating material is recessed to form STI regions 96. The insulating material is recessed such that the nanostructure 92 protrudes between adjacent STI regions 96. The top of the semiconductor fin 90 may also protrude between adjacent STI regions 96. Furthermore, the top surface of the STI region 96 may have a flat surface, a convex surface, a concave surface (e.g., recessed), or a combination thereof, as shown. The top surface of the STI region 96 can be formed as flat, convex, and / or concave by appropriate etching. The STI region 96 can be recessed using an acceptable etching process, such as an etching process selective for the material of the insulating material (e.g., etching the material of the insulating material at a faster rate than etching the materials of the semiconductor fin 90 and the nanostructure 92). For example, chemical oxide removal can be performed using a suitable etchant (e.g., dilute hydrofluoric acid (dHF)).

[0028] Still referencing Figure 4A and Figure 4B A dummy dielectric layer 97 is formed on the nanostructure 92 and the STI region 96. For example, the dummy dielectric layer 97 may be silicon oxide, silicon nitride, a combination thereof, etc., and may be deposited or thermally grown according to acceptable techniques. In one embodiment, a silicon layer is conformally formed on the nanostructure 92 and the upper surface of the STI region 96, and a thermal oxidation process is performed to convert the deposited silicon layer into an oxide layer as the dummy dielectric layer 97.

[0029] Next, in Figures 5A-5CIn this process, a dummy gate 102 is formed above the fin 90 and the nanostructure 92. To form the dummy gate 102, a dummy gate layer can be formed above the dummy dielectric layer 97. The dummy gate layer can be deposited on the dummy dielectric layer 97 and then planarized (e.g., by CMP). The dummy gate layer can be a conductive material and can be selected from the group consisting of amorphous silicon, polysilicon, poly-SiGe, etc. The dummy gate layer can be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques known and used in the art. The dummy gate layer can be made of other materials that have high etch selectivity for the isolation region 96.

[0030] A mask 104 is then formed over the dummy gate layer. The mask 104 can be formed of silicon nitride, silicon oxynitride, combinations thereof, etc., and can be patterned using acceptable photolithography and etching techniques. In the illustrated embodiment, the mask 104 includes a first mask layer 104A (e.g., a silicon oxide layer) and a second mask layer 104B (e.g., a silicon nitride layer). The pattern of the mask 104 is then transferred to the dummy gate layer using an acceptable etching technique to form a dummy gate 102, and then transferred to a dummy dielectric layer using an acceptable etching technique to form a dummy gate dielectric 97. The dummy gate 102 covers the corresponding channel region of the nanostructure 92. The pattern of the mask 104 can be used to physically separate each dummy gate 102 from adjacent dummy gates. The length direction of the dummy gate 102 can also be substantially perpendicular to the length direction of the fin 90. In some embodiments, the dummy gate 102 and the dummy gate dielectric 97 are collectively referred to as the dummy gate structure.

[0031] Next, a gate spacer layer 108 is formed by conformally depositing an insulating material over the nanostructure 92, the STI region 96, and the dummy gate 102. The insulating material may be silicon nitride, silicon carbonitride, a combination thereof, etc. In some embodiments, the gate spacer layer 108 includes a plurality of sublayers. For example, a first sublayer (sometimes referred to as a gate sealing spacer layer) may be formed by thermal oxidation or deposition, and a second sublayer (sometimes referred to as a main gate spacer layer) may be conformally deposited on the first sublayer.

[0032] Figure 5B and Figure 5C It shows Figure 5A A cross-sectional view of the NSFET device 100, but along... Figure 5A Sections EE and FF in the diagram. Sections EE and FF correspond to... Figure 1 Sections DD and AA in the diagram.

[0033] Next, in Figures 6A-6C In this process, the gate spacer layer 108 is etched using an anisotropic etching process to form the gate spacer 108. The anisotropic etching process can remove the horizontal portion of the gate spacer layer 108 (e.g., the portion above the STI region 96 and the dummy gate 102), and the remaining vertical portion of the gate spacer layer 108 (e.g., along the sidewalls of the dummy gate 102 and the dummy gate dielectric 97) forms the gate spacer 108.

[0034] Figure 6B and Figure 6C It shows Figure 6A A cross-sectional view of the NSFET device 100, but along sections EE and FF respectively. Figure 6B In this embodiment, a portion of the gate spacer layer 108 is shown on the upper surface of the STI region 96 between adjacent fins. Because the small distance between adjacent fins reduces the efficiency of the anisotropic etching process described above, the anisotropic etching process may not completely remove the gate spacer layer 108 disposed between adjacent fins, so these portions of the gate spacer layer 108 can be retained. In other embodiments, the portions of the gate spacer layer 108 disposed on the upper surface of the STI region 96 between adjacent fins are completely removed by anisotropic etching.

[0035] After forming the gate spacer 108, implantation can be performed into the lightly doped source / drain (LDD) region (not shown). An appropriate type of impurity (e.g., p-type or n-type) can be implanted into the exposed nanostructure 92 and / or semiconductor fin 90. The n-type impurity can be any suitable n-type impurity, such as phosphorus, arsenic, antimony, etc., and the p-type impurity can be any suitable p-type impurity, such as boron, BF2, indium, etc. The lightly doped source / drain region can have approximately 10-1... 15 cm -3 To about 10 16 cm -3 The concentration of impurities. Annealing can be used to activate the injected impurities.

[0036] Next, an opening 110 (also referred to as a recess) is formed in the nanostructure 92. The opening 110 may extend through the nanostructure 92 and into the semiconductor fin 90. The opening 110 may be formed by any acceptable etching technique, such as using a dummy gate 102 as an etching mask.

[0037] After forming the opening 110, a selective etching process is performed to recess the end of the first semiconductor material 52 exposed by the opening 110, without substantially etching the second semiconductor material 54. After the selective etching process, a recess is formed in the first semiconductor material 52 at the location where the removed end once stood.

[0038] Next, an internal spacer layer is formed in the opening 110 (e.g., conformally). The internal spacer layer also fills the recesses in the first semiconductor material 52 formed by the previous selective etching process. The internal spacer layer can be a suitable dielectric material formed by a suitable deposition method (e.g., PVD, CVD, ALD, etc.), such as silicon carbonitride (SiCN), silicon carbonitride oxynitride (SiOCN), etc. Next, an etching process, such as an anisotropic etching process, is performed to remove the portion of the internal spacer layer disposed outside the recesses in the first semiconductor material 52. The remaining portion of the internal spacer layer (e.g., the portion disposed inside the recesses in the first semiconductor material 52) forms the internal spacer 55. Figure 6B and Figure 6C It shows Figure 6A A cross-sectional view of the NSFET device 100, but along... Figure 6A The cross sections EE and FF in the diagram.

[0039] Next, in Figures 7A-7C In the illustrated embodiment, a source / drain region 112 is formed in the opening 110. In this embodiment, the source / drain region 112 is formed of one or more epitaxial materials and is therefore also referred to as an epitaxial source / drain region 112. In some embodiments, the epitaxial source / drain region 112 is formed in the opening 110 to apply stress to the respective channel region of the formed NSFET device, thereby improving performance. The epitaxial source / drain regions 112 are formed such that each dummy gate 102 is disposed between corresponding adjacent epitaxial source / drain regions 112. In some embodiments, a gate spacer 108 is used to separate the epitaxial source / drain regions 112 from the dummy gate 102 by an appropriate lateral distance such that the epitaxial source / drain regions 112 do not short-circuit the gate of the subsequently formed NSFET device.

[0040] Epitaxial source / drain regions 112 are epitaxially grown in openings 110. Epitaxial source / drain regions 112 can include any acceptable material, such as materials suitable for n-type or p-type devices. For example, when forming an n-type device, epitaxial source / drain regions 112 can include materials that apply tensile strain to the channel region, such as silicon, SiC, SiCP, SiP, etc. Similarly, when forming a p-type device, epitaxial source / drain regions 112 can include materials that apply compressive strain to the channel region, such as SiGe, SiGeB, Ge, GeSn, etc. Epitaxial source / drain regions 112 can have surfaces protruding from the surface of the corresponding fins and can have facets.

[0041] The epitaxial source / drain regions 112 and / or fins can be implanted with dopants to form source / drain regions, similar to the previously discussed process for forming lightly doped source / drain regions, followed by annealing. The impurity concentration of the source / drain regions can be around 10. 19 cm -3 To about 10 21 cm -3 Between. The n-type and / or p-type impurities used for the source / drain regions can be any impurities discussed previously. In some embodiments, the epitaxial source / drain regions 112 can be doped in situ during growth.

[0042] As a result of the epitaxial process used to form the epitaxial source / drain regions 112, the upper surface of the epitaxial source / drain regions 112 has facets that extend laterally outward beyond the sidewalls of the fin 90. In the illustrated embodiment, after the epitaxial process is completed, adjacent epitaxial source / drain regions 112 remain separated (see [reference]). Figure 7B In other embodiments, these small planes cause adjacent epitaxial source / drain regions 112 of the same NSFET to merge.

[0043] Next, a contact etch stop layer (CESL) 116 is formed over the source / drain region 112 and the dummy gate 102 (e.g., conformally), and then a first inter-layer dielectric (ILD) 114 is deposited over the CESL 116. The CESL 116 is formed of a material having a different etch rate than the first ILD 114, and can be formed from silicon nitride using PECVD, but alternatively other dielectric materials such as silicon oxide, silicon oxynitride, combinations thereof, etc., and alternative techniques for forming the CESL 116, such as low-pressure CVD (LPCVD), PVD, etc., can be used.

[0044] The first ILD 114 can be formed of a dielectric material and can be deposited by any suitable method (e.g., CVD, plasma-enhanced CVD (PECVD), or FCVD). The dielectric material used for the first ILD 114 can include silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process can be used. Figure 7B and Figure 7C It shows Figure 7A A cross-sectional view of the NSFET device 100, but along... Figure 7AThe cross sections EE and FF in the diagram.

[0045] Next, in Figure 8A and Figure 8B In this process, the dummy gate 102 is removed. To remove the dummy gate 102, a planarization process such as CMP is performed to make the top surfaces of the first ILD 114 and CESL 116 flush with the top surfaces of the dummy gate 102 and the gate spacer 108. This planarization process also removes the mask 104 on the dummy gate 102 (see [link to documentation]). Figure 7A The dummy gate 102, the gate spacer 108, and the top surfaces of the first ILD layer 114 are flush after the planarization process. Therefore, the top surface of the dummy gate 102 is exposed through the first ILD 114.

[0046] Next, the dummy gate 102 is removed in one or more etching steps to form a recess 103. In some embodiments, the dummy gate 102 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using one or more reactive gases that selectively etch the dummy gate 102 without etching the first ILD 114 or the gate spacer 108. Each recess 103 exposes a channel region of the NSFET. Each channel region is disposed between adjacent pairs of epitaxial source / drain regions 112. During the removal of the dummy gate 102, the dummy gate dielectric 97 may be used as an etch stop layer when etching the dummy gate 102. The dummy gate dielectric 97 may then be removed after the removal of the dummy gate 102. Figure 8B It shows Figure 8A A cross-sectional view of the NSFET device 100, but along section FF.

[0047] Next, in Figure 9A and Figure 9B In the process, the dummy gate dielectric 97 in the recess 103 is removed. An etching process, such as an isotropic etching process, can be performed to remove the dummy gate dielectric 97. In one embodiment, an isotropic etching process using an etching gas comprising HF and NH3 is performed to remove the dummy gate dielectric 97.

[0048] Next, in Figure 10A and Figure 10B In the process, the first semiconductor material 52 is removed to release the second semiconductor material 54. After removing the first semiconductor material 52, the second semiconductor material 54 forms a plurality of horizontally extending (e.g., parallel to the main upper surface of the substrate 50) nanosheets 54. The nanosheets 54 may be collectively referred to as the channel region 93 or channel layer 93 of the formed NSFET device 100. Figure 10AAs shown, gaps 53 (e.g., empty spaces) are formed between nanosheets 54 by removing the first semiconductor material 52.

[0049] In some embodiments, the first semiconductor material 52 is removed by a selective etching process using an etchant that is selective to the first semiconductor material 52 (e.g., has a higher etching rate), such that the first semiconductor material 52 is removed without substantially corroding the second semiconductor material 54. In one embodiment, an isotropic etching process is performed to remove the first semiconductor material 52. The isotropic etching process can be performed using an etching gas (and optionally a carrier gas), wherein the etching gas includes F2 and HF, and the carrier gas can be an inert gas such as Ar, He, N2, or combinations thereof.

[0050] Figure 10A A cross-sectional view of the NSFET device 100 along the longitudinal axis of the fin (e.g., along the direction of current flow in the fin) is shown, and Figure 10B A cross-sectional view of the NSFET device 100 along section FF is shown. Section FF is a cross-section along a direction perpendicular to the longitudinal axis of the fin and passing through the middle portion of the nanosheet 54.

[0051] Figures 11-13 A gate layer stack 120 for forming around the nanosheet 54 and along the sidewalls of the recess 103 is shown (see example). Figure 15A and Figure 15B The subsequent processing steps, in the illustrated embodiment, involve a gate layer stack 120 comprising an interface dielectric material 121, a gate dielectric material 123, a work function material 125, and a liner material 129. For simplicity, Figures 11-13 The NSFET device 100 is shown in Figure 10B A cross-sectional view of part of region 56.

[0052] Next, refer to Figure 11 Interfacial dielectric material 121 and gate dielectric material 123 are successively formed around each nanosheet 54. Although in Figures 11-13 Not shown in (but in Figure 15B (As shown in the diagram), different constituent materials of the gate layer stack 120 are also formed on the exposed surface of the fin 90 and the upper surface of the STI region 96, such as... Figure 15B As shown in the image.

[0053] The interface dielectric material 121 is a suitable dielectric material, such as silicon oxide formed by a suitable method (e.g., CVD, PVD, ALD, thermal oxidation, etc.). In one embodiment, the interface dielectric material 121 is formed by converting the outer portion of the nanosheet 54 (e.g., silicon) into an oxide (e.g., silicon oxide) through a thermal oxidation process. As an example, the thickness of the interface dielectric material 121 is between about 5 angstroms and about 20 angstroms.

[0054] Next, a gate dielectric material 123 (e.g., conformally) is formed around the nanosheet 54 and around the interface dielectric material 121. According to some embodiments, the gate dielectric material 123 comprises silicon oxide, silicon nitride, or a multilayer thereof. In some embodiments, the gate dielectric material 123 comprises a high-k dielectric material, and in these embodiments, the gate dielectric material 123 may have a k value greater than about 7.0, and may comprise metal oxides or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, or combinations thereof. Methods for forming the gate dielectric material 123 may include molecular beam deposition (MBD), ALD, PECVD, etc. As an example, the thickness of the gate dielectric material may be between about 5 angstroms and about 35 angstroms.

[0055] Next, in Figure 12 In this configuration, work function material 125 is formed around nanosheet 54 and gate dielectric material 123. Exemplary p-type work function materials (also referred to as p-type work function metals) include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or combinations thereof. Exemplary n-type work function materials (also referred to as n-type work function metals) include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof. The work function value is related to the material composition of the work function material, and therefore, the work function material is selected to adjust its work function value, thereby achieving the target threshold voltage V in the device to be formed. THOne or more work function materials can be deposited using ALD, CVD, physical vapor deposition (PVD), and / or other suitable processes. In one embodiment, the NSFET device 100 is an n-type device, and the work function material 125 is titanium aluminum (TiAl) formed by ALD. In some embodiments, the thickness of the work function material 125 is between about 10 angstroms and about 40 angstroms. If the thickness of the work function material 125 is too small (e.g., less than about 10 angstroms), the work function material 125 may not form a continuous film (e.g., it may have pinholes), and the aluminum in the work function material 125 (e.g., TiAl) may not be sufficient to adjust the work function of the work function material 125. If the thickness of the work function material 125 is too large (e.g., greater than about 40 angstroms), the work function material 125 may occupy too much space and may be difficult to form other layers between adjacent nanosheets 54.

[0056] Next, in Figure 13 In this embodiment, a liner material 129 (e.g., conformally) is formed around the nanosheet 54 and the work function material 125. In the illustrated embodiment, the liner material 129 is formed of a material capable of preventing or reducing the diffusion of aluminum from the work function material 125 (e.g., TiAl) to other layers of the NSFET device 100. As an example, the liner material 129 may be formed of alumina, silicon oxide, or silicon. Any suitable formation method (e.g., ALD, PVD, CVD, etc.) may be used to form the liner material 129. In some embodiments, the thickness of the liner material 129 is between about 5 angstroms and about 30 angstroms. The lower limit of the thickness range of the liner material 129 disclosed above ensures the formation of a continuous layer without pinholes, and the upper limit of the range disclosed above can be determined by design constraints, such as the space remaining between adjacent nanosheets 54. In the discussion herein, the interface dielectric material 121, the gate dielectric material 123, the work function material 125, and the liner material 129 are collectively referred to as the gate layer stack 120.

[0057] In one embodiment, the lining material 129 is alumina. Any suitable formation method can be used to form alumina. For example, an ALD process using trimethylaluminum (e.g., Al2(CH3)6, also known as TMA) as a first precursor (e.g., an aluminum-containing precursor) and H2O as a second precursor (e.g., an oxygen-containing precursor) can be performed to form the lining material 129. The chemical reaction between the first and second precursors can be described by the following chemical equation:

[0058] Al2(CH3)6 + H2O → AlO + CH3 + CH4

[0059] As another example, the alumina used for lining material 129 can be formed by, for example, an ALD or CVD process using aluminum dimethyl isopropoxide (e.g., (CH3)2AlOCH(CH3)2, also known as DMAI) and H2O as precursors. As yet another example, the alumina used for lining material 129 can be formed by, for example, an ALD or CVD process using AlCl3 and H2O as precursors.

[0060] In one embodiment, the lining material 129 is silicon and can be formed using a suitable formation method (e.g., PVD, CVD, ALD, etc.). Silicon can be formed using silicon-containing precursors (e.g., silanes, silyl ethers, etc.) as the lining material 129. In yet another embodiment, the lining material 129 is silicon oxide and can be formed by first forming silicon and then oxidizing the formed silicon to form silicon oxide as the lining material 129. For example, the lining material 129 (e.g., silicon oxide) can be formed by immersing silanes or silyl ethers in oxygen-containing ambient air at a temperature between about 250°C and about 650°C.

[0061] In U.S. Patent Application No. 16 / 904,751, two lining materials (e.g., titanium nitride, tantalum nitride, or titanium carbide) are formed around each nanosheet, and a work function material surrounding each nanosheet is sandwiched between the two lining materials. This disclosure discloses different structures for the lining materials. Furthermore, the materials disclosed in this disclosure (e.g., alumina, silicon oxide, or silicon) provide improved ability to prevent the diffusion of aluminum in the work function material.

[0062] exist Figure 13 In the example, the lining material 129 between adjacent nanosheets 54 is fused together (e.g., in solid contact with each other). For example, in Figure 13 In region 130B (i.e., the region between adjacent nanosheets 54), the gate layer stack 120 completely fills the space between adjacent nanosheets 54. As a result, the subsequently formed gate electrode 122 (see...) Figure 15B The material does not extend into the space between adjacent nanosheets 54. In other words, there is no gate electrode material in the space between adjacent nanosheets 54. The list of material layers between two adjacent nanosheets 54 (e.g., 54A and 54B) therefore includes: interface dielectric material layer 121, gate dielectric material layer 123, work function material layer 125, (merged) liner material layer 129, work function material layer 125, gate dielectric material layer 123, and interface dielectric material layer 121.

[0063] Still referencing Figure 13Note that in region 130A (i.e., the region above the uppermost nanosheet 54 (e.g., 54C) away from fin 90), the gate layer stack 120 has a first thickness, while in region 130B, the gate layer stack 120 has a second thickness, which is greater than the first thickness. This is because, as described above, in region 130B, the gate layer stacks 120 around two adjacent nanosheets 54 merge (e.g., physically contact) and form a thicker (merged) gate layer stack 120. Furthermore, because the liner material 129 between adjacent nanosheets 54 merges together, the liner material 129 between adjacent nanosheets 54 (e.g., in region 130B) is approximately twice as thick as the liner material 129 at other locations (e.g., above the uppermost nanosheet 54 (e.g., in region 130A), or along the sidewalls of the nanosheets 54). For example, in Figure 13 In this embodiment, the thickness T2 of the lining material 129, measured between adjacent nanosheets 54, is between about 150% and about 250% of the thickness T1 of the lining material 129 measured above the uppermost nanosheet 54C, for example, between about 180% and about 220%. In some embodiments, the ratio between the thickness T3 of the work function material 125 and the thickness T2 of the lining material 129 is in the range of about 1 to about 2. Such a ratio ensures that both the work function material 125 and the lining material 129 are formed as a continuous layer (e.g., without pinholes), while ensuring that the work function material 125 has sufficient aluminum to adjust the work function, and that the thickness of the lining material 129 is sufficient to prevent or reduce aluminum diffusion.

[0064] By forming a liner material 129 around the work function material 125, the work function material 125 around two adjacent nanosheets 54 is separated from each other, and each layer of work function material 125 around each nanosheet 54 remains a conformal layer with a substantially uniform thickness (e.g., uniform within the constraints of the manufacturing process). In some embodiments, the aluminum in the work function material 125 determines the threshold voltage V of the NSFET device 100. TH This plays a crucial role. Without the currently disclosed method (e.g., without liner material 129), the work function material 125 between two adjacent nanosheets 54 could merge and form a thicker work function material layer 125 in region 130B than, for example, in region 130A, which could lead to threshold voltage variations in the formed device. Conversely, the currently disclosed method prevents the merging of the work function material 125 between adjacent nanosheets 54 and thus ensures that the work function material 125 around each nanosheet 54 has a substantially uniform thickness. As a result, threshold voltage variations are avoided or reduced.

[0065] The lining material 129 also prevents or reduces the movement (e.g., diffusion) of aluminum in the work function material 125 (e.g., TiAl), and can therefore also be referred to as a barrier layer. Note that although the lining material 129 may be an aluminum-containing material (e.g., alumina), the molecular bonds between aluminum and oxygen in alumina are much stronger than the molecular bonds between aluminum and titanium in titanium-aluminum, and therefore, the lining material 129 does not have an aluminum diffusion problem.

[0066] Now for reference Figure 14 In some embodiments, a capping layer 127 is formed around the work function material 125 to protect it after the work function material 125 is formed and before the liner material 129 is formed. The capping layer 127 can be formed from a suitable material such as titanium nitride using suitable forming methods such as ALD, CVD, etc. The thickness of the capping layer 127 can be less than about 20 angstroms (e.g., between 0 angstroms and about 20 angstroms). Therefore, with Figure 13 Compared to the gate layer stack 120 in the middle, Figure 14 The gate layer stack 120 in the middle has an additional cap layer 127. As a result, in Figure 14 In the example, the list of material layers between two adjacent nanosheets 54 (e.g., 54A and 54B) thus includes: interface dielectric material layer 121, gate dielectric material layer 123, work function material layer 125, capping layer 127, (merged) liner material layer 129, capping layer 127, work function material layer 125, gate dielectric material layer 123, and interface dielectric material layer 121. Figure 14 In region 130B, the thickness of the gate layer stack 120 (or the thickness of the liner material 129) is approximately twice that in region 130A, with details similar to... Figure 13 Similarly, so I won't go into detail again. The following discussion will focus on... Figure 13 Taking the gate layer stack 120 in the example, it can be understood that... Figure 14 The gate layer stack 120 in the example can be used instead of Figure 13 The gate layer is stacked 120.

[0067] Next, in Figure 15A and Figure 15B In the middle, in the recess 103 (see Figure 10AA gate electrode material (e.g., a conductive material) is formed in the recess 103 to form the gate electrode 122. The gate electrode material fills the remaining portion of the recess 103. The gate electrode material can be a metal-containing material, such as TiN, TiO, TaN, TaC, Co, Ru, Al, W, combinations thereof, or multiples thereof. After filling the recess 103 with the gate electrode material, a planarization process such as CMP can be performed to remove excess portions of the gate layer stack 120 and the gate electrode material located above the top surface of the first ILD 114. The gate electrode material and the remaining portion of the gate layer stack 120 thus form the replacement gate of the resulting NSFET device 100. Each gate electrode 122 and the corresponding gate layer stack 120 can be collectively referred to as a gate stack, a replacement gate structure, or a metal gate structure. Each gate stack extends around a corresponding nanosheet 54.

[0068] Please note that, for simplicity, the various constituent materials of the gate layer stack 120 are not shown. Figure 15A As shown in the text, but Figure 15B As shown in the figure, Figure 15B It is the NSFET device 100 along Figure 15A A cross-sectional view of section FF. Figure 15A The text also shows a comparison with... Figure 13 Regions 130A and 130B correspond to regions 130A and 130B. For example... Figure 15B As shown, the gate layer stack 120 also completely fills the space between the bottommost nanosheet 54 (e.g., 54A) and the fin 90, and the gate electrode 122 extends around at least some portions of the gate layer stack 120. In other words, the gate electrode 122 extends (and is in solid contact with) portions of the gate layer stack 120 located on the sidewalls of the nanosheet 54 and on the upper surface of the topmost nanosheet 54C, but the gate electrode 122 does not extend between the spaces between two vertically adjacent nanosheets 54 (or between the fin 90 and the bottommost nanosheet 54A).

[0069] As will be readily understood by those skilled in the art, additional processes can be performed to complete the fabrication of the NSFET device 100, and therefore details are not discussed here. For example, a second ILD can be deposited on top of the first ILD 114. Gate contacts and source / drain contacts can be formed through the second ILD and / or the first ILD 114 to be electrically coupled to the gate electrode 122 and the source / drain region 112, respectively. Furthermore, interconnect structures can be formed on the second ILD to electrically connect underlying electronic components (e.g., transistors) to form functional circuitry.

[0070] Variations of the disclosed embodiments are possible and are fully intended to be included within the scope of this disclosure. For example, depending on the type of device formed (e.g., n-type or p-type device), the second semiconductor material 54 may be removed, and the first semiconductor material 52 may be retained to form nanosheets that serve as the channel region of the formed NSFET device. In embodiments where the first semiconductor material 52 is retained to form nanosheets, internal spacers are formed in recesses at the ends of the second semiconductor material 54, as will be readily understood by those skilled in the art, prior to removal of the second semiconductor material 54.

[0071] Figure 16 , Figure 17 , Figure 18A and Figure 18B This is a cross-sectional view of a nanosheet field-effect transistor (NSFET) device 200 at various stages of fabrication according to yet another embodiment. Reference Figure 16 The NSFET device 200 is similar to Figure 13 The NSFET device 100 is shown, but the NSFET device 200 has an n-type device region 210 and a p-type device region 220. In the illustrated embodiment, Figure 16 The structure in the n-type device region 210 (e.g., a nanosheet 54 with a gate layer stack 120) and Figure 13 The structures shown are identical and are arranged according to the methods used for forming. Figure 13 The structure in Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figures 5A-5C , Figures 6A-6C , Figures 7A-7C , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B and Figures 11-13 The same processing steps shown are formed. Furthermore, Figure 16 The structure (nanosheet 52 and gate layer stack 120) formed in the p-type device region 220 is also shown, which is formed in a similar processing step as the structure in the n-type device region 210. For example, since a p-type channel region is formed in the p-type device region 220, the second semiconductor material 54 (e.g., Si) is removed to release the first semiconductor material 52 (e.g., SiGe) to form the nanosheet 52. Furthermore, internal spacers 55 are formed between the nanosheets 52 in the p-type device region 220 (see [link to documentation]). Figure 18B ). Figures 6A-6C , Figures 7A-7C , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A and Figure 10B The process shown can be applied to the formation of nanosheets 52, therefore details are not discussed. Figure 16 In the diagram, region 131B defines the region between adjacent nanosheets 52, and region 131A defines the region above the uppermost nanosheet 52 (e.g., 52C).

[0072] In one embodiment, to form the NSFET device 200, both the n-type device region 210 and the p-type device region 220 are subjected to... Figure 2 , Figure 3A , Figure 3B , Figure 4A , Figure 4B and Figures 5A-5C The processing steps are shown below. Next, the n-type device region 210 is processed. Figures 6A-6C , Figures 7A-7C , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A and Figure 10B Simultaneously with the processing steps shown, the p-type device region 220 is covered with a first patterned mask layer (e.g., a patterned photoresist) to form a nanosheet 54. Next, the first patterned mask layer is removed, and the n-type device region 210 is covered with a second patterned mask layer. Similar processing steps (e.g., similar to...) are then performed on the p-type device region 220. Figures 6A-6C , Figures 7A-7C , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A and Figure 10B As shown, but modified to form nanosheet 52, the second patterned mask layer is removed, and both n-type device region 210 and p-type device region 220 are subjected to [further steps]. Figures 11-13 The processing steps shown are for forming Figure 16 The structure shown.

[0073] Next, in Figure 17In the process, a third patterned mask layer is formed to cover the n-type device region 210, and one or more etching processes are performed to remove the liner material 129 and the work function material 125, thereby exposing the gate dielectric material 123 around the nanosheet 52. Next, the work function material 124 (e.g., a p-type work function material (e.g., TiN)) is formed around the nanosheet 52 and around the gate dielectric material 123. After the work function material 124 is formed, the third patterned mask layer is removed. The interface dielectric material 121, the gate dielectric material 123, and the work function material 124 form a gate layer stack 126 for the p-type device region 220.

[0074] Please note that in Figure 17 In the example, the work function material 124 between adjacent nanosheets 52 (in region 131B) is merged together. Therefore, the thickness of the work function material 124 in region 131B can be two or more times the thickness of the work function material 124 in region 131A. The list of material layers between two adjacent nanosheets 52 (e.g., 52A and 52B) thus includes: interface dielectric material layer 121, gate dielectric material layer 123, (merged) work function material layer 124, gate dielectric material layer 123, and interface dielectric material layer 121. In the illustrated embodiment, the work function material 124 (e.g., a p-type work function material, such as TiN) does not contain aluminum (which is easily diffused), and therefore, a liner material 129 is not used in the p-type device region 220. The increased space between adjacent nanosheets 52 allows for more flexible adjustments to the structure of the work function material 124, such as the number and thickness of sublayers within the work function material 124. Please note that although the work function material 124 (or 125) is shown as a single layer in the figure, the work function material 124 (or 125) can have a multilayer structure with multiple sublayers.

[0075] Next, as Figure 18A and Figure 18B As shown, the gate electrode 122 is formed around the nanosheets 54 / 52 and around the layer stack 120 / 126. Figure 18A A cross-sectional view of the NSFET device 200 along the longitudinal direction of the fins in the n-type device region 210 is shown, and Figure 18B A cross-sectional view of the NSFET device 200 along the longitudinal direction of the fins in the p-type device region 220 is shown.

[0076] In the illustrated embodiment, Figure 18A cross-sectional view and Figure 15A The cross-sectional views are the same, so details will not be repeated. Figure 18B In this process, the gate layer stack 126 fills the space between adjacent nanosheets 52 in the p-type device region 220, and therefore, in Figure 18B There is no gate electrode 122 between adjacent nanosheets 52. Furthermore, since the gate electrode 122 fills the space left by removing the uppermost layer of the second semiconductor material 54, the gate electrode 122 has a first width W1 measured between the gate spacers 108 and a second width W2 measured between the uppermost inner spacers 55, wherein W2 is greater than W1.

[0077] Figure 19 A flowchart illustrating a method for manufacturing a semiconductor device according to some embodiments is shown. It should be understood that... Figure 19 The illustrated embodiments are merely examples of many possible embodiments. Those skilled in the art will recognize many variations, substitutions, and modifications. For example, additions, removals, substitutions, rearrangements, or repetitions may be made. Figure 19 The various steps shown.

[0078] refer to Figure 19 In box 1010, a fin protruding above the substrate is formed. In box 1020, a source / drain region is formed above the fin. In box 1030, a first nanosheet and a second nanosheet are formed above the fin and between the source / drain regions, the first nanosheet being disposed between the fin and the second nanosheet. In box 1040, a gate dielectric material is formed around the first and second nanosheets. In box 1050, a work function material is formed around the gate dielectric material, wherein a first portion of the work function material extends along a first surface of the first nanosheet facing away from the substrate, and a second portion of the work function material extends along a second surface of the second nanosheet facing the substrate. In box 1060, a liner material is formed around the work function material, wherein the liner material fills the gap between the first and second portions of the work function material. In box 1070, a gate material is formed on the first and second nanosheets.

[0079] The embodiments offer advantages. By forming a liner material, the disclosed method prevents the work function material around adjacent nanosheets from coalescing and forms a thicker work function layer between adjacent nanosheets, thereby avoiding or reducing threshold voltage variations. Furthermore, the liner material prevents or reduces the diffusion of aluminum from the work function layer into other layers of the NSFET device.

[0080] In one embodiment, a semiconductor device includes: fins protruding above a substrate; source / drain regions located above the fins; nanosheets located between the source / drain regions; and a gate structure located above the fins and between the source / drain regions, the gate structure including: a gate dielectric material located around each nanosheet; a work function material located around the gate dielectric material; a liner material located around the work function material, wherein the liner material has a non-uniform thickness and is thicker at a first location between the nanosheets than at a second location along the sidewalls of the nanosheets; and a gate electrode material located around at least some portions of the liner material. In one embodiment, the work function material is an aluminum-containing material, and the liner material is an oxide. In one embodiment, the work function material is titanium-aluminum, and the liner material is aluminum oxide or silicon oxide. In one embodiment, the liner material is silicon. In one embodiment, the work function material is titanium-aluminum. In one embodiment, the nanosheet includes a first nanosheet and a second nanosheet, wherein the first nanosheet is located between the second nanosheet and a substrate, wherein a work function material surrounding the first nanosheet has a first surface facing the second nanosheet, and a work function material surrounding the second nanosheet has a second surface facing the first nanosheet, wherein a liner material fills the space between the first and second surfaces of the work function material. In one embodiment, there is no gate electrode material in the space between the first and second surfaces of the work function material. In one embodiment, the semiconductor device further includes an interface dielectric material between each nanosheet in the nanosheet and a gate dielectric material. In one embodiment, the nanosheet includes a first nanosheet and a second nanosheet perpendicularly adjacent to the first nanosheet, wherein the interface dielectric material, the gate dielectric material, the work function material, and the liner material completely fill the space between the first and second nanosheets. In one embodiment, the interface dielectric material, the gate dielectric material, the work function material, and the liner material also completely fill the space between the fin and the bottommost nanosheet closest to the fin. In one embodiment, the lining material has a first thickness at a first surface of the first nanosheet facing away from the substrate and a second thickness at a second surface of the first nanosheet facing the substrate, wherein the first nanosheet is the uppermost nanosheet furthest from the substrate, and wherein the second thickness is greater than the first thickness. In one embodiment, the second thickness is approximately twice the first thickness.

[0081] In one embodiment, a semiconductor device includes: a fin protruding above a substrate; a gate structure located above the fin; source / drain regions located above the fin and on opposite sides of the gate structure; and a first channel layer and a second channel layer disposed between the source / drain regions and above the fin, wherein the first channel layer is located between the second channel layer and the fin, wherein the gate structure includes: a gate dielectric material surrounding the first channel layer and the second channel layer; a work function material surrounding the gate dielectric material; a liner material surrounding the work function material, wherein the liner material has a first thickness above the upper surface of the second channel layer away from the fin and a second thickness between the first and second channel layers, wherein the first thickness is less than the second thickness; and a gate electrode. In one embodiment, the semiconductor device further includes an internal spacer located between a first end of the first channel layer and a second end of the second channel layer, wherein the gate dielectric material, the work function material, and the liner material fill the space between the internal spacer. In one embodiment, the work function material is titanium aluminum, and the liner material is aluminum oxide, silicon oxide, or silicon. In one embodiment, the second thickness is approximately twice the first thickness. In one embodiment, the semiconductor device further includes an interface dielectric material located between the gate dielectric material and the first channel layer and between the gate dielectric material and the second channel layer, wherein the interface dielectric material, the gate dielectric material, the work function material, and the liner material fill the space between the first channel layer and the second channel layer.

[0082] In one embodiment, a method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming source / drain regions on the fin; forming a first nanosheet and a second nanosheet located on the fin and between the source / drain regions, the first nanosheet disposed between the fin and the second nanosheet; forming a gate dielectric material around the first and second nanosheets; forming a work function material around the gate dielectric material, wherein a first portion of the work function material extends along a first surface of the first nanosheet away from the substrate, and a second portion of the work function material extends along a second surface of the second nanosheet facing the substrate; forming a liner material around the work function material, wherein the liner material fills the gap between the first and second portions of the work function material; and forming a gate material on the first and second nanosheets. In one embodiment, there is no gate material in the gap between the first and second portions of the work function material. In one embodiment, the liner material is formed of titanium aluminum, and the work function material is formed of aluminum oxide, silicon oxide, or silicon.

[0083] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

[0084] Example 1. A semiconductor device, comprising:

[0085] The fins protrude above the substrate;

[0086] The source / drain region is located above the fin;

[0087] Nanosheets are located between the source / drain regions; and

[0088] A gate structure, located above the fin and between the source / drain regions, the gate structure comprising:

[0089] A gate dielectric material is located around each of the nanosheets in the nanosheets;

[0090] The work function material is located around the gate dielectric material;

[0091] A lining material, located around the work function material, wherein the lining material has a non-uniform thickness and is thicker at a first location between the nanosheets than at a second location along the sidewalls of the nanosheets; and

[0092] Gate electrode material is located around at least some portions of the liner material.

[0093] Example 2. The semiconductor device according to Example 1, wherein the work function material is an aluminum-containing material and the liner material is an oxide.

[0094] Example 3. The semiconductor device according to Example 2, wherein the work function material is titanium aluminum and the lining material is aluminum oxide or silicon oxide.

[0095] Example 4. The semiconductor device according to Example 1, wherein the liner material is silicon.

[0096] Example 5. The semiconductor device according to Example 4, wherein the work function material is titanium aluminum.

[0097] Example 6. A semiconductor device according to Example 1, wherein the nanosheet comprises a first nanosheet and a second nanosheet, wherein the first nanosheet is located between the second nanosheet and the substrate, wherein the work function material surrounding the first nanosheet has a first surface facing the second nanosheet, and the work function material surrounding the second nanosheet has a second surface facing the first nanosheet, wherein the lining material fills the space between the first surface and the second surface of the work function material.

[0098] Example 7. The semiconductor device according to Example 6, wherein the space between the first surface and the second surface of the work function material is free of the gate electrode material.

[0099] Example 8. The semiconductor device according to Example 1 further includes an interface dielectric material located between each nanosheet in the nanosheet and the gate dielectric material.

[0100] Example 9. A semiconductor device according to Example 8, wherein the nanosheet comprises a first nanosheet and a second nanosheet perpendicularly adjacent to the first nanosheet, wherein the interface dielectric material, the gate dielectric material, the work function material and the liner material completely fill the space between the first nanosheet and the second nanosheet.

[0101] Example 10. The semiconductor device according to Example 9, wherein the interface dielectric material, the gate dielectric material, the work function material and the liner material further completely fill the space between the fin and the lowest nanosheet closest to the fin.

[0102] Example 11. The semiconductor device according to Example 1, wherein the liner material has a first thickness at a first surface of the first nanosheet facing away from the substrate and a second thickness at a second surface of the first nanosheet facing the substrate, wherein the first nanosheet is the uppermost nanosheet farthest from the substrate, and wherein the second thickness is greater than the first thickness.

[0103] Example 12. The semiconductor device according to Example 11, wherein the second thickness is approximately twice the first thickness.

[0104] Example 13. A semiconductor device comprising:

[0105] The fins protrude above the substrate;

[0106] A gate structure is located on the fin;

[0107] Source / drain regions, located above the fin and on opposite sides of the gate structure; and

[0108] A first channel layer and a second channel layer are disposed between the source / drain regions and above the fin, wherein the first channel layer is located between the second channel layer and the fin, and wherein the gate structure includes:

[0109] A gate dielectric material is located around the first channel layer and around the second channel layer;

[0110] The work function material is located around the gate dielectric material;

[0111] A lining material, located around the work function material, wherein the lining material has a first thickness above the upper surface of the second channel layer away from the fin, and a second thickness between the first channel layer and the second channel layer, wherein the first thickness is less than the second thickness; and

[0112] Gate electrode.

[0113] Example 14. The semiconductor device according to Example 13 further includes an internal spacer located between a first end of the first channel layer and a second end of the second channel layer, wherein the gate dielectric material, the work function material and the liner material fill the space between the internal spacer.

[0114] Example 15. The semiconductor device according to Example 13, wherein the work function material is titanium aluminum and the lining material is aluminum oxide, silicon oxide or silicon.

[0115] Example 16. The semiconductor device according to Example 13, wherein the second thickness is approximately twice the first thickness.

[0116] Example 17. The semiconductor device according to Example 13 further includes an interface dielectric material located between the gate dielectric material and the first channel layer and between the gate dielectric material and the second channel layer, wherein the interface dielectric material, the gate dielectric material, the work function material and the liner material fill the space between the first channel layer and the second channel layer.

[0117] Example 18. A method of forming a semiconductor device, the method comprising:

[0118] Forming fins that protrude above the substrate;

[0119] A source / drain region is formed on the fin;

[0120] A first nanosheet and a second nanosheet are formed on the fin and between the source / drain regions, with the first nanosheet disposed between the fin and the second nanosheet.

[0121] A gate dielectric material is formed around the first nanosheet and the second nanosheet;

[0122] A work function material is formed around the gate dielectric material, wherein a first portion of the work function material extends along a first surface of the first nanosheet away from the substrate, and a second portion of the work function material extends along a second surface of the second nanosheet facing the substrate.

[0123] A lining material is formed around the work function material, wherein the lining material fills the gap between the first portion and the second portion of the work function material; and

[0124] A gate material is formed on the first nanosheet and the second nanosheet.

[0125] Example 19. The method according to Example 18, wherein the gap between the first portion and the second portion of the work function material is free of the gate material.

[0126] Example 20. The method according to Example 18, wherein the lining material is formed of titanium aluminum, and the work function material is formed of aluminum oxide, silicon oxide, or silicon.

Claims

1. A semiconductor device, comprising: The fins protrude above the substrate; The source / drain region is located above the fin; Nanosheets are located between the source / drain regions; as well as A gate structure, located above the fin and between the source / drain regions, the gate structure comprising: A gate dielectric material is located around each of the nanosheets in the nanosheets; A work function material is located around the gate dielectric material, and the work function material is an aluminum-containing material. A lining material, located around the work function material, wherein the lining material has a non-uniform thickness and is thicker at a first location between the nanosheets than at a second location along the sidewalls of the nanosheets, and the lining material is an oxide to prevent or reduce the diffusion of aluminum from the work function material; and Gate electrode material is located around at least some portions of the liner material.

2. The semiconductor device according to claim 1, wherein, The work function material is titanium aluminum, and the lining material is aluminum oxide or silicon oxide.

3. The semiconductor device according to claim 1, wherein, The lining material is silicon.

4. The semiconductor device according to claim 3, wherein, The work function material is titanium aluminum.

5. The semiconductor device according to claim 1, wherein, The nanosheet includes a first nanosheet and a second nanosheet, wherein the first nanosheet is located between the second nanosheet and the substrate, wherein the work function material surrounding the first nanosheet has a first surface facing the second nanosheet, and the work function material surrounding the second nanosheet has a second surface facing the first nanosheet, wherein the lining material fills the space between the first and second surfaces of the work function material.

6. The semiconductor device according to claim 5, wherein, The space between the first and second surfaces of the work function material is free of the gate electrode material.

7. The semiconductor device of claim 1, further comprising an interface dielectric material located between each nanosheet in the nanosheet and the gate dielectric material.

8. The semiconductor device according to claim 7, wherein, The nanosheet includes a first nanosheet and a second nanosheet perpendicularly adjacent to the first nanosheet, wherein the interface dielectric material, the gate dielectric material, the work function material, and the liner material completely fill the space between the first nanosheet and the second nanosheet.

9. The semiconductor device according to claim 8, wherein, The interface dielectric material, the gate dielectric material, the work function material, and the liner material also completely fill the space between the fin and the lowest nanosheet closest to the fin.

10. The semiconductor device according to claim 1, wherein, The lining material has a first thickness at a first surface of the first nanosheet facing away from the substrate and a second thickness at a second surface of the first nanosheet facing the substrate, wherein the first nanosheet is the uppermost nanosheet farthest from the substrate, and wherein the second thickness is greater than the first thickness.

11. The semiconductor device according to claim 10, wherein, The second thickness is twice the first thickness.

12. A semiconductor device, comprising: The fins protrude above the substrate; A gate structure is located on the fin; The source / drain region is located above the fin and on the opposite side of the gate structure; as well as A first channel layer and a second channel layer are disposed between the source / drain regions and above the fin, wherein the first channel layer is located between the second channel layer and the fin, and wherein the gate structure includes: A gate dielectric material is located around the first channel layer and around the second channel layer; A work function material is located around the gate dielectric material, and the work function material is an aluminum-containing material. A lining material, located around the work function material, wherein the lining material has a first thickness above the upper surface of the second channel layer away from the fin, and a second thickness between the first channel layer and the second channel layer, wherein the first thickness is less than the second thickness, and the lining material is an oxide to prevent or reduce the diffusion of aluminum from the work function material; and Gate electrode.

13. The semiconductor device of claim 12, further comprising an internal spacer located between a first end of the first channel layer and a second end of the second channel layer, wherein, The gate dielectric material, the work function material, and the liner material fill the space between the internal spacers.

14. The semiconductor device according to claim 12, wherein, The work function material is titanium aluminum, and the lining material is alumina, silicon oxide, or silicon.

15. The semiconductor device according to claim 12, wherein, The second thickness is twice the first thickness.

16. The semiconductor device of claim 12, further comprising an interface dielectric material located between the gate dielectric material and the first channel layer and between the gate dielectric material and the second channel layer, wherein, The interface dielectric material, the gate dielectric material, the work function material, and the liner material fill the space between the first channel layer and the second channel layer.

17. A method of forming a semiconductor device, the method comprising: Forming fins that protrude above the substrate; A source / drain region is formed on the fin; A first nanosheet and a second nanosheet are formed on the fin and between the source / drain regions, with the first nanosheet disposed between the fin and the second nanosheet. A gate dielectric material is formed around the first nanosheet and the second nanosheet; A work function material is formed around the gate dielectric material, wherein the work function material is an aluminum-containing material, and a first portion of the work function material extends along a first surface of the first nanosheet facing away from the substrate, and a second portion of the work function material extends along a second surface of the second nanosheet facing the substrate. A lining material is formed around the work function material, wherein the lining material fills the gap between the first and second portions of the work function material, and the lining material is an oxide to prevent or reduce the diffusion of aluminum from the work function material; and A gate material is formed on the first nanosheet and the second nanosheet.

18. The method according to claim 17, wherein, The gap between the first and second portions of the work function material does not contain the gate material.

19. The method of claim 17, wherein, The lining material is formed of titanium aluminum, and the work function material is formed of aluminum oxide, silicon oxide, or silicon.

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