Process optimization method and system

Abstract

The present disclosure provides a process optimization method and system. The process optimization method comprises: manufacturing a plurality of test units with different channel lengths according to a current channel-halo doping ratio; obtaining a variation curve between threshold voltage and channel length based on the plurality of test units; determining a process sensitivity corresponding to a target channel length according to the variation curve; in response to the process sensitivity being greater than a first set value, adjusting the current channel-halo doping ratio; repeating the above steps until the process sensitivity is not greater than the first set value or the variation of the process sensitivity of adjacent two times is not greater than a second set value, and taking the current channel-halo doping ratio as a final channel-halo doping ratio. The present disclosure realizes process monitoring of a core device by designing a test unit, improves the channel-halo doping ratio of the core device, thereby reducing the process sensitivity of the characteristics of the core device, and further reducing the mismatch degree of the core device.

Description

Technical Field

[0001] This disclosure belongs to the field of semiconductor device manufacturing technology, and specifically relates to a process optimization method and system. Background Technology

[0002] The core components of Dynamic Random Access Memory (DRAM) are located near the memory array and often consist of paired transistors that play a crucial role in the memory's read and write functions. Taking an inductive amplifier as an example, its main function is to amplify the capacitance point signals in the DRAM to the external circuitry. When there is a mismatch between the paired transistors in the inductive amplifier, it will lead to an increase in signal amplification time, and in severe cases, it will cause the read capacitance signal to fail (either "0" or "1"). Similarly, with word line drivers, when there is a mismatch between the paired transistors in the word line driver, it will cause differences in the sub-word line currents. Summary of the Invention

[0003] To address the above problems, some embodiments of this disclosure provide a process optimization method, including:

[0004] 1) Based on the current channel-halo doping ratio, fabricate multiple test cells with different channel lengths;

[0005] 2) Obtain the variation curve between the threshold voltage and the channel length based on the multiple test units;

[0006] 3) Based on the aforementioned variation curve, determine the process sensitivity corresponding to the target channel length;

[0007] 4) In response to the process sensitivity being greater than a first set value, adjust the current channel-halo doping ratio;

[0008] 5) Repeat steps 1) to 4) until the process sensitivity is not greater than the first set value or the change in the process sensitivity between two adjacent steps is not greater than the second set value, and take the current channel-halo doping ratio as the final channel-halo doping ratio.

[0009] For example, determining the process sensitivity corresponding to the target channel length based on the variation curve includes:

[0010] The absolute value of the slope corresponding to the target channel length is used to characterize the process sensitivity.

[0011] For example, the range of the first set value is [0.1, 0.3].

[0012] For example, the range of the second set value is [0.01, 0.05].

[0013] For example, adjusting the current channel-halo doping ratio includes:

[0014] When the slope is greater than 0, keep the channel doping concentration constant and increase the halo doping concentration, or keep the halo doping concentration constant and decrease the channel doping concentration, or increase the halo doping concentration while decreasing the channel doping concentration.

[0015] When the slope is less than 0, the channel doping concentration is kept constant while the halo doping concentration is decreased, or the halo doping concentration is kept constant while the channel doping concentration is increased, or the halo doping concentration is decreased while the channel doping concentration is increased.

[0016] For example, the magnitude of the change in channel doping concentration and the magnitude of the change in halo ring doping concentration are both determined based on the deviation between the process sensitivity and the first set value.

[0017] For example, obtaining the variation curve between the threshold voltage and the channel length based on the multiple test units includes:

[0018] Detect the threshold voltage of each of the test units;

[0019] The variation curves are constructed based on the threshold voltage and channel length of each of the test units.

[0020] For example, the plurality of test units have the same structure, and apart from the channel length, all other process parameters of the plurality of test units that are not related to the channel length are the same.

[0021] For example, the channel length of one of the multiple test units is the target channel length.

[0022] For example, the channel length of at least one of the plurality of test units is greater than the target channel length, and the channel length of at least one of the plurality of test units is less than the target channel length.

[0023] For example, each of the test units includes a pair of transistors having the same structure and process parameters, and the channel length of each test unit is the channel length of any one of the pairs of transistors it includes.

[0024] For example, it also includes:

[0025] 6) Fabricate a semiconductor device according to the final channel-halo doping ratio, wherein the semiconductor device includes the same functional units as the test unit having the target channel length.

[0026] For example, the semiconductor device includes at least one of a sensing amplifier and a word line driver.

[0027] Other embodiments of this disclosure also provide a process optimization system, including:

[0028] The manufacturing apparatus is configured to manufacture multiple test cells with different channel lengths according to the current channel-halo doping ratio;

[0029] The testing apparatus is configured to acquire a curve showing the relationship between the threshold voltage and the channel length based on the plurality of testing units;

[0030] The computing device is configured to determine the process sensitivity corresponding to the target channel length based on the change curve.

[0031] The parameter adjustment device is configured to adjust the current channel-halo ring doping ratio in response to the process sensitivity being greater than a first set value.

[0032] The process optimization system is configured to control the manufacturing device, the testing device, the computing device, and the parameter adjustment device to operate sequentially until the process sensitivity is not greater than the first set value or the change in the process sensitivity between two adjacent times is not greater than the second set value, and the current channel-halo doping ratio is taken as the final channel-halo doping ratio.

[0033] For example, the manufacturing apparatus is also configured to manufacture a semiconductor device according to the final channel-halo doping ratio, wherein the semiconductor device includes the same functional units as the test unit having the target channel length.

[0034] The embodiments of this disclosure have at least the following advantages: mainly by designing the test unit of the dynamic random access memory, the process monitoring of the core device is realized, and by optimizing the process method of the core device, the channel-halo ring doping ratio of the core device is improved, thereby reducing the process sensitivity of the core device characteristics, and thus reducing the mismatch of the core device, effectively improving the stability of the dynamic random access memory.

[0035] Other features and advantages of this disclosure will be set forth in the following description and will be apparent in part from the description or may be learned by practicing the disclosure. The objectives and other advantages of this disclosure may be realized and obtained by means of the structures pointed out in the description, claims and drawings. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 A schematic diagram of a test structure is shown;

[0038] Figure 2 A flowchart of a process optimization method according to an embodiment of the present disclosure is shown;

[0039] Figure 3 A schematic diagram of a test structure according to an embodiment of the present disclosure is shown;

[0040] Figure 4 A variation curve according to an embodiment of this disclosure is shown;

[0041] Figure 5 A variation curve two according to an embodiment of this disclosure is shown;

[0042] Figure 6 A schematic diagram of a process optimization system according to an embodiment of the present disclosure is shown. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0044] Figure 1 A schematic diagram of a test structure is shown. For example... Figure 1 As shown, the test structure includes multiple identical test units. Each test unit includes an active region 10 and a first gate 21 and a second gate 22 located on the active region 10. The active region 10 includes a source region 11 located between the first gate 21 and the second gate 22, a first drain region 12 located on the side of the first gate 21 away from the second gate 22, and a second drain region 13 located on the side of the second gate 22 away from the first gate 21. Figure 1As shown, each test unit also includes a contact 31 disposed on the source region 11, a contact 32 disposed on the first drain region 12, and a contact 33 disposed on the second drain region 13. Each contact is used to make an electrical connection with the corresponding test pad. It can be understood that corresponding contacts can also be disposed on the first gate 21 and the second gate 22 to make an electrical connection with the corresponding test pad.

[0045] like Figure 1 As shown, each test unit has a symmetrical structure. Specifically, the first gate 21 and the second gate 22 are symmetrically distributed on both sides of the source region 11, and the first drain region 12 and the second drain region 13 are symmetrically distributed on both sides of the source region 11. The distance between the contact 31 and the first gate 21 is approximately equal to the distance between the contact 31 and the second gate 22. Contacts 32 and 33 are symmetrically distributed on both sides of the contact 31, and the distance between the contact 32 and the first gate 21 is approximately equal to the distance between the contact 33 and the second gate 22. It can be understood that each test unit includes two transistors appearing in pairs (referred to as paired transistors), one corresponding to the first gate 21 and the first drain region 12, and the other corresponding to the second gate 22 and the second drain region 13, and both sharing the source region 11. Paired transistors often have the same structure and process parameters (including size, doping method and doping concentration of the source and drain regions, etc.).

[0046] During the research, the inventors of this application discovered Figure 1 The test structure shown has at least the following problems: the test units in the above test structure directly replicate the core devices in the dynamic random access memory (DRAM), repeatedly setting up multiple identical test units. Each test unit has the same structure and process parameters, allowing only basic electrical monitoring (e.g., testing threshold voltage and current switching ratio), wasting a significant amount of valuable space on the wafer. Furthermore, the inventors of this application have also discovered that most core devices include paired transistors. In circuit design, the electrical properties of paired transistors should be completely identical. However, in reality, process instability often causes mismatch in core devices, resulting in unstable characteristics of the DRAM. Therefore, there is an urgent need to develop a process optimization method to improve process stability and reduce the mismatch of core devices.

[0047] Figure 2 A flowchart of a process optimization method according to an embodiment of this disclosure is shown. Figure 2 As shown, according to some embodiments, the first aspect of this disclosure provides a process optimization method, including the following steps:

[0048] Step 1): Based on the current channel-halo doping ratio, fabricate multiple test cells with different channel lengths;

[0049] Step 2): Obtain the variation curve between the threshold voltage and the channel length based on the multiple test units;

[0050] Step 3): Determine the process sensitivity corresponding to the target channel length based on the aforementioned change curve;

[0051] Step 4): In response to the process sensitivity being greater than the first set value, adjust the current channel-halo doping ratio;

[0052] Step 5): Repeat steps 1) to 4) until the process sensitivity is not greater than the first set value or the change in the process sensitivity between two adjacent steps is not greater than the second set value, and take the current channel-halo doping ratio as the final channel-halo doping ratio.

[0053] The process optimization method provided in this disclosure mainly achieves process monitoring of core devices by designing test units, and improves the channel-halo ring doping ratio of core devices by optimizing the process methods of core devices, thereby reducing the process sensitivity of core device characteristics and reducing the mismatch of core devices, effectively improving the stability of dynamic random access memory, and has the advantages of simple operation and strong practicality.

[0054] To make the content of this disclosure clearer and easier to understand, the following description, in conjunction with the accompanying drawings, further illustrates the content of this disclosure. Of course, this disclosure is not limited to this specific embodiment, and common substitutions well-known to those skilled in the art are also covered within the scope of protection of this disclosure.

[0055] Figure 3 A schematic diagram of a test structure according to an embodiment of this disclosure is shown. Figure 3 As shown, this test structure includes multiple test units with different channel lengths. Figure 3 As shown, in step 1), the multiple test units with different channel lengths have the same structure. Each test unit includes an active region 110 and a first gate 121 and a second gate 122 located on the active region 110. The active region 110 includes a source region 111 located between the first gate 121 and the second gate 122, a first drain region 112 located on the side of the first gate 121 away from the second gate 122, and a second drain region 113 located on the side of the second gate 122 away from the first gate 121. Each test unit may also include a contact 131 disposed on the source region 111, a contact 132 disposed on the first drain region 112, and a contact 133 disposed on the second drain region 113. Each contact is used to electrically connect with the corresponding test pad. It can be understood that corresponding contacts can also be disposed on the first gate 121 and the second gate 122 to electrically connect with the corresponding test pads. Figure 3As shown, each test unit has a symmetrical structure. The first gate 121 and the second gate 122 are symmetrically distributed on both sides of the source region 111, the first drain region 112 and the second drain region 113 are symmetrically distributed on both sides of the source region 111, and contacts 132 and 133 are symmetrically distributed on both sides of the contact 131. That is to say, Figure 3 The test unit and Figure 1 The test units in the series have the same structure.

[0056] like Figure 3 As shown, each test unit has a symmetrical structure. For example, the first gate 121 and the second gate 122 are symmetrically distributed on both sides of the source region 111, the first drain region 112 and the second drain region 113 are symmetrically distributed on both sides of the source region 111, the distance between the contact 131 and the first gate 121 is approximately equal to the distance between the contact 131 and the second gate 122, and the contacts 132 and 133 are symmetrically distributed on both sides of the contact 131, with the distance between the contact 132 and the first gate 121 being approximately equal to the distance between the contact 133 and the second gate 122. It can be understood that each test unit includes two transistors appearing in pairs (referred to as paired transistors), one corresponding to the first gate 121 and the first drain region 112, and the other corresponding to the second gate 122 and the second drain region 113, and both sharing the source region 111. Paired transistors often have the same structure and process parameters (including size, doping method and doping concentration of the source and drain regions, etc.). It should be noted that the multiple test units in the embodiments of this disclosure have different channel lengths, such as Figure 3 As shown, the channel length of the test cell gradually increases from left to right, and correspondingly, the gate width (corresponding to the channel length) also gradually increases. Furthermore, as the channel length increases sequentially, the active region length a of the test cell also gradually increases.

[0057] Multiple test units have identical structures, and all process parameters unrelated to the channel length are the same, except for the channel length. For example, the process parameters of the test units include channel length, channel width, contact dimensions, contact-to-gate distance, and active region length / width. The active region length 'a' of the multiple test units gradually increases with the channel length, while process parameters unrelated to the channel length, such as channel width, contact dimensions, contact-to-gate distance, and active region width, remain the same.

[0058] It should be noted that process errors are permissible during the fabrication of test units. The fabrication process involves hundreds of steps, such as deposition, photoresist coating, exposure, development, etching, ion implantation, and encapsulation. In each step, instability in the process and layout asymmetry may lead to process errors between different batches or even within the same batch of test units. This is due to process reasons and is difficult to avoid. As long as the produced test units meet the process requirements in each step and meet all test indicators after fabrication, it is acceptable.

[0059] The channel length of one of the multiple test units mentioned above is the target channel length.

[0060] In some embodiments, the channel length of at least one of the plurality of test units is greater than the target channel length, and the channel length of at least one of the plurality of test units is less than the target channel length. That is, the target channel length is neither the maximum channel length nor the minimum channel length, thereby ensuring test accuracy.

[0061] like Figure 3 As shown, in some embodiments, the dynamic random access memory includes seven test units. For example, from left to right, the first channel length of the first test unit is designed to be 50 nm, the second channel length of the second test unit is designed to be 80 nm, the third channel length of the third test unit is designed to be 100 nm, the fourth channel length of the fourth test unit is designed to be 200 nm, the fifth channel length of the fifth test unit is designed to be 500 nm, the sixth channel length of the sixth test unit is designed to be 1000 nm, and the seventh channel length of the seventh test unit is designed to be 2000 nm.

[0062] Although the seven test units are used as an example, this disclosure is not limited thereto. It can be designed with multiple channel lengths, and any design that achieves the beneficial effects of this disclosure is within its protection scope. Those skilled in the art can comprehensively consider the principles of this disclosure and practical applications, as long as the principles of this disclosure are implemented.

[0063] In some embodiments of this disclosure, the above-described design can effectively reduce the size of the test unit, thereby saving valuable space in the dynamic random access memory (DRAM) and allowing more semiconductor devices to be designed within a limited space, thereby improving the performance of the DRAM. On the other hand, it can also be used to monitor process parameters. When an anomaly is detected, the above-described process optimization method can be used to reduce the mismatch of the core device with the target channel length, which helps the DRAM to operate stably for a long time.

[0064] In step 2), the specific steps for obtaining the change curve between the threshold voltage and the channel length based on the multiple test units are as follows:

[0065] Multiple test units with different channel lengths are prepared and tested to detect the threshold voltage of each test unit;

[0066] The variation curves are constructed based on the threshold voltage and channel length of each of the test units.

[0067] In step 3), the process sensitivity corresponding to the target channel length is characterized by the absolute value of the slope corresponding to the target channel length. For example, when the slope corresponding to the target channel length is 1, the slope is greater than 0, so the process sensitivity corresponding to the target channel length is 1; when the slope corresponding to the target channel length is -0.5, the slope is less than 0, and the absolute value is 0.5, that is, the process sensitivity corresponding to the target channel length is 0.5.

[0068] In step 4), the current channel-halo doping ratio is adjusted, specifically including the following steps:

[0069] When the slope is greater than 0, keep the channel doping concentration constant and increase the halo doping concentration; or keep the halo doping concentration constant and decrease the channel doping concentration; or increase the halo doping concentration while decreasing the channel doping concentration.

[0070] When the slope is less than 0, keep the channel doping concentration constant and decrease the halo doping concentration; or keep the halo doping concentration constant and increase the channel doping concentration; or decrease the halo doping concentration while increasing the channel doping concentration.

[0071] In some embodiments, the channel doping type differs from the halo doping type. For example, N-type doping is performed in the channel and P-type doping is performed in the halo; or, P-type doping is performed in the channel and N-type doping is performed in the halo.

[0072] In some embodiments, the ratio of channel doping concentration to halo ring doping concentration is 1:10 to 1:25. The energy range of channel ion implantation is 5 to 15 keV, the energy range of halo ring ion implantation is 30 to 50 keV, the channel ion implantation has no angle, and the angle range of halo ring ion implantation is 10 to 30°.

[0073] The magnitudes of changes in both the channel doping concentration and the halo doping concentration can be determined based on the deviation between the process sensitivity and the first set value. For example, when the deviation is large, the adjustment of the channel doping concentration and / or halo doping concentration can be relatively large; when the deviation is small, the adjustment of the channel doping concentration and / or halo doping concentration can be relatively small. Of course, the magnitudes of changes in both the channel doping concentration and the halo doping concentration can also be set to fixed values.

[0074] When adjusting the channel doping concentration (assuming a constant change in channel doping concentration), a smaller channel length generally results in a smaller change in the threshold voltage, while a larger channel length generally results in a larger change in the threshold voltage. Similarly, when adjusting the halo doping concentration (assuming a constant change in halo doping concentration), a larger channel length generally results in a larger change in the threshold voltage, while a larger channel length generally results in a smaller change in the threshold voltage. For example, increasing / decreasing the channel doping concentration by 1*10-1 12 / cm 2 For smaller channel lengths, the threshold voltage will increase / decrease by 5–15 mV, while for larger channel lengths, it will increase / decrease by 50–100 mV. The halo doping concentration increases / decreases by 1*10⁻⁶ mV. 12 / cm 2 The threshold voltage corresponding to a smaller channel length will increase / decrease by 3–8 mV, while the threshold voltage corresponding to a larger channel length will increase / decrease by 0.1–0.5 mV. For example, the larger channel length is 2 μm or more, and the smaller channel length is 0–500 nm.

[0075] Channel doping typically has an effect on large dimensions, while halo doping has an effect on small dimensions. Therefore, by adjusting the two ion implantation schemes, the slope corresponding to the target channel length can be minimized. By adjusting the ratio of channel ion implantation to halo ion implantation, the variation curve can be continuously adjusted to flatten its slope, thereby improving the mismatch of the core device under different channel lengths and ensuring that the electrical properties of the core device meet the requirements for chip operation.

[0076] For example, Figure 4 A variation curve according to an embodiment of this disclosure is shown. For example... Figure 4 As shown by the dashed line, currently, the slope corresponding to the target channel length L0 is greater than 0, and the process sensitivity corresponding to the target channel length L0 is greater than the first set value. For example, in Figure 4 In the figure, the horizontal axis (i.e., channel length L) is in micrometers (um), and the vertical axis (i.e., threshold voltage Vt) is in millivolts (mV).

[0077] In this case, the first control method is to keep the channel doping concentration constant and increase the halo ring doping concentration. If, after the initial control, the process sensitivity corresponding to the target channel length L0 is still greater than the first set value, and the slope corresponding to the target channel length L0 is still greater than 0 (if the slope corresponding to the target channel length L0 is less than 0 at this time, then it can be referred to...), Figure 5 If the halo doping concentration is adjusted as shown in the embodiment, it can be adjusted again (the change in halo doping concentration can remain unchanged or be reduced accordingly) until the process sensitivity corresponding to the target channel length L0 is not greater than the first set value or the change in process sensitivity corresponding to the target channel length L0 after two adjacent adjustments is not greater than the second set value. For example, in one example, the current channel doping concentration is 1.2*10 12 / cm 2 The halo ring doping concentration is 1.2*10 13 / cm 2 The first setting value is selected as 0.2, the second setting value is selected as 0.03, and the halo ring doping concentration change can be set to 0.05*10. 13 / cm 2 ~0.2*10 13 / cm 2 .

[0078] In this case, the second control method is to keep the halo ring doping concentration constant and reduce the channel doping concentration. If, after the initial control, the process sensitivity corresponding to the target channel length L0 is still greater than the first set value, and the slope corresponding to the target channel length L0 is still greater than 0 (if the slope corresponding to the target channel length L0 is less than 0 at this time, then it can be referred to...), Figure 5 If the channel doping concentration is adjusted again (the change can remain constant or be reduced accordingly) as shown in the embodiment, it can be adjusted again until the process sensitivity corresponding to the target channel length L0 is no greater than the first set value or the change in process sensitivity corresponding to the target channel length L0 after two adjacent adjustments is no greater than the second set value. For example, in one example, the current channel doping concentration is 1.2*10 12 / cm 2 The halo ring doping concentration is 1.2*10 13 / cm 2 The first setting value is selected as 0.2, the second setting value is selected as 0.03, and the channel doping concentration variation can be set to 0.05*10. 12 / cm 2 ~0.2*10 12 / cm 2 .

[0079] In this case, the third control method is to increase the halo ring doping concentration while decreasing the channel doping concentration. If, after the initial control, the process sensitivity corresponding to the target channel length L0 is still greater than the first set value, and the slope corresponding to the target channel length L0 is still greater than 0 (if the slope corresponding to the target channel length L0 is less than 0 at this time, then reference can be made to...), then the process sensitivity corresponding to the target channel length L0 is still greater than the first set value, and the slope corresponding to the target channel length L0 is still greater than 0. Figure 5 If the halo doping concentration is adjusted as shown in the embodiment, further adjustments can be made (the change in halo doping concentration can remain constant or be reduced accordingly, and the change in channel doping concentration can remain constant or be reduced accordingly) until the process sensitivity corresponding to the target channel length L0 is not greater than the first set value or the change in process sensitivity corresponding to the target channel length L0 after two adjacent adjustments is not greater than the second set value. For example, in one example, the current channel doping concentration is 1.2*10 12 / cm 2 The halo ring doping concentration is 1.2*10 13 / cm 2 The first setting is selected as 0.2, the second setting is selected as 0.03, and the halo ring doping concentration variation can be set to 0.05*10. 13 / cm 2 ~0.15*10 13 / cm 2 The channel doping concentration variation can be set to 0.05*10. 12 / cm 2 ~0.15*10 12 / cm 2 .

[0080] Figure 4 The solid line shows the results obtained according to the third control method. After control, the process sensitivity near the target channel length L0 is significantly reduced, which is beneficial for improving the mismatch of core devices with the target channel length.

[0081] For example, Figure 5 A variation curve two according to an embodiment of this disclosure is shown. For example... Figure 5 As shown by the dashed line, currently, the slope corresponding to the target channel length L1 is less than 0, and the process sensitivity corresponding to the target channel length L1 is greater than the first set value. For example, in Figure 5 In the figure, the horizontal axis (i.e., channel length L) is in micrometers (um), and the vertical axis (i.e., threshold voltage Vt) is in millivolts (mV).

[0082] In this situation, the first control method is to keep the channel doping concentration constant and reduce the halo doping concentration; the second control method is to keep the halo doping concentration constant and increase the channel doping concentration; the third control method is to reduce the halo doping concentration while increasing the channel doping concentration. It should be noted that... Figure 5The three control methods shown in the embodiments can be referred to accordingly. Figure 4 The three control methods shown in the embodiments will not be elaborated further here. Of course, if the slope corresponding to the target channel length L1 is greater than 0 during the control process, then... Figure 4 The embodiments shown are used for regulation.

[0083] Figure 5 The solid line shows the results obtained according to the third control method. After control, the process sensitivity near the target channel length L1 is significantly reduced, which is beneficial for improving the mismatch of core devices with the target channel length.

[0084] The above description is merely illustrative and should not be construed as limiting the implementation process of the embodiments of this disclosure. Those skilled in the art can make multiple adjustments based on actual production processes / requirements, as long as the principles of this disclosure are achieved. It should be noted that... Figure 4 , Figure 5 The curves shown are merely schematic representations of overall trends and do not involve specific data or trends. They are for illustrative purposes only and should not be construed as limiting the implementation process of the embodiments of this disclosure.

[0085] In some embodiments, each test unit includes a pair of transistors having the same structure and process parameters, and the channel length of each test unit is any one of the channel lengths of the pair of transistors it includes. If the channel length of a transistor deviates from the target channel length, but the deviation is small, it will not cause a change in the threshold voltage, and is considered not to have caused a mismatch in the paired transistors.

[0086] In some embodiments, the core components of a dynamic random access memory include a sense amplifier and a word line driver.

[0087] In some embodiments, the first set value ranges from [0.1, 0.3]. For example, the first set value can be 0.1, 0.15, 0.2, 0.25, 0.28, or 0.3.

[0088] In some embodiments, the range of the second set value is [0.01, 0.05]. For example, the second set value can be 0.01, 0.02, 0.025, 0.03, 0.04, 0.045 or 0.05.

[0089] For example, the process optimization method may also include the following steps:

[0090] Step 6): Fabricate a semiconductor device according to the final channel-halo doping ratio, wherein the semiconductor device includes the same functional units as the test unit having the target channel length.

[0091] For example, a semiconductor device includes at least one of an inductive amplifier and a word line driver.

[0092] Figure 6 A schematic diagram of a process optimization system according to an embodiment of the present disclosure is shown. Figure 6 As shown, according to some embodiments, a second aspect of this disclosure provides a process optimization system, including:

[0093] The manufacturing apparatus is configured to manufacture multiple test cells with different channel lengths according to the current channel-halo doping ratio;

[0094] The testing apparatus is configured to acquire a curve showing the relationship between the threshold voltage and the channel length based on the plurality of testing units;

[0095] The computing device is configured to determine the process sensitivity corresponding to the target channel length based on the change curve.

[0096] The parameter adjustment device is configured to adjust the current channel-halo ring doping ratio in response to the process sensitivity being greater than a first set value.

[0097] The process optimization system is configured to control the manufacturing device, the testing device, the computing device, and the parameter adjustment device to operate sequentially until the process sensitivity is not greater than the first set value or the change in the process sensitivity between two adjacent times is not greater than the second set value, and the current channel-halo doping ratio is taken as the final channel-halo doping ratio.

[0098] In an optional embodiment, the manufacturing apparatus is further configured to manufacture a semiconductor device according to the final channel-halo doping ratio, wherein the semiconductor device includes the same functional units as the test unit having the target channel length.

[0099] In an optional embodiment, the computing device is further configured to characterize the process sensitivity using the absolute value of the slope corresponding to the target channel length.

[0100] In an optional embodiment, the parameter adjustment device is further configured to, when the slope is greater than 0, keep the channel doping concentration constant and increase the halo doping concentration, or keep the halo doping concentration constant and decrease the channel doping concentration, or increase the halo doping concentration while decreasing the channel doping concentration; and when the slope is less than 0, keep the channel doping concentration constant and decrease the halo doping concentration, or keep the halo doping concentration constant and increase the channel doping concentration, or decrease the halo doping concentration while increasing the channel doping concentration.

[0101] In an optional embodiment, the parameter adjustment device is further configured to determine the magnitude of the change in channel doping concentration and the magnitude of the change in halo doping concentration based on the deviation between the process sensitivity and the first set value.

[0102] In an optional embodiment, the testing device is further configured to detect the threshold voltage of each of the test units and construct the variation curve based on the threshold voltage of each of the test units and the channel length.

[0103] It should be understood that the phrases "one embodiment" or "some embodiments" throughout the specification mean that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "in some embodiments" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0104] It is understood that the terms "first," "second," etc., as used in this disclosure may be used to describe various channel lengths, but these channel lengths are not limited by these terms. These terms are only used to distinguish one channel length from another.

[0105] Although the present disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A process optimization method, characterized in that, include: 1) Based on the current channel-halo doping ratio, fabricate multiple test cells with different channel lengths; 2) Obtain the variation curve between the threshold voltage and the channel length based on the multiple test units; 3) Based on the aforementioned variation curve, determine the process sensitivity corresponding to the target channel length; 4) In response to the process sensitivity being greater than a first set value, adjust the current channel-halo doping ratio; 5) Repeat steps 1) to 4) until the process sensitivity is not greater than the first set value or the absolute value of the difference between two adjacent process sensitivities is not greater than the second set value, and take the current channel-halo doping ratio as the final channel-halo doping ratio.

2. The process optimization method according to claim 1, characterized in that, Determining the process sensitivity corresponding to the target channel length based on the variation curve includes: The absolute value of the slope corresponding to the target channel length is used to characterize the process sensitivity.

3. The process optimization method according to claim 2, characterized in that, The range of the first set value is [0.1, 0.3].

4. The process optimization method according to claim 2 or 3, characterized in that, The range of the second set value is [0.01, 0.05].

5. The process optimization method according to claim 2 or 3, characterized in that, Adjusting the current channel-halo doping ratio includes: When the slope is greater than 0, keep the channel doping concentration constant and increase the halo doping concentration, or keep the halo doping concentration constant and decrease the channel doping concentration, or increase the halo doping concentration while decreasing the channel doping concentration. When the slope is less than 0, the channel doping concentration is kept constant while the halo doping concentration is decreased, or the halo doping concentration is kept constant while the channel doping concentration is increased, or the halo doping concentration is decreased while the channel doping concentration is increased.

6. The process optimization method according to claim 5, characterized in that, The magnitude of the change in channel doping concentration and the magnitude of the change in halo doping concentration are both determined based on the deviation between the process sensitivity and the first set value.

7. The process optimization method according to any one of claims 1-3, characterized in that, Based on the multiple test units, the variation curve between the threshold voltage and the channel length is obtained, including: Detect the threshold voltage of each of the test units; The variation curves are constructed based on the threshold voltage and channel length of each of the test units.

8. The process optimization method according to any one of claims 1-3, characterized in that, The plurality of test units have the same structure, and except for the channel length, all other process parameters of the plurality of test units that are not related to the channel length are the same.

9. The process optimization method according to any one of claims 1-3, characterized in that, The channel length of one of the multiple test units is the target channel length.

10. The process optimization method according to claim 9, characterized in that, The channel length of at least one of the plurality of test units is greater than the target channel length, and the channel length of at least one of the plurality of test units is less than the target channel length.

11. The process optimization method according to any one of claims 1-3, characterized in that, Each of the test units includes a pair of transistors having the same structure and process parameters, and the channel length of each test unit is the channel length of any one of the pair of transistors it includes.

12. The process optimization method according to claim 11, characterized in that, Also includes: 6) Fabricate a semiconductor device according to the final channel-halo doping ratio, wherein the semiconductor device includes the same functional units as the test unit having the target channel length.

13. The process optimization method according to claim 12, characterized in that, The semiconductor device includes at least one of a sensing amplifier and a word line driver.

14. A process optimization system, characterized in that, include: The manufacturing apparatus is configured to manufacture multiple test cells with different channel lengths according to the current channel-halo doping ratio; The testing apparatus is configured to acquire a curve showing the relationship between the threshold voltage and the channel length based on the plurality of testing units; The computing device is configured to determine the process sensitivity corresponding to the target channel length based on the change curve. The parameter adjustment device is configured to adjust the current channel-halo ring doping ratio in response to the process sensitivity being greater than a first set value. The process optimization system is configured to control the manufacturing device, the testing device, the computing device, and the parameter adjustment device to operate sequentially until the process sensitivity is not greater than the first set value or the absolute value of the difference between two adjacent process sensitivities is not greater than the second set value, and the current channel-halo doping ratio is taken as the final channel-halo doping ratio.

15. The process optimization system according to claim 14, characterized in that, The manufacturing apparatus is also configured to manufacture a semiconductor device according to the final channel-halo doping ratio, wherein the semiconductor device includes the same functional units as the test unit having the target channel length.

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