Three-dimensional memory and methods of making the same

Abstract

The application provides a three-dimensional memory and a preparation method thereof. The method comprises: forming a stack structure on a substrate, wherein the stack structure comprises a storage region, a step region between the storage regions, and a connection region, the step region comprises a first step region and a second step region with different heights in the extending direction of the step region, and the height of the first step region is greater than that of the second step region; depositing a filling layer above the stack structure; performing first etching on the filling layer above the storage region, the first step region, and part of the connection region; performing second etching on the stack structure to remove part of the filling layer above the storage region and reduce the height of the filling layer above the storage region; and performing planarization on the stack structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor design and manufacturing, and more specifically, to the structure of a three-dimensional memory (3D NAND) and its fabrication method. Background Technology

[0002] Three-dimensional memory comprises a stacked structure of alternating gate and insulating layers. The central region of this stacked structure can be further divided into a memory region (Giant block, GB) containing the memory array, a staircase structure (SS) with multiple steps, and a connection region (Great wall, GW) located on one side of the steps, perpendicular to the direction of the staircase structure's extension. After forming the staircase structure, it needs to be filled to form a fill layer. However, after forming the fill layer, planarization is usually required to obtain a flat surface for subsequent processes. Therefore, the fill layer of the memory needs to be etched and chemically mechanically polished (CMP).

[0003] As the demand for integration and data storage density continues to increase, the number of gate layers and insulating layers stacked in the stacked structure increases, and the step area also increases. Therefore, the thickness of the deposited fill layer also increases, which puts more strain on the polishing equipment. Generally, two chemical mechanical polishing processes are required, and the time required for chemical mechanical polishing is long, reducing production efficiency.

[0004] Therefore, how to quickly remove the filler layer and obtain a smooth three-dimensional memory surface is a problem that urgently needs to be solved. Summary of the Invention

[0005] Some embodiments of this application provide a three-dimensional memory and a method for its fabrication that can at least partially solve the problems existing in the prior art.

[0006] According to one aspect of this application, a method for fabricating a three-dimensional memory is provided, the method comprising: forming a stacked structure on a substrate, wherein the stacked structure includes storage regions, step regions located between the storage regions, and connection regions, the step regions including a first step region and a second step region of different heights in their extending direction, the height of the first step region being greater than the height of the second step region; depositing a fill layer over the stacked structure; performing a first etching on the fill layer located over the storage regions, the first step regions, and a portion of the connection regions, wherein, in a direction perpendicular to the substrate, the height of the first step region is greater than the height of the second step region; performing a second etching on the stacked structure to remove a portion of the fill layer located over the storage regions, reducing the height of the fill layer located over the storage regions; and planarizing the stacked structure.

[0007] In one embodiment of this application, the first etching is photolithography, and the photolithography step may include: depositing a photoresist layer over the filler layer; disposing a mask with a mask pattern over the photoresist layer; patterning the photoresist layer via the mask; and etching the filler layer located over the storage region, the first step region, and a portion of the connection region via the patterned photoresist layer.

[0008] In one embodiment of this application, the storage region includes an etch stop layer disposed thereon, and the second etching of the stacked structure may further include: removing the fill layer located above the storage region to expose the etch stop layer.

[0009] In one embodiment of this application, the step region includes a plurality of step substructures, and the connecting region includes a plurality of connecting substructures. The step substructures and the connecting substructures are distributed alternately in a direction perpendicular to the extension of the step region, wherein the number of connecting substructures is greater than the number of step structures.

[0010] In one embodiment of this application, the mask pattern of the mask plate has openings above the storage area, the step substructure located in the first step area, and the connecting substructure located between adjacent step structures.

[0011] In one embodiment of this application, the mask pattern of the mask plate has a chamfer at the opening at the connection between the step substructure in the first step region and the outermost connecting substructure.

[0012] In one embodiment of this application, the mask pattern of the mask plate does not have openings in the second step region and between the second step region and the bridging region.

[0013] In one embodiment of this application, the width of the opening provided above the connecting substructure located between adjacent step substructures is less than or equal to the width of the corresponding connecting substructure.

[0014] In one embodiment of this application, after etching the fill layer according to the patterned mask, the method may further include: removing the photoresist layer.

[0015] This application also provides a three-dimensional memory, which may include: a substrate; a stacked structure located on the substrate and including a storage region, a step region located between the storage regions, and a connection region, wherein the storage region includes an etch stop layer disposed thereon, the step region includes a first step region and a second step region with different heights, the height of the first step region being greater than the height of the second step region; and a filling layer covering the step region and the connection region.

[0016] According to the three-dimensional memory and its fabrication method according to the embodiments of this application, the filling layer is etched twice. The first etching preferentially removes the filling layer above the storage region, the first step region, and the higher portion of the connecting region. Then, the filling layer above the storage region is removed again by the second etching, further reducing the grinding range. To a certain extent, this can reduce the time of chemical mechanical polishing (CMP), save material consumption during the grinding process, and further reduce production costs. Attached Figure Description

[0017] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Wherein:

[0018] Figure 1 This is a flowchart of a three-dimensional memory fabrication method according to an embodiment of this application;

[0019] Figure 2 This is a schematic XY plane view of a stacked structure formed on a substrate according to an exemplary embodiment of this application;

[0020] Figure 3 This is a cross-sectional schematic diagram showing the formation of a multilayer structure on a substrate according to an exemplary embodiment of this application;

[0021] Figure 4 This is a cross-sectional view of a stepped region formed on a substrate according to an exemplary embodiment of this application;

[0022] Figure 5 This is a cross-sectional view of the filling layer after its formation according to an exemplary embodiment of this application;

[0023] Figure 6 This is a schematic diagram of a first photomask according to an exemplary embodiment of this application;

[0024] Figure 7 This is a schematic cross-sectional view of the memory after the first etching according to an exemplary embodiment of this application;

[0025] Figure 8 A schematic cross-sectional view of the memory after a second etching according to an exemplary embodiment of this application; and

[0026] Figure 9 This is a cross-sectional schematic diagram of a planarized memory according to an exemplary embodiment of this application. Detailed Implementation

[0027] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0028] In the accompanying drawings, the size, dimensions, and shapes of the elements have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not strictly to scale. As used herein, the terms “approximately,” “about,” and similar terms are used to indicate approximation, not degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art. Furthermore, the order in which the steps are described in this application does not necessarily indicate the order in which these steps occur in actual operation, unless otherwise expressly defined or deduced from the context.

[0029] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0030] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0031] It should be noted that, where there is no conflict, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0032] Figure 1 This is a flowchart of a three-dimensional memory fabrication method according to an embodiment of this application. Figure 1 As shown, this application provides a method 1000 for fabricating a three-dimensional memory, comprising:

[0033] Step S100: Form a stacked structure on the substrate, wherein the stacked structure includes a storage region, a step region located between the storage regions, and a connection region, and the step region includes a first step region and a second step region with different heights, wherein the height of the first step region is greater than the height of the second step region;

[0034] Step S200: Deposit a filler layer on top of the stacked structure;

[0035] Step S300: Perform the first etching on the filling layer located above the storage region, the first step region, and part of the connection region;

[0036] Step S400: Perform a second etching on the stacked structure to remove part of the fill layer located above the memory region, reducing the height of the fill layer located above the memory region; and

[0037] Step S500: Planarize the stacked structure.

[0038] The following will combine Figures 2 to 9 The specific processes for each step of the above preparation method 1000 are described in detail.

[0039] First, according to some embodiments of this application, the method 1000 for fabricating a three-dimensional memory starts from step S100, in which a stacked structure is formed on a substrate. The stacked structure includes a storage region, a step region located between the storage regions, and a connection region. The step region includes a first step region and a second step region with different heights.

[0040] A three-dimensional memory may include a storage area (Giant block, GB) and a staircase structure (SS) connecting the storage areas. The storage area GB is used for storing information, and the staircase structure SS is located in the middle of the storage area GB and is used to transmit signals to the storage area GB to realize read, write, erase and other operations of the storage area GB. Figure 2 This is a schematic XY plane view of a stacked structure formed on a substrate according to an exemplary embodiment of this application. Figure 2 As shown, in the XY plane direction, the stacked structure may include storage areas GB, connecting areas (Great Wall, abbreviated as GW), and stepped areas SS. The storage areas GB are arranged opposite each other along the X direction, and the stepped areas SS and GW are located between and connected to the two storage areas GB. The stepped area SS includes multiple stepped substructures, and the connecting area GW includes multiple connecting substructures. In the direction perpendicular to the extension of the stepped areas SS, i.e., the Y direction, the stepped substructures and connecting substructures are distributed alternately. In the direction of the extension of the stepped areas, i.e., the X direction, the stepped areas SS may include a first stepped area SS1 and a second stepped area SS2, wherein the height of the first stepped area SS1 is greater than the height of the second stepped area SS2. Those skilled in the art will understand that... Figure 2 This is a schematic diagram of the XY plane portion after the stacked structure is completed. The XY plane may also include other storage areas, step areas, and connection areas.

[0041] Figure 3 This is a cross-sectional schematic diagram showing the formation of a multilayer structure on a substrate according to an exemplary embodiment of this application. Figure 3 As shown, a stacked structure 120 is formed on a substrate 110. The substrate 110 can be any suitable semiconductor material, such as group III-V compounds such as single-crystal silicon (Si), single-crystal germanium (Ge), silicon-germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), or germanium-on-insulator (GOI). It is worth noting that the substrate 110 of this application can also be prepared using at least one of other semiconductor materials known in the art.

[0042] The laminated structure 120 includes alternately stacked insulating layers 121 and sacrificial layers 122. The thicknesses of the multiple sacrificial layers 122 may be the same or different, and the thicknesses of the multiple insulating layers 121 may also be the same or different. The thicknesses of the insulating layers 121 and sacrificial layers 122 can be set according to specific process requirements. Furthermore, the laminated structure 120 may include multiple pairs of alternately stacked insulating layers 121 and sacrificial layers 122. For example, the laminated structure 120 may include 64 pairs, 128 pairs, or more than 128 pairs of insulating layers 121 and sacrificial layers 122. Although a specific number of pairs of insulating layers 121 and sacrificial layers 122 is exemplified here, other numbers of pairs of insulating layers 121 and sacrificial layers 122 may be used in other embodiments, and this application does not limit this.

[0043] The stacked structure 120 may also include an etch stop layer 123, which may be deposited over the alternately stacked insulating layer 121 and sacrificial layer 122 using thin film deposition processes such as CVD, PVD, ALD or any combination thereof. The etch stop layer 123 can stop the etching process at this layer, thereby facilitating better control of the etching depth and protecting the underlying insulating layer 121 and sacrificial layer 122 from the effects of etching.

[0044] In some embodiments, the materials used for the insulating layer 121 and the sacrificial layer 122 may have different etching selectivity ratios. The sacrificial layer 122 may be removed and replaced by a conductive material in subsequent processes to form the gate layer, i.e., the word line. Optionally, the material of the insulating layer 121 may include, for example, silicon oxide, and the material of the sacrificial layer 122 may include, for example, silicon nitride. The more insulating layers 121 and sacrificial layers 122 in the stacked structure 120, the higher the integration density and the more memory cells formed therefrom. The number of stacked layers and the stacking height of the stacked structure 120 can be designed according to actual memory requirements, and this application does not impose specific limitations on this.

[0045] As the demand for storage capacity in 3D memory continues to increase, the size of memory stacks is gradually increasing. To overcome the limitations of traditional processes, dual-stack or multi-stack technologies can be used. This involves sequentially stacking N (N≥2) sub-stacks along the thickness of the stack to form a layered structure. Each sub-stack may include multiple alternately stacked sacrificial layers 122 and insulating layers 121. The number of layers in each sub-stack may be the same or different. This application uses a single stack as an example; however, those skilled in the art will understand that subsequent fabrication processes can be performed based on either a multi-stack or single-stack structure.

[0046] Figure 4 This is a cross-sectional view showing the formation of a stepped region on a substrate according to an exemplary embodiment of this application. Figure 4As shown, by performing multiple "trimming-etching" cycles on the etch stop layer 123, part of the insulating layer 121, and part of the sacrificial layer 122 in the stepped region of the stacked structure 120, the stacked structure 120 can be made to have one or more inclined edges, forming a stepped region 140. In the stepped region 140, the length of the insulating layer 121 and sacrificial layer 122 pair on the side away from the substrate 110 is less than the length of the insulating layer 121 and sacrificial layer 122 pair on the side closer to the substrate 110. Each pair of insulating layer 121 and sacrificial layer 122 forms a step, and multiple pairs of insulating layer 121 and sacrificial layer 122 constitute the stepped region 140.

[0047] Then, step S200 is performed to deposit a filler layer 210 on top of the stacked structure 120. Figure 5 This is a cross-sectional view showing the filling layer after it has been formed according to an exemplary embodiment of this application. Figure 5 As shown, a filler layer 210 can be deposited over the stacked structure 120 using thin film deposition processes such as CVD, PVD, ALD, or any combination thereof. The filler layer 210 may include a first sub-filler layer 211 and a second sub-filler layer 212. In an exemplary embodiment of this application, the material of the first sub-filler layer 211 may include high-density plasma (HDP), and the material of the second sub-filler layer 212 may include tetraethyl orthosilicate (TEOS). In this embodiment, both the first sub-filler layer 211 and the second sub-filler layer 212 are filler layers; therefore, in subsequent steps, the first sub-filler layer 211 and the second sub-filler layer 212 will be collectively referred to as filler layer 210. Those skilled in the art will understand that the filler layer in this application consists of two layers, a first sub-filler layer and a second sub-filler layer, and may also include other numbers of filler layers; this application is not limited thereto.

[0048] Then, step S300 is executed to perform a first etching on the filling layer located above the storage region, the first step region, and the partial connection region. In an exemplary embodiment of this application, the first etching can be photolithography, in which a photoresist layer (PR) can be covered on the filling layer 210, a mask with a mask pattern is set on the photoresist layer, the photoresist layer is patterned through the mask, and then the filling layer 210 is further etched through the patterned photoresist layer. Since photoresist is generally divided into positive and negative photoresist, and the settings of the mask for positive and negative photoresist are exactly opposite, this application uses positive photoresist as an example for explanation. Figure 6 This is a schematic diagram of a first photomask according to an exemplary embodiment of this application. Figure 6 As shown, in the direction perpendicular to the extension of the step region SS, i.e., the Y direction, the connecting region GW includes multiple connecting substructures GW. 11~GWnn, the stepped region SS includes multiple stepped substructures SS 11 ~SSmm, and the number of connecting substructures is greater than the number of stepped substructures. The stepped substructures and connecting substructures are distributed alternately, and the outermost part of the alternating distribution of stepped substructures and connecting substructures is the connecting substructure GW. 11 The patterned mask has multiple openings, including an opening 10 above the storage region GB, the step substructure located in the first step region SS1, and the connecting substructure alternating with the step substructure located in the first step region SS1. The photoresist layer is patterned through the opening 10 of the mask, and the storage region GB, the step substructure of the first step region SS1, and the connecting substructure alternating with the step substructure located in the first step region SS1 are further etched. In an exemplary embodiment of this application, the mask is used for the first step region and the outermost connecting substructure GWnn and the connecting substructure GW. 11 The opening 10 at the connection point has a chamfer, such as Figure 6 As shown in the example embodiment of this application, the opening 10 is a certain distance from the edge of the storage region GB. During the etching of the filling layer via patterned photoresist, either dry etching or wet etching can be used. For example, during dry etching, the incident angle of the plasma and the potential for plasma sputtering from the opening edge can cause the actual etched size to be larger than the opening size of the mask. Therefore, the opening 10's distance from the edge of the storage region GB can, to a certain extent, protect the chamfered portion of the storage region GB and the first step region SS1 during subsequent etching processes, preventing over-etching and damage to the memory's performance.

[0049] In an exemplary embodiment of this application, in the direction perpendicular to the extension of the step region, i.e., the Y direction, the mask has an opening width above the internal connecting substructure that is less than or equal to the width of the connecting substructure. For example... Figure 6 The opening 20 shown, except for the outermost connecting substructure GWnn and connecting substructure GW 11 In addition, openings 20 are provided above the remaining connecting substructures, and the width of the openings 20 is less than or equal to the width of the connecting substructures in the direction perpendicular to the step region. During the etching of the filling layer via patterned photoresist, either dry etching or wet etching can be used. For example, in dry etching, the incident angle of the plasma and the potential for plasma sputtering from the opening edge can cause the actual etched size to be larger than the opening size of the mask. Therefore, the width of the openings 20 being less than or equal to the width of the connecting substructures can, to some extent, protect the second step region SS2 during subsequent etching processes, preventing over-etching and damage to the memory performance.

[0050] In an exemplary embodiment of this application, the mask plate has a step substructure SS in the second step region SS2. 11 No opening is provided above SSmm. In the direction perpendicular to the substrate, the height of the step substructure in the second step region SS2 is less than the height of the step structure in the first step region SS1. Therefore, after depositing the fill layer, the sum of the heights of the step substructure in the second step region SS2 and the fill layer is less than the sum of the heights of the step structure in the first step region SS1 and the fill layer. Therefore, during the first photolithography process, the step substructure in the second step region SS2 can be protected to prevent over-etching of the step substructure in the second step region SS2 during subsequent etching processes, which could affect the memory's performance.

[0051] In an exemplary embodiment of this application, the etching depth can be further controlled by the etching time. In the direction perpendicular to the substrate, i.e., the Z direction, the maximum depth of the first etching can be the position of the lowest point of the first step region SS1, wherein the position of the lowest point of the first step region SS1 is higher than the height of the storage region GB. By controlling the etching height, the filler layer located in the first step region can be removed as much as possible, reducing the time of chemical mechanical polishing (CMP) in subsequent processes.

[0052] The filling layer 210 is etched through the mask with the aforementioned opening. The cross-sectional view of the etched memory is shown below. Figure 7 As shown. Due to Figure 7 This is a cross-sectional view along the XZ direction, therefore the connection area is not shown. In an exemplary embodiment of this application, the first etching may be followed by removing the photoresist layer and cleaning it. Those skilled in the art will understand that in the above etching method, the photoresist used is positive photoresist, and the mask is set to match the positive photoresist. The photoresist in this application may also be negative photoresist, and the mask is set to match the negative photoresist. This application does not impose any limitations on this.

[0053] According to an exemplary embodiment of this application, by etching the filling layer above the storage region GB, the first step region SS1, and the connection region GW, the higher portion of the filling layer is removed, which helps to reduce the time of chemical mechanical polishing (CMP) in subsequent processes, thus saving costs to a certain extent. Furthermore, the mask has chamfered openings at the edges of the storage region GB and the first step region SS1. During subsequent etching, the chamfered portions of the storage region GB and the first step region SS1 can be protected to a certain extent, preventing over-etching and damage to memory performance. No opening is provided for the lower-height second step region SS2, which better protects the filling layer at the lower height, resulting in a smoother top surface during subsequent CMP. The chamfered openings at the connection between the step substructure and the outermost connection substructure of the first step region in the direction perpendicular to the extension of the step region SS better protect the chamfered portion in subsequent processes, thus improving memory yield to a certain extent.

[0054] Then, steps S400 and S500 are performed to conduct a second etching on the stacked structure, removing part of the fill layer above the memory region and reducing the height of the fill layer above the memory region. In an exemplary embodiment of this application, the second etching can be photolithography. For example, a photoresist layer (PR) can be covered on the fill layer 210 after the first etching. A mask with an opening above the memory region GB is provided on the photoresist layer. Then, the photoresist layer is patterned through the opening of the mask, and the fill layer 210 is etched through the patterned photoresist layer to remove part of the fill layer 210 above the memory region, further reducing the height of the fill layer above the memory region. Exemplarily, the fill layer 210 above the memory region can be removed by controlling the etching time until the etching stop layer 123 is exposed. This application describes the case of exposing the etching stop layer after the second etching as an example. The cross-sectional view of the memory after the second etching is shown below. Figure 8 As shown.

[0055] According to an exemplary embodiment of this application, by etching the filler layer above the storage region again, the height of the filler layer above the storage region is further reduced in the direction perpendicular to the substrate, thereby reducing the time of subsequent chemical mechanical polishing (CMP). Furthermore, by controlling the etching time to remove the filler layer above the storage region until the etching stop layer is exposed, not only is the height of the filler layer above the storage region reduced in the direction perpendicular to the substrate, but the area to be covered by subsequent CMP is also further reduced. This reduces the time of subsequent CMP and also saves material consumption during the polishing process, further reducing production costs.

[0056] In an exemplary embodiment of this application, the second etching may further include removing the photoresist layer and cleaning it. Figure 9 This is a cross-sectional view of a planarized memory according to an exemplary embodiment of this application. Figure 9 As shown in the exemplary embodiments of this application, the method for fabricating a three-dimensional memory may further include planarizing the stacked structure after the second etching. For example, chemical mechanical polishing (CMP) or other processes may be used to further planarize the surface of the filling layer 210, so that the filling layer 210 can provide a substantially flat surface for subsequent processes.

[0057] According to an exemplary embodiment of this application, by performing two etching processes on the filler layer, the first etching preferentially removes the higher portion of the filler layer, and then the second etching removes the filler layer above the storage area, the grinding range is further reduced. To a certain extent, this can reduce the time of chemical mechanical polishing (CMP), save material consumption during the grinding process, and further reduce production costs. Furthermore, by rationally setting the shape of the mask, damage to the memory caused by excessive etching can be avoided to a certain extent, further improving production yield.

[0058] This application also provides a three-dimensional memory. Figure 9 This is a cross-sectional view of an exemplary three-dimensional memory according to this application. Figure 9 As shown, the memory of this application may include a substrate 110, a stacked structure 120, and a fill layer 210. The stacked structure 120 is located above the substrate 110 and includes a storage region GB, a stepped region SS connected to the storage region, and a connection region GW (not shown) located between the storage regions GB. The stepped region SS includes a first stepped region SS1 and a second stepped region SS2 with different heights, wherein the height of the first stepped region SS1 is greater than the height of the second stepped region SS2. The storage region GB is used for storing information, and the stepped region SS is located in the middle of the storage region GB and is used to transmit signals to the storage region GB to realize read, write, erase, and other operations on the storage region GB. The fill layer 210 is located above the stepped region SS and the connection region GW. In an exemplary embodiment of this application, the fill layer 210 may include a first sub-fill layer 211 and a second sub-fill layer 212. The material of the first sub-filling layer 211 may include high-density plasma (HDP), and the material of the second sub-filling layer 212 may include tetraethyl orthosilicate (TEOS). In the embodiments of this application, both the first sub-filling layer 211 and the second sub-filling layer 212 are filling layers, and therefore are collectively referred to as filling layer 210. Those skilled in the art will understand that the filling layer in this application consists of two layers, the first sub-filling layer and the second sub-filling layer, and may also include other numbers of filling layers; this application is not limited thereto.

[0059] Since the content and structure described in the preparation method 1000 above can be fully or partially applied to the three-dimensional memory described here, related or similar content will not be repeated.

[0060] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the invention. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for fabricating a three-dimensional memory, characterized in that, The method includes: A stacked structure is formed on a substrate, wherein the stacked structure includes at least two storage regions, a step region located between the storage regions, and a connection region, the storage regions being connected to the connection region, the storage regions including an etch stop layer disposed thereon, and the step region including a first step region and a second step region with different heights in its extending direction, the first step region having a greater height than the second step region; A filler layer is deposited on top of the stacked structure; A first etching is performed on the filling layer located above the storage region, the first step region, and a portion of the connection region; A second etching is performed on the stacked structure to remove part of the fill layer above the memory region, reduce the height of the fill layer above the memory region, and expose the etch stop layer; and The stacked structure is planarized.

2. The method according to claim 1, characterized in that, The first etching is photolithography, and the photolithography steps include: A photoresist layer is deposited over the filler layer; A mask with a mask pattern is disposed above the photoresist layer; Patterning the photoresist layer using the photomask; and The fill layer located above the storage region, the first step region, and a portion of the connection region is etched via the patterned photoresist layer.

3. The method according to claim 2, characterized in that, The stepped area includes multiple stepped substructures, and the connecting area includes multiple connecting substructures. The stepped substructures and the connecting substructures are distributed alternately in a direction perpendicular to the extension of the stepped area, wherein the number of connecting substructures is greater than the number of stepped substructures.

4. The method according to claim 3, characterized in that, The mask pattern of the mask plate has openings above the storage area, the step substructure located in the first step area, and the connecting substructure located between adjacent step structures.

5. The method according to claim 4, characterized in that, The mask pattern of the mask plate has a chamfer at the opening at the connection between the step substructure located in the first step region and the outermost connecting substructure.

6. The method according to claim 3, characterized in that, The mask pattern of the mask plate does not have an opening at the step substructure located in the second step region.

7. The method according to claim 4, characterized in that, The width of the opening located above the connecting substructure between adjacent step substructures is less than or equal to the width of the corresponding connecting substructure.

8. The method according to any one of claims 2-7, characterized in that, After etching the filling layer according to the patterned mask, the method further includes: Remove the photoresist layer.

9. A three-dimensional memory, characterized in that, The three-dimensional memory includes: Substrate; A stacked structure is located on the substrate and includes at least two storage regions, a step region between the storage regions, and a connection region, wherein the storage regions are connected to the connection region, each storage region includes an etch stop layer disposed thereon, and the step region includes a first step region and a second step region of different heights, wherein the height of the first step region is greater than the height of the second step region; and A filling layer covers the stepped area and the connecting area.

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