A memory and a method for manufacturing the same, a storage system

Abstract

The application discloses a memory and a preparation method thereof, and a storage system. A first stop layer covering a first region is formed on a stack layer, and then a patterned hard mask layer is formed on the stack layer. The patterned hard mask layer includes a first opening pattern located directly above the first stop layer and a channel hole pattern corresponding to a second region. Then, a channel hole corresponding to the channel hole pattern is formed based on the patterned hard mask layer. The first stop layer covering the first region can ensure that the stack layer of the first region is not etched. The channel hole pattern is etched at a position corresponding to the second region, and the first opening pattern is etched at a position corresponding to the first region. Therefore, when the stack layer is etched, at the boundary between the region where the channel hole needs to be formed and the region where the channel hole does not need to be formed, the influence of the accumulation of residual molecules at the boundary on the etching of the stack layer can be reduced, and thus the channel hole etching process of the edge of the second region can be improved, and the etching difficulty can be reduced.

Description

Technical Field

[0001] This invention relates generally to the field of electronic devices, and more specifically to a memory, a method for its fabrication, and a storage system. Background Technology

[0002] In 3D NAND, vias are arranged in an array and divided into multiple memory blocks or memory fingers by multiple gate line slots. Generally, multiple rows of vias (e.g., 9 rows) can be arranged between any two adjacent gate line slots, and the spacing between the multiple rows of vias is equal. The vias adjacent to the gate line slots can be called outer vias (which may include one, two or more rows).

[0003] External holes are prone to various problems during the etching process, and the etching of channel holes is more difficult. Summary of the Invention

[0004] The purpose of this invention is to provide a memory and its fabrication method and storage system, which aims to improve the etching process of the channel hole at the edge of the second region and reduce the etching difficulty.

[0005] In a first aspect, embodiments of the present invention provide a preparation method comprising: Provide substrate; A stacked layer is formed on the substrate, the stacked layer including a first region extending along a first direction and a second region adjacent to the first region; A first stop layer is formed on the stacked layers, the first stop layer covering the first region; A patterned hard mask layer is formed on the stacked layer, the patterned hard mask layer covering the first stop layer, and the patterned hard mask layer includes a first opening pattern located directly above the first stop layer, and a channel hole pattern located on the stacked layer corresponding to the second region; The stacked layers are etched based on the patterned hard mask layer to form a channel hole corresponding to the channel hole pattern in the second region.

[0006] Furthermore, the etch selectivity ratio of the first stop layer relative to the patterned hard mask layer is less than 1.

[0007] Furthermore, the first region is used to form grid line gaps.

[0008] Furthermore, the step of forming a first stop layer on the stacked layers includes: A first stop material is deposited on the stacked layer, the first stop material covering the first region and the second region; The first stop material located in the second region is etched to form the first stop layer located in the first region.

[0009] Furthermore, the step of forming a first stop layer on the stacked layers includes: An insulating layer is formed on the stacked layers; The insulating layer is etched to form an opening corresponding to the first region; The first stop layer is filled into the opening.

[0010] Furthermore, the depth of the opening is less than the thickness of the insulating layer.

[0011] Furthermore, the width of the opening is greater than the width of the first region.

[0012] Furthermore, the step of forming a patterned hard mask layer on the stacked layers includes: A hard mask layer is formed on the stacked layers, the hard mask layer covering the first stop layer; The hard mask layer is etched to form the first opening pattern and the channel hole pattern.

[0013] Furthermore, the stacked layer also includes a third region located around the second region; the method for fabricating the memory further includes: forming a second stop layer on the stacked layer, the second stop layer covering the third region; After the patterned hard mask layer is formed, the patterned hard mask layer also covers the second stop layer, and the patterned hard mask layer also includes a second opening pattern located directly above the second stop layer.

[0014] Furthermore, the first opening pattern and the second opening pattern are formed using the same mask.

[0015] Furthermore, the third region surrounds the second region.

[0016] Furthermore, after the step of etching the stacked layers based on the patterned hard mask layer, the method for fabricating the memory further includes: Remove the patterned hard mask layer and the first stop layer.

[0017] Furthermore, the first opening pattern includes a plurality of virtual holes located directly above the first stop layer.

[0018] Furthermore, the first opening pattern is a groove extending along the first direction.

[0019] Furthermore, the material of the first stop layer includes one of tungsten, polycrystalline silicon, silicon nitride, silicon oxynitride, and aluminum oxide.

[0020] In a second aspect, embodiments of the present invention provide a memory, comprising: Substrate; A stacked structure is located on the substrate and includes a first region extending along a first direction and a second region adjacent to the first region; Multiple channel structures, a stacked structure that runs through the second region.

[0021] Thirdly, embodiments of the present invention provide a storage system, including: The memory as described in the second aspect; A controller, electrically connected to the memory, is used to control the memory to store data.

[0022] The beneficial effects of this invention are as follows: It provides a memory and its fabrication method and memory system. First, a stacked layer is formed on a substrate. The stacked layer includes a first region extending along a first direction and a second region adjacent to the first region. Then, a first stop layer covering the first region is formed on the stacked layer. Next, a patterned hard mask layer covering the first stop layer is formed on the stacked layer. The patterned hard mask layer includes a first opening pattern located directly above the first stop layer and a channel hole pattern located on the stacked layer corresponding to the second region. Finally, the stacked layer is etched based on the patterned hard mask layer to form a channel hole corresponding to the channel hole pattern in the second region. The first stop layer covering the first region ensures that the stacked layer in the first region is not etched, and only the channel hole is etched in the second region. Since the channel hole pattern is etched at the location corresponding to the second region and the first opening pattern is etched at the location corresponding to the first region during the formation process of the patterned hard mask layer, the height difference between the first region where the channel hole is not needed and the second region where the channel hole is needed can be avoided. Therefore, when etching the stacked layers, the accumulation of residual molecules at the interface can be reduced, which can affect the etching of the stacked layers and improve the etching process of the channel holes at the edge of the second region, thus reducing the etching difficulty. Attached Figure Description

[0023] The technical solution and other beneficial effects of the present invention will become apparent from the following detailed description of specific embodiments of the invention, in conjunction with the accompanying drawings.

[0024] Figure 1 This is a schematic flowchart of the method for fabricating a memory according to an embodiment of the present invention; Figures 2a-2j This is a schematic diagram of the structure of the memory provided in the embodiment of the present invention during the manufacturing process; Figures 3a-3i This is a schematic diagram of the structure of a memory during its fabrication process according to another embodiment of the present invention; Figure 4 This is a schematic diagram of the structure of the memory provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of the storage system provided in an embodiment of the present invention. Detailed Implementation

[0025] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0026] It should be understood that although the terms first, second, etc., may be used herein to describe various components, these components should not be limited to these terms. These terms are used to distinguish one component from another. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component, without departing from the scope of the invention.

[0027] It should be understood that when a component is said to be "on" or "connected" to another component, it can be directly on or connected to the other component, or there may be an inserted component. Other terms used to describe relationships between components should be interpreted in a similar manner.

[0028] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer may extend over the entirety of an underlying or upper layer structure, or may have a extent smaller than that of the underlying or upper layer structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive layers and contact layers (where contacts, interconnects, and one or more dielectric layers are formed).

[0029] It should be noted that the illustrations provided in the embodiments of the present invention are only schematic representations of the basic concept of the present invention. Although the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components, the form, quantity and proportion of each component can be arbitrarily changed in actual implementation, and the layout of the components may also be more complex.

[0030] This paper uses a Cartesian coordinate system (X, Y, and Z) to represent the orientation of the memory, where the XY plane is parallel to the substrate and the Z direction is perpendicular to the substrate.

[0031] Please see Figure 1 , Figure 1 This is a schematic flowchart illustrating the method for fabricating a memory according to an embodiment of the present invention. Please also refer to... Figures 2a-2j , Figures 2a-2j This is a schematic diagram of the structure of the memory provided in the embodiment of the present invention during the fabrication process. The fabrication method of the memory includes steps S1-S5.

[0032] Please see Figure 1 Steps S1-S2 and Figure 2a .

[0033] Step S1: Provide substrate 10.

[0034] The substrate 10 can be a semiconductor substrate, such as silicon (Si), germanium (Ge), SiGe substrate, silicon on insulator (SOI), or germanium on insulator (GOI). The semiconductor substrate can also be a substrate containing other elemental semiconductors or compound semiconductors, and can also be a stacked structure, such as Si / SiGe.

[0035] Step S2: A stacked layer 20 is formed on the substrate 10, the stacked layer 20 including a first region 21 extending along a first direction and a second region 22 adjacent to the first region 21.

[0036] Specifically, the stacked layer 20 is formed by alternately depositing an interlayer insulating layer 201 and an interlayer sacrificial layer 202 on the substrate 10. An exemplary material for the interlayer insulating layer 201 may be silicon oxide, and an exemplary material for the interlayer sacrificial layer 202 may be silicon nitride. The interlayer insulating layer 201 and the interlayer sacrificial layer 202 have different etching selectivity.

[0037] Stacked layer 20 includes a first region 21 and a second region 22 extending along a first direction (Y), the second region 22 being adjacent to the first region 21. Figure 2a The diagram shows a first region 21 and two second regions 22 adjacent to the first region 21. The first region 21 is used to form gate line slots (i.e., no channel holes are formed), and the second regions 22 are used to form an array of channel holes. In this embodiment, there is a gap between the second regions 22 and the first region 21; that is, there is a gap between the channel holes and the gate line slots, and this gap does not form either channel holes or gate line slots.

[0038] In one embodiment, the stacked layer 20 may include a plurality of parallel first regions 21 and a second region 22 located between any two adjacent first regions 21.

[0039] In one embodiment, the stacked layer 20 further includes a third region 23 located around all the second regions 22. The third region 23 may be disposed around one side of all or the entire second region 22, or around both sides of the entire second region 22, or around three sides or all four sides of the entire second region 22. Figure 2a The third region 23 can be located on either side (left and right sides) of the entire second region 22, or it can be located around the entire second region 22. In one specific embodiment, when the second region 22 is a core region, the third region 23 can refer to a stepped region. In another specific embodiment, the second region 22 can include a core region and a stepped region, where the channel holes in the core region can be storage channel holes, the channel holes in the stepped region can be virtual channel holes, and the third region 23 can be a peripheral device region or a dicing region.

[0040] It should be noted that neither the first region 21 nor the third region 23 will form vias (both can be referred to as non-patterned regions). However, the second region 22 will form vias (which can be referred to as a patterned region). The inventors discovered that various problems easily arise during via etching at the boundaries of patterned regions. Further research revealed that one reason for these problems is that etching vias requires forming a hard mask layer across the entire structure, and etching vias in patterned regions consumes the hard mask layer above them. However, non-patterned regions do not require via etching, so their hard mask layers are not consumed or are consumed more slowly. Therefore, during the etching process, the height of the hard mask layer in non-patterned regions will be greater than that in patterned regions. Consequently, during the via etching process, etching residues accumulate at the locations of the height difference in the hard mask layer, thus affecting the etching of vias at the boundaries of patterned regions.

[0041] Please see Figure 1 Step S3 and Figures 2b-2e .

[0042] Step S3: A first stop layer 31 is formed on the stacked layer 20, the first stop layer 31 covering the first region 21.

[0043] First, a first stop material 30 is deposited on the stacked layer 20, covering the first region 21, the second region 22, and the third region 23 of the stacked layer 20. Then, a first patterned photoresist layer 40 is formed on the first stop material 30. The first stop material 30 may include one of tungsten, polysilicon, silicon nitride, silicon oxynitride, and aluminum oxide. The pattern of the photomask used to form the first patterned photoresist layer 40 is as follows: Figure 2c As shown, the unfilled blank areas represent openings. The first patterned photoresist layer 40 is a negative photoresist, meaning that after development and exposure, the negative photoresist corresponding to the openings is retained, forming a pattern as shown. Figure 2bThe pattern shown. When the first patterned photoresist layer 40 is a positive photoresist, the pattern of the photomask used is the same as... Figure 2c The pattern on the masking template is reversed. This is understandable. Figure 2b The number of first regions 21 is only an example; in some embodiments, there may be multiple first regions 21.

[0044] In one embodiment, the stacked layer 20 may include a plurality of parallel first regions 21, a second region 22 located between any two adjacent first regions 21, and a third region 23 located on one side of all the second regions 22. Correspondingly, as... Figure 2d As shown, the photomask has multiple first openings 210 corresponding to multiple first regions 21, and a second opening 230 corresponding to a third region 23. The first patterned photoresist layer 40 is a negative photoresist, and the negative photoresist at the opening is retained.

[0045] After forming the first patterned photoresist layer 40, the pattern of the first patterned photoresist layer 40 is transferred to the first stop material 30. That is, the first stop material 30 located in the second region 22 is removed by an etching process, the first stop material 30 in the first region 21 is retained to form the first stop layer 31, and the first stop material 30 in the third region 23 is retained to form the second stop layer 32 (e.g., ...). Figure 2e (As shown). Among them, the first stop layer 31 covers the first region 21, and the second stop layer 32 covers the third region 23.

[0046] Please see Figure 1 Step S4 and Figure 2f-2h .

[0047] Step S4: A patterned hard mask layer 50B is formed on the stacked layer 20. The patterned hard mask layer 50B covers the first stop layer 31, and the patterned hard mask layer 50B includes a first opening pattern 51 located directly above the first stop layer 31, and a channel hole pattern 52 located on the stacked layer 20 corresponding to the second region 22.

[0048] like Figure 2f As shown, a hard mask layer 50A (e.g., carbon) is first formed on the stacked layer 20, and then a second patterned photoresist layer 60 is formed on the hard mask layer 50A using a photolithography process. The pattern of the second patterned photoresist layer 60 is as follows. Figure 2g As shown. When the second patterned photoresist layer 60 is a positive photoresist, the photomask used in the photolithography process has the same pattern as the second patterned photoresist layer 60.

[0049] After forming the second patterned photoresist layer 60, as Figure 2hAs shown, the pattern of the second patterned photoresist layer 60 is transferred to the hard mask layer 50A. Specifically, the hard mask layer 50A can be etched based on the second patterned photoresist layer 60 to form a patterned hard mask layer 50B. The patterned hard mask layer 50B includes a first opening pattern 51 located directly above the first stop layer 31, a channel hole pattern 52 located on the stacked layer 20 corresponding to the second region 22, and a second opening pattern 53 located directly above the second stop layer 32. That is, the first opening pattern 51, the channel hole pattern 52, and the second opening pattern 53 can be formed using the same mask through photolithography and etching processes. Both the first opening pattern 51 and the second opening pattern 53 can include multiple virtual holes 501. The virtual holes 501 are located directly above the first stop layer 31 and the second stop layer 32, and no channel holes are formed below the virtual holes 501. The openings 502 in the channel hole pattern 52 penetrate the hard mask layer 50A to expose part of the structure of the stacked layer 20, for forming channel holes below it.

[0050] Wherein, the etching selectivity ratio of the first stop layer 31 relative to the patterned hard mask layer 50B (or hard mask layer 50A) is less than 1, and the etching selectivity ratio of the second stop layer 32 relative to the patterned hard mask layer 50B (or hard mask layer 50A) is less than 1, so that during the etching of the hard mask layer 50A, the etching process stops on or in the first stop layer 31 and the second stop layer 32.

[0051] The pattern of the mask used in this step (such as...) Figure 2g (As shown) This method is simple, low-cost, and requires no special design. In areas where etched vias are not required or in unpatterned areas (e.g., first region 21 and third region 23), stop layers (including first stop layer 31 and second stop layer 32) block the etching of the underlying stacked layer 20. Therefore, this mask does not require special design for specific areas (e.g., areas where vias are not formed or unpatterned areas), and it can also be used to etch the hard mask layer 50A to form an opening pattern in unpatterned areas, making the process in unpatterned areas the same as the process in second region 22, thus avoiding differences from second region 22 and preventing various problems.

[0052] For example, if the hard mask layer 50A is not etched in the non-patterned area, but is etched in the second region 22 to form the channel hole pattern 52, this will cause differences. For example, if the hard mask layer 50A in the non-patterned area is higher, then when the stacked layer 20 is etched to form the channel hole, the residual molecules will accumulate at the height difference (the junction of the second region 22 and the non-patterned area or the edge of the second region 22). Then the etching of the channel hole at the edge of the second region 22 will be affected, causing various problems in the edge etching process.

[0053] In some embodiments, the pattern of the second patterned photoresist layer 60 (or the pattern of the photomask) at the positions corresponding to the first region 21 and the third region 23 may also be in the shape of a trench. Correspondingly, the first opening pattern 51 and the second opening pattern 53 may also be in the shape of a trench, and the trench extends along the first direction (Y).

[0054] Please see Figure 1 Step S5 and Figure 2i-2j .

[0055] Step S5: Etch the stacked layer 20 based on the patterned hard mask layer 50B to form a channel hole 70 corresponding to the channel hole pattern 52 in the second region 22.

[0056] Since a first stop layer 31 and a second stop layer 32 are formed above the first region 21 and the third region 23, the etching process will only etch the stacked layer 20 of the second region 22. After the channel hole 70 is formed, the patterned hard mask layer 50B is removed by an ashing process, and then the first stop layer 31 and the second stop layer 32 are removed by a wet cleaning process.

[0057] Please see Figures 3a-3i , Figures 3a-3i This is a schematic diagram of the structure of a memory during its fabrication process, provided in another embodiment of the present invention.

[0058] In this embodiment, forming the first stop layer 31a and the second stop layer 32a may include the following steps: 1) As... Figure 3a As shown, an insulating layer 80 is deposited on the stacked layer 20. The material of the insulating layer 80 can be an insulating material such as silicon oxide. The insulating layer 80 is made of a different material than the patterned hard mask layer 50B, for example, the material of the patterned hard mask layer 50B is carbon. 2) A third patterned photoresist layer 81 is formed on the insulating layer 80 using deposition and photolithography processes. 3) As shown Figure 3b As shown, the insulating layer 80 is etched based on the third patterned photoresist layer 81 to form a third opening 801 corresponding to the first region 21 and a fourth opening 802 corresponding to the third region 23. 4) As Figure 3c As shown, the first stop layer 31a and the second stop layer 32a are filled in the third opening 801 and the fourth opening 802, respectively.

[0059] The depths of the third opening 801 and the fourth opening 802 are less than the thickness of the insulating layer 80. This means that the insulating layer 80 is not etched to the bottom; a portion of the insulating layer 80 remains between the third opening 801 and the fourth opening 802 and the stacked layer 20. This prevents the stop layer from being etched through during subsequent etching of the stacked layer 20 to form a channel, thus avoiding the etching of the stacked layer below the stop layer. The direction of "depth" is perpendicular to the substrate 10, i.e., parallel to the Z-direction.

[0060] In some embodiments, the width W1 of the third opening 801 is greater than the width W2 of the first region 21, so that the third opening 801 can cover the gap between the first region 21 and the second region 22. This ensures that no channel holes are formed in the gap after the first stop layer 31a is formed in the third opening 801. The direction of the "width" is parallel to the extension direction (X) of the first region 21.

[0061] Please see Figures 3d-3e Next, a patterned hard mask layer 50D is formed. Specifically, a hard mask layer 50C is first deposited on the first stop layer 31a, the second stop layer 32a, and the insulating layer 80. Then, the second patterned photoresist layer 60' is formed on the hard mask layer 50C. Next, the hard mask layer 50C is etched based on the second patterned photoresist layer 60' to form the patterned hard mask layer 50D. The patterned hard mask layer 50D includes a first opening pattern 51a located directly above the first stop layer 31a, a channel hole pattern 52a corresponding to the second region 22, and a second opening pattern 53a located directly above the second stop layer 32a. The specific process can be found in step S4 above. The pattern of the second patterned photoresist layer 60' or the pattern of the mask used can be referenced... Figure 2g .

[0062] Please see Figure 3f Based on the patterned hard mask layer 50D, the insulating layer 80 and the stacked layer 20 are etched to form the channel hole 70' corresponding to the channel hole pattern 52. Then, the patterned hard mask layer 50D is removed using an ashing process. Please refer to [link to relevant documentation]. Figure 3g The first stop layer 31a and the second stop layer 32a are removed using a wet cleaning process. Please refer to [link / reference]. Figure 3h A sacrificial layer 71 is filled into the third opening 801, the fourth opening 802, and the channel via 70'. The sacrificial layer 71 can be made of polycrystalline silicon. See also... Figure 3i The sacrificial layer 71 located in the third opening 801 and the fourth opening 802 is removed using a chemical mechanical polishing process. Then, another stacked layer can be formed on the stacked layer 20, thereby forming a dual-stack structure.

[0063] In other embodiments, it is possible to Figure 3gBased on this, the insulating layer 80 is removed or smoothed by chemical mechanical polishing, and then a channel structure is formed in the channel hole 70'. The channel structure includes a storage function layer and a channel layer.

[0064] The memory fabrication method provided in this invention first forms a stop layer on the stacked layer 20 corresponding to the non-patterned regions (first region 21 and third region 23) to ensure that no vias are formed in the non-patterned regions. Then, a patterned hard mask layer covering the stop layer is formed. During the process of forming the patterned hard mask layer, the hard mask layers of the patterned and non-patterned regions are etched simultaneously to form the opening pattern corresponding to the non-patterned region and the via pattern corresponding to the patterned region (second region 22). Therefore, differences between the hard mask layers of the patterned and non-patterned regions can be avoided, reducing the difficulty of subsequent via etching. In particular, it can improve the etching process of vias at the boundary of the patterned region, reducing various problems. Furthermore, this invention does not require a special mask design, simplifying the mask design and avoiding the risks associated with increasing the top size of the vias at the boundary of the patterned region, such as overlapping via tops or excessively deep etching at the bottom.

[0065] Please see Figure 4 , Figure 4 This is a schematic diagram of the structure of the memory provided in an embodiment of the present invention.

[0066] The memory 100 includes a substrate 10, a stacked structure 20a on the substrate 10, a plurality of channel structures 60a, and a gate line slot structure 211. The stacked structure 20a includes a first region 21 extending along a first direction (Y) and a second region 22 adjacent to the first region 21. The plurality of channel structures 60a penetrate the stacked structure 20a through the second region 22. The gate line slot structure 211 is located in the first region 21 and penetrates the stacked structure 20a.

[0067] The stacked structure 20a includes an interlayer insulating layer 201 and a gate layer 202a that are alternately stacked. An exemplary material for the interlayer insulating layer 201 may be silicon oxide, and an exemplary material for the gate layer 202a may be tungsten.

[0068] In the memory 100 provided in this embodiment of the invention, the top diameters of multiple channel structures 60a can be equal; that is, the top diameters of the channel structures 60a at the boundary and in the middle of the second region 22 can be equal. Compared to a structure where the top diameter of the channel structure 60a at the boundary of the second region 22 is larger than the top diameter of the channel structure 60a in the middle of the second region 22, the channel structures 60a in this embodiment of the invention do not have the problems of overlapping tops at the boundary and excessively deep etching at the boundary. Moreover, the design of the mask used in the fabrication process is simple and the cost is low.

[0069] Please see Figure 5 , Figure 5 This is a schematic diagram of the structure of a storage system provided in an embodiment of the present invention. The storage system 400 includes a memory 401 and a controller 402. The memory 401 can be the memory in any of the above embodiments. The controller 402 is electrically connected to the memory 401 and is used to control the memory 401 to store data. The memory 401 can perform data storage operations based on the control of the controller 402.

[0070] In some implementations, the storage system may be implemented as a Universal Flash Storage (UFS) device, a Solid State Drive (SSD), a Multimedia Card in the form of MMC, eMMC, RS-MMC, and Micro MMC, a Secure Digital Card in the form of SD, Mini SD, and Micro SD, a PCMCIA card type storage device, a Peripheral Component Interconnect (PCI) type storage device, a High Speed ​​PCI (PCI-E) type storage device, a Compact Flash (CF) card, a Smart Media Card, or a Memory Stick, etc.

[0071] The memory 401 includes a substrate, a stacked structure on the substrate, and a plurality of channel structures. The stacked structure includes a first region extending along a first direction and a second region adjacent to the first region. The plurality of channel structures penetrate the stacked structure through the second region.

[0072] The above description of the embodiments is only for the purpose of helping to understand the technical solutions and core ideas of the present invention; those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for fabricating a memory, characterized in that, include: Provide substrate; A stacked layer is formed on the substrate, the stacked layer including a first region extending along a first direction and a second region spaced from the first region, the second region being used to form a channel via; A first stop layer is formed on the stacked layers, the first stop layer covering the first region; A patterned hard mask layer is formed on the stacked layer, the patterned hard mask layer covering the first stop layer, and the patterned hard mask layer includes a first opening pattern located directly above the first stop layer, and a channel hole pattern located on the stacked layer corresponding to the second region; The stacked layers are etched based on the patterned hard mask layer to form a channel hole corresponding to the channel hole pattern in the second region.

2. The method for fabricating a memory according to claim 1, characterized in that, During the etching process of the hard mask layer, the etching process stops at or in the first stop layer.

3. The method for fabricating a memory according to claim 1, characterized in that, The first region is used to form grid line gaps.

4. The method for fabricating a memory according to claim 1, characterized in that, The step of forming a first stop layer on the stacked layers includes: A first stop material is deposited on the stacked layer, the first stop material covering the first region and the second region; The first stop material located in the second region is etched to form the first stop layer located in the first region.

5. The method for fabricating a memory according to claim 1, characterized in that, The step of forming a first stop layer on the stacked layers includes: An insulating layer is formed on the stacked layers; The insulating layer is etched to form an opening corresponding to the first region; The first stop layer is filled into the opening.

6. The method for fabricating a memory according to claim 5, characterized in that, The depth of the opening is less than the thickness of the insulating layer.

7. The method for fabricating a memory according to claim 5, characterized in that, The opening also covers the gap between the first region and the second region.

8. The method for fabricating a memory according to claim 1, characterized in that, The step of forming a patterned hard mask layer on the stacked layers includes: A hard mask layer is formed on the stacked layers, the hard mask layer covering the first stop layer; The hard mask layer is etched to form the first opening pattern and the channel hole pattern.

9. The method for fabricating a memory according to claim 1, characterized in that, The stacked layer further includes a third region located outside the second region, the third region being a non-patterned region; the method for fabricating the memory further includes: forming a second stop layer on the stacked layer, the second stop layer covering the third region; After the patterned hard mask layer is formed, the patterned hard mask layer also covers the second stop layer, and the patterned hard mask layer also includes a second opening pattern located directly above the second stop layer.

10. The method for fabricating a memory according to claim 9, characterized in that, The first opening pattern and the second opening pattern are formed using the same mask.

11. The method for fabricating a memory according to claim 9, characterized in that, The third region surrounds the second region.

12. The method for fabricating a memory according to claim 1, characterized in that, Following the step of etching the stacked layers based on the patterned hard mask layer, the method for fabricating the memory further includes: Remove the patterned hard mask layer and the first stop layer.

13. The method for fabricating a memory according to claim 1, characterized in that, The first opening pattern includes a plurality of virtual holes located directly above the first stop layer, the shape of which is the same as the shape of the holes in the channel pattern.

14. The method for fabricating a memory according to claim 1, characterized in that, The first opening pattern is a groove extending along the first direction.

15. The method for fabricating a memory according to claim 1, characterized in that, The material of the first stop layer includes one of tungsten, polycrystalline silicon, silicon nitride, silicon oxynitride, and aluminum oxide.

16. A memory, characterized in that, The memory is prepared by the method of preparing the memory according to any one of claims 1 to 15, wherein the memory comprises: Substrate; A stacked structure is located on the substrate and includes a first region extending along a first direction and a second region adjacent to the first region; Multiple channel structures, a stacked structure that runs through the second region.

17. A storage system, characterized in that, include: The memory as described in claim 16; A controller, electrically connected to the memory, is used to control the memory to store data.

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