Semiconductor memory device

Abstract

A semiconductor storage device of one embodiment includes a substrate including first and second block regions (BLK) each extending in a first direction and arranged in a second direction; first and second components (SLT) each extending in the first direction at a boundary region of the first and second block regions (BLK) and arranged in the first direction; a support pillar (HRa) arranged between the first and second components (SLT) in the boundary region; first and second conductor layers (WL) arranged in a third direction and separated from each other, which are separated by the first and second components (SLT) and the support pillar (HRa); and a memory pillar (MP) functioning as first and second memory cells (MT) in portions where the first and second conductor layers (WL) cross. The support pillar (HRa) has a shape in which a side surface of a lower pillar (LMP) is extended and a side surface of an upper pillar (UMP) is extended to be offset in a plane including the second and third directions.

Description

[0001] Related applications

[0002] This application enjoys priority to Japanese Patent Application No. 2021-24143 (filed on February 18, 2021). This application incorporates the entire contents of the basic application by reference to that basic application. Technical Field

[0003] The implementation method mainly relates to a semiconductor memory device. Background Technology

[0004] NAND flash memory is well known as a semiconductor storage device capable of non-volatile data storage. In semiconductor storage devices such as NAND flash memory, a three-dimensional storage structure is employed to achieve high integration and large capacity. Summary of the Invention

[0005] The implementation method improves the yield of semiconductor memory devices.

[0006] A semiconductor memory device according to an embodiment includes: a substrate comprising a first block region and a second block region, each extending along a first direction and arranged along a second direction intersecting the first direction; a first component and a second component, each extending along the first direction and arranged along the first direction in a first boundary region between the first block region and the second block region; a first support pillar disposed between the first component and the second component in the first boundary region; a plurality of conductive layers arranged and separated from each other along a third direction intersecting the first direction and the second direction, and separated by the first component, the second component, and the first support pillar into a first portion located in the first block region and a second portion located in the second block region; and a first memory pillar penetrating the plurality of conductive layers. The plurality of conductive layers includes: a first conductive layer; and a second conductive layer located between the substrate and the first conductive layer. In the first storage column, the portion intersecting with the first conductor layer functions as the first storage cell, and the portion intersecting with the second conductor layer functions as the second storage cell adjacent to the first storage cell in the third direction. The first support column comprises a lower column and an upper column, and has a first shape. The lower column has an upper end between the first and second conductor layers, and the upper column has a lower end between the first and second conductor layers. The first shape is such that the extensions of the side surfaces of the lower column and the upper column are offset within a plane encompassing both the second and third directions. Attached Figure Description

[0007] Figure 1 This is a block diagram illustrating the configuration of a storage system including the semiconductor storage device of the first embodiment.

[0008] Figure 2 This is a circuit diagram illustrating an example of the circuit configuration of the memory cell array included in the semiconductor memory device of the first embodiment.

[0009] Figure 3 This is a top view showing an example of the planar layout of the memory cell array included in the semiconductor memory device of the first embodiment.

[0010] Figure 4 This is a top view showing an example of a detailed planar layout of the storage area of ​​the storage cell array included in the semiconductor storage device of the first embodiment.

[0011] Figure 5 This is an example of the cross-sectional structure of the memory cell array included in the semiconductor memory device of the first embodiment. Figure 4 A cross-sectional view of the VV line.

[0012] Figure 6 This is an example of the cross-sectional structure of the memory cell array included in the semiconductor memory device of the first embodiment. Figure 5 A magnified view of region VI.

[0013] Figure 7 This is an example of the cross-sectional structure of the memory pillar in the semiconductor memory device of the first embodiment. Figure 5 A sectional view along line VII-VII.

[0014] Figure 8 This is a top view showing an example of a detailed planar layout of the lead-out area of ​​the memory cell array included in the semiconductor memory device of the first embodiment.

[0015] Figure 9 This is an example of the cross-sectional structure of the lead-out region of the memory cell array included in the semiconductor memory device of the first embodiment. Figure 8 A cross-sectional view of the IX-IX line.

[0016] Figure 10 This is an example of the cross-sectional structure of the lead-out region of the memory cell array included in the semiconductor memory device of the first embodiment. Figure 8 A cross-sectional view along the XX line.

[0017] Figure 11 This is an example of the cross-sectional structure of the lead-out region of the memory cell array included in the semiconductor memory device of the first embodiment. Figure 10 A magnified view of region XI.

[0018] Figure 12 This is an example of the cross-sectional structure of the lead-out region of the memory cell array included in the semiconductor memory device of the first embodiment. Figure 8 A cross-sectional view along line XII-XII.

[0019] Figure 13 This is a flowchart illustrating an example of a method for manufacturing a semiconductor memory device according to the first embodiment.

[0020] Figure 14 This is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device of the first embodiment during manufacturing.

[0021] Figure 15 This is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device of the first embodiment during manufacturing.

[0022] Figure 16 This is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device of the first embodiment during manufacturing.

[0023] Figure 17 This is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device of the first embodiment during manufacturing.

[0024] Figure 18 This is a top view showing an example of the planar layout during the manufacturing process of the semiconductor memory device according to the first embodiment.

[0025] Figure 19 This is a top view showing an example of the planar layout during the manufacturing process of the semiconductor memory device according to the first embodiment.

[0026] Figure 20 This is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device of the first embodiment during manufacturing.

[0027] Figure 21 (A) and (B) are cross-sectional views illustrating an example of the slit processing flow during the manufacturing of the semiconductor memory device according to the first embodiment.

[0028] Figure 22 This is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device of the first embodiment during manufacturing.

[0029] Figure 23 This is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device of the first embodiment during manufacturing.

[0030] Figure 24 This is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device of the first embodiment during manufacturing.

[0031] Figure 25 This is a top view showing an example of a detailed planar layout of the lead-out area of ​​the memory cell array provided in the first variation of the first embodiment of the semiconductor memory device.

[0032] Figure 26 This is a top view showing an example of a detailed planar layout of the lead-out area of ​​the memory cell array in the second variation of the first embodiment of the semiconductor memory device.

[0033] Figure 27 This is an example of the cross-sectional structure of the lead-out region of the memory cell array in the second variation of the first embodiment of the semiconductor memory device. Figure 26 A sectional view of the XXVII-XXVII line.

[0034] Figure 28 This is an example of the cross-sectional structure of the lead-out region of the memory cell array in the second variation of the first embodiment of the semiconductor memory device. Figure 26 A cross-sectional view of the XXVIII-XXVIII line.

[0035] Figure 29 This is a top view showing an example of a detailed planar layout of the lead-out area of ​​the memory cell array in the third variation of the first embodiment of the semiconductor memory device.

[0036] Figure 30 This is a top view showing an example of the planar layout of the memory cell array included in the semiconductor memory device of the second embodiment.

[0037] Figure 31 This is a top view showing an example of a detailed planar layout of the lead-out area of ​​the memory cell array provided in the semiconductor memory device of the second embodiment.

[0038] Figure 32 This is an example of the cross-sectional structure of the lead-out region of the memory cell array included in the semiconductor memory device of the second embodiment. Figure 31 A sectional view of the XXXII-XXXII line.

[0039] Figure 33 This is an example of the cross-sectional structure of the lead-out region of the memory cell array included in the semiconductor memory device of the second embodiment. Figure 31 A sectional view of line XXXIII-XXXIII.

[0040] Figure 34 This is an example of the cross-sectional structure of the lead-out region of the memory cell array included in the semiconductor memory device of the second embodiment. Figure 31A sectional view of the XXXIV-XXXIV line.

[0041] Figure 35 This is an example of the cross-sectional structure of the lead-out region of the memory cell array included in the semiconductor memory device of the second embodiment. Figure 34 A magnified view of region XXXV.

[0042] Figure 36 This is an example of the cross-sectional structure of the lead-out region of the memory cell array included in the semiconductor memory device of the second embodiment. Figure 31 A sectional view of the XXXVI-XXXVI line.

[0043] Figure 37 This is a flowchart illustrating an example of a method for manufacturing a semiconductor memory device according to the second embodiment.

[0044] Figure 38 This is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device during manufacturing according to the second embodiment.

[0045] Figure 39 This is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device during manufacturing according to the second embodiment.

[0046] Figure 40 This is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device during manufacturing according to the second embodiment.

[0047] Figure 41 This is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device during manufacturing according to the second embodiment.

[0048] Figure 42 This is a top view showing an example of the planar layout during the manufacturing process of the semiconductor memory device according to the second embodiment.

[0049] Figure 43 This is a top view showing an example of the planar layout during the manufacturing process of the semiconductor memory device according to the second embodiment.

[0050] Figure 44 This is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device during manufacturing according to the second embodiment.

[0051] Figure 45 This is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device during manufacturing according to the second embodiment.

[0052] Figure 46 This is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device during manufacturing according to the second embodiment.

[0053] Figure 47 This is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device during manufacturing according to the second embodiment.

[0054] Figure 48 This is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device during manufacturing according to the second embodiment.

[0055] Figure 49 This is a top view showing an example of a detailed planar layout of the lead-out area of ​​the memory cell array provided in the first variation of the second embodiment of the semiconductor memory device.

[0056] Figure 50 This is a top view showing an example of a detailed planar layout of the lead-out area of ​​the memory cell array in the second variation of the second embodiment of the semiconductor memory device.

[0057] Figure 51 This is a top view showing an example of a detailed planar layout of the lead-out area of ​​the memory cell array in the third variation of the second embodiment of the semiconductor memory device.

[0058] Figure 52 This is a top view showing an example of a detailed planar layout of the storage area of ​​the memory cell array provided by the semiconductor memory device of the first common variation.

[0059] Figure 53 This is a sectional view showing an example of the cross-sectional structure of the support column in the second common variation example. Detailed Implementation

[0060] The embodiments will now be described with reference to the accompanying drawings. The dimensions and scale of the drawings may not be the same as those of the actual objects.

[0061] In addition, in the following description, constituent elements with roughly the same function and structure are marked with the same symbol. When there is a special distinction between constituent elements with the same structure, different words or numbers may be added to the end of the same symbol.

[0062] 1. First Implementation Method

[0063] 1.1 Composition

[0064] 1.1.1 Storage System

[0065] Figure 1 This is a block diagram illustrating the configuration of the storage system according to the first embodiment. The storage system is a storage device configured to be connected to an external host device (not shown). Examples of storage systems include SD (secure digital). TM(touch memory，接触式存储器)The card includes a memory card, UFS (universal flash storage), and SSD (solid state drive). Storage system 1 includes a storage controller 2 and a semiconductor storage device 3.

[0066] The storage controller 2 is, for example, an integrated circuit such as a system-on-a-chip (SoC). The storage controller 2 controls the semiconductor storage device 3 according to requests from the host device. Specifically, for example, the storage controller 2 writes data requested by the host device into the semiconductor storage device 3. Furthermore, the storage controller 2 reads data requested by the host device from the semiconductor storage device 3 and sends it to the host device.

[0067] Semiconductor memory device 3 is a non-volatile memory for storing data. Semiconductor memory device 3 is, for example, a NAND flash memory.

[0068] The storage controller 2 and the semiconductor storage device 3 communicate, for example, via an SDR (single data rate) interface, a DDR (double data rate) interface, or an ONFI (Open NAND flash interface).

[0069] 1.1.2 Semiconductor memory devices

[0070] Then, referring to Figure 1 The block diagram shown illustrates the internal configuration of the semiconductor memory device according to the first embodiment. The semiconductor memory device 3 includes, for example, a memory cell array 10, an instruction register 11, an address register 12, a sequencer 13, a driver module 14, a line decoder module 15, and a sense amplifier module 16.

[0071] The storage cell array 10 comprises multiple blocks BLK0 to BLKn (n is an integer greater than or equal to 1). A block BLK is a collection of multiple storage cells capable of non-volatile data storage, used for example as a data erasure unit. Furthermore, the storage cell array 10 is provided with multiple bit lines and multiple word lines. Each storage cell is associated with, for example, one bit line and one word line. The detailed configuration of the storage cell array 10 will be described below.

[0072] Instruction register 11 stores instructions (CMDs) received by semiconductor memory device 3 from memory controller 2. Instructions (CMDs) may include commands that cause sequencer 13 to perform read, write, erase, etc.

[0073] Address register 12 stores address information ADD received by semiconductor memory device 3 from memory controller 2. Address information ADD includes, for example, block address BAd, page address PAd, and column address CAd. For example, block address BAd, page address PAd, and column address CAd are used to select block BLK, word line, and bit line, respectively.

[0074] The sequencer 13 controls the operation of the entire semiconductor memory device 3. For example, the sequencer 13 controls the driver module 14, the line decoder module 15, and the sense amplifier module 16, etc., to perform read operations, write operations, erase operations, etc., according to the instruction CMD stored in the instruction register 11.

[0075] The driver module 14 generates the voltage used in read operations, write operations, erase operations, etc. Moreover, the driver module 14 applies the generated voltage to the signal line corresponding to the selected word line, for example, according to the page address PA stored in the address register 12.

[0076] The row decoder module 15 selects one block BLK in the corresponding memory cell array 10 according to the block address BAd stored in the address register 12. Moreover, the row decoder module 15 transmits, for example, the voltage applied to the signal line to the selected word line in the selected block BLK, which corresponds to the selected word line.

[0077] During the write operation, the sense amplifier module 16 applies the required voltage to each bit line based on the write data DAT received from the memory controller 2. Furthermore, during the read operation, the sense amplifier module 16 determines the data stored in the memory cell based on the voltage of the bit line and transmits the determination result as read data DAT to the memory controller 2.

[0078] 1.1.3 Circuit configuration of memory cell array

[0079] Figure 2 This is a circuit diagram illustrating an example of the circuit configuration of the memory cell array included in the semiconductor memory device of the first embodiment. Figure 2 The image shows one block BLK out of a plurality of blocks BLKs contained in the storage cell array 10. For example... Figure 2 As shown, block BLK contains, for example, five string groups SU0 to SU4.

[0080] Each string group SU contains multiple NAND strings NS that are associated with bit lines BL0 to BLm (where m is an integer greater than or equal to 1). Each NAND string NS includes, for example, memory cell transistors MT0 to MT7, and select transistors ST1 and ST2. Each memory cell transistor MT contains a control gate and a charge storage layer, which non-volatilely stores data. Select transistors ST1 and ST2 are used to select the string group SU during various operations.

[0081] In each NAND string NS, memory cell transistors MT0 to MT8 are connected in series. The drain of selection transistor ST1 is connected to the bit line BL for establishing the association, and the source of selection transistor ST1 is connected to one end of the series-connected memory cell transistors MT0 to MT8. The drain of selection transistor ST2 is connected to the other end of the series-connected memory cell transistors MT0 to MT7. The source of selection transistor ST2 is connected to the source line SL.

[0082] Within the same block BLK, the control gates of memory cell transistors MT0 to MT7 are connected to word lines WL0 to WL7, respectively. The gates of select transistors ST1 in the string groups SU0 to SU4 are connected to select gate lines SGD0 to SGD4, respectively. The gates of multiple select transistors ST2 are connected to the select gate line SGS.

[0083] Each bit line BL0 to BLm is assigned a different column address. Each bit line BL is shared by NAND strings NS that have been assigned the same column address across multiple blocks BLK. Word lines WL0 to WL7 are set in each block BLK. For example, the source line SL is shared across multiple blocks BLK.

[0084] A collection of multiple memory cell transistors MT connected to a common word line WL in a string group SU is called a cell group CU. For example, the storage capacity of a cell group CU is defined as "1 page of data", which contains memory cell transistors MT that each store 1 bit of data. A cell group CU can have a storage capacity of more than 2 pages of data depending on the number of bits of data stored by the memory cell transistors MT.

[0085] Furthermore, the circuit configuration of the memory cell array 10 included in the semiconductor memory device 3 of the first embodiment is not limited to the configuration described above. For example, the number of string groups SU included in each block BLK can be designed to be arbitrary. The number of memory cell transistors MT and selection transistors ST1 and ST2 included in each NAND string NS can also be designed to be arbitrary.

[0086] 1.1.4 Structure of Storage Cell Array

[0087] Hereinafter, an example of the structure of the memory cell array included in the semiconductor memory device of the first embodiment will be described. In the accompanying drawings, the X-axis corresponds to the extension direction of the word line WL, the Y-axis corresponds to the extension direction of the bit line BL, and the Z-axis corresponds to the vertical direction, which is the vertical direction relative to the surface of the semiconductor substrate 20 used to form the semiconductor memory device 3. For ease of observation, shading lines are appropriately added to the top view. The shading lines added to the top view are not necessarily related to the material or characteristics of the constituent elements to which the shading lines are added. For ease of observation, the structural illustrations are appropriately omitted in the cross-sectional views.

[0088] 1.1.4.1 Overview of the floor plan

[0089] Figure 3 This is a top view showing an example of the planar layout of the memory cell array included in the semiconductor memory device of the first embodiment. Figure 3 The text shows the regions corresponding to the four blocks BLK0 to BLK3. For example... Figure 3 As shown, the planar layout of the memory cell array 10 is, for example, divided in the X direction into a memory region MA and lead-out regions HA1 and HA2. Furthermore, the memory cell array 10 includes multiple components SLT and SHE.

[0090] The storage region MA is configured between the lead-out regions HA1 and HA2. The storage region MA is a region containing multiple NAND strings NS. The lead-out regions HA1 and HA2 are the regions used for the connection between the stack-up wiring (e.g., word lines WL0 to WL7, and select gate lines SGD and SGS) and the row decoder module 15, respectively.

[0091] Multiple component SLTs each have multiple portions (not shown) extending along the X direction and arranged along the Y direction. Each component SLT traverses the storage region MA and lead-out regions HA1 and HA2 along the X direction in the boundary region between adjacent blocks BLK. Furthermore, each component SLT has, for example, a structure with embedded insulators and plate-shaped contacts. Moreover, each component SLT, together with the support pillars (not shown), disconnects the stacked wiring adjacent to that component SLT.

[0092] Multiple select gate elements (SHEs) extend along the X-direction and are arranged along the Y-direction. In this example, four SHEs are positioned between adjacent select gate elements (SLTs). Each SHE traverses the memory region MA along the X-direction. The two ends of each SHE are contained within lead-out regions HA1 and HA2, respectively. Furthermore, each SHE may have a structure incorporating an insulator. Moreover, each SHE disconnects the select gate line (SGD) adjacent to that SHE.

[0093] In the planar layout of the memory cell array 10 described above, each area separated by the component SLT corresponds to one block BLK. Furthermore, each area separated by the components SLT and SHE corresponds to one string group SU. Moreover, for example... Figure 3 The layout shown is repeated along the Y direction in the storage cell array 10.

[0094] Furthermore, the planar layout of the memory cell array 10 included in the semiconductor memory device 3 of the embodiment is not limited to the layout described above. For example, the number of components SHE disposed between adjacent components SLT can be designed to be any number. The number of string groups SU formed between adjacent components SLT can be varied depending on the number of components SHE disposed between adjacent components SLT.

[0095] 1.1.4.2 Storage Area

[0096] (Floor plan layout)

[0097] Figure 4 This is a top view showing an example of a detailed planar layout in the storage region MA of the storage cell array included in the semiconductor storage device of the first embodiment. Figure 4 The diagram shows an area containing one block BLK (i.e., serial groups SU0 to SU4) and two components SLT separated by that block. For example... Figure 4 As shown, in the storage region MA, the storage cell array 10 includes multiple storage columns MP, multiple contacts CV, and multiple bit lines BL. Furthermore, each component SLT includes contacts LI and spacers SP.

[0098] Each memory column (MP) functions as a NAND string (NS). Multiple memory columns (MPs) are arranged in 24 columns, for example, in a sawtooth pattern, in the area between two adjacent components (SLTs). Furthermore, for example, a component (SHE) overlaps with the 5th, 10th, 15th, and 20th memory columns (MPs) from the top of the paper.

[0099] Multiple bit lines BL extend along the Y direction and are arranged along the X direction. Each bit line BL in each string group SU is configured to overlap with at least one memory column MP. Figure 4 In the example shown, two bit lines BL are configured to overlap with one memory column MP. One of the multiple bit lines BL overlapping the memory column MP is electrically connected to the corresponding memory column MP via a contact CV.

[0100] For example, the contact CV between the memory pillar MP and the bit line BL that contacts the component SHE is omitted. In other words, the contact CV between the memory pillar MP that connects to two different select gate lines SGD and the bit line BL is omitted. The number and arrangement of memory pillars MP, components SHE, etc., between adjacent components SLT are not limited to the use of Figure 4 The described configuration can be modified as appropriate. The number of bit lines BL overlapping each memory cylinder MP can be designed to be arbitrary.

[0101] The contact LI is a conductor extending in the XZ plane. The spacer SP is an insulator disposed on the side of the contact LI. In other words, the contact LI is surrounded by the spacer SP when viewed from above.

[0102] (Cross-section structure)

[0103] Figure 5 This is an example of the cross-sectional structure of the storage region MA of the memory cell array included in the semiconductor memory device of the first embodiment. Figure 4 A cross-sectional view of the VV line. (e.g.) Figure 5 As shown, the memory cell array 10 also includes a semiconductor substrate 20 and conductive layers 22-26. Furthermore, Figure 6 This is an example of the cross-sectional structure of the memory pillars in the semiconductor memory device of the first embodiment. Figure 5 A magnified view of region VI.

[0104] Semiconductor substrate 20 has a P-type well region. The P-type well region is a region containing P-type impurities (e.g., boron) disposed near the surface of semiconductor substrate 20. The P-type well region includes an N-type semiconductor region 21. The N-type semiconductor region 21 is a diffusion region of N-type impurities disposed near the surface of the P-type well region. For example, phosphorus is doped into the N-type semiconductor region 21.

[0105] A conductive layer 22 is disposed above the semiconductor substrate 20, separated by an insulating layer (not shown). The conductive layer 22 is formed, for example, in a plate shape extending along the XY plane. The conductive layer 22 serves as the select gate line SGS. The conductive layer 22 contains, for example, tungsten.

[0106] An insulating layer (not shown) and a conductive layer 23 are alternately stacked above the conductive layer 22. The conductive layer 23 is formed, for example, as a plate extending along the XY plane. The stacked conductive layers 23 are sequentially used as word lines WL0 to WL3 from the semiconductor substrate 20 side. The conductive layer 23 contains, for example, tungsten.

[0107] An insulating layer (not shown) and a conductive layer 24 are alternately stacked above the uppermost conductive layer 23. The conductive layer 24 is formed, for example, as a plate extending along the XY plane. The stacked conductive layers 24 are sequentially used as word lines WL4 to WL7 from the semiconductor substrate 20 side. The conductive layer 24 contains, for example, tungsten.

[0108] A conductive layer 25 is disposed above the uppermost conductive layer 24, separated by an insulating layer (not shown). The conductive layer 25 is, for example, formed as a plate extending along the XY plane. The conductive layer 25 serves as the select gate line (SGD). The conductive layer 25 contains, for example, tungsten.

[0109] A conductive layer 26 is disposed above the conductive layer 25, separated by an insulating layer (not shown). The conductive layer 26 is formed, for example, as a line extending in the Y direction, serving as a bit line BL. That is, in the region not shown, multiple conductive layers 26 are arranged along the X direction. The conductive layer 26 contains, for example, copper.

[0110] Each storage column (MP) extends along the Z-direction and includes an upper column (UMP) and a lower column (LMP). The lower column (LMP) penetrates conductor layers 22 and 23. The upper column (UMP) penetrates conductor layers 24 and 25. The lower end of the lower column (LMP) is connected to the P-type well region. The upper ends of the lower column (LMP) and the upper column (UMP) are connected between the uppermost conductor layer 23 and the lowermost conductor layer 24. The cross-sectional area (XY cross-sectional area) of the lower column (LMP) and the upper column (UMP) along the XY plane increases from bottom to top. The XY cross-sectional area of ​​the upper end of the lower column (LMP) is larger than that of the lower end of the upper column (UMP). The extension of the side LMP_s of the lower column (LMP) and the extension of the side UMP_s of the upper column (UMP) are... Figure 6 The single-point chain lines (as illustrated in the diagram) are staggered and inconsistent. The stagger between the extension of the side LMP_s of the lower column LMP and the extension of the side UMP_s of the upper column UMP is not limited to... Figure 6 The YZ section shown will produce this effect in any section including the Z direction.

[0111] The portion where the storage pillar MP intersects with conductor layer 22 functions as selection transistor ST2. The portion where the storage pillar MP intersects with either conductor layer 23 or conductor layer 24 functions as a storage cell transistor MT. The portion where the storage pillar MP intersects with conductor layer 25 functions as selection transistor ST1.

[0112] Furthermore, each memory column MP includes, for example, a core film 30, a semiconductor film 31, and a stacked film 32. The core film 30 extends along the Z-direction. For example, the upper end of the core film 30 is contained in a layer above the conductor layer 25, and the lower end of the core film 30 is contained in a layer above the P-well region. The semiconductor film 31 covers the periphery of the core film 30. At the lower part of the memory column MP, a portion of the semiconductor film 31 is in contact with the P-well region. The stacked film 32 covers the sides and bottom of the semiconductor film 31, except for the portion where the semiconductor film 31 contacts the P-well region. The core film 30 includes, for example, an insulator such as silicon oxide. The semiconductor film 31 includes, for example, silicon.

[0113] A columnar contact CV is provided on the upper surface of the semiconductor film 31 within the memory column MP. One contact CV is shown in the illustrated area, and this one contact CV corresponds to one of the two memory columns MP in each cross-sectional area separated by components SLT and SHE. In the memory region MA, memory columns MP that do not overlap with component SHE and are not connected to contact CV are connected to corresponding contact CVs in areas not shown.

[0114] One conductive layer 26, i.e., one bit line BL, is connected to the upper surface of the contact CV. One conductive layer 26 is connected to one contact CV in each space separated by components SLT and SHE. That is, the storage post MP disposed between adjacent components SLT and SHE, and the storage post MP disposed between two adjacent components SHE are electrically connected to each conductive layer 26.

[0115] Component SLT, for example, has a portion disposed along the XZ plane, which breaks the conductive layers 22-25. The YZ cross-section of component SLT, for example, has a bowing shape. Specifically, the length of component SLT along the Y direction is minimum at the upper or lower end, and maximum between the upper and lower ends.

[0116] The contact LI within component SLT is disposed along spacer SP. The upper end of contact LI is located in the layer between conductor layer 25 and conductor layer 26. The lower end of contact LI is connected to N-type semiconductor region 21. Spacer SP is disposed between contact LI and conductor layers 22-25. Contact LI is isolated and insulated from conductor layers 22-25 by spacer SP.

[0117] The component SHE, for example, has a portion disposed along the XZ plane, which breaks the conductor layer 25. The upper end of the component SHE is located in the layer between conductor layer 25 and conductor layer 26. The lower end of the component SHE is located in the layer between conductor layer 24 and conductor layer 25. The component SHE, for example, includes an insulator such as silicon oxide. The upper end of the component SHE may or may not be aligned with the upper end of the component SLT. Furthermore, the upper end of the component SHE may or may not be aligned with the upper end of the storage column MP. In addition, the number of each conductor layer 22 to 25 can be arbitrary. For example, when multiple conductor layers 25 are provided, the lower end of the component SHE is located between the uppermost conductor layer 24 and the lowermost conductor layer 25. That is, the lower end of the component SHE becomes deeper according to the number of conductor layers 25.

[0118] Figure 7 This is an example of the cross-sectional structure of the memory pillar in the semiconductor memory device of the first embodiment. Figure 5 A cross-sectional view along line VII-VII. Specifically... Figure 7 This represents the cross-sectional structure of the storage pillar MP in a layer containing the conductive layer 23 that is parallel to the surface of the semiconductor substrate 20. For example... Figure 7 As shown, the laminated film 32 includes, for example, a tunnel insulating film 33, a charge storage film 34, and a barrier insulating film 35.

[0119] In the cross-section containing the conductive layer 23, the core film 30 is, for example, disposed in the central portion of the storage column MP. A semiconductor film 31 surrounds the sides of the core film 30. A tunnel insulating film 33 surrounds the sides of the semiconductor film 31. A charge storage film 34 surrounds the sides of the tunnel insulating film 33. A barrier insulating film 35 surrounds the sides of the charge storage film 34. The conductive layer 23 surrounds the sides of the barrier insulating film 35.

[0120] Semiconductor film 31 serves as a channel (current path) for memory cell transistors MT0 to MT7 and selection transistors ST1 and ST2. Tunnel insulating film 33 and barrier insulating film 35 each contain, for example, silicon oxide. Charge storage film 34 has the function of storing charge and may contain, for example, silicon nitride. Thus, each memory pillar MP can function as a NAND string NS.

[0121] The semiconductor memory device 3 of the first embodiment can form a current path between the semiconductor film 31 within the memory pillar MP and the contact LI near the surface of the P-type well region and the N-type semiconductor region 21 by applying a voltage to the bottommost conductive layer 22. Thus, the semiconductor memory device 3 can allow current to flow between the bit line BL and the contact LI via the memory pillar MP. That is, the contact LI, provided within the component SLT, can be used as part of the source line SL.

[0122] 1.1.4.3 Lead-out region

[0123] (Floor plan layout)

[0124] In the semiconductor memory device 3 of the first embodiment, the structure of the even-numbered block BLK in the lead-out region HA1 is similar to the structure of the odd-numbered block BLK in the lead-out region HA2. Furthermore, the structure of the even-numbered block BLK in the lead-out region HA2 is similar to the structure of the odd-numbered block BLK in the lead-out region HA1.

[0125] Specifically, for example, the planar layout of block BLK0 in lead-out region HA2 is the same as the following layout, which is obtained by reversing the structure of block BLK1 in lead-out region HA1 in the X and Y directions respectively. The planar layout of block BLK1 in lead-out region HA2 is the same as the following layout, which is obtained by reversing the structure of block BLK0 in lead-out region HA1 in the X and Y directions respectively. In the first embodiment, even-numbered blocks BLK are referred to as "BLKe", and odd-numbered blocks BLK are referred to as "BLKo".

[0126] Figure 8 This is a top view showing an example of a detailed planar layout of the lead-out area of ​​the memory cell array included in the semiconductor memory device of the first embodiment. Figure 8 In addition to showing the areas corresponding to the adjacent blocks BLKe and BLKo in the outgoing area HA1, a portion of the nearby storage area MA is also shown. The following is based on... Figure 8 The planar layout of blocks BLKe and BLKo in the shown lead-out area HA1 is explained, and the planar layout of block BLK in lead-out areas HA1 and HA2 is described.

[0127] like Figure 8 As shown, in the lead-out region HA1, the select gate line SGS, word lines WL0 to WL7, and select gate line SGD each have a portion (step portion) that does not overlap with the upper wiring layer (conductor layer) in the stacked wiring. Furthermore, in the lead-out region HA1, the memory cell array 10 includes multiple contacts CC, multiple bridging wiring layers CH, and multiple support pillars HRa and HRb.

[0128] In the lead-out region HA1, the shape of the portion that does not overlap with the upper wiring layer resembles a step, a terrace, or a rimstone. Specifically, there are step differences between the select gate line SGS and the word line WL0, between word line WL0 and word line WL1, ..., between word line WL6 and word line WL7, and between word line WL7 and the select gate line SGD. Figure 8The example shows that the ends of the word lines WL0 to WL7 are set in two columns of steps. These two columns of steps have one level difference in the Y direction and multiple levels in the X direction.

[0129] In the region where the lead-out area HA1 overlaps with the block BLKo, multiple contacts CC are respectively disposed on the stepped portions of the select gate line SGS, word lines WL0 to WL7, and select gate lines SGD0 to SGD4. Furthermore, in the region where the lead-out area HA1 overlaps with the block BLKo, multiple contacts CC relative to the multilayer wiring are omitted.

[0130] On the other hand, in the area where the lead-out region HA2 overlaps with the block BLKo, multiple contacts CC are respectively disposed on the stepped portions of the select gate line SGS, word lines WL0 to WL7, and select gate lines SGD0 to SGD4, but this is omitted from the illustration. Furthermore, in the area where the lead-out region HA2 overlaps with the block BLKo, multiple contacts CC relative to the multilayer wiring are omitted.

[0131] The select gate line SGS, word lines WL0-WL7, and select gate lines SGD0-SGD4 are electrically connected to the horizontal decoder module 15 via their respective contacts CC. That is, for example, a voltage is applied to each of the select gate lines SGS, WL0-WL7, and SGD0-SGD4 from the contact CC located in either of the lead-out areas HA1 and HA2. Alternatively, in each wiring layer, lead-out areas HA1 and HA2 may also be connected to contacts CC. In this case, for example, a voltage is applied to the word line WL from both sides of the contacts CC in lead-out areas HA1 and HA2.

[0132] In the lead-out regions HA1 and HA2, multiple support pillars HRa are configured in the boundary region of two adjacent blocks BLK. Each component SLT is broken into multiple parts by at least one support pillar HRa. Figure 8 The example illustrates a scenario where a component SLT is divided into four parts by configuring three support posts HRa for each component SLT. Additionally, three support posts HRa are also configured in the lead-out area HA2 (not shown). Thus, the component SLT, including the area not shown, is divided into seven parts. The length of the support post HRa along the Y direction is longer than the width of the component SLT along the Y direction. The support posts HRa, respectively configured in the two boundary areas separated by block BLK, are positioned at the same location in the X direction.

[0133] The support post HRa is connected to the spacers SP of the two sections of the component SLT that are separated by the support post HRa. The contacts LI in the two sections of the component SLT that are separated by the support post HRa are electrically connected through the bridging wiring layer CH formed above the support post HRa.

[0134] In the lead-out areas HA1 and HA2, multiple support pillars HRb are appropriately arranged in the area that does not include the portion where the component SLT and support pillar HRa are formed, or the portion where the contact CC is formed.

[0135] (Cross-section structure)

[0136] Figure 9 , Figure 10 , Figure 11 ,and Figure 12 This illustrates an example of the cross-sectional structure of the lead-out region of the memory cell array included in the semiconductor memory device of the first embodiment. Figure 9 It is along Figure 8 A cross-sectional view of the IX-IX line. Figure 10 It is along Figure 8 A cross-sectional view along the XX line. Figure 11 yes Figure 10 A magnified view of region XI. Figure 12 It is along Figure 8 A cross-sectional view along line XII-XII.

[0137] like Figure 9 As shown, in the lead-out region HA1, the memory cell array 10 also includes multiple conductive layers 27. Furthermore, the ends of the conductive layer 22 corresponding to the select gate line SGS, the ends of the multiple conductive layers 23 and 24 corresponding to the word line WL, and the ends of the conductive layer 25 corresponding to the select gate line SGD are set in a stepped shape.

[0138] Multiple contacts CC are respectively disposed on the stepped portions of the select gate line SGS, word lines WL0 to WL7, and select gate line SGD. A conductive layer 27 is disposed above each contact CC. Each conductive layer 27 is electrically connected to the line decoder module 15, for example, contained in the same layer as conductive layer 26. Thus, each conductive layer 22 to 25 is electrically connected to the line decoder module 15 via the contacts CC and conductive layer 27. Each conductive layer 22 to 25 can also be electrically connected to the line decoder module 15 via a wiring layer (not shown), which is a layer above conductive layer 27.

[0139] like Figure 10As shown, in the lead-out regions HA1 and HA2, multiple wiring layers (specifically, conductor layer 24 corresponding to word line WL4 and conductor layer 24 corresponding to word line WL5) are formed in a stepped shape along the Y direction. Therefore, in the lead-out regions HA1 and HA2, the YZ cross-section of the stacked wiring structure of the block BLK unit is asymmetrical relative to the central axis along the Z direction.

[0140] As described above, the bridging wiring layer CH is disposed directly above the support post HRa. Furthermore, the bridging wiring layer CH is arranged to overlap with the ends of the components SLT on both sides disconnected from the support post HRa. The lower end of the bridging wiring layer CH has, for example, a portion that coincides with the upper end of the contact LI within the component SLT and a portion that coincides with the upper end of the support post HRa. The lower end of the bridging wiring layer CH has a portion that connects to the upper ends of each contact LI within the component SLT on both sides of the support post HRa. On the other hand, a portion of the lower end of the bridging wiring layer CH may or may not connect to the upper end of the support post HRa.

[0141] In addition, such as Figures 10 to 12 As shown, each support post HRa and HRb has a structure in which an insulator is embedded in a hole extending along the Z direction, and it penetrates the multilayer wiring structure.

[0142] The support column HRa comprises an upper column UHRa and a lower column LHRa. The lower end of the lower column LHRa is connected to the P-type well region. The upper end of the lower column LHRa and the lower end of the upper column UHRa are connected between the uppermost conductive layer 23 and the lowermost conductive layer 24. The XY cross-sectional area of ​​both the lower column LHRa and the upper column UHRa increases from bottom to top.

[0143] Furthermore, the XY cross-sectional area of ​​the upper end of the lower column LHRa is greater than the XY cross-sectional area of ​​the lower end of the upper column UHRa. Specifically, the upper end of the lower column LHRa is longer along the Y direction than the lower end of the upper column UHRa. The extension of the side surface LHRa_s of the lower column LHRa is similar to the extension of the side surface UHRa_s of the upper column UHRa. Figure 11 (The single-point chain diagram is shown in the figure.) The segments are staggered and inconsistent within the YZ section. On the other hand, the upper end of the lower column LHRa and the lower end of the upper column UHRa have the same length along the X direction. The extension of the side surface LHRa_s of the lower column LHRa and the extension of the side surface UHRc_s of the upper column UHRa are consistent within the XZ section.

[0144] The support pillar HRb comprises an upper pillar UHRb and a lower pillar LHRb. The lower end of the lower pillar LHRb is connected to the P-type well region. The upper end of the lower pillar LHRb and the lower end of the upper pillar UHRb are connected between the uppermost conductive layer 23 and the lowermost conductive layer 24. The boundary height between the upper end of the lower pillar LHRb and the lower end of the upper pillar UHRb is the same as the boundary height between the upper end of the lower pillar LHRb and the lower end of the upper pillar UHRb. The cross-sectional area along the XY plane of each lower pillar LHRb and upper pillar UHRb increases from bottom to top. The XY cross-sectional area of ​​the upper end of the lower pillar LHRb is greater than the XY cross-sectional area of ​​the lower end of the upper pillar UHRb. Therefore, the extension of the side LHRb_s of the lower pillar LHRb is similar to the extension of the side UHRb_s of the upper pillar UHRb. Figure 11 The single-point chain lines (as illustrated in the diagram) are staggered and inconsistent. The stagger between the extension of the side LHRb_s of the lower column LHRb and the extension of the side UHRb_s of the upper column UHRb is not limited to... Figure 11 The YZ section shown will produce this effect in any section including the Z direction.

[0145] 1.2 Manufacturing method of semiconductor memory device

[0146] Figure 13 This is a flowchart illustrating an example of a method for manufacturing a semiconductor memory device according to the first embodiment. Figures 14-24 Examples of planar layouts or cross-sectional structures during the manufacturing process of the semiconductor memory device according to the first embodiment are shown. The illustrated planar layouts are shown in the diagrams. Figure 8 The corresponding area. Except Figure 21 The cross-sectional structures other than those shown in the diagram are also represented. Figure 10 The corresponding region, and a part of the storage region MA. Figure 21 The cross-sectional structure shown in the figure is represented by... Figure 12 The corresponding area. For example... Figure 13 As shown, in the manufacturing process of the semiconductor memory device 3 according to the first embodiment, processes S101 to S112 are performed sequentially. Hereinafter, reference will be made as appropriate. Figure 13 An example of the manufacturing process of the multilayer wiring structure within the memory cell array 10 of the semiconductor memory device 3 will be described.

[0147] First, processes S101 through S103 are executed sequentially, such as... Figure 14 The lower part of the laminated structure shown is formed by sacrificial components 42 and 44, a stepped structure is formed in the lower part of the laminated structure, and multiple holes LMH, LHa and LHb are formed.

[0148] In short, an insulating layer 41 is first formed on a semiconductor substrate 20. A sacrificial member 42 and an insulating layer 43 are sequentially formed on the insulating layer 41. A sacrificial member 44 and an insulating layer 43 are alternately deposited on the insulating layer 43 (S101).

[0149] Then, the ends of the sacrificial members 42 and 44 of the laminate are machined into a stepped shape within the lead-out regions HA1 and HA2. Subsequently, the stepped portions within the lead-out regions HA1 and HA2 are embedded by an insulating layer. The upper surface of the laminated structure is planarized, for example, by CMP (Chemical Mechanical Polishing) (S102).

[0150] Subsequently, a mask is formed to create openings in the regions corresponding to the lower pillars LMP, LHRa, and LHRb using photolithography or similar methods. Then, via anisotropic etching of this mask, vias LMH, LHa, and LHb are formed, for example, penetrating the insulating layers 41 and 43, and the sacrificial components 42 and 44, respectively. At the bottom of each via LMH, LHa, and LHb, a portion of the P-type well region is exposed (S103). The vias LMH, LHa, and LHb correspond to the lower pillars LMP, LHRa, and LHRb, respectively. Subsequently, as... Figure 15 As shown, sacrificial members 45 are embedded in holes LMH, LHa, and LHb. The sacrificial members 45 formed on the upper surface of the laminated structure are removed, for example, by CMP, thereby exposing the surfaces corresponding to the upper ends of each lower pillar LMP, LHRa, and LHRb.

[0151] Next, processes S104 to S106 are executed sequentially, such as... Figure 15 The upper part of the laminated structure, which includes sacrificial components 47 and 48, is formed, as is the stepped structure of the upper part of the laminated structure, and multiple holes UMH, UHa and UHb are formed.

[0152] In short, firstly, an insulating layer 46 is formed on the laminated structure. Sacrificial members 47 and insulating layers 46 are alternately laminated on the insulating layer 46. Sacrificial members 48 and insulating layers 49 are sequentially formed on the insulating layer 46 (S104).

[0153] Then, the ends of the stacked sacrificial members 47 and 48 are machined into a stepped shape within the lead-out regions HA1 and HA2. Subsequently, the stepped portions within the lead-out regions HA1 and HA2 are embedded by an insulating layer. The upper surface of the stacked structure is planarized, for example, by CMP (S105).

[0154] Subsequently, a mask with openings corresponding to the upper pillars UMP, UHRa, and UHRb is formed by photolithography or the like. Then, by anisotropic etching of the mask, holes UMH, UHa, and UHb are formed, for example, penetrating the insulating layers 46 and 49, and the sacrificial members 47 and 48, respectively. At the bottom of hole UMH, a portion of the sacrificial member 45(MP) embedded in hole LMH is exposed. At the bottom of hole UHa, a portion of the sacrificial member 45(HRa) embedded in hole LHa is exposed. At the bottom of hole UHb, a portion of the sacrificial member 45(HRb) embedded in hole LHb is exposed (S106). Holes UMH, UHa, and UHb correspond to the upper pillars UMP, UHRa, and UHRb, respectively.

[0155] Next, multiple support columns HRa and HRb (S107) are formed. Specifically, as follows: Figure 16 As shown, the sacrificial components 45 formed within the holes LMH, LHa, and LHb are first removed, for example, by wet etching. This forms the holes MH corresponding to LMH and UMH, Ha corresponding to LHa and UHa, and Hb corresponding to LHb and UHb (none not shown). Then, a mask 50 is formed by embedding the hole MH. Subsequently, an insulator is formed by filling the holes Ha and Hb, thereby forming the support pillars HRa and HRb.

[0156] Next, multiple storage columns MP are formed (S108). Specifically, as follows: Figure 17 As shown, the mask 50 is first removed. Then, a barrier insulating film 35, a charge storage film 34, and a tunnel insulating film 33 are sequentially formed on the side and bottom surfaces of each aperture MH. Next, a portion of the barrier insulating film 35, charge storage film 34, and tunnel insulating film 33 located at the bottom of the aperture MH is removed, and a semiconductor film 31 and a core film 30 are formed within the aperture MH. Subsequently, a portion of the core film 30 located at the top of the aperture MH is removed, and a semiconductor film 31 is formed in that portion. Thus, a structure corresponding to the storage pillar MP is formed within each aperture MH.

[0157] Through the processing up to S108, such as Figure 18 As shown, multiple support pillars HRa and HRb are formed in the lead-out areas HA1 and HA2, and multiple storage pillars MP are formed in the storage area MA. The multiple support pillars HRa are disposed in a predetermined area for forming the component SLT. The multiple support pillars HRb are disposed in areas of the lead-out areas HA1 and HA2 other than the predetermined areas for forming the component SLT and the contact CC.

[0158] Next, as Figure 19 and Figure 20Multiple slits SH are formed (S109). Specifically, a mask corresponding to the region opening of the component SLT is first formed by photolithography or the like. Then, slits SH are formed, for example, by anisotropic etching of the mask, which penetrate insulating layers 41, 43, 46, and 49, and sacrificial components 42, 44, 47, and 48, respectively. Subsequently, N-type impurities (e.g., phosphorus) are implanted into a portion of the P-type well region exposed through the slits SH using ion implantation. This forms an N-type semiconductor region 21.

[0159] Furthermore, the slit SH is formed by dividing the structure into multiple parts in a way that, when viewed from above, a portion of the remaining support column HRa is visible, thus breaking the laminated structure. Specifically, as... Figure 21 As shown, the opposing YZ end faces of the two slits SH of the support column HRa continuously intersect the upper and lower ends of the support column HRa. Therefore, the length of the support column HRa in the X direction changes from the length D1 before the slits SH are formed during the processing in S107 to the interval D2 (< D1) between the two slits SH of the support column HRa. That is, the length of the upper end of the lower column LHRa in the X direction is the same as the length of the lower end of the upper column UHRa in the X direction.

[0160] Next, the replacement process for the sacrificial components of the stacked structure is performed, such as... Figure 22 The multilayer wiring structure is formed as shown in S110. Specifically, sacrificial components 42, 44, 47, and 48 are first selectively removed via slit SH by wet etching using hot phosphoric acid or the like. Then, the three-dimensional structure of the removed sacrificial components 42, 44, 47, and 48 is maintained by multiple storage pillars MP and multiple support pillars HRa and HRb. Subsequently, a conductor is embedded via slit SH into the space created by removing the sacrificial components 42, 44, 47, and 48. The conductor in this process is formed, for example, using CVD (Chemical Vapor Deposition).

[0161] Subsequently, the conductors formed inside the slit SH are removed by an etch-back process, thereby separating the conductors formed in adjacent wiring layers. This results in the formation of a conductor layer 22 functioning as the select gate line SGS, multiple conductor layers 23 functioning as word lines WL0 to WL3, multiple conductor layers 24 functioning as word lines WL4 to WL7, and multiple conductor layers 25 functioning as the select gate line SGD. Furthermore, the conductor layers 22 to 25 formed in this process may also include barrier metal. In this case, when forming the conductors after removing sacrificial components 42, 44, 47, and 48, tungsten is formed as the barrier metal, for example, after titanium nitride film formation.

[0162] Next, as Figure 23 As shown, a component SLT (S111) is formed within each slit SH. Specifically, an insulating portion (spacer SP) is first formed to cover the sides and bottom of the slit SH. Then, a portion of the spacer SP formed at the bottom of the slit SH is removed, exposing a portion of the N-type semiconductor region 21 at the bottom of the slit SH. Subsequently, a conductor (contact LI) is formed within the slit SH, for example, by removing the conductor formed outside the slit SH using CMP. Furthermore, a component SHE is formed in an area not shown, which further divides the conductor layer 25 in the multilayer wiring structure into multiple portions.

[0163] Finally, as Figure 24 As shown, multiple contacts CC and multiple bridging wiring layers CH (S112) are formed. Specifically, a mask with openings corresponding to the regions of the contacts CC is formed by photolithography or the like. Then, holes are formed by anisotropic etching of the mask, through which an insulator, for example, is formed above a stepped portion. At the bottom of each hole, the corresponding conductive layer is exposed. Subsequently, a conductor is embedded in the hole. For example, the conductor formed on the upper surface of the multilayer structure is removed by CMP, thereby exposing the surfaces corresponding to the upper ends of each of the multiple contacts CC.

[0164] Then, a mask with openings corresponding to the bridging wiring layers CH is formed by photolithography or the like. Next, holes are formed, for example, above the support pillars HRa, using anisotropic etching of this mask. At the bottom of the holes, the contacts LI within the components SLT on both sides of the corresponding support pillars HRa are exposed. Subsequently, a conductor is embedded into the hole. For example, the conductor formed on the upper surface of the multilayer structure is removed by CMP, thereby exposing the surfaces corresponding to the upper ends of the multiple bridging wiring layers CH.

[0165] The multilayer wiring structure within the memory cell array 10 is formed through the manufacturing processes described above. Furthermore, the manufacturing processes described above are merely examples, and the present invention is not limited thereto. For example, other processes may be inserted between the manufacturing processes, or some processes may be omitted or combined. Moreover, the manufacturing processes may be interchanged within permissible limits. For example, the process of forming the memory pillar MP may be interchanged with the process of forming the support pillars HRa and HRb.

[0166] 1.3 Effects of this implementation method

[0167] According to the first embodiment, the yield of semiconductor memory devices can be improved. The effects of this embodiment will be explained below.

[0168] The support pillar HRa is formed in the boundary region of two adjacent blocks BLK. Furthermore, the slit SH is formed by dividing the laminated structure into multiple parts by leaving a portion of the support pillar HRa. Therefore, during the film deposition process of conductor layers 22-25, the two laminated structures, previously separated by the slit SH and the support pillar HRa, become physically connected via the support pillar HRa. This suppresses incline of the laminated structure that occurs during the film deposition process of conductor layers 22-25.

[0169] The following further explanation is provided: the YZ cross-section of the laminated structure in each block BLK is asymmetrical relative to the central axis along the Z direction. In particular, in the lead-out regions HA1 and HA2, a gradient along the Y direction sometimes forms, and this asymmetry tends to increase. Consequently, during the film formation process of conductor layers 22-25, stress in the Y direction caused by this asymmetry is generated in the laminated structure. The upper part of the laminated structure interrupted by the slit SH is unsupported, and therefore the laminated structure may tilt due to this stress in the Y direction, potentially closing the slit SH, which is undesirable.

[0170] According to the first embodiment, the support pillar HRa physically connects the stacked structures that are disconnected by the slit SH in the lead-out regions HA1 and HA2. Thus, one of the adjacent stacked structures transmits stress in the Y direction to the other stacked structure via the support pillar HRa. Therefore, tilting of the stacked structures can be suppressed, thereby improving the yield of the semiconductor memory device.

[0171] Furthermore, the support pillar HRa has a lower pillar LHRa and an upper pillar UHRa, and the extension of the side surface LHRa_s of the lower pillar LHRa is offset from the extension of the side surface UHRa_s of the upper pillar UHRa within the YZ section. This support pillar HRa is formed in a two-layer structure. That is, the support pillar HRa is formed together with another support pillar HRb. Therefore, tilting of the multilayer structure can be suppressed without adding a new process for forming the support pillar HRa. This, in turn, reduces the increase in the manufacturing load of the semiconductor memory device 3.

[0172] Furthermore, the length of the support post HRa in the Y direction is longer than the width of the component SLT in the Y direction. This prevents the spacing between the two parts of the laminated structure from being shorter than the width of the component SLT. Therefore, the voltage withstand capability reduction between the two conductive layers 22-25 can be suppressed. Moreover, even when the position of the slit SH is offset relative to the support post HRa in the Y direction, sufficient margin for separating the laminated structures can be reliably ensured.

[0173] 1.4 Variation Examples

[0174] Furthermore, the first embodiment is not limited to the above example, and various variations are also applicable.

[0175] 1.4.1 First Variation of the First Embodiment

[0176] Figure 25 This is a top view showing an example of the detailed planar layout of the lead-out area of ​​a semiconductor memory device according to a first variation of the first embodiment. Figure 25 Corresponding to Figure 8 .

[0177] like Figure 25 As shown, in the lead-out areas HA1 and HA2, the part of component SLT that is connected to the lower stepped part is wider in the Y direction.

[0178] The closer a support column HRa is to the lower stepped section, the larger its XY cross-sectional area. Specifically, the length of the support column HRa along the Y direction is longer than the width of the component SLT at that location.

[0179] The closer the support column HRb is to the lower platform section, the larger the XY cross-sectional area of ​​the support column HRb.

[0180] The following additional explanation is provided: When creating openings in a multilayer structure containing oxide and nitride films using anisotropic etching, there is a tendency that the more oxide film is processed, the larger the opening area. Furthermore, in the lead-out regions HA1 and HA2, the region with the stepped portion corresponding to the underlying wiring layer has a higher proportion of oxide film in the multilayer structure. Therefore, when creating openings in the multilayer structure in the lead-out regions HA1 and HA2 using anisotropic etching, even when using masks with the same shape for multiple opening regions, the region with the stepped portion corresponding to the underlying wiring layer has a larger opening area.

[0181] As described above, the support pillar HRa is formed together with the support pillar HRb. That is, the hole Ha, which forms the opening for the support pillar HRa, is formed by anisotropic etching to open the multilayer structure containing the oxide film and the nitride film. As a result, as the width of the component SLT increases, the XY cross-sectional area of ​​the support pillar HRa increases.

[0182] 1.4.2 Second variation of the first embodiment

[0183] Furthermore, in the first variation of the first embodiment, it was explained that the support column HRa, which is more connected to the lower step portion, has a larger XY cross-sectional area, but this is not a limitation. For example, it is also possible to configure the XY cross-sectional area of ​​the support column HRa so that it does not change regardless of its placement.

[0184] Figure 26This is a top view showing an example of the detailed plan layout of the lead-out area of ​​a semiconductor memory device in a second variation of the first embodiment. Figure 26 Corresponding to Figure 25 .like Figure 26 As shown, the component SLT becomes wider in the Y direction the further it is from the storage region MA. On the other hand, in the lead-out regions HA1 and HA2, the XY cross-sectional areas of the support pillars HRa and HRb do not change significantly regardless of their distance from the storage region MA. For example, the XY cross-sectional area of ​​support pillar HRa can be the same size as that of support pillar HRb.

[0185] In this case, two support columns HRa arranged along the Y direction are configured to break the component SLT into two parts. Figure 26 The example illustrates the following situation: the component SLT is divided into four parts by arranging three groups of two support columns HRa along the X direction relative to one component SLT, and the two support columns HRa are arranged along the Y direction.

[0186] A third portion of the multilayer wiring structure is disposed between two support posts HRa arranged along the Y direction. This third portion of the multilayer wiring structure is disconnected from either the first portion of the multilayer wiring structure corresponding to block BLK0 or the second portion of the multilayer wiring structure corresponding to block BLK1. That is, the third portion of the multilayer wiring structure is surrounded by the two portions of component SLT and the two support posts HRa in top view. Similar to the first and second portions of the multilayer wiring structure, the third portion of the multilayer wiring structure is formed by replacing the sacrificial component with a wiring layer through a displacement process.

[0187] Figure 27 This is an example of the cross-sectional structure of the lead-out region of the semiconductor memory device, representing a second variation of the first embodiment. Figure 26 A sectional view of the XXVII-XXVII line. Figure 27 The diagram shows the four parts of the component SLT, the three third parts of the multilayer wiring structure, and the three bridging wiring layers CH.

[0188] like Figure 27 As shown, at least a portion of conductive layers 22 (SEP) to 25 (SEP) are provided in the third part of the multilayer wiring structure, and the conductive layers 22 (SEP) to 25 (SEP) are arranged separately from each other along the Z direction. Figure 27In this example, a conductive layer 22 (SEP) and one conductive layer 23 (SEP) are provided in the third part of the multilayer wiring structure on the left side of the paper. A conductive layer 22 (SEP), four conductive layers 23 (SEP), and one conductive layer 24 (SEP) are provided in the third part of the multilayer wiring structure in the center of the paper. A conductive layer 22 (SEP), four conductive layers 23 (SEP), four conductive layers 24 (SEP), and a conductive layer 25 (SEP) are provided in the third part of the multilayer wiring structure on the right side of the paper. The conductive layers 22 (SEP) to 25 (SEP) are formed simultaneously with the conductive layers 22 to 25 during the replacement process of the sacrificial component.

[0189] Conductor layers 22 (SEP) to 25 (SEP) are disposed at the same height relative to conductor layers 22 to 25 and are electrically insulated from each other. In addition, the conductor layers 22 (SEP) to 25 (SEP) disposed in the three third parts of the multilayer wiring structure are also electrically insulated from each other.

[0190] Figure 28 This is an example of the cross-sectional structure of the lead-out region of the semiconductor memory device, representing a second variation of the first embodiment. Figure 26 A cross-sectional view of the XXVIII-XXVIII line. Figure 28 The YZ section of the support column HRa at the position where it connects with the X-direction end of component SLT is shown. Furthermore, the contact surface between the X-direction end of component SLT and support column HRa is indicated by a single-point chain line.

[0191] like Figure 28 As shown, the contact surface (YZ end face) of component SLT with the two support columns HRa has two edges E1 and E2 extending along the Z direction. Edge E1 spans from the upper end to the lower end of one of the two support columns HRa and continuously intersects with that support column HRa. Edge E2 spans from the upper end to the lower end of the other support column HRa and continuously intersects with that other support column HRa.

[0192] As described above, the YZ section of component SLT has a curved shape, therefore the positions of edges E1 and E2 along the Y direction vary within range D3. Furthermore, the length of the upper end of the lower column LHRa of the support column HRa in the Y direction is longer than the length of the lower end of the upper column UHRa in the Y direction. Therefore, the range D4, from the upper end to the lower end of the support column HRa, is the range containing the portion of the support column HRa with the shortest length in the Y direction. By arranging two support columns HRa such that range D3 is included within range D4, the conditions related to the aforementioned edges E1 and E2 are satisfied.

[0193] Based on the above configuration, even without increasing the XY cross-sectional area of ​​the support column HRa corresponding to the increase in the width of the component SLT, the laminated structure can be disconnected in each block BLK by forming a slit SH, and the two disconnected laminated structures can be physically connected. Therefore, the tilting of the laminated structure that occurs during the film formation process of the conductor layers 22-25 can be suppressed.

[0194] Furthermore, by making the opening areas of holes Ha and Hb consistent, the etching process of hole Ha, which has a larger opening area, can be prevented from being over-etched compared to hole Hb, which has a smaller opening area. Therefore, the manufacturing load on support pillars HRa and HRb can be reduced.

[0195] 1.4.3 Third variation of the first embodiment

[0196] Furthermore, the first embodiment describes a situation where the support pillars HRa, respectively located in two boundary regions separated by block BLK, are positioned at the same location in the X direction, but this is not a limitation. For example, the multiple support pillars HRa may also be configured in a zigzag pattern.

[0197] Figure 29 This is a top view showing an example of a detailed planar layout of the lead-out area of ​​the memory cell array in the third variation of the first embodiment of the semiconductor memory device. Figure 29 Corresponding to Figure 8 .

[0198] like Figure 29 As shown, the support columns HRa, respectively located in the two boundary regions separated by block BLKo, are positioned at different locations in the X direction. The support columns HRa, respectively located in the two boundary regions separated by block BLKe, are also positioned at different locations in the X direction. Conversely, the support columns HRa, respectively located in the two boundary regions separated by blocks BLKo and BLKe, are positioned at the same location in the X direction.

[0199] With the above configuration, the stress in the Y direction generated in the laminated structure during the replacement of the sacrificial component can also be transferred to other laminated structures via the support column HRa. Thus, the same effect as in the first embodiment can be achieved.

[0200] 2. Second Implementation Method

[0201] Next, the semiconductor memory device according to the second embodiment will be described. In the semiconductor memory device of the second embodiment, the multilayer wiring structure is arranged above the peripheral circuits such as the line decoder module 15. Furthermore, the semiconductor memory device of the second embodiment differs from the semiconductor memory device of the first embodiment in that the lead-out region HA is located in the central portion separated by the memory region MA. In the following description, the configuration and manufacturing method identical to those of the first embodiment will be omitted; the description will primarily focus on the configuration and manufacturing method different from those of the first embodiment.

[0202] 2.1 Composition

[0203] 2.1.1 Overview of the planar layout of the memory cell array

[0204] Figure 30 This is a top view showing an example of the planar layout of the memory cell array included in the semiconductor memory device of the second embodiment. Figure 30 The text shows the regions corresponding to the eight blocks BLK0 to BLK7. For example... Figure 30 As shown, the memory cell array 10 includes multiple components SLT and multiple components SHE. Furthermore, the planar layout of the memory cell array 10 is, for example, divided in the X direction into memory regions MA1 and MA2, and an outgoing region HA. The outgoing region HA is disposed between memory regions MA1 and MA2.

[0205] Multiple component SLTs each have multiple sections (not shown) extending along the X direction and arranged along the Y direction. Each component SLT traverses storage areas MA1 and MA2 and the lead-out area HA along the X direction in the boundary region between adjacent blocks BLK.

[0206] In the second embodiment, the component SLT connected to block BLKk (k = 4 × i (i is an integer greater than or equal to 0)) on the upper side of the paper is called "SLTa". The component SLT connected to block BLK(k+1) on the upper side of the paper is called "SLTb". The component SLT connected to block BLK(k+2) on the upper side of the paper is called "SLTc". The component SLT connected to block BLK(k+3) on the upper side of the paper is called "SLTd". That is, in the memory cell array 10, there are multiple groups of components SLTa, SLTb, SLTc and SLTd arranged along the Y direction.

[0207] Multiple component SHEs are configured in storage areas MA1 and MA2 respectively. The component SHEs corresponding to storage area MA1 are arranged transversely across storage area MA1 and along the Y-direction. The component SHEs corresponding to storage area MA2 are arranged transversely across storage area MA2 and along the Y-direction.

[0208] The lead-out area HA contains multiple lead-out sections HP arranged along the Y direction. Each lead-out section HP is configured in units of two blocks BLK. In other words, each lead-out section HP is configured within the lead-out area HA in an area separated by two components SLT separated by two adjacent blocks BLK.

[0209] Hereinafter, odd-numbered headers HP will be referred to as "HPo", and even-numbered headers HP will be referred to as "HPe". For example, headers HPo are configured in the header region HA in the group of blocks BLK0 and BLK1, and in the group of blocks BLK4 and BLK5. Headers HPe are configured in the header region HA in the group of blocks BLK2 and BLK3, and in the group of blocks BLK6 and BLK7.

[0210] Each lead-out section HP includes a contact area CCT and two contact areas C4T. The contact area CCT is the region containing the stepped structure of the multilayer wiring. The contact area C4T is the insulating region that runs through the multilayer wiring structure. The contact areas CCT and C4T are arranged along the X-direction.

[0211] In each lead-out section HP, the contact area CCT is configured such that it spans a component SLT between two adjacent block areas and overlaps with a portion of the respective Y-direction region of the two adjacent block areas. The component SLT intersecting the contact area CCT is a stepped structure that divides the stacked wiring of two adjacent BLK blocks for each BLK block, which share the contact area CCT. Specifically, the contact areas CCT in lead-out sections HPo corresponding to blocks BLK0 and BLK1, and the contact areas CCT in lead-out sections HPo corresponding to blocks BLK4 and BLK5, are respectively divided by component SLTb. The contact areas CCT in lead-out sections HPe corresponding to blocks BLK2 and BLK3, and the contact areas CCT in lead-out sections HPe corresponding to blocks BLK6 and BLK7, are respectively divided by component SLTd.

[0212] In each lead-out section HP, two contact regions C4T are provided in each of two adjacent blocks BLK. Each contact region C4T is separated by two components OST arranged separately along the Y direction. Each component OST extends along the X direction and has a structure with an insulator embedded inside. The multilayer wiring of each block BLK is electrically connected by bypassing the contact region C4T between storage regions MA1 and MA2. That is, the multilayer wiring has a portion arranged along the Y direction with the contact region C4T.

[0213] In the lead-out region HA, the contact regions CCT and C4T of each lead-out section HP are arranged alternately. Specifically, the arrangement of the contact regions CCT and C4T in lead-out section HPe is the same as the arrangement obtained by reversing the contact regions CCT and C4T in the X direction in lead-out section HPo. That is, in lead-out section HPo, the contact region CCT is arranged on the storage region MA1 side, and the contact region C4T is arranged on the storage region MA2 side. In lead-out section HPe, the contact region C4T is arranged on the storage region MA1 side, and the contact region CCT is arranged on the storage region MA2 side.

[0214] 2.1.2 Lead-out area

[0215] (Floor plan layout)

[0216] Figure 31 This is a top view showing an example of a detailed planar layout of the lead-out area of ​​the memory cell array provided in the semiconductor memory device of the second embodiment. Figure 31 In addition to showing the areas corresponding to the two blocks BLK0 and BLK1 that correspond to the lead-out section HPo, a portion of the nearby storage areas MA1 and MA2 is also shown.

[0217] like Figure 31 As shown, in the lead-out area HA, the storage cell array 10 includes multiple contacts CC and C4, multiple bridging wiring layers CH, multiple components OST, and multiple support pillars HRa, HRb and HRc.

[0218] In the lead-out region HA, the select gate line SGD has a stepped portion that does not overlap with the upper conductor layer. In the contact region CCT, the select gate line SGS and word lines WL0 to WL7 each have stepped portions that do not overlap with the upper conductor layer. The contact region C4T is the region that does not include the select gate lines SGS and SGD, and the word lines WL0 to WL7.

[0219] The stepped portion in the lead-out region HA has a shape similar to a step, a platform, or a curb. Specifically, there are step differences between the select gate line SGS and the word line WL0, between word line WL0 and word line WL1, ..., between word line WL6 and word line WL7, and between word line WL7 and the select gate line SGD. Figure 31 The example shows the following situation, in which a portion of each word line WL0 to WL7 is set in a stepped shape with a grade difference in the X direction.

[0220] Multiple contacts CC are respectively disposed on the stepped portions of the select gate line SGS, word lines WL0 to WL7, and select gate lines SGD0 to SGD4 within each block BLK. Multiple contacts C4 are disposed within the contact area C4T corresponding to the select gate line SGS and word lines WL0 to WL7. Multiple contacts CC and multiple contacts C4 disposed within the lead-out portion HP and within a block BLK are, for example, arranged in a straight line. These contacts do not necessarily have to be arranged in a straight line; they can also be staggered vertically.

[0221] Each stacked layer wiring connected to the NAND string NS is electrically connected to the line decoder module 15, for example, via a group of contacts CC and C4. In this example, the select gate line SGS and word lines WL0 to WL7 are connected to the line decoder module 15 via a group of contacts CC and C4 configured in the lead-out area HA, respectively. The select gate line SGD can be connected to the line decoder module 15 via the same path as the word line WL, or it can be connected to the line decoder module 15 via an area outside the lead-out area HA.

[0222] In the lead-out area HA, each component SLT is broken into multiple parts by at least one support post HRa. Figure 31 The example illustrates a situation where six support posts HRa are configured relative to one component SLT, dividing the component SLT into seven parts. Each of the parts opposite the contact area CCT and the part opposite the contact area C4T is configured with six support posts HRa.

[0223] In the lead-out area HA, multiple support posts HRc are arranged along the contact area C4T. Each component OST is broken into multiple parts by at least one support post HRc. Figure 31 The example illustrates a situation where a component OST is divided into three parts by configuring two support posts HRc relative to it. The support posts HRc, positioned across the contact region C4T in the Y direction, are located at the same position in the X direction. The contact region C4T is isolated from the multilayer wiring along the Y direction by the component OST and the support posts HRc. That is, the component OST and the support posts HRc are located in the portion of the multilayer wiring aligned with the contact region C4T along the Y direction and in the boundary region of the contact region C4T.

[0224] In the lead-out area HA, multiple support pillars HRb are appropriately configured in the following area, which does not include the portion forming component SLT and support pillar HRa, the portion forming component OST and support pillar HRc, and the portion forming contacts CC and C4.

[0225] (Cross-section structure)

[0226] Figure 32This is an example of the cross-sectional structure of the lead-out region of the memory cell array included in the semiconductor memory device of the second embodiment. Figure 31 A sectional view of the XXXII-XXXII line. Figure 32 This indicates the outgoing region HA, and a portion of the storage regions MA1 and MA2.

[0227] like Figure 32 As shown, the memory cell array 10 further includes a conductive layer 29 disposed between the semiconductor substrate 20 and the conductive layer 22. The lower end of the memory pillar MP is configured to be connected to the conductive layer 29. The conductive layer 29 is formed, for example, as a plate extending along the XY plane and serves as the source line SL. The conductive layer 29 includes, for example, phosphorus-doped silicon.

[0228] In the lead-out region HA, a portion of each of the multiple conductive layers 22-25 is configured in a stepped shape. Similarly, in the contact region CCT, a portion of each of the multiple conductive layers 22-24 is configured in a stepped shape.

[0229] In the contact region C4T, a portion of the conductive layer 29 is replaced by the insulating layer INS. Furthermore, in the contact region C4T, multiple sacrificial components SM (42, 44, and 47) remain unreplaced within the multiple conductive layers 22-24. Moreover, multiple contacts C4 penetrate the multiple sacrificial components SM and the insulating layer INS. That is, each contact C4 is isolated from and electrically insulated from the multiple conductive layers 22-24 and 29.

[0230] Furthermore, the memory cell array 10 also includes a plurality of conductive layers 28 disposed within an insulating layer between the semiconductor substrate 20 and the conductive layer 29. In the contact region C4T, a plurality of contacts C4 are disposed between the plurality of conductive layers 27 and the plurality of conductive layers 28 respectively. Each conductive layer 28 is connected to a transistor TR. Within the semiconductor substrate 20 and in the insulating layer between the semiconductor substrate 20 and the conductive layer 29, circuitry corresponding to, for example, a line decoder module 15 and a sense amplifier module 16, is provided as circuitry including the transistor TR, but this is not shown in the figure.

[0231] Figure 33 This is an example of the cross-sectional structure of the lead-out region of the memory cell array included in the semiconductor memory device of the second embodiment. Figure 31 A sectional view of line XXXIII-XXXIII. Figure 33 The diagram shows the YZ cross-section of support post HRa and two support posts HRb. Support post HRa disconnects the contact area CCT of blocks BLK0 and BLK1 and its nearby wiring layer, bridging wiring layer CH, two contacts CC, components SLTa and SLTc, and component SLTb.

[0232] like Figure 33 As shown, in the contact region CCT, the regions corresponding to each block BLK, the regions forming the stepped portions of the wiring layer and the regions that are not the stepped portions of any of the conductive layers 22-24 are arranged along the Y direction. Therefore, in the contact region CCT, the YZ cross-section of the multilayer wiring structure of the block BLK unit is asymmetrical along the central axis in the Z direction.

[0233] Figure 34 , Figure 35 and Figure 36 This illustrates an example of the cross-sectional structure of the lead-out region of the memory cell array included in the semiconductor memory device of the second embodiment. Figure 34 It is along Figure 31 A sectional view of the XXXIV-XXXIV line. Figure 34 The diagram shows the YZ cross-section of support post HRa and two support posts HRc. Support post HRa disconnects the contact area C4T of each block BLK0 and BLK1 and its nearby wiring layer, bridging wiring layer CH, components SLTa and SLTc, two components OST of block BLK1, and component SLTb. The two support posts HRc disconnect the two components OST of block BLK0. Figure 35 yes Figure 34 A magnified view of region XXXV. Figure 36 It is along Figure 31 A sectional view of the XXXVI-XXXVI line. Figure 36 The XZ section represents the three parts of component OST and the two support columns HRc.

[0234] like Figures 34 to 36 As shown, the component OST has multiple portions extending along the X direction and is disposed between the conductive layers 22-24 and the sacrificial component SM. The YZ cross-section of the component OST is, for example, curved. Specifically, the length of the component OST along the Y direction is minimum at the upper or lower end and maximum between the upper and lower ends. Furthermore, the component OST may have internal pores (Voids). Pores (Voids) are formed in each portion of the component OST that is interrupted by support pillars (HRc). Therefore, the length of each pore (Void) along the X direction is shorter than the interval between the two support pillars (HRc) arranged along the X direction.

[0235] The support column HRc has a structure in which an insulator is embedded in a hole extending along the Z direction, and it has a through-layer structure. The support column HRc includes an upper column UHRc and a lower column LHRc. The lower end of the lower column LHRc is connected to the conductive layer 29. The upper end of the lower column LHRc and the lower end of the upper column UHRc are connected between the uppermost conductive layer 23 and the lowermost conductive layer 24. The boundary height between the upper end of the lower column LHRc and the lower end of the upper column UHRc is the same as the boundary height between the upper end of the lower column LHRc and the lower end of the upper column UHRc. The XY cross-sectional area of ​​each lower column LHRc and upper column UHRc increases from bottom to top.

[0236] Furthermore, the XY cross-sectional area of ​​the upper end of the lower column LHRc is larger than that of the lower end of the upper column UHRc. Specifically, the upper end of the lower column LHRc is longer along the Y direction than the lower end of the upper column UHRc. The extension of the side surface LHRc_s of the lower column LHRc is similar to the extension of the side surface UHRc_s of the upper column UHRc. Figure 35 (The single-point chain diagram is shown in the figure.) The segments are staggered and not aligned within the YZ section. On the other hand, the upper end of the lower column LHRc and the lower end of the upper column UHRc have the same length along the X direction. The extension of the side surface LHRc_s of the lower column LHRc and the extension of the side surface UHRc_s of the upper column UHRc are aligned within the XZ section.

[0237] In addition, the components SLT and the support pillars HRa and HRb have the same structure as in the first embodiment, except that the lower end is connected to the conductor layer 29, so the description is omitted.

[0238] 2.2 Manufacturing method of semiconductor memory device

[0239] Figure 37 This is a flowchart illustrating an example of a method for manufacturing a semiconductor memory device according to the second embodiment. Figures 38-48 Examples of planar layouts or cross-sectional structures during the manufacturing process of the semiconductor memory device according to the second embodiment are shown. The illustrated planar layouts are shown in the diagrams. Figure 31 The corresponding area. The cross-sectional structure shown in the diagram is also represented. Figure 34 The corresponding region is part of the storage region MA. For example... Figure 37 As shown, in the manufacturing process of the semiconductor memory device 3 according to the second embodiment, processes S201 to S213 are performed sequentially. Hereinafter, reference will be made as appropriate. Figure 37 An example of the manufacturing process of the multilayer wiring structure within the memory cell array 10 of the semiconductor memory device 3 will be described.

[0240] First, execute the processes S201 to S203 in sequence, such as... Figure 38As shown, a lower part of a laminated structure including sacrificial components 42 and 44 is formed, a stepped structure is formed in the lower part of the laminated structure, and multiple holes LMH, LHa, LHb and LHc are formed. The multiple holes LHb are not shown.

[0241] In short, peripheral circuits such as the line decoder module 15 are first formed on the semiconductor substrate 20. Above the peripheral circuits, a layer including a conductive layer 29 and an insulating layer INS is formed. An insulating layer 41 is formed on this layer. Sacrificial components 42 and insulating layers 43 are sequentially formed on the insulating layer 41. Sacrificial components 44 and insulating layers 43 are alternately deposited on the insulating layer 43 (S201).

[0242] Then, the ends of the sacrificial members 42 and 44 of the laminate are machined into a stepped shape within the lead-out region HA. Subsequently, an insulating layer is embedded into the stepped portion within the lead-out region HA. The upper surface of the laminated structure is planarized, for example, by CMP (S202).

[0243] Subsequently, a mask is formed by photolithography to create openings in the regions corresponding to the lower pillars LMP, LHRa, LHRb, and LHRc. Then, holes LMH, LHa, LHb, and LHc are formed by anisotropic etching of this mask. These holes LMH, LHa, LHb, and LHc penetrate, for example, insulating layers 41 and 43, and sacrificial components 42 and 44. At the bottom of each hole LMH, LHa, LHb, and LHc, a portion of the conductive layer 29 is exposed (S203). Holes LMH, LHa, LHb, and LHc correspond to the lower pillars LMP, LHRa, LHRb, and LHRc, respectively. Subsequently, as... Figure 39 As shown, sacrificial members 45 are embedded in holes LMH, LHa, LHb, and LHc. By removing the sacrificial members 45 formed on the upper surface of the laminated structure using, for example, CMP, the surfaces corresponding to the upper ends of each lower pillar LMP, LHRa, LHRb, and LHRc are exposed.

[0244] Next, processes S204 to S206 are executed sequentially, such as... Figure 39 As shown, a stacked structure upper part including sacrificial components 47 and 48 is formed, a stepped structure is formed in the stacked structure upper part, and multiple holes UMH, UHa, UHb and UHc are formed.

[0245] In short, firstly, an insulating layer 46 is formed on the laminated structure. Sacrificial members 47 and insulating layers 46 are alternately laminated on the insulating layer 46. Sacrificial members 48 and insulating layers 49 are sequentially formed on the insulating layer 46 (S204).

[0246] Then, the ends of the sacrificial members 47 and 48 of the laminate are machined into a stepped shape within the lead-out region HA. Subsequently, an insulating layer is embedded into the stepped portion within the lead-out region HA. The upper surface of the laminated structure is planarized, for example, by CMP (S205).

[0247] Subsequently, a mask with openings corresponding to the upper pillars UMP, UHRa, UHRb, and UHRc is formed by photolithography or the like. Then, holes UMH, UHa, UHb, and UHc are formed by anisotropic etching of this mask. Hole UMH penetrates, for example, insulating layers 46 and 49, and sacrificial members 47 and 48. Holes UHa, UHb, and UHc penetrate, for example, insulating layer 46, and sacrificial member 47. At the bottom of hole UMH, a portion of the sacrificial member 45(MP) embedded in hole LMH is exposed. At the bottom of hole UHa, a portion of the sacrificial member 45(HRa) embedded in hole LHa is exposed. At the bottom of hole UHb, a portion of the sacrificial member 45(HRb) embedded in hole LHb is exposed. At the bottom of hole UHc, a portion of the sacrificial member 45(HRc) embedded in hole LHc is exposed (S206). The holes UMH, UHa, UHb and UHc correspond to the upper columns UMP, UHRa, UHRb and UHRc, respectively.

[0248] Next, multiple support columns HRa, HRb, and HRc (S207) are formed. Specifically, as follows: Figure 40 As shown, the sacrificial components 45 formed in the holes LMH, LHa, LHb, and LHc are first removed, for example, by wet etching. This forms the holes MH corresponding to LMH and UMH, Ha corresponding to LHa and UHa, Hb corresponding to LHb and UHb, and Hc corresponding to LHc and UHc (all not shown). Then, a mask 50 is formed by embedding the hole MH. Subsequently, an insulator is formed by filling the holes Ha, Hb, and Hc, thereby forming the support pillars HRa, HRb, and HRc.

[0249] Next, as Figure 41 Multiple storage columns MP are formed as shown (S208). The process for forming the storage columns MP is the same as in the first embodiment, so the description is omitted.

[0250] Through the processing up to S208, such as Figure 42As shown, multiple support pillars HRa, HRb, and HRc are formed in the lead-out area HA, and multiple memory pillars MP are formed in the memory areas MA1 and MA2. The multiple support pillars HRa are configured in a predetermined area for forming the component SLT. The multiple support pillars HRc are configured in a predetermined area for forming the component OST. The multiple support pillars HRb are appropriately configured in an area that does not include predetermined portions for forming the component SLT and support pillars HRa, predetermined portions for forming the component OST and support pillars HRc, and predetermined portions for forming contacts CC and C4.

[0251] Next, as Figure 43 and Figure 44 As shown, multiple slits SH, including slits SGa to SHc, and multiple OSHs are formed (S209). Specifically, firstly, a mask with openings corresponding to the regions of components SLT and OST is formed by photolithography or the like. Subsequently, slits SH are formed by anisotropic etching of the mask, and these slits SH penetrate, for example, insulating layers 41, 43, 46, and 49, and sacrificial components 42, 44, 47, and 48. Furthermore, slits OSH are formed, and these slits SH penetrate, for example, insulating layers 41, 43, and 46, and sacrificial components 42, 44, and 47.

[0252] Furthermore, the slit OSH is formed by dividing a portion of the remaining support column HRc in a top view into multiple parts. Specifically, similar to the relationship between the slit SH and the support column HRa, the opposing YZ end faces of the two slit OSHs separated by the support column HRc continuously intersect the upper to lower ends of the support column HRc. Therefore, the length of the support column HRc along the X direction is equal to the interval between the two slit OSHs separated by the support column HRc. That is, the length of the upper end of the lower column LHRc along the X direction is the same as the length of the lower end of the upper column UHRc along the X direction.

[0253] Next, as Figure 45 As shown, component OST (S210) is formed within each slit OSH. Specifically, an insulating portion is first formed to cover the sides and bottom of the slit OSH. Then, the insulating portion formed outside the slit OSH is removed, for example, by CMP. Additionally, a pore Void is formed within each component OST. The pore Void is interrupted by the support column HRc, just like the component OST.

[0254] Next, the replacement process for the sacrificial components of the stacked structure is performed, such as... Figure 46The multilayer wiring structure is formed as shown (S211). The replacement process of the sacrificial component is the same as in the first embodiment, so the description is omitted. In addition, the sacrificial component SM located in the contact area C4T is blocked from the intrusion of hot phosphoric acid, etc. by the component OST and the support pillar HRc, so it is not replaced and remains. Therefore, the area in the multilayer wiring structure that overlaps with the contact area C4T becomes an insulating area.

[0255] Next, as Figure 47 As shown, component SLT (S212) is formed within each slit SH. The forming process of component SLT is the same as in the first embodiment, so the description is omitted.

[0256] Finally, as Figure 48 The diagram shows the formation of multiple contacts CC, multiple contacts C4, and multiple bridging wiring layers CH (S213). Specifically, a mask with openings corresponding to the regions of contacts C4 is formed by photolithography or the like. Then, holes penetrating the contact regions C4T are formed, for example, by anisotropic etching of the mask. The corresponding conductive layer 28 is exposed at the bottom of each hole. Subsequently, a conductor is embedded in the hole. For example, the conductor formed on the upper surface of the multilayer structure is removed by CMP, thereby exposing the surfaces corresponding to the upper ends of each of the multiple contacts C4.

[0257] Furthermore, the formation process of the contact CC and the bridging wiring layer CH is the same as in the first embodiment, so the description is omitted.

[0258] The multilayer wiring structure within the memory cell array 10 is formed through the manufacturing processes described above. Furthermore, the manufacturing processes described above are merely examples, and the present invention is not limited thereto. For example, other processes may be inserted between the manufacturing processes, or some processes may be omitted or combined. Moreover, the manufacturing processes may be interchanged within permissible limits. For example, the process of forming the memory pillar MP may be interchanged with the process of forming the support pillars HRa, HRb, and HRc.

[0259] 2.3 Effects of this implementation method

[0260] The contact region CCT is configured to span the component SLT between the two block regions and overlap with a portion of each of the two block regions in the Y direction. Therefore, similar to the first embodiment, the YZ cross-section of the laminated structure of each block BLK in the region containing the contact region CCT is asymmetrical along the central axis in the Z direction. Consequently, during the film formation process of the conductive layers 22-25, stress is generated in the laminated structure near the contact region CCT, causing the laminated structure to tilt in the Y direction.

[0261] Furthermore, in the lead-out region HA, two components OST extending in the X direction are arranged in the Y direction with the contact region C4T separated from them. Therefore, during the film formation process of conductor layers 22-25, one portion of the laminated structure separated by the slit SH and the component OST is supported by the component OST, while the other is unrestrained. Moreover, due to the voids within the component OST, the restraining force in the Y direction of the laminated structure decreases, which may cause tilting in the laminated structure near the contact region C4T during the film formation process of conductor layers 22-25.

[0262] According to the second embodiment, the support column HRa physically connects the laminated structures that are disconnected by the slit SH near each contact region CCT and C4T in the lead-out region HA. Thus, one of the adjacent laminated structures can transmit stress in the Y direction to the other laminated structure via the support column HRa. Therefore, tilting of the laminated structures can be suppressed near each of the contact regions CCT and C4T.

[0263] Furthermore, the support post HRc is positioned at the point where the component OST extending along the X direction is disconnected. Moreover, the slit OSH is formed by dividing it into multiple parts with a portion remaining from the support post HRc. Thus, the support post HRc can divide the void within the component OST into multiple parts. Therefore, the effect of binding the laminated structures at both ends of the component OST together can be achieved. This further suppresses the tilting of the laminated structure near the contact area C4T.

[0264] Furthermore, the support pillar HRc has a lower pillar LHRc and an upper pillar UHRc, forming a two-tiered structure. Specifically, the extension of the side surface LHRc_s of the lower pillar LHRc is offset from the extension of the side surface UHRc_s of the upper pillar UHRc within the YZ section. That is, the support pillar HRc is formed together with the other support pillars HRa and HRb. Therefore, tilting of the multilayer structure can be suppressed without adding a new process for forming the support pillar HRc. This, in turn, reduces the increase in the manufacturing load of the semiconductor memory device 3.

[0265] 2.4 Variation Examples

[0266] Furthermore, the second embodiment is not limited to the above example and can be adapted to various variations similar to the first embodiment.

[0267] 2.4.1 First variation of the second embodiment

[0268] Figure 49 This is a top view showing an example of the detailed planar layout of the lead-out area of ​​the semiconductor memory device in the first variation of the second embodiment. Figure 49 Corresponding to Figure 31 .

[0269] like Figure 49 As shown, in the region overlapping with the contact area CCT, the portion of component SLTb that is closer to the lower stepped portion has a wider width in the Y direction. Similarly, in the region overlapping with the contact area CCT, the portion of component SLTd that is closer to the lower stepped portion has a wider width in the Y direction, but this illustration is omitted. On the other hand, in the region not overlapping with the contact area CCT, the width of each component SLTb and SLTd in the Y direction does not change significantly due to their position in the X direction. Furthermore, components SLTa and SLTc do not overlap with the contact area CCT, therefore their width in the Y direction does not change significantly due to their position in the X direction.

[0270] The closer a support column HRa is to the lower stepped section, the larger its XY cross-sectional area becomes in the area overlapping with the contact area CCT. More specifically, the length of the support column HRa in the Y direction in the area overlapping with the contact area CCT is longer than the width of the component SLTb (or SLTd) at that location. On the other hand, the XY cross-sectional area of ​​the support column HRa in the area not overlapping with the contact area CCT does not change significantly due to its placement position in the X direction.

[0271] For support columns HRb located in the area overlapping with the contact area CCT, the closer the support column HRb is to the lower stepped portion, the larger its XY cross-sectional area becomes. On the other hand, the XY cross-sectional area of ​​support columns HRb located in the area not overlapping with the contact area CCT does not change significantly with their location in the X direction.

[0272] The support post HRc is not positioned in the area overlapping with the contact area CCT. Therefore, the XY cross-sectional area of ​​the support post HRc does not change significantly due to its placement in the X direction.

[0273] As described above, the support pillar HRa is formed together with the support pillar HRb. That is, a hole Ha is formed by anisotropic etching to open the multilayer structure containing the oxide film and the nitride film, and this hole Ha is the opening used to form the support pillar HRa. Thus, similar to the first variation of the first embodiment, the XY cross-sectional area of ​​the support pillar HRa increases with the increase of the width of the component SLT.

[0274] 2.4.2 Second variation of the second embodiment

[0275] Furthermore, in the first variation of the second embodiment, it was explained that the support column HRa, which is more connected to the lower step portion, has a larger XY cross-sectional area, but this is not a limitation. For example, the XY cross-sectional area of ​​the support column HRa can also be set so that it does not change regardless of its placement.

[0276] Figure 50 This is a top view showing an example of the detailed plan layout of the lead-out area of ​​a semiconductor memory device in a second variation of the second embodiment. Figure 50 Corresponding to Figure 49 .like Figure 50 As shown, for the portion of component SLTb that overlaps with the contact area CCT, the wider the support column HRa is in the Y direction, the closer it is to the lower stepped portion. On the other hand, in the region overlapping with the contact area CCT, the XY cross-sectional areas of support columns HRa and HRb do not significantly change due to the depth of the layer where the connected stepped portion is located. For example, the XY cross-sectional areas of support columns HRa and HRc can be the same size as the XY cross-sectional area of ​​support column HRb.

[0277] Figure 50 In this example, similar to the first variation of the first embodiment, two support posts HRa arranged along the Y direction are configured to divide the component SLT into two parts. Furthermore, a third part of the multilayer wiring structure is disposed between the two support posts HRa arranged along the Y direction. This third part of the multilayer wiring structure is disconnected from either the first part of the multilayer wiring structure corresponding to block BLK0 or the second part of the multilayer wiring structure corresponding to block BLK1. That is, the third part of the multilayer wiring structure is surrounded by the two parts of the component SLT and the two support posts HRa in a top view.

[0278] Furthermore, two support posts HRc arranged along the Y direction are configured to divide the component OST into two parts. Additionally, a second part of a multilayer structure containing a sacrificial component SM is disposed between the two support posts HRc arranged along the Y direction. This second part of the multilayer structure is disconnected from either the first part of the multilayer wiring structure containing conductor layers 22-24 or the first part of the multilayer structure containing the sacrificial component SM. That is, the second part of the multilayer structure, viewed from above, is surrounded by the two parts of the component OST and the two support posts HRc.

[0279] The relationship between the support column HRa and component SLT, and the relationship between the support column HRc and component OST in the second variation of the second embodiment are the same as the relationship between the support column HRa and component SLT in the second variation of the first embodiment.

[0280] Based on the above configuration, even without increasing the XY cross-sectional area of ​​the support column HRa to correspond to the increase in the width of the component SLT, the laminated structure can be broken in each block BLK by forming a slit SH, and the two broken laminated structures can be physically connected. Therefore, the tilting of the laminated structure that occurs during the film formation process of the conductor layers 22-25 can be suppressed.

[0281] Furthermore, by ensuring that the opening areas of holes Ha to Hc are consistent, the etching of holes Ha and Hc, which have larger opening areas, can be prevented from being excessively etched compared to holes Hb, which have smaller opening areas. Therefore, the manufacturing load on the support pillars HRa to HRc can be reduced.

[0282] 2.4.3 Third variation of the second embodiment

[0283] Furthermore, the second embodiment describes a situation where the support pillars HRa, which are respectively arranged in the two boundary regions separated by block BLK, and the support pillars HRc, which are respectively arranged separated by contact region C4T, are arranged at the same position in the X direction, but this is not a limitation. For example, the multiple support pillars HRa and the multiple support pillars HRc may also be arranged in a serrated shape in the XY plane.

[0284] Figure 51 This is a top view showing an example of a detailed planar layout of the lead-out area of ​​the memory cell array in the third variation of the second embodiment of the semiconductor memory device. Figure 51 Corresponding to Figure 31 .

[0285] like Figure 51 As shown, the support pillars HRa, respectively located in the two boundary regions separated by block BLK0, are positioned at different locations in the X-direction. Similarly, the support pillars HRa, respectively located in the two boundary regions separated by block BLK1, are positioned at different locations in the X-direction. Conversely, the support pillars HRa, respectively located in the two boundary regions separated by blocks BLK0 and BLK1, are positioned at the same location in the X-direction. The support pillars HRc, respectively located across the contact region C4T, are positioned at different locations in the X-direction.

[0286] Based on the above configuration, the stress in the Y direction generated in the laminated structure during the replacement of the sacrificial component can be transferred to other laminated structures via the support column HRa. Furthermore, the void within the component OST can be disconnected via the support column HRc. Thus, the same effects as in the second embodiment can be achieved.

[0287] 3. Other variations

[0288] Furthermore, the embodiments described herein illustrate the case where a support column HRa is configured in the lead-out region HA, but are not limited thereto.

[0289] Figure 52 This is a top view showing an example of a detailed planar layout of the lead-out area of ​​the memory cell array in a semiconductor memory device of the first common variation. Figure 52 Corresponding to Figure 4 .like Figure 52 As shown, the support column HRa can also be configured in the area where the boundary region of two adjacent blocks BLK overlaps with the storage region MA.

[0290] Within the storage region MA, the YZ cross-section of the stacked wiring structure exhibits greater symmetry along the central axis in the Z direction compared to the lead-out regions HA1 and HA2. However, asymmetry arises due to the misalignment between the location of the storage column MP and the location of the slot SH opening. Consequently, a tilting of the stacked wiring structure also occurs within the storage region MA.

[0291] According to the first common variation, the support column HRa is positioned in the region where the storage region MA overlaps with the boundary region, thus disconnecting the component SLT. Therefore, during the replacement of the sacrificial component, adjacent laminated structures in the storage region MA are also physically connected via the support column HRa. Thus, the stress in the Y direction generated in the storage region MA can be transferred to other laminated structures via the support column HRa. This helps to suppress the tilting of the laminated wiring structure in the storage region MA.

[0292] Furthermore, in each of the embodiments described, the case where the XY cross-sectional area of ​​the upper end of the lower column LHRa is greater than the XY cross-sectional area of ​​the lower end of the upper column UHRa, and the case where the XY cross-sectional area of ​​the upper end of the lower column LHRc is greater than the XY cross-sectional area of ​​the lower end of the upper column UHRc are explained. However, each embodiment is not limited to the examples described above.

[0293] Figure 53 This is a cross-sectional view of an example of the cross-sectional structure of a support column that includes the second common variation. Figure 53 Corresponding to Figure 11 .like Figure 53 As shown, the upper end of the lower column LHRa is not angular but has a curved shape. Therefore, Figure 53 In this context, it cannot be definitively stated that the XY cross-sectional area of ​​the upper end of the lower column LHRa is greater than the XY cross-sectional area of ​​the lower end of the upper column UHRa.

[0294] However, in Figure 53 In this case, the supporting column HRa also forms a two-tiered structure, therefore the Y-direction portion of the side surface at the boundary between the upper and lower columns is a discontinuity. Therefore, in the YZ section, it becomes the extension of the side surface LHRa_s of the lower column LHRa and the extension of the side surface UHRa_s of the upper column UHRa (… Figure 53The structure is staggered (as shown in the single-point chain diagram). That is, the XY cross-sectional area of ​​the upper end of the lower column LHRa may not be greater than the XY cross-sectional area of ​​the lower end of the upper column UHRa.

[0295] Furthermore, the aforementioned characteristics shown for the support column HRa also apply to the support columns HRb and HRc, and the storage column MP. However, for the support column HRb and the storage column MP, the misalignment of the two sides is not limited to the YZ section; the two sides will be misaligned in any section including the Z direction, such as the XZ section.

[0296] Furthermore, while the embodiments described herein illustrate a case where the component SLT has a structure including contacts LI, they are not limited to this. For example, the component SLT may also be formed by embedding an insulator within the slit SH. In this case, the bridging wiring layer CH is not formed.

[0297] Furthermore, the embodiments described above illustrate the case where the contacts LI of two adjacent portions of component SLT are electrically connected to each other through a bridging wiring layer CH, but are not limited to this. For example, if the resistance of the source line SL is sufficiently small, the bridging wiring layer CH may be omitted.

[0298] Furthermore, while each of the embodiments described illustrates a case where the semiconductor memory device 3 has a structure configured on a single chip, it is not limited to this. For example, the semiconductor memory device 3 may also be a structure formed by bonding a chip equipped with a sensing amplifier module 16, etc., to a chip equipped with a memory cell array 10.

[0299] Furthermore, while the embodiments described herein present a structure where the word line WL is adjacent to the select gate line SGS and the select gate line SGD, this is not a limitation. For example, a dummy word line may be provided between the uppermost word line WL and the select gate line SGD. Similarly, a dummy word line may be provided between the lowermost word line WL and the select gate line SGS. Moreover, in a structure with multiple pillars having a two-tier structure, the conductive layer near the boundary between the upper and lower pillars may also be used as a dummy word line.

[0300] Furthermore, in the second embodiment, the semiconductor film 31 and the conductive layer 29 are electrically connected via the bottom of the memory pillar MP, but this is not a limitation. The semiconductor film 31 and the conductive layer 29 can also be electrically connected via the side of the memory pillar MP. In this case, a structure is formed in which a portion of the laminated film formed on the side of the memory pillar MP is removed, and the semiconductor film 31 and the conductive layer 29 contact via this portion.

[0301] Several embodiments of the present invention have been described, but these embodiments are merely illustrative and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, and are included in and within the same scope as the invention described in the claims.

Claims

1. A semiconductor memory device comprising: The substrate includes a first block region and a second block region, each extending along a first direction and arranged along a second direction intersecting the first direction; The first component and the second component each extend along the first direction in the first boundary region between the first block region and the second block region, and are arranged along the first direction; The first support column is disposed between the first component and the second component in the first boundary region; Multiple conductive layers, including a first conductive layer and a second conductive layer, are arranged and separated from each other along a third direction that intersects the first direction and the second direction respectively, and are broken by the first component, the second component and the first support column into a first part located in the first block region and a second part located in the second block region; and A first storage column extends through the plurality of conductive layers. The portion intersecting with the first conductive layer functions as a first storage cell, and the portion intersecting with the second conductive layer functions as a second storage cell. This second storage cell is adjacent to the first storage cell in the third direction. The first support column comprises: a lower column having an upper end between the first conductive layer and the second conductive layer; and an upper column having a lower end between the first conductive layer and the second conductive layer; and the first support column has a first shape in which the extensions of the side surface of the lower column and the extensions of the side surface of the upper column are offset in a plane including the second direction and the third direction. The first shape is such that the extension of the side surface of the lower column and the extension of the side surface of the upper column coincide in a plane including the first direction and the third direction; The substrate further includes a first region and a second region arranged along the first direction. The first storage column is configured in the first region. The plurality of conductive layers each have a plurality of stepped portions in the second region that do not overlap with the upper conductive layer.

2. The semiconductor memory device according to claim 1, wherein The first support column is disposed in the region where the first boundary region and the second region overlap, and is connected to the first step portion of the plurality of step portions.

3. The semiconductor memory device according to claim 2, wherein... The region overlapping the first boundary region and the second region further includes: The third component, located on the opposite side to the first component relative to the second component, is arranged along the first direction with respect to both the first and second components; and The second support column is disposed between the second component and the third component, and is connected to the second step portion which is lower than the first step portion among the plurality of step portions, and has the first shape; The length of the second support column along the second direction is longer than the length of the first support column along the second direction.

4. The semiconductor memory device according to claim 3, wherein The width of each of the first, second, and third components along the second direction is longer for the portion corresponding to a lower step.

5. The semiconductor memory device according to claim 2, wherein... The second region overlaps with the ends of the first block region and the second block region along the first direction.

6. The semiconductor memory device according to claim 2, wherein The substrate further includes a third region, which is spaced from the first region by the second region along the first direction. The semiconductor memory device further includes a second memory pillar disposed in the third region and extending through the plurality of conductive layers. The portion of the second memory pillar that intersects with the first conductive layer functions as a third memory cell, and the portion that intersects with the second conductive layer functions as a fourth memory cell. The fourth memory cell is adjacent to the third memory cell in the third direction.

7. The semiconductor memory device according to claim 6, wherein The second region includes a sub-region configured to extend across the first boundary region and overlap with a portion of both the first block region and the second block region in the second direction. The plurality of conductive layers have the plurality of stepped portions in the sub-region.

8. The semiconductor memory device according to claim 1, wherein The first support column is disposed in the region where the first boundary region overlaps with the first region, the first region extending along the second direction and for arranging the first storage column.

9. The semiconductor memory device according to claim 1, wherein The first component and the second component each comprise: The contact point extends along the third direction; An insulator is disposed between the contact and the first support post and the plurality of conductive layers; The semiconductor memory device further includes a conductor that electrically connects the contacts of the first component to the contacts of the second component above the first support post.

10. The semiconductor memory device according to claim 1, wherein The substrate further includes a third block region, which is located on the opposite side of the first block region relative to the second block region, and is aligned along the second direction with both the first and second block regions. The semiconductor memory device also includes: The fourth and fifth components, in the second boundary region between the second block region and the third block region, each extend along the first direction and are arranged along the first direction; and The fourth support column is disposed between the fourth component and the fifth component in the second boundary region and has the first shape; The first support column and the fourth support column are arranged at different positions along the first direction.

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