integrated circuit

Abstract

An integrated circuit is provided. The integrated circuit includes a three-dimensional memory device, a first word line drive circuit, and a second word line drive circuit. The three-dimensional memory device includes stacked structures extending along a column direction, respectively. Each stacked structure includes a stack of word lines. The stacked structure has a first staircase structure at a first side and a second staircase structure at a second side. The word lines extend to steps of the first and second staircase structures. The first word line drive circuit and the second word line drive circuit are located below the three-dimensional memory device and extend along the first side and the second side, respectively. Some of the word lines in each stacked structure are wired from the first staircase structure to the first word line drive circuit, and other word lines in each stacked structure are wired from the second staircase structure to the second word line drive circuit.

Description

Technical Field

[0001] Embodiments of the present invention relate to an integrated circuit. Background Technology

[0002] Over the past few decades, the ever-increasing demand for data storage has led to the continuous expansion of non-volatile memory (NDRAM) and the evolution of NDRAM cells from single-level cell (SLC) to multi-level cell (MLC). However, these solutions are limited by two-dimensional design. All cells in NDRAM are arranged in a string adjacent to each other, but there is only one level of cells. This ultimately limits the capacity that NDRAM can provide.

[0003] 3D memory represents a new evolution that addresses the storage capacity issue of non-volatile memory. By vertically stacking cells, storage capacity can be significantly increased without substantially increasing the footprint of non-volatile memory. However, as the storage capacity of 3D memory continues to grow, the interconnection between 3D memory and driving devices becomes more complex. Summary of the Invention

[0004] According to one aspect of the present invention, an integrated circuit is provided, comprising: a three-dimensional memory device including stacked structures extending respectively along a column direction, wherein the stacked structures have a first step structure located on a first side of the three-dimensional memory device and a second step structure located on a second side of the three-dimensional memory device; a first word line driving circuit located below the three-dimensional memory device and extending along the first side of the three-dimensional memory device, wherein a first set of word lines in each stacked structure is connected from one of the first step structures to the first word line driving circuit; and a second word line driving circuit located below the three-dimensional memory device and extending along the second side of the three-dimensional memory device, wherein the first word line driving circuit and the second word line driving circuit are laterally spaced apart from each other, and a second set of word lines in each stacked structure is connected from one of the second step structures to the second word line driving circuit.

[0005] According to another aspect of the present invention, an integrated circuit is provided, comprising: a three-dimensional memory device including stacked structures extending respectively along a column direction, wherein the stacked structures have a first step structure located on a first side of the three-dimensional memory device and a second step structure located on a second side of the three-dimensional memory device; a first word line driving circuit located below the three-dimensional memory device and overlapping the first step structure; a first word line wiring extending from the first step structure to the first word line driving circuit, wherein a first set of word lines in each stacked structure is connected to the first word line driving circuit from one of the first step structure through a portion of the first word line wiring; a second word line driving circuit located below the three-dimensional memory device and overlapping the second step structure; and a second word line wiring extending from the second step structure to the second word line driving circuit, wherein a second set of word lines in each stacked structure is connected to the second word line driving circuit from one of the second step structure through a portion of the second word line wiring.

[0006] According to another aspect of the present invention, an integrated circuit is provided, comprising: a semiconductor substrate; a first word line driving circuit and a second word line driving circuit formed on the semiconductor substrate and laterally spaced apart from each other; and a three-dimensional memory device formed above the first word line driving circuit and the second word line driving circuit, and comprising stacked structures extending in a column direction, wherein a first set of word lines in each stacked structure is connected to the first word line driving circuit, and a second set of word lines in each stacked structure is connected to the second word line driving circuit. Attached Figure Description

[0007] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industrial practice, the various components are not drawn to scale and are for illustrative purposes only. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0008] Figure 1A These are schematic illustrations of a portion of a three-dimensional device according to some embodiments of the present disclosure.

[0009] Figure 1B It is for reference. Figure 1A The equivalent circuit diagram of a portion of the described three-dimensional memory device 10.

[0010] Figure 2 This is a schematic diagram illustrating a three-dimensional view of a three-dimensional memory device having a stepped structure on opposite sides according to some embodiments of the present disclosure.

[0011] Figure 3AThis is a schematic diagram illustrating an integrated circuit including a three-dimensional memory device according to some embodiments of the present disclosure.

[0012] Figure 3B This is a schematic diagram illustrating the configuration of a driving circuit and a three-dimensional memory device in an integrated circuit according to some embodiments of the present disclosure.

[0013] Figure 3C This is a cross-sectional view illustrating the word line routing scheme in the same stacking structure according to some embodiments of the present disclosure.

[0014] Figure 3D This is a schematic diagram illustrating word line routing schemes and source line / bit line routing schemes according to some embodiments of the present disclosure.

[0015] Figure 4A This is a diagram for reference. Figure 3A and Figure 3C Another schematic diagram of the described word line routing scheme.

[0016] Figure 4B This is a diagram for reference. Figure 3D Another schematic diagram of the described source line / bit line routing scheme.

[0017] Figure 5 This is a schematic plan view of an integrated circuit according to an alternative embodiment of the present disclosure.

[0018] Figure 6A These are schematic illustrations for reference to some embodiments of this disclosure. Figure 3A , Figure 3C , Figure 4A A three-dimensional view of the driving circuitry and word line routing scheme on another three-dimensional memory device.

[0019] Figure 6B As shown in the diagram Figure 6A A cross-sectional view of the memory cell string in the three-dimensional memory device 10a shown. Detailed Implementation

[0020] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0021] Furthermore, for ease of description, this document may use spacing terms such as “below,” “under,” “lower,” “above,” “upper,” etc., to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spacing terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spacing descriptors used herein may be interpreted accordingly.

[0022] Figure 1A This is a schematic three-dimensional view illustrating a portion of a three-dimensional memory device 10 according to some embodiments of the present disclosure.

[0023] refer to Figure 1A The memory device 10 is a three-dimensional memory device and includes a stack of memory cells MC formed on a base layer 100. In some embodiments, the base layer 100 is an etch stop layer over a semiconductor substrate (not shown), such as a semiconductor wafer or a semiconductor-on-insulator (SOI) wafer. In these embodiments, active devices (e.g., transistors) and interconnections of these active devices (both not shown) may be formed between the base layer 100 and the semiconductor wafer (or SOI wafer).

[0024] The memory cell MC stacks are arranged in columns extending along the Y direction (also called the column direction). These columns are arranged along the X direction (also called the row direction) intersecting the Y direction. To clearly illustrate the elements in each memory cell MC stack, the memory cell MC stack in one of these columns is specifically depicted as standing alone on the base layer 100. Although not shown, other memory cell MC stacks are actually present in that column. Figure 1AAs shown, each memory cell MC stack includes a segment of a stacking structure 102 formed on the base layer 100. Multiple stacking structures 102 extend along the column direction (i.e., direction Y) and are laterally spaced from each other along the row direction (i.e., direction X). Memory cell MC stacks in the same column share the same stacking structure 102, and each stacking structure 102 can be shared by memory cell MC stacks in adjacent columns.

[0025] Word lines 104 and isolation layers 106 are alternately stacked along the vertical direction Z in each stack structure 102. The top layer in the stack structure 102 can be one of the word lines 104 or one of the isolation layers 106. Similarly, the bottom layer in the stack structure 102 can be one of the word lines 104 or one of the isolation layers 106. Furthermore, those skilled in the art can adjust the number of word lines 104 and isolation layers 106 in each stack structure 102, and this disclosure is not limited thereto. The word lines 104 can be formed of a conductive material, while the isolation layers 106 can be formed of an insulating material. For example, conductive materials may include tungsten, titanium nitride, ruthenium, molybdenum, tungsten nitride, etc., while insulating materials may include silicon oxide, silicon nitride, silicon oxynitride, etc.

[0026] The switch layer 108 spans the sidewall of the stack structure 102 and makes lateral contact with the word line 104 and the isolation layer 106 in the stack structure 102. In some embodiments, such as Figure 1A As shown, the switching layer 108 does not extend along a portion of the base layer 100 between the stacked structures 102. In these embodiments, the switching layers 108 are laterally spaced apart from each other. In an alternative embodiment, the switching layers 108 between adjacent stacked structures 102 are connected to each other by portions extending laterally along portions of the base layer 100 between these stacked structures 102. The switching layer 108 may be formed of a ferroelectric material. For example, the ferroelectric material may include a hafnium oxide-based material (e.g., hafnium zirconium oxide (Hf... 1-x Zr x O), erbium hafnium oxide (Hf) 1-x Er x O), hafnium oxide (Hf) 1-x La x O), hafnium oxide (Hf) 1-x Y x O), hafnium gadolinium oxide (Hf) 1-x Gd x O), hafnium oxide (Hf) 1-x Al x O), hafnium oxide (Hf) 1-x Ti x O), hafnium tantalum oxide (Hf) 1-x Ta xMaterials such as barium titanate (e.g., BaTiO3), lead titanate (e.g., PbTiO3), lead zirconate (e.g., PbZrO3), lithium niobate (LiNbO3), sodium niobate (NaNbO3), potassium niobate (e.g., KNbO3), potassium tantalate (KTaO3), bismuth scandium (BiScO3), bismuth iron oxide (e.g., BiFeO3), aluminum scandium nitride (AlScN), etc., or combinations thereof. Optionally, the switching layer 108 can be a multilayer structure, which at least includes a charge trapping layer sandwiched between the tunnel dielectric layer and the gate dielectric layer. For example, the charge trapping layer can be formed of silicon oxide, while the tunnel dielectric layer and the gate dielectric layer can be formed of silicon oxide, respectively.

[0027] The channel layer 110 covers the sidewalls of the switch layer 108 and laterally contacts the word line 104 and isolation layer 106 in the stacked structure 102 through the switch layer 108. In some embodiments, the opposite sidewalls of each stacked structure 102 are laterally spaced by one of the channel layers 110, such that each channel layer 110 can be exclusively shared by the memory cell MC stack. In these embodiments, crosstalk between adjacent memory cell MC stacks arranged in the Y direction can be reduced. Furthermore, in some embodiments, the channel layers 110 are laterally spaced at the opposite sidewalls of adjacent stacked structures 102. In these embodiments, the channel layers 110 may or may not extend laterally along a portion of the base layer 100 between the stacked structures 102, but each of the channel layers 110 may not extend further to contact the other of the channel layers 110. The channel layer 110 may be formed of polysilicon or a metal oxide semiconductor material. The metal oxide semiconductor material may include indium-based oxide materials, such as indium gallium zinc oxide (IGZO).

[0028] The conductive posts 112 stand opposite each other on portions of the base layer 100 between the stacked structures 102. The conductive posts 112 in each pair are located between two channel layers 110 covering opposite sidewalls of adjacent stacked structures 102 and are in lateral contact with the two channel layers 110. Additionally, pairs of adjacent conductive posts 112 arranged in the Y direction are also laterally separated. In some embodiments, isolation structures 114 are respectively filled between the conductive posts 112 in each pair to isolate the conductive posts 112 in each pair from each other. Furthermore, in some embodiments, isolation posts 116 stand between pairs of adjacent conductive posts 112. In these embodiments, the isolation posts 116 may further extend to laterally contact the switching layer 108 to separate the channel layers 110 from each other. Furthermore, in some embodiments, pairs of conductive posts 112 on one side of the stacked structure 102 are offset from pairs of conductive posts 112 on the other side of the stacked structure 102 in the Y direction. In these embodiments, the memory cells MC may be referred to as being arranged in an interleaved configuration. The conductive pillar 112 is formed of a conductive material, while the isolation structure 114 and the isolation pillar 116 are formed of insulating materials. For example, the conductive material may include Al, Ti, TiN, TaN, Co, Ag, Au, Cu, Ni, Cr, Hf, Ru, W, Pt, etc., while the insulating material may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbide, silicon carbonitride, etc.

[0029] A segment of a word line 104, a portion of a switching layer 108 laterally contacting that segment of the word line 104, a portion of a channel layer 110 capacitively coupled to that segment of the word line 104 via the switching layer 108, and a pair of conductive posts 112 contacting the channel layer 110 together form a field-effect transistor (FET). The segment of the word line 104 serves as the gate terminal of the FET, and the pair of conductive posts 112 serves as the source and drain terminals of the FET. When the FET is turned on, a conductive path can be formed in the portion of the channel layer 110 and extends between the pairs of conductive posts 112. Conversely, when the FET is turned off, the conductive path can be cut off or does not exist. The function of the portion of the switching layer 108 is to achieve capacitive coupling between the segment of the word line 104 and the portion of the channel layer 110, and to switch the threshold voltage of the FET from a lower value to a higher value (or vice versa). During programming operations, dipole moments are stored in the switching layer 108 due to ferropolarization, or charges may be inserted into the switching layer 108 due to the tunneling effect. Conversely, during erasure operations, dipole moment reversal or removal of trapped charges can be observed in the switching layer 108. By storing dipole moments with opposite directions or inserting / removing charges, the field-effect transistor (FET) can have relatively high and relatively low threshold voltages, thereby allowing the storage of high and low logic states. Therefore, the FET is capable of storing data, referred to in this invention as a memory cell (MC).

[0030] like Figure 1A As shown, memory cells MC in the same stack can share the same switch layer 108, the same channel layer 110, and the same pairs of conductive pillars 112, while being controlled by different word lines 104 in the same stack structure 102. Memory cell MC stacks on opposite sides of the pairs of conductive pillars 112 can share the same pairs of conductive pillars 112, while having different channel layers 110 and being controlled by word lines 104 in adjacent stack structures 102. Memory cell MC stacks on opposite sides of the same stack structure 102 can share the word lines 104 in the stack structure 102, while having different switch layers 108, different channel layers 110, and different pairs of conductive pillars 112. Furthermore, adjacent memory cell MC stacks in the same column can share the same switch layer 108 and the same word lines 104 in the same stack structure 102, but have different channel layers 110 and different pairs of conductive pillars 112.

[0031] Figure 1B It is for reference. Figure 1A The equivalent circuit diagram of a portion of the described three-dimensional memory device 10.

[0032] refer to Figure 1A and Figure 1B Word lines 104 are stacked vertically in the Z direction. Each word line 104 connects to the gate terminal G of the column of two laterally adjacent memory cells MC. Furthermore, pairs of conductive posts 112 are connected to the source and drain terminals S and D of the memory cell MC stack. The gate terminal G of each memory cell MC stack is connected to one of the word lines 104. Additionally, the source terminals S of each memory cell MC stack are connected together via one of the conductive posts 112, and the drain terminals D of each memory cell MC stack are connected together via the other of the conductive posts 112. Therefore, the channel CH between the source and drain terminals S and D of each memory cell MC stack is connected in parallel.

[0033] Return to reference Figure 1A As shown, the ends of the stacked structure 102 are shaped into a stepped structure SC, and word lines 104 extend to the steps of the stepped structure SC. Since each word line 104 can extend to one of the steps, the word lines 104 can be independently out-routed. It should be noted that... Figure 1A Only the stepped structure SC on one side of the three-dimensional memory device 10 is shown. (Reference) Figure 2 As further described, the opposite sides of each stacked structure 102 can be respectively shaped into a stepped structure SC.

[0034] Figure 2 This is a schematic three-dimensional view of a three-dimensional memory device 10 having stepped structures SC1, SC2 on opposite sides according to some embodiments of the present disclosure.

[0035] refer to Figure 2As shown, each stacked structure 102 has two ends formed as stepped structures SC. The stepped structure SC on one side of the three-dimensional memory device 10 is called stepped structure SC1, and the stepped structure SC on the other side of the three-dimensional memory device 10 is called stepped structure SC2. Furthermore, the portion of the three-dimensional memory device 10 in which the memory cells MC are stacked can be referred to as an array region. The opposite end of each word line 104 (except the topmost word line 104) in the stacked structure 102 protrudes relative to the end of the overriding word line 104 in the same stacked structure 102 along the column direction (i.e., direction Y), to form a step at the same level and opposite ends of the stacked structure 102. Additionally, the end of the topmost word line 104 in the stacked structure 102 may define the top step of the stepped structures SC1 and SC2 at the opposite ends of the stacked structure 102. In this way, each of the word lines 104 can have an end not covered by other word lines 104, thus allowing for independent outward wiring. In some embodiments, the end of each isolation layer 106 in the stacked structure 102 is aligned with the end of the overlying word line 104, and each defines the bottom of a step. In these embodiments, each step of the stepped structure SC consists of the end of one of the word lines 104 and the underlying isolation layer 106. Furthermore, although not shown, components (other than the conductive pillar 112 and the channel layer 110) between adjacent stacked structures 102 may be further extended between adjacent stepped structures SC1 and adjacent stepped structures SC2. Additionally, similar to reference... Figure 3C The described insulating structure 118, the stepped structures SC1 and SC2 can be covered by the insulating structure, and the top surface of the insulating structure is substantially coplanar with or higher than the top surface of the stacked structure 102.

[0036] Figure 3A This is a schematic diagram illustrating an integrated circuit 20 including the three-dimensional memory device 10 as described above, according to some embodiments of the present disclosure.

[0037] refer to Figure 3A The integrated circuit 20 includes a three-dimensional memory device 10 and a driving circuit 30 configured to drive the three-dimensional memory device 10. In some embodiments, the driving circuit 30 is located below the three-dimensional memory device 10. The driving circuit 30 may include active devices formed on the surface of a semiconductor substrate 300 and may include interconnects extending over the active devices and configured to interconnect the active devices. The semiconductor substrate 300 is, for example, a semiconductor wafer (e.g., a silicon wafer) or a semiconductor-on-insulator (SOI) wafer (e.g., a silicon-on-insulator wafer). For example, the active devices may include metal-oxide-semiconductor (MOS) transistors. Furthermore, the active devices may be front-end process (FEOL) structures in the integrated circuit 20 (e.g., referenced to...). Figure 3CThe described FEOL structure (FE) is a part of the structure, and the interconnects can be integrated into a back-end process (BEOL) structure formed on the FEOL structure (e.g., referring to...). Figure 3C The BEOL structure described is used in some embodiments. In some embodiments, the 3D memory device 10 is also integrated in the BEOL structure and is located above the interconnects of the drive circuit 30. In some embodiments, the drive circuit 30 includes word line drive circuits 302, 304. Word lines 104 in the 3D memory device 10 are routed from the steps of the stepped structures SC1, SC2 to the word line drive circuits 302, 304 and can be controlled by the word line drive circuits 302, 304. Each of the word line drive circuits 302, 304 may include a plurality of transistors T, each of which is connected to one of the word lines 104. In some embodiments, the word lines 104 are routed to the source / drain (S / D) terminals of one of the transistors T. Although only a few transistors T are depicted, each of the word line drive circuits 302, 304 may include more transistors T, and these transistors T may be arranged along rows and columns in each of the word line drive circuits 302, 304.

[0038] Figure 3B This is a schematic diagram illustrating the configuration of the drive circuit 30 and the three-dimensional memory device 10 according to some embodiments of the present disclosure.

[0039] refer to Figure 3A and Figure 3B In some embodiments, the stepped structures SC1 and SC2 on opposite sides of the three-dimensional memory device 10 overlap with one of the word line driving circuits 302 and 304, respectively. For example, stepped structure SC1 may overlap with word line driving circuit 302, while stepped structure SC2 may overlap with word line driving circuit 304. Word line driving circuit 302 may extend along one side of the three-dimensional memory device 10, wherein the stacked structure 102 is shaped into stepped structure SC1. The length L of word line driving circuit 302 measured along direction X is... 302 It can be substantially equal to the length L of the three-dimensional memory device 10 measured along the same direction. 10 In some embodiments, the outer boundary OB of the word line driving circuit 302 302 The outer boundary OB of the overlying stepped structure SC1 SC1 Essentially aligned, the outer boundary is defined by the sidewall of the bottom step of the stepped structure SC1. Furthermore, the word line drive circuit 302 extends along the column direction (i.e., direction Y) from the outer boundary OB. 302 Crossing to the inner boundary IB 302 In some embodiments, the word line driving circuit 302 occupies a larger area than the stepped structure SC1, and extends from the outer boundary OB. 302 to the inner boundary IB 302Measured width W 302 Greater than width W SC1 The stepped structure SC1 extends from the outer boundary OB through the width WSC1. SC1 In these embodiments, essentially the entire stepped structure SC1 can overlap with the word line driving circuit 302. Additionally, the outer portion of the word line driving circuit 302 can overlap with the stepped structure SC1, while the inner portion of the word line driving circuit 302 can overlap with the stepped structure SC1. The word line driving circuit 302 can overlap with the array region of the three-dimensional memory device 10 located between the stepped structures SC1 and SC2.

[0040] On the other hand, the word line driving circuit 304 can extend along the other side of the three-dimensional memory device 10, wherein the stacked structure 102 is formed into a stepped structure SC2. The length L of the word line driving circuit 304, measured along direction X. 304 It can be substantially equal to the length L of the three-dimensional memory device 10 measured along the same direction. 10 In some embodiments, the outer boundary OB of the word line driving circuit 304 304 With the outer boundary OB of the overlying stepped structure SC2 SC2 Essentially aligned, the outer boundary is defined by the sidewall of the bottom step of the stepped structure SC2. Furthermore, the word line drive circuit 304 extends along the column direction (i.e., direction Y) from the outer boundary OB. 304 Crossing to the inner boundary IB 304 In some embodiments, the word line driving circuit 304 occupies a larger area than the stepped structure SC2, and extends from the outer boundary OB. 304 to the inner boundary IB 304 Measured width W 304 Greater than width W SC2 The stepped structure SC2 extends from the outer boundary OB through the width WSC2. SC2 In these embodiments, essentially the entire stepped structure SC2 can overlap with the word line driving circuit 304. Additionally, the outer portion of the word line driving circuit 304 can overlap with the stepped structure SC2, while the inner portion of the word line driving circuit 304 can overlap with the array region of the three-dimensional memory device 10 located between the stepped structures SC1 and SC2.

[0041] like Figure 3A As shown, word lines 104 are routed to word line driver circuits 302, 304 via word line routing WR. Each of the word line routing WRs may have a combination of a vertical extension VE and a lateral extension LE for routing one of the word lines 104 to a corresponding transistor T in the word line driver circuits 302, 304. The lateral extension LE of the word line routing WR is located in a BEOL structure (e.g., referencing...). Figure 3CThe BEOL structure (BE) described herein is located on one of the interlayer dielectric layers and may also be referred to as a conductive trace. On the other hand, the vertical extension of the word line routing WR (VE) penetrates one or more of the interlayer dielectric layers in the BEOL structure to establish an electrical connection with one or more lateral extensions of the same word line routing WR, and may include one or more conductive vias. See reference... Figure 3C As described, the stepped structure SC can be made of an insulating structure (e.g., such as...) Figure 3C The insulating structure 118 shown is used to cover the word line 104. To route word lines 104 outward from the steps of the stepped structure SC, a first portion P1 of the corresponding word line routing WR can extend from the steps through this insulating structure via a vertical extension VE (referred to as vertical extension VE1) to a lateral extension LE (referred to as lateral extension LE1) located above the three-dimensional memory device 10. The lateral extension LE1 of the first portion P1 can extend along the row direction (i.e., direction X) to the boundary next to the stepped structure SC. A second portion P2 of the word line routing WR can extend from the boundary of the lateral extension LE1 of the first portion P1 to the corresponding transistor T below the three-dimensional memory device 10. The landing terminals (e.g., source / drain terminals) of the transistor T can be laterally offset along the column direction (i.e., direction Y) from the boundary of the lateral extension LE1 of the first portion P1, such that the second portion P2 of the word line routing WR can include a lateral extension LE (referred to as lateral extension LE2) extending along the column direction (i.e., direction Y), and can include a longitudinal extension VE (referred to as longitudinal extension VE2) connected to the opposite end of the lateral extension LE2. One of the vertical extensions VE2 connects the lateral extension LE2 to the first part P1 of the word line wiring WR, and the other vertical extensions VE2 connect the lateral extension LE2 to the transistor T.

[0042] refer to Figure 3A and Figure 3B The word line routing WR extending from the step of the stepped structure SC1 to the transistor T in the word line driver circuit 302 can be called word line routing WR1. The transistor T in the word line driver circuit 302 extends from the outer boundary OB of the stepped structure SC1... SC1 Basically aligned outer boundary OB 302 to the inner boundary IB 302 With a width W greater than that of the stepped structure SC1 SC1 The width W302 is arranged. Furthermore, the transistors T in the word line drive circuit 302 are arranged in multiple columns extending in the direction Y. Word line wiring WR1 extending from the stepped structure SC1 can be connected to the columns of transistors T. Word line wiring WR1 extending from the higher step of the stepped structure SC1 can be connected to transistors T that are further away from the outer boundary OB than transistors T wiring from the lower steps of the same stepped structure SC1. 302Furthermore, the pitch of transistor T in the column can be much larger than the step width of the stepped structure SC1 measured along the column direction (i.e., direction Y). Therefore, the distance by which a higher step in the stepped structure SC1 is offset from its corresponding transistor T along the direction Y can be greater than the offset of a lower step relative to its corresponding transistor T. Thus, at least some word line wirings WR1 can have a distance along the column direction (i.e., direction Y) away from the outer boundary OB. 302 The lateral extension LE2 is provided to compensate for lateral offset. Furthermore, the word line wiring WR1 connected to the higher step may have a lateral extension LE2, the extension distance of which is greater than the extension distance of the lateral extension LE2 of the word line wiring WR1 connected to the lower step (e.g., ...). Figure 3C and Figure 3D (As shown).

[0043] On the other hand, the word line routing WR extending from the step of the stepped structure SC2 to the transistor T in the word line driving circuit 304 can be called word line routing WR2. The transistor T in the word line driving circuit 302 extends from the outer boundary OB of the stepped structure SC2 with a width greater than the width W304 of the stepped structure SC2. SC2 Basically aligned outer boundary OB 304 to the inner boundary IB 304 Arrangement. Furthermore, the transistors T in the word line drive circuit 304 are arranged in multiple columns extending along the Y direction. Word line wiring WR2 extending from the stepped structure SC2 can be connected to columns of transistors T. Word line wiring WR2 extending from a higher step of the stepped structure SC2 can be connected to transistors T that are further away from the outer boundary OB than transistors T wiring from lower steps in the same stepped structure SC2. 304 Furthermore, the pitch of the transistor T in the column can be much larger than the step width of the stair structure SC2 measured along the column direction (i.e., direction Y). Therefore, higher steps in the stair structure SC2 can be offset from the corresponding transistor T along direction Y by a distance greater than the offset of lower steps relative to the corresponding transistor T. Thus, at least some word line wiring WR2 can have a distance along the column direction (i.e., direction Y) away from the outer boundary OB. 304 The extended lateral extension LE2. Furthermore, the word line wiring WR2 connected to the higher step may have a lateral extension LE2 that extends a greater distance than the lateral extension LE2 of the word line wiring WR2 connected to the lower step (e.g., ...). Figure 3C and Figure 3D (As shown).

[0044] Word line routings (WRs) should be spaced apart from each other. To separate word line routings (WRs) extending from the steps of the same step structure SC1 / SC2, the lateral extensions (LE2) of these word line routings (WRs) can be provided in the BEOL structure (e.g., referencing...). Figure 3C The BEOL structure (BE) described herein is constructed on different interlayer dielectric layers. In other words, the lateral extensions LE2 of word line wiring WR extending from the steps of the same ladder structure SC1 / SC2 can be formed in metallization layers at different horizontal levels. For example, one of these lateral extensions LE2 can be a portion of the nth metallization layer, and one of adjacent lateral extensions LE2 can be a portion of the (n+1)th metallization layer. As the number of word lines 104 in each stack structure 102 increases, more metallization layers are required in the BEOL structure. In some embodiments, some word lines 104 in the stack structure 102 are routed from the ladder structure SC1 to the word line driver circuit 302 via some word line wiring WR1, while other word lines 104 in the stack structure 102 are routed from the ladder structure SC2 to the word line driver circuit 302 via some word line wiring WR2. Since word lines WR1 and WR2 are located on opposite sides of the three-dimensional memory device 10, the lateral extensions LE2 of word lines WR1 can be sufficiently spaced apart from the lateral extensions LE2 of word lines WR2. Therefore, the metallization layer in the BEOL structure can be shared by some lateral extensions LE2 of word lines WR1 and some lateral extensions LE2 of word lines WR2. Thus, the amount of metallization layer in the BEOL structure can be reduced. Optionally, each stack structure 102 may include more word lines 104.

[0045] Figure 3C This is a schematic cross-sectional view illustrating the routing scheme of word lines 104 in the same stacked structure 102 according to some embodiments of the present disclosure.

[0046] In some embodiments, such as Figure 3C As indicated by the arrows along word line 104 shown, word lines 104 in the same stacked structure 102 are alternately routed to word line driver circuit 302 and word line driver circuit 304. Word lines 104 routed to word line driver circuit 302 are connected to word line routing WR1, while word lines 104 routed to word line driver circuit 304 are connected to word line routing WR2. (See diagram) Figure 3C As shown in the example, word lines 104 in the stacked structure 102 may include word lines 104-1, 104-2, 104-3, and 104-4 sequentially stacked on the base layer 100 and separated from each other by an isolation layer 106. Word lines 104-1 and 104-3 are routed to the word line driver circuit 302 via word line routing WR1, which includes word line routing WR1-1 and WR1-3. Word lines 104-2 and 104-4 are routed to the word line driver circuit 304 via word line routing WR2, which includes word line routing WR2-2 and WR2-4. It should be noted that word line routing WR1-1, WR1-3, WR2-2, and WR2-4 are all partially depicted on the base layer 100. Figure 3C In, and actually similar to Figure 3A The word lines WR1 and WR2 are depicted in the diagram. Word line wiring WR1-1 may have a lateral extension LE2 as a portion of the nth metallization layer, and word line wiring WR1-3 may have a lateral extension LE2 as a portion of the (n+1)th metallization layer above the nth metallization layer. Since word lines WR2-2 and WR2-4 are located on the other side of the three-dimensional memory device 10, the lateral extensions LE2 of word lines WR2-2 and WR2-4 do not need to be formed in other metallization layers to maintain a distance from the lateral extensions LE2 of word lines WR1-1 and WR1-3. In some embodiments, the lateral extension LE2 of word line wiring WR2-2 may be another portion of the nth metallization layer, and the lateral extension LE2 of word line wiring WR2-4 may be another portion of the (n+1)th metallization layer. In other words, the nth metallization layer can be shared by the lateral extensions LE2 of word lines WR1-1 and WR2-2, and the (n+1)th metallization layer can be shared by the lateral extensions LE2 of word lines WR1-3 and WR2-4. As a result, the number of metallization layers in the BEOL structure can be significantly reduced.

[0047] Similarly, Figure 3C As shown, stepped structures SC1 and SC2 are covered by an insulating structure 118, and an interlayer dielectric layer 120 is located on the insulating structure 118 and the three-dimensional memory device 10. Furthermore, a stack of interlayer dielectric layers 302 is located below the base layer 100 of the three-dimensional memory device 10. Transistors T are formed on a surface region of the semiconductor substrate 300 and are covered by the interlayer dielectric layer 302. Each transistor T may include a gate electrode GE above the semiconductor substrate 300 and capacitively coupled to the semiconductor substrate 300 through a gate dielectric layer GD, and may include a source / drain structure SD on opposite sides of a gate stack structure, the gate stack structure including the gate electrode GE and the gate dielectric layer GD. In some embodiments, the gate stack structure is laterally surrounded by gate spacers SP. It should be noted that although transistor T is depicted as a planar field-effect transistor, according to other embodiments of this disclosure, transistor T may also be alternatively formed as a fin-FET or a gate-all-around (GAA) field-effect transistor. The semiconductor substrate 300 and the components (including transistors T) formed on the surface of the semiconductor substrate 300 are referred to as the FEOL structure FE. Furthermore, the components formed on the FEOL structure FE are referred to as the BEOL structure BE. The word line wiring WR and the three-dimensional memory device 10 are integrated in the BEOL structure BE, and the bottom of the word line wiring WR can be considered to extend into the FEOL structure FE.

[0048] refer to Figure 3A and Figure 3BThe driving circuit 30 may further include a source line / bit line driving circuit 306. The source line / bit line driving circuit 306 may be formed between word line driving circuits 302 and 304. The length L of the source line / bit line driving circuit 306, measured along direction X, is... 306 It can be substantially equal to the length L of the three-dimensional memory device 10 measured along the same direction. 10 In some embodiments, the source line / bit line driver circuit 306 is laterally spaced from the word line driver circuits 302, 304. In these embodiments, buffer circuitry, row / column decoders, power generation circuitry, and combinations thereof may be formed in the space between the source line / bit line driver circuit 306 and the word line driver circuits 302, 304. In alternative embodiments, the source line / bit line driver circuit 306 may be adjacent to the word line driver circuits 302, 304 without the need for additional circuitry between them (e.g., buffer circuitry, row / column decoders, power generation circuitry, etc.). Although Figure 3A Not shown, but the conductive post 112 of each memory cell MC in the three-dimensional memory device 10 is connected to the source line and the bit line, respectively. The source line and the bit line are located above and / or below the three-dimensional memory device 10, and the source line and the bit line are routed to the source line / bit line drive circuit 306.

[0049] Figure 3D This is a schematic diagram illustrating word line routing schemes and source line / bit line routing schemes according to some embodiments of the present disclosure.

[0050] refer to Figure 3A and Figure 3D Partially displayed Figure 3D The word line routing WR extends between the stepped structure SC and the word line driving circuits 302 and 304. In some embodiments, source lines / bit lines SB are disposed below the three-dimensional memory device 10 and connected to conductive pillars 112 via conductive vias (not shown) penetrating the substrate 100. The source lines / bit lines SB can extend in the row direction (i.e., direction X) and can be arranged in the column direction (i.e., direction Y). Some of the source lines / bit lines SB overlap with the source line / bit line driving circuit 306 and may be referred to as source lines / bit lines SB-1. The source lines / bit lines SB-1 are routed to the underlying source line / bit line driving circuit 306 via source line / bit line routing SBR-1. The source line / bit line routing SBR-1 can extend in the vertical direction Z and each includes a vertical extension. The vertical extension may each include a portion penetrating at least one interlayer dielectric layer (e.g., reference 1). Figure 3COne or more conductive vias are described in the interlayer dielectric layer 302. In some embodiments, source line / bit line wiring SBR-1 is connected to the active device SA of the source line / bit line drive circuit 306. The active device SA may be a sense amplifier, a bit line selector, etc. On the other hand, other source lines / bit lines SB do not overlap with the source line / bit line drive circuit 306 and may be referred to as source lines / bit lines SB-2. Similar to source lines / bit lines SB-1, source lines / bit lines SB-2 are wired to the active device SA of the source line / bit line drive circuit 306. Since source lines / bit lines SB-2 are offset from the source line / bit line drive circuit 306, the source line / bit line wiring SBR-2 extending from source lines / bit lines SB-2 to the active device SA may each include a lateral extension LE to compensate for this lateral offset. Similar to the lateral extension LE2 of the word line routing WR, the lateral extension LE of the source line / bit line routing SBR-2 can extend between two vertical extensions in the same source line / bit line routing SBR-2. In some embodiments, the lateral extension LE of the source line / bit line routing SBR-2 extends along the column direction (i.e., direction Y). Furthermore, in some embodiments, the lateral extension LE of the source line / bit line routing SBR-2 can be located above or below the lateral extension LE2 of the word line routing WR. However, in alternative embodiments, the lateral extension LE of the source line / bit line routing SBR-2 and the lateral extension LE2 of the word line routing WR are portions of the same metallization layer, provided that these lateral extensions are spaced apart from each other.

[0051] In other embodiments, source lines and / or bit lines extend above the 3D memory device 10. In these embodiments, the source lines and / or bit lines located above the 3D memory device 10 can be directed to the source line / bit line driving circuit 306 via a vertical path adjacent to the 3D memory device 10 and lateral and vertical paths extending below the 3D memory device 10 to the active device SA in the source line / bit line driving circuit 306. Furthermore, some source lines / bit lines SB (e.g., source lines) can be routed to a ground terminal in the source line / bit line driving circuit 306 instead of to the active device SA.

[0052] Figure 4A This is a schematic diagram for reference. Figure 3A and Figure 3C Another diagram illustrating the described word line routing scheme.

[0053] refer to Figure 3A and Figure 4AThe three-dimensional memory device 10 overlaps with the underlying driving circuitry 30. Only the stepped structures SC1, SC2 and word lines 104 of the three-dimensional memory device 10 are depicted to indicate the location of the three-dimensional memory device 10. The stepped structures SC1 and SC2 are located on opposite sides of the three-dimensional memory device 10. The stepped structure SC1 overlaps with the outer portion of the underlying word line driving circuitry 302, and the stepped structure SC2 overlaps with the outer portion of the underlying word line driving circuitry 304. The word lines 104 extend between the opposite sides of the three-dimensional memory device 10 to the steps of the stepped structures SC1 and SC2. The stacking of each word line 104 is depicted by bidirectional arrows, indicating that some word lines 104 in each stack can be routed outward via one of the stepped structures SC1 on one side of the three-dimensional memory device 10, while other word lines 104 in each stack can be routed outward via one of the stepped structures SC2 on the other side of the three-dimensional memory device 10. The area enclosed by dashed lines and leading to the stepped structure SC1 depicts the word line routing WR1 extending from the stepped structure SC1 to the transistor T in the word line drive circuit 302. Conversely, the area enclosed by dashed lines and leading to the stepped structure SC2 depicts the word line routing WR2 extending from the stepped structure SC2 to the transistor T in the word line drive circuit 304. (See reference...) Figure 3A and Figure 3C As described, by applying such a bidirectional word line routing scheme, the number of metallization layers in the BEOL structure can be significantly reduced.

[0054] Figure 4B This is a schematic diagram for reference. Figure 3D Another diagram illustrating the described source line / bit line routing scheme.

[0055] refer to Figure 3D and Figure 4B The three-dimensional memory device 10 overlaps with the driving circuit 30 below. Only the stepped structures SC1, SC2 and the source / bit line SB of the three-dimensional memory device 10 are depicted to indicate the location of the driving circuit 30. It should be noted that, for the sake of brevity, Figure 4B Word line 104 and word line routing WR are omitted. Source line / bit line SB-1 overlaps with source line / bit line driver circuit 306 and is routed to source line / bit line driver circuit 306 via source line / bit line routing SBR-1. Figure 4B The solid dots shown indicate this. On the other hand, the source line / bit line SB-2 does not overlap with the source line / bit line driver circuit 306, and is routed to the source line / bit line driver circuit 306 via the source line / bit line routing SBR-2. Figure 4B The “L”-shaped line indicates this.

[0056] Figure 5This is a schematic plan view illustrating an integrated circuit 20a according to an alternative embodiment of the present disclosure. Integrated circuit 20a is similar to reference numeral 20a. Figures 3A-3D , Figure 4A , Figure 4B The integrated circuit 20 described will therefore only describe the differences between integrated circuits 20 and 20a, and the same or similar parts of integrated circuits 20 and 20a will not be repeated.

[0057] refer to Figure 5 As shown, in addition to word line driver circuits 302 and 304, integrated circuit 20a may also include additional word line driver circuits 308 and 310. Word line driver circuits 302 and 304 and additional word line driver circuits 308 and 310 may laterally surround source line / bit line driver circuit 306. In some embodiments, additional word line driver circuits 308 and 310 are adjacent to source line / bit line driver circuit 306 without additional circuitry (e.g., buffer circuitry, row / column decoder, power generation circuitry, etc.). In alternative embodiments, additional circuitry may also be disposed between source line / bit line driver circuit 306 and additional word line driver circuits 308 and 310. Furthermore, additional word line driver circuits 308 and 310 may or may not overlap with the three-dimensional memory device 10. Although not shown, some word lines 104 in each stack can be routed to word line driver circuits 302, 304 via word line routing WR1, WR2, and other word lines 104 in each stack can be routed to additional word line driver circuits 308, 310 via additional word line routing. As a result, the number of word line routings connected to each word line driver circuit 302, 304, 308, 310 can be further reduced. Since the word line driver circuits 302, 304, 308, 310 are located on different sides of the three-dimensional memory device 10, the lateral extensions of word line routings at the same height can share the same metallization layer without being too close to each other.

[0058] Figure 6A The illustration is schematic and refers to another three-dimensional memory device 10a according to some embodiments of the present disclosure. Figure 3A , Figure 3C , Figure 4A A three-dimensional view of the described drive circuit 30 and word line routing scheme. Figure 6B It is a schematic diagram, such as Figure 6A A cross-sectional view of the memory cell MC' string in the three-dimensional memory device 10a shown. Figure 6A The integrated circuit 20b shown is similar to the reference circuit. Figure 3A The described integrated circuit 20. Only the differences between these integrated circuits 20 and 20b will be described; identical or similar parts will not be repeated.

[0059] refer to Figure 6AThe three-dimensional memory device 10a may include a stacked structure 602 formed on a substrate 600. The substrate 600 is similar to a reference. Figure 1A The described base layer 100 may be an etch stop layer above the semiconductor substrate 300. Stacked structures 602 extend along the column direction (i.e., direction Y) and are separately arranged along the row direction (i.e., direction X). Each stacked structure 602 includes word lines 604 and isolation layers (not shown) alternately stacked along the vertical direction Z. The word lines 604 are similar to those in the reference [reference]. Figure 1A The word line 104 is described, but it can be thicker than word line 104 (regarding the dimension along the X direction). Similarly, the isolation layer is similar to the reference. Figure 1A The isolation layer 106 is described, but may be thicker than isolation layer 106 (regarding the dimension along direction X). Furthermore, multiple select lines 606 are disposed on word lines 604 in each stack structure 602. The select lines 606 extend along the column direction (i.e., direction Y) and are arranged separately along the row direction (i.e., direction X). The select lines 606 may be made of the same material as the word lines 604, but may be narrower than the word lines 604 (regarding the dimension along direction X).

[0060] The first side of each stack structure 602 is shaped as a stepped structure SC1', and the second side of each stack structure 602 is shaped as a stepped structure SC2'. Similar to the reference... Figure 2 The described stacking structure 102 has stepped structures SC1 and SC2, with word lines 604 in each stacking structure 602 extending to the steps of stepped structures SC1' and SC2'. Opposite ends of select lines 606 in each stacking structure 602 are laterally recessed from opposite ends of the topmost word line 604 in the same stacking structure 602, forming the topmost step of the stepped structures SC1' and SC2'. Although not shown, each isolation layer located below a word line 604 may have opposite ends substantially aligned with the opposite ends of the overlying word line 604. Similarly, isolation layers located below select lines 606 in each stacking structure may have opposite ends substantially aligned with the opposite ends of these overlying select lines 606.

[0061] Multiple channel posts 608 extend through the stack structure 602 in the vertical direction Z and are located in the array region of the three-dimensional memory device 60 between the stepped structures SC1' and SC2'. The channel posts 608 may be arranged along columns (extending in the direction Y) and rows (extending in the direction X). In some embodiments, each stack structure 602 is penetrated by multiple columns (e.g., 4 to 8 columns of channel posts 608). In these embodiments, each select line 606 in one of the stack structures 602 is penetrated by a column of channel posts 608.

[0062] refer to Figure 6A and Figure 6BEach channel pillar 608 may be formed of a semiconductor material, and each channel pillar 608 is surrounded by a stack of word lines 604 and an overlying select line 606. A switch layer 610 extends along the sidewalls of the channel pillar 608 and separates the channel pillar 608 from the second bottommost word line 604 surrounding the word lines 604 to the topmost word line 604. Similar to the reference. Figure 1A The described switching layer 108 and switching layer 610 may be formed of a ferroelectric material or may be a multilayer structure including at least a charge trapping layer sandwiched between a tunnel dielectric layer and a gate dielectric layer. Each of these word lines 604 (i.e., from the second bottommost word line 604 to the topmost word line 604 in the stack), penetrating one of the channel pillars 608 and the switching layer 610 therebetween, may form a storage transistor, which may be referred to as a memory cell MC'. In this way, strings of memory cells MC' are formed along the channel pillars 608. The top and bottom ends of the channel pillars 608 may serve as common source and drain terminals for the strings of memory cells MC'. In some embodiments, the top end of each channel pillar 608 is connected to a bit line (not shown), while the bottom end of each channel pillar 608 is connected to a source line / plane (not shown).

[0063] In some embodiments, a gate dielectric layer 612 is located between a channel pillar 608 and a surrounding select line 606. The select line 606, penetrating one of the channel pillars 608 and the gate dielectric layer 612 therebetween, form a top select transistor SG1. The top select transistor SG1 controls one of the common source / drain terminals of the memory cell string MC'. Furthermore, in some embodiments, a gate dielectric layer 614 is located between a channel pillar 608 and the bottommost word line 604 of the surrounding word lines 604. The bottommost word line 604, penetrating one of the channel pillars 608 and the gate dielectric layer 614 therebetween, form a bottom select transistor SG2. The top select transistor SG1 controls the other of the common source / drain terminals of the memory cell string MC'. Thus, the top select transistor SG1 and the bottom select transistor SG2 on opposite sides of each channel pillar 608 control access to that channel pillar 608.

[0064] Refer again Figure 6A The three-dimensional memory device 10a can be formed above the driving circuit 30 and embedded in the BEOL structure of the integrated circuit 20b, which is similar to the reference. Figure 3CThe described BEOL structure. Word line driving circuits 302 and 304 are configured to drive word lines 604 in the three-dimensional memory device 10a. Word line driving circuit 302 in driving circuit 30 extends along one side of the stacked structure 602 of the three-dimensional memory device 10a, which is formed into a stepped structure SC1', and word line driving circuit 304 in driving circuit 30 extends along the other side of the stacked structure 602 of the three-dimensional memory device 10a, which is formed into a stepped structure SC2'. In some embodiments, the word line driving circuit 302 is located near the outer boundary OB. 302 The outer portion overlaps with the stepped structure SC1', and the word line drive circuit 302 is near the inner boundary IB. 302 The internal portion overlaps with the array region of the three-dimensional memory device 10a between the stepped structures SC1' and SC2'. Similarly, the word line drive circuit 304 is closer to the outer boundary OB. 304 The outer portion overlaps with the stepped structure SC2', and the word line drive circuit 304 is closer to the inner boundary IB. 304 The internal portion overlaps with the array region of the three-dimensional memory device 10a. Similar to the reference... Figure 3A , Figure 3C , Figure 4A In the described word line routing scheme, some word lines 604 in each stack structure 602 are routed to the word line driver circuit 302 via a ladder structure SC1', while other word lines 604 in the same stack structure 602 are routed to the word line driver circuit 304 via a ladder structure SC2'. In some embodiments, such as Figure 6A As indicated by the arrows along word lines 604, word lines 604 in each stacked structure 602 are alternately routed from their step structures SC1, SC2 to word line drive circuits 302, 304. Although not shown, the first word line routing extends between the step structure SC1 and the word line drive circuit 302, and the second word line routing extends between the step structure SC2 and the word line drive circuit 304. Since the first and second word line routings extend on opposite sides of the three-dimensional memory device 10a, the lateral extensions of the first word line routing can share the same metallization layer with the lateral extensions of the second word line routing, while remaining spaced apart from the lateral extensions of the second word line routing. As a result, the amount of metallization layer in the BEOL structure can be significantly reduced.

[0065] Source line / bit line driver circuit 306 is located between word line driver circuits 302 and 304 and is configured to drive bit lines and / or source lines / planes (not shown) connected to channel pillars 608 of the 3D memory device 10a. In some embodiments, the source plane (not shown) is disposed below the substrate 600, while the bit lines (also not shown) extend above the 3D memory device 10a. In these embodiments, the bit lines may be routed to the source line / bit line driver circuit 306 via a vertical path adjacent to the 3D memory device 10a and lateral and vertical paths extending below the 3D memory device 10a and to the source line / bit line driver circuit 306.

[0066] In other embodiments, as referenced Figure 5 The described drive circuit 30a is used to drive the reference. Figure 6A and Figure 6B The described three-dimensional memory device 10a can be further configured with additional word line wiring to connect the ladder structures SC1', SC2' to the additional word line drive circuits 308, 310.

[0067] As described above, the word line routing scheme according to embodiments of this disclosure includes two word line driving circuits disposed along opposite sides of an overlying three-dimensional memory device, wherein the stacked structure in the three-dimensional memory device is formed into a stepped structure on opposite sides of the three-dimensional memory device. A first set of word lines in the stacked structure is routed to one of the word line driving circuits, and a second set of word lines in the same stacked structure is routed to the other word line driving circuit. The first word line routing extending from the stepped structure on one side of the three-dimensional memory device is sufficiently spaced from the second word line routing extending from the stepped structure on the other side of the three-dimensional memory device. Therefore, the lateral extensions of the first and second word line routings can share the same metallization layer while remaining spaced apart from each other. As a result, the word line routing requires far fewer metallization layers and can significantly reduce manufacturing costs.

[0068] It should be noted that the word line routing scheme can be applied to various three-dimensional memory devices. This disclosure only provides two possible three-dimensional memory devices 10, 10a. However, other three-dimensional memory devices with a stepped structure on opposite sides should be able to use the word line routing scheme.

[0069] In one aspect of this disclosure, an integrated circuit is provided. The integrated circuit includes: a three-dimensional memory device including stacked structures extending respectively along a column direction, wherein the stacked structures have a first step structure located on a first side of the three-dimensional memory device and a second step structure located on a second side of the three-dimensional memory device; a first word line driving circuit located below the three-dimensional memory device and extending along the first side of the three-dimensional memory device, wherein a first set of word lines in each stacked structure is connected from one of the first step structures to the first word line driving circuit; and a second word line driving circuit located below the three-dimensional memory device and extending along the second side of the three-dimensional memory device, wherein the first word line driving circuit and the second word line driving circuit are laterally spaced apart from each other, and a second set of word lines in each stacked structure is connected from one of the second step structures to the second word line driving circuit.

[0070] In the aforementioned integrated circuit, word lines in each stacked structure are alternately connected to a first word line driving circuit and a second word line driving circuit.

[0071] In the aforementioned integrated circuit, the length of the first word line driving circuit, measured along the row direction that intersects the column direction, is substantially equal to the length of the three-dimensional memory device measured along the row direction, and the length of the second word line driving circuit, measured along the row direction, is also substantially equal to the length of the three-dimensional memory device.

[0072] In the aforementioned integrated circuit, the first ladder structure completely overlaps with the first word line driving circuit, and the second ladder structure completely overlaps with the second word line driving circuit.

[0073] In the aforementioned integrated circuit, the outer boundary of the first word line driving circuit along the row direction intersecting the column direction is basically aligned with the outer boundary of the first step structure along the row direction, and the outer boundary of the second word line driving circuit along the row direction is basically aligned with the outer boundary of the second step structure along the row direction.

[0074] In the aforementioned integrated circuit, the width spanned by the first word line driving circuit along the column direction from its outer boundary is greater than the width spanned by the first step structure along the column direction from its outer boundary, and the width spanned by the second word line driving circuit along the column direction from its outer boundary is greater than the width spanned by the second step structure along the column direction from its outer boundary.

[0075] In the aforementioned integrated circuit, the outer portion of the first word line driving circuit overlaps with the first step structure, the inner portion of the first word line driving circuit overlaps with the array region of the three-dimensional memory device located between the first step structure and the second step structure, the outer portion of the second word line driving circuit overlaps with the second step structure, and the inner portion of the second word line driving circuit overlaps with the array region of the three-dimensional memory device.

[0076] The aforementioned integrated circuit further includes: a third word line driving circuit extending below the three-dimensional memory device along the column direction and located on the third side of the three-dimensional memory device; and a fourth word line driving circuit extending below the three-dimensional memory device along the column direction and located on the fourth side of the three-dimensional memory device.

[0077] In the aforementioned integrated circuit, the third group of word lines in each stacked structure is routed to the third word line driver circuit, and the fourth group of word lines in each stacked structure is routed to the fourth word line driver circuit.

[0078] In another aspect of this disclosure, an integrated circuit is provided. The integrated circuit includes: a three-dimensional memory device including stacked structures extending respectively along a column direction, wherein the stacked structures have a first step structure located on a first side of the three-dimensional memory device and a second step structure located on a second side of the three-dimensional memory device; a first word line driving circuit located below the three-dimensional memory device and overlapping the first step structure; a first word line wiring extending from the first step structure to the first word line driving circuit, wherein a first set of word lines in each stacked structure is connected to the first word line driving circuit from one of the first step structure through a portion of the first word line wiring; a second word line driving circuit located below the three-dimensional memory device and overlapping the second step structure; and a second word line wiring extending from the second step structure to the second word line driving circuit, wherein a second set of word lines in each stacked structure is connected to the second word line driving circuit from one of the second step structure through a portion of the second word line wiring.

[0079] In the aforementioned integrated circuit, the lower portion of each first word line wiring is located below the three-dimensional memory device and has a lateral extension extending along the column direction, and the lateral extensions of the first word line wiring extending from the same stacked structure are perpendicularly spaced apart from each other; the lower portion of each second word line wiring is located below the three-dimensional memory device and has a lateral extension extending along the column direction, and the lateral extensions of the second word line wiring extending from the same stacked structure are perpendicularly spaced apart from each other.

[0080] In the aforementioned integrated circuit, a lateral extension of one of the first word lines extending from one of the stacked structures is at the same horizontal level as a lateral extension of one of the second word lines extending from one of the stacked structures.

[0081] In the aforementioned integrated circuit, the lateral extension of the first word line wiring is laterally spaced from the lateral extension of the second word line wiring, and is at least partially located at the same horizontal level as the lateral extension of the second word line wiring.

[0082] In another aspect of this disclosure, an integrated circuit is provided. The integrated circuit includes: a semiconductor substrate; a first word line driving circuit and a second word line driving circuit formed on the semiconductor substrate and laterally spaced apart from each other; a three-dimensional memory device formed above the first word line driving circuit and the second word line driving circuit, and including stacked structures extending respectively along column directions, wherein a first set of word lines in each stacked structure is connected to the first word line driving circuit, and a second set of word lines in each stacked structure is connected to the second word line driving circuit.

[0083] In the aforementioned integrated circuit, the interconnects of the first word line driving circuit, the interconnects of the second word line driving circuit, and the three-dimensional memory device are embedded in a back-end process (BEOL) structure formed on a semiconductor substrate.

[0084] In the aforementioned integrated circuit, the first word line wiring connects the first set of word lines in each stacked structure to the first word line driving circuit, and the second word line wiring connects the second set of word lines in each stacked structure embedded in the back-end process structure.

[0085] In the aforementioned integrated circuit, the first word line wiring has a lateral extension extending below the three-dimensional memory device, the second word line wiring has a lateral extension extending below the three-dimensional memory device, and the lateral extensions of the first word line wiring and the lateral extensions of the second word line wiring share a metallization layer in the back-end structure.

[0086] In the aforementioned integrated circuit, the stacked structure has a first step structure on the first side of the three-dimensional memory device and a second step structure on the second side of the three-dimensional memory device.

[0087] In the aforementioned integrated circuit, the first word line driving circuit extends along the first side of the three-dimensional memory device and overlaps with the first step structure, and the second word line driving circuit extends along the second side of the three-dimensional memory device and overlaps with the second step structure.

[0088] In the aforementioned integrated circuit, word lines in each stacked structure are stacked vertically and spaced perpendicularly from each other.

[0089] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent structures do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made within the invention without departing from its spirit and scope.

Claims

1. An integrated circuit, comprising: A three-dimensional memory device includes stacked structures extending along column directions, wherein the stacked structures have a first stepped structure located on a first side of the three-dimensional memory device and a second stepped structure located on a second side of the three-dimensional memory device; Switching layers and channel layers extend between the stacked structures and cover the sidewalls of the stacked structures; Conductive pillars are positioned between the stacked structures and are in lateral contact with the stacked structures through the switching layer and the channel layer; A first word line driving circuit is located below the three-dimensional memory device and extends along the first side of the three-dimensional memory device, wherein a first set of word lines in each stacked structure connects to the first word line driving circuit from one of the first staircase structures; and The second word line driving circuit is located below the three-dimensional memory device and extends along the second side of the three-dimensional memory device, wherein the first word line driving circuit and the second word line driving circuit are laterally spaced apart from each other, and the second set of word lines in each stack structure is connected from one of the second ladder structures to the second word line driving circuit.

2. The integrated circuit according to claim 1, wherein, In each stacked structure, word lines are alternately connected to the first word line driver circuit and the second word line driver circuit.

3. The integrated circuit according to claim 1, wherein, The length of the first word line driving circuit, measured along the row direction intersecting the column direction, is equal to the length of the three-dimensional memory device, measured along the row direction, and the length of the second word line driving circuit, measured along the row direction, is also equal to the length of the three-dimensional memory device.

4. The integrated circuit according to claim 1, wherein, The first stepped structure completely overlaps with the first word line driving circuit, and the second stepped structure completely overlaps with the second word line driving circuit.

5. The integrated circuit according to claim 1, wherein The outer boundary of the first word line driving circuit along the row direction intersecting the column direction is aligned with the outer boundary of the first stepped structure along the row direction. The outer boundary of the second word line driving circuit along the row direction is aligned with the outer boundary of the second step structure along the row direction.

6. The integrated circuit according to claim 5, wherein The width spanned by the first word line driving circuit from its outer boundary along the column direction is greater than the width spanned by the first stepped structure from its outer boundary along the column direction. The width spanned by the second word line driving circuit from its outer boundary along the column direction is greater than the width spanned by the second step structure from its outer boundary along the column direction.

7. The integrated circuit according to claim 6, wherein The outer portion of the first word line driving circuit overlaps with the first stepped structure, and the inner portion of the first word line driving circuit overlaps with the array region of the three-dimensional memory device located between the first stepped structure and the second stepped structure. The outer portion of the second word line driving circuit overlaps with the second stepped structure, and the inner portion of the second word line driving circuit overlaps with the array region of the three-dimensional memory device.

8. The integrated circuit according to claim 1, further comprising: The third word line driving circuit extends below the three-dimensional memory device along the column direction and is located on the third side of the three-dimensional memory device; as well as The fourth word line driving circuit extends below the three-dimensional memory device along the column direction and is located on the fourth side of the three-dimensional memory device.

9. The integrated circuit according to claim 8, wherein, The third group of word lines in each stack structure is routed to the third word line driver circuit, and the fourth group of word lines in each stack structure is routed to the fourth word line driver circuit.

10. An integrated circuit, comprising: A three-dimensional memory device includes stacked structures extending along column directions, wherein the stacked structures have a first stepped structure located on a first side of the three-dimensional memory device and a second stepped structure located on a second side of the three-dimensional memory device; The first word line driving circuit is located below the three-dimensional memory device and overlaps with the first stepped structure; The first word line wiring extends from the first ladder structure to the first word line driving circuit, wherein the first set of word lines in each stack structure is connected from one of the first ladder structures to the first word line driving circuit through a portion of the first word line wiring. The second word line driving circuit is located below the three-dimensional memory device and overlaps with the second stepped structure; and The second word line wiring extends from the second ladder structure to the second word line driver circuit, wherein the second set of word lines in each stack structure is connected to the second word line driver circuit from one of the second ladder structures through a portion of the second word line wiring. In this configuration, a set of first word line wiring connects the first group of word lines in each stacked structure to the first transistors arranged along the column direction in the first word line driving circuit, and a set of second word line wiring connects the second group of word lines in each stacked structure to the second transistors arranged along the column direction in the second word line driving circuit.

11. The integrated circuit according to claim 10, wherein The lower portion of each first word line wiring is located below the three-dimensional memory device and has a lateral extension extending along the column direction, and the lateral extensions of the first word lines wiring extending from the same stacking structure are perpendicularly spaced from each other; and The lower portion of each second word line wiring is located below the three-dimensional memory device and has a lateral extension extending along the column direction, and the lateral extensions of the second word line wirings extending from the same stack structure are perpendicularly spaced from each other.

12. The integrated circuit according to claim 11, wherein, The lateral extension of one of the first word lines extending from one of the stacked structures is at the same horizontal level as the lateral extension of one of the second word lines extending from one of the stacked structures.

13. The integrated circuit according to claim 11, wherein, The lateral extension of the first character line wiring is laterally spaced from the lateral extension of the second character line wiring, and is at least partially located at the same horizontal level as the lateral extension of the second character line wiring.

14. An integrated circuit, comprising: Semiconductor substrate; The first word line driving circuit and the second word line driving circuit are formed on the semiconductor substrate and are laterally spaced apart from each other. as well as A three-dimensional memory device is formed above a first word line driving circuit and a second word line driving circuit, and includes stacked structures extending along the column direction, wherein a first set of word lines in each stacked structure is connected to the first word line driving circuit, and a second set of word lines in each stacked structure is connected to the second word line driving circuit. Source lines / bit lines are disposed above or below the three-dimensional memory device and extend along a row direction intersecting the column direction, wherein a first group of source lines / bit lines overlaps with the first word line driving circuit, and a second group of source lines / bit lines overlaps with the second word line driving circuit.

15. The integrated circuit according to claim 14, wherein, The interconnects of the first word line driving circuit, the interconnects of the second word line driving circuit, the three-dimensional memory device, and the source line / bit line are embedded in a back-end process structure formed on the semiconductor substrate.

16. The integrated circuit according to claim 15, wherein, The first word line routing connects the first group of word lines in each stack structure to the first word line driver circuit, and the second word line routing connects the second group of word lines embedded in each stack structure in the back-end process structure.

17. The integrated circuit of claim 16, wherein, The first word line wiring has a lateral extension extending below the three-dimensional memory device, the second word line wiring has a lateral extension extending below the three-dimensional memory device, and the lateral extensions of the first word line wiring and the lateral extensions of the second word line wiring share a metallization layer in the back-end process structure.

18. The integrated circuit according to claim 14, wherein, The stacked structure has a first step structure on the first side of the three-dimensional memory device and a second step structure on the second side of the three-dimensional memory device.

19. The integrated circuit according to claim 18, wherein The first word line driving circuit extends along the first side of the three-dimensional memory device and overlaps with the first stepped structure. The second word line driving circuit extends along the second side of the three-dimensional memory device and overlaps with the second stepped structure.

20. The integrated circuit according to claim 14, wherein, In each stacked structure, the word lines are stacked vertically and spaced perpendicularly from each other.

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