3D memory device and method for manufacturing conductive channel

Abstract

The present application discloses a 3D memory device, a 3D memory device and a manufacturing method of a conductive channel. The manufacturing method of the conductive channel comprises: forming a channel hole penetrating through a stacked layer structure in the 3D memory device in a step region of the 3D memory device, and side walls of a plurality of gate conductor layers of the stacked layer structure are exposed in the channel hole; forming a first isolation layer covering the side walls of the plurality of gate conductor layers in the inside of the channel hole; forming a first connection layer on the surface of the gate conductor layer which provides a step face among the plurality of gate conductor layers; and filling the channel hole with a conductive material to form a conductive channel, wherein the conductive channel and the plurality of gate conductor layers are separated from each other by the first isolation layer, and the conductive channel and the gate conductor layer which provides the step face are electrically connected through the first connection layer. The manufacturing method reduces the process complexity and difficulty of the conductive channel, and improves the reliability of the bit line connection.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for fabricating a 3D memory device and a conductive channel. Background Technology

[0002] The development trend of semiconductor technology is towards smaller feature sizes and higher integration density. For memory devices, the increase in storage density is closely related to advancements in semiconductor manufacturing processes. As the feature sizes of semiconductor manufacturing processes become smaller, the storage density of memory devices increases. To further improve storage density, three-dimensional memory devices (i.e., 3D memory devices) have been developed. These 3D memory devices consist of multiple memory cells stacked along a vertical direction, which can significantly increase integration density on a unit area of ​​wafer while reducing costs.

[0003] Generally, 3D memory comprises a stacked structure consisting of alternating gate layers and interlayer insulating layers. External circuitry is electrically connected to the gate via contacts located in the stepped regions of the stacked structure. In the actual fabrication of 3D memory, to achieve electrical connection between the contacts and the gate layers in the stacked structure, contact holes are etched in the dielectric layer covering the stacked structure to expose the top surfaces of each gate layer in the stepped regions. These contact holes are then filled with conductive material to form the contacts. However, as the number of layers in a 3D memory increases, the depth difference during contact hole etching becomes significant. When the deepest contact hole is just etched, the shallowest contact hole may experience etching through-holes, causing a short circuit. To avoid over-etching the shallowest contact hole, vertical vias corresponding to different regions of the metal gate layer are typically etched in segments. This method requires multiple photolithography and etching steps, resulting in high costs and time, severely impacting mass production rates. Furthermore, the more layers of memory cells are stacked, the more photolithography and etching processes are required. Summary of the Invention

[0004] In view of the above problems, the purpose of this invention is to provide a method for manufacturing 3D memory devices and conductive channels, thereby solving the defects mentioned in the prior art.

[0005] According to one aspect of the present invention, a method for fabricating a conductive channel in a 3D memory device is provided. The method includes: forming a channel hole penetrating a stacked layer structure in the 3D memory device in a stepped region, wherein the sidewalls of a plurality of gate conductor layers of the stacked layer structure are exposed in the channel hole; forming a first isolation layer inside the channel hole, the first isolation layer covering the sidewalls of the plurality of gate conductor layers; forming a first connection layer on the surface of a gate conductor layer providing a stepped surface in the plurality of gate conductor layers; and filling the channel hole with a conductive material to form a conductive channel, wherein the conductive channel is separated from the plurality of gate conductor layers by the first isolation layer, and the conductive channel is electrically connected to the gate conductor layer providing the stepped surface via the first connection layer.

[0006] Optionally, the conductive channel extends through the first connecting layer and contacts the sidewall of the first connecting layer.

[0007] Optionally, the first connecting layer and the conductive channel are formed simultaneously.

[0008] Optionally, the step of forming the first interconnect layer includes: forming a first sacrificial layer on the upper surface of the gate conductor layer that provides the stepped surface; and replacing the first sacrificial layer with the first interconnect layer.

[0009] Optionally, the first sacrificial layer is a topologically selective film, the material of which includes polycrystalline silicon or alumina.

[0010] Optionally, the step of forming the first isolation layer includes: etching the sidewalls of the plurality of gate conductor layers or the second sacrificial layer through the channel hole to form a groove extending along the periphery of the sidewall of the channel hole; forming an insulating layer on the sidewall of the channel hole, wherein the insulating layer fills the groove; and using etch-back to remove the portion of the insulating layer located on the sidewall of the channel hole, while retaining the portion of the insulating layer filling the groove.

[0011] Optionally, the gate conductor layer formation step in the stacked layer structure includes: forming a dielectric layer and a second sacrificial layer alternately stacked with the dielectric layer on a substrate; and replacing the second sacrificial layer with the gate conductor layer, wherein, prior to the step of replacing the second sacrificial layer with the gate conductor layer, a first sacrificial layer, the channel hole, and the first isolation layer are formed such that the channel hole penetrates the stacked layer structure in the step region.

[0012] Optionally, the step of forming the first isolation layer includes: etching the sidewalls of the plurality of second sacrificial layers or the plurality of gate conductor layers through the channel hole to form a groove extending along the periphery of the sidewall of the channel hole; forming an insulating layer on the sidewall of the channel hole, wherein the insulating layer fills the groove; and removing the portion of the insulating layer located on the sidewall of the channel hole by etching back, while retaining the portion of the insulating layer filling the groove.

[0013] According to another aspect of the present invention, a method for manufacturing a 3D storage device is provided, comprising: A substrate and a stacked layer structure on the substrate are formed, the stacked layer structure including alternately stacked dielectric layers and gate conductor layers, the stacked layer structure including adjacent memory array regions and step regions, the gate conductors and the step regions forming step surfaces; in the memory array regions, channel pillars are formed through the stacked layer structure; in the step regions, conductive channels are formed through the stacked layer structure and the second isolation layer using the conductive channel fabrication method described above; bit lines are formed connecting to the top ends of the channel pillars; and word lines are formed connecting to the top ends of the conductive channels.

[0014] Optionally, before replacing the second sacrificial layer with the gate conductor layer, the channel hole is filled with a third sacrificial layer to form a support pillar; and after replacing the second sacrificial layer with the gate conductor layer, the third sacrificial layer is removed to reform the channel hole, wherein the support pillar is used to support the dielectric layer during the step of replacing the second sacrificial layer with the gate conductor layer.

[0015] Optionally, the support column includes closed pores.

[0016] Optionally, the method of replacing the second sacrificial layer with a gate conductor layer includes: anisotropically etching the stacked structure to form a gate line gap; removing the second sacrificial layer through the gate line gap to form a gap between adjacent dielectric layers of the sacrificial stacked structure; and filling the gap with a conductive material through the gate line gap to form a gate conductor layer.

[0017] According to another aspect of the present invention, a 3D memory device is provided, comprising: a substrate; and a stack. The stacked layer structure includes alternating dielectric layers and gate conductor layers, the stacked layer structure being located on a substrate, the stacked layer structure including adjacent memory array regions and step regions, the gate conductors forming step surfaces in the step regions; a conductive channel, the step regions penetrating the stacked layer structure; a first isolation layer located between the conductive channel and a plurality of gate conductor layers; a first connection layer located on the surface of a gate conductor layer providing a step surface among the plurality of gate conductor layers; wherein the conductive channel is electrically connected to the gate conductor layer providing the step surface via the first connection layer, and the conductive channel is separated from the other gate conductor layers of the plurality of gate conductor layers by the first isolation layer.

[0018] Optionally, the conductive channel extends through the first connecting layer and contacts the sidewall of the first connecting layer.

[0019] Optionally, the conductive channel extends through the stacked layer structure and extends to the substrate.

[0020] Optionally, the filling material of the conductive channel includes tungsten, titanium nitride, tungsten alloy, or a combination thereof.

[0021] Optionally, the material of the gate conductor layer includes any one or a combination of polycrystalline silicon, tungsten, titanium nitride, and tungsten alloys.

[0022] This invention provides a via hole penetrating at least a portion of the gate conductor layer, in which an isolation layer is formed, and the via hole is filled to form a conductive channel. A first interconnect layer is formed in the space created by removing the first sacrificial layer, connecting the gate to the conductive channel. The topmost gate layer penetrated by the via hole can form an electrical connection with the conductive channel through this first interconnect layer. The conductive channel formed by this fabrication method penetrates the gate conductor layer and is interconnected with it via the first interconnect layer. During the etching process to form the via hole, it is not necessary to precisely stop at the top surface of the gate conductor layer, thus reducing the process complexity and difficulty of the conductive channel and improving the reliability of the bit line connection.

[0023] Furthermore, a method is provided where a sacrificial stacked structure is formed on a substrate before forming the stacked layer structure. A third sacrificial layer within a via acts as a support for the entire stacked structure when replacing the gate sacrificial layer. Subsequently, the third sacrificial layer is removed to form a conductive channel. This via integrates the supporting third sacrificial layer and the connecting conductive channel, allowing the third sacrificial layer and the conductive channel to be formed sequentially within the via. This reduces the number of etching operations required and lowers process costs.

[0024] The first sacrificial layer located on the top surface of the stepped structure is made of a topologically selective film material. Since the etching rate of the topologically selective film of silicon nitride is about two to three times that of conventional silicon nitride (SiN), the first sacrificial layer containing the topologically selective film of silicon nitride is etched away laterally at a much faster rate than the third sacrificial layer below it. This accelerates the etching rate, makes the etching of the first sacrificial layer more thorough, and increases the contact area between the gate conductor layer and the first interconnection layer, thereby enhancing the data transmission performance of the 3D memory devices subsequently fabricated in this process.

[0025] The 3D memory device manufacturing method provided by this invention involves setting a multi-step stacked structure on a substrate, forming a first sacrificial layer on the top surface of each step using a topology-selective film material to accelerate the lateral etching rate, forming a channel hole penetrating the step region and the dielectric layer in a first longitudinal direction perpendicular to the substrate, wherein the channel hole has a groove at the junction with the second sacrificial layer, and an isolation layer is formed on the inner wall of the channel hole to fill the channel hole, replacing the second sacrificial layer with a gate conductor layer, etching a mask above the dielectric layer to form contact holes, and a third sacrificial layer in the channel hole supporting the entire stacked structure when replacing the gate sacrificial layer. The structure removes the first sacrificial layer and the third sacrificial layer in the channel hole, and fills the space formed by removing the first sacrificial layer and the third sacrificial layer with conductive material to form a conductive channel. Furthermore, in the memory array region, a channel pillar is formed that penetrates the stacked layer structure, a bit line is formed that connects to the top of the channel pillar, and a word line is formed that connects to the top of the conductive channel, thus constituting a 3D memory device with complete functionality. The aforementioned channel hole integrates the third sacrificial layer that plays a supporting role and the conductive channel that plays a connecting role, reducing the number of photolithography and etching processes and lowering the manufacturing cost. Attached Figure Description

[0026] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which: Figure 1a and Figure 1b The circuit diagram and structural schematic diagram of the storage cell string of the 3D storage device are shown respectively; Figure 2 A perspective view of a 3D storage device is shown; Figure 3 A flowchart illustrating a method for manufacturing conductive channels in a 3D memory device according to a first embodiment of the present invention is shown; Figures 4a to 4g Cross-sectional views of various stages of a method for manufacturing conductive channels in a 3D memory device according to a first embodiment of the present invention are shown. Figure 5 A flowchart illustrating a method for manufacturing conductive channels in a 3D memory device according to a second embodiment of the present invention is shown; Figures 6a to 6j Cross-sectional views of various stages of a method for manufacturing conductive channels in a 3D memory device according to a second embodiment of the present invention are shown. Figure 7 A front view of the 3D storage device of the present invention is shown. Detailed Implementation

[0027] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements or modules are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.

[0028] Furthermore, certain terms are used in this patent specification and claims to refer to specific components. Those skilled in the art will understand that hardware manufacturers may use different names to refer to the same component. This patent specification and claims do not distinguish components based on differences in name, but rather on differences in function.

[0029] In this application, the term "semiconductor structure" refers to the collective term for the entire semiconductor structure formed in the various steps of manufacturing a memory device, including all layers or regions that have been formed. Many specific details of the invention, such as the structure, materials, dimensions, processing techniques, and methods of the device, are described below to provide a clearer understanding of the invention. However, as those skilled in the art will understand, the invention may be implemented without adhering to these specific details.

[0030] Figure 1a and 1b The circuit diagram and structural schematic diagram of the storage cell string of the 3D storage device are shown respectively. In this embodiment, the storage cell string shown includes four storage cells. It is understood that the invention is not limited thereto, and the number of storage cells in the storage cell string can be any number, for example, 32 or 64.

[0031] like Figure 1a As shown, the first end of the memory cell string 100 is connected to the bit line BL, and the second end is connected to the source line SL. The memory cell string 100 includes a plurality of transistors connected in series between the first and second ends, including: a first selection transistor Q1, storage transistors M1 to M4, and a second selection transistor Q2. The gate of the first selection transistor Q1 is connected to the first selection line SSL, and the gate of the second selection transistor Q2 is connected to the second selection line GSL. The gates of the storage transistors M1 to M4 are respectively connected to the corresponding word lines WL1 to WL4.

[0032] like Figure 1bAs shown, the first selection transistor Q1 and the second selection transistor Q2 of the memory cell string 100 each include gate conductors 109b and 109c, and the memory transistors M1 to M4 each include a gate conductor 109a. The gate conductors 109a, 109b, and 109c are arranged in the same stacking order as the transistors in the memory cell string 100, and adjacent gate conductors are separated from each other by an interlayer insulating layer, thereby forming a gate stack structure. Further, the memory cell string 100 includes a channel pillar 110. The channel pillar 110 is adjacent to or penetrates the gate stack structure. In the middle portion of the channel pillar 110, a tunneling dielectric layer 112, a charge storage layer 113, and a barrier dielectric layer 114 are sandwiched between the gate conductor 109a and the channel layer 111, thereby forming the memory transistors M1 to M4. At both ends of the channel pillar 110, a barrier dielectric layer 114 is sandwiched between the gate conductors 109b and 109c and the channel layer 111, thereby forming a first selection transistor Q1 and a second selection transistor Q2.

[0033] In this embodiment, the channel layer 111 is composed, for example, of doped polysilicon; the tunneling dielectric layer 112 and the barrier dielectric layer 114 are each composed of oxides, such as silicon oxide; the charge storage layer 113 is composed of an insulating layer containing quantum dots or nanocrystals, such as silicon nitride and silicon oxynitride containing metal or semiconductor particles; and the gate conductors 109a, 109b, and 109c are composed of metals, such as tungsten. The channel layer 111 provides the channel region for the select transistor and the storage transistor, and the doping type of the channel layer 111 is the same as the type of the select transistor and the storage transistor. For example, for an N-type select transistor and a storage transistor, the channel layer 111 may be N-type doped polysilicon.

[0034] In this embodiment, the core of the channel post 110 is a channel layer 111, and the tunneling dielectric layer 112, charge storage layer 113, and barrier dielectric layer 114 form a stacked structure surrounding the sidewalls of the core. In an alternative embodiment, the core of the channel post 110 is an additional insulating layer, and the channel layer 111, tunneling dielectric layer 112, charge storage layer 113, and barrier dielectric layer 114 form a stacked structure surrounding the core.

[0035] In this embodiment, the first selection transistor Q1, the second selection transistor Q2, and the storage transistors M1 to M4 use a common channel layer 111 and a barrier dielectric layer 114. In the channel pillar 110, the channel layer 111 provides the source / drain regions and channel layer for the plurality of transistors. In an alternative embodiment, the semiconductor layers and barrier dielectric layers of the first selection transistor Q1 and the second selection transistor Q2, as well as the semiconductor layers and barrier dielectric layers of the storage transistors M1 to M4, can be formed in separate steps. In the channel pillar 110, the semiconductor layers of the first selection transistor Q1 and the second selection transistor Q2 are electrically connected to each other with the semiconductor layers of the storage transistors M1 to M4.

[0036] During the write operation, the memory cell string 100 utilizes the tunneling effect to write data to selected memory transistors among memory transistors M1 to M4. Taking memory transistor M2 as an example, while the source line SL is grounded, the second gate selective line GSL is biased to approximately zero volts, causing the selector transistor Q2 corresponding to the second gate selective line GSL to turn off, and the first source selective line SSL is biased to a high voltage VDD, causing the selector transistor Q1 corresponding to the first selective line SSL to turn on. Further, the bit line BL2 is grounded, the word line WL2 is biased to the programming voltage VPG, for example, around 20V, and the remaining word lines are biased to a low voltage VPS1. Since only the word line voltage of the selected memory transistor M2 is higher than the tunneling voltage, electrons in the channel region of the memory transistor M2 reach the charge storage layer 113 through the tunneling dielectric layer 112, thereby converting the data into charge and storing it in the charge storage layer 113 of the memory transistor M2.

[0037] During the read operation, the memory cell string 100 determines the amount of charge in the charge storage layer based on the conduction state of selected memory transistors M1 to M4, thereby obtaining the data represented by that charge amount. Taking memory transistor M2 as an example, word line WL2 is biased at the read voltage VRD, while the other word lines are biased at a high voltage VPS2. The conduction state of memory transistor M2 is related to its threshold voltage, i.e., related to the amount of charge in the charge storage layer, thus the data value can be determined based on the conduction state of memory transistor M2. Memory transistors M1, M3, and M4 are always in the conduction state; therefore, the conduction state of memory cell string 100 depends on the conduction state of memory transistor M2. The control circuit determines the conduction state of memory transistor M2 based on the electrical signals detected on bit line BL and source line SL, thereby obtaining the data stored in memory transistor M2.

[0038] Figure 2 A perspective view of the 3D storage device is shown. For clarity, [the view is shown in the original text]. Figure 2 The individual insulating layers in the 3D storage device are not shown.

[0039] The 3D storage device 200 shown in this embodiment includes 16 4x4 storage cell strings 100, each storage cell string 100 including 4 storage cells, thereby forming a 4x4x4 storage cell array with a total of 64 storage cells. It is understood that the present invention is not limited thereto; the 3D storage device may include any number of storage cell strings, for example, 1024, and the number of storage cells in each storage cell string may be any number, for example, 32 or 64.

[0040] In the 3D memory device 200, each memory cell string includes its own channel pillar 110 and a common gate conductor layer 121, 122, and 123. The gate conductor layers 121, 122, and 123 are arranged in the same order as the transistors in the memory cell string 100, and adjacent gate conductors are separated from each other by an interlayer insulating layer, thereby forming a gate stack structure 120. The interlayer insulating layer is not shown in the figure.

[0041] The internal structure of the channel column 110 is as follows Figure 1b As shown, no further detailed description will be provided here. The channel pillars 110 penetrate the gate stack structure 120 and are arranged in an array. The first ends of multiple channel pillars 110 in the same column are connected to the same bit line (i.e., one of bit lines BL1 to BL4), and the second ends are connected to the substrate 101. The second ends form a common source connection through the substrate 100.

[0042] The gate conductor layer 122 of the first selection transistor Q1 is divided into different gate lines by a gate line slit 135. The gate lines of multiple channel pillars 110 in the same row are connected to the same series select line (i.e., one of the series select lines SSL1 to SSL4).

[0043] The gate conductor layers 121 of storage transistors M1 and M4 are respectively connected to the corresponding word lines. If the gate conductor layers 121 of storage transistors M1 and M4 are divided into different gate lines by gate line gaps 135, the gate lines on the same layer reach the interconnect layer 132 through their respective conductive channels 109, thereby interconnecting with each other, and then connected to the same word line (i.e., one of word lines WL1 to WL4) through conductive channels 109.

[0044] The gate conductors of the second selection transistor Q2 are connected as one. If the gate conductor layer 123 of the second selection transistor Q2 is divided into different gate lines by the gate line gap 135, the gate lines reach the interconnect layer 132 through their respective conductive channels 109, thereby interconnecting with each other, and then connected to the same ground selection line GSL through the conductive channel 133.

[0045] This application provides a method for manufacturing a 3D memory according to a first embodiment of the present invention. Figure 3 A flowchart of the method is shown.

[0046] like Figure 3 As shown: The method for manufacturing the 3D memory according to the first embodiment may include the following steps: S1: A stacked layer structure with multiple stepped steps is formed on a substrate, a first sacrificial layer is formed on the top surface of each stepped step, and a dielectric layer is formed above the stepped step; (see...) Figure 4a ); S2: A channel hole is formed in the first longitudinal direction perpendicular to the substrate, penetrating the stacked layer structure of the stepped region. A groove is formed at the junction of the channel hole and the gate layer (see...). Figure 4b and 4c ); S3: Form an isolation layer on the inner wall of the channel hole (see...) Figure 4d and 4e ); S4: Etch a second isolation layer over the dielectric layer to form a contact hole (see...) Figure 4f ); S5: Remove the first sacrificial layer, and fill the space and channel holes formed by removing the first sacrificial layer with conductive material to form a conductive channel (see...). Figure 4g ); Figures 4a to 4g Cross-sectional views are shown of various stages of a method for manufacturing conductive channels in a 3D memory device according to an embodiment of the present invention. The cross-sectional views are along... Figure 2 The AA line in the middle is cut off.

[0047] like Figure 4a As shown, a substrate 101 is first formed, and then a stacked layer structure 130 is formed on the substrate 101, consisting of alternating gate conductor layers 121, 122, 123 and a dielectric layer 103. The stacked layer structure 130 may include a memory array region (with memory cells) and a stepped region (with word line interconnects). The stacked layer structure 130 extends from the memory array region to the stepped region, and the two are adjacent. A portion of the surface of the gate conductor layers 121, 123, 123 of this stacked layer structure forms a stepped surface. The substrate 101 is, for example, a single-crystal silicon substrate. The material of the dielectric layer 103 includes, but is not limited to, silicon oxide. The material of the gate conductor layer includes, but is not limited to, polycrystalline silicon, tungsten, titanium nitride, tungsten alloys, and other conductive materials.

[0048] Furthermore, a first sacrificial layer 104 is formed on the top surface of the gate conductor layers providing step surfaces in the stacked layer structure 130 of the stepped region. That is, the first sacrificial layer 104 covers the step surfaces of the multiple gate conductor layers; for example, the first sacrificial layer 104 can be formed on the top surface of each stepped surface by one or more deposition processes, including but not limited to atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), or any combination thereof. For example, the first sacrificial layer 104 can be formed by an atomic layer deposition process. The material forming the first sacrificial layer can be a topologically selective film (TS), including alumina and polysilicon. For example, when wet etching is performed using phosphoric acid or the like as an etchant, the topologically selective film material has an etching rate approximately two to three times that of a normal silicon nitride material. This characteristic of the topologically selective silicon nitride film material is beneficial for the subsequent formation of the first interconnect layer.

[0049] It should be noted that the formation of the first sacrificial layer 104 on the top surface of the stacked layer structure 130 in the stepped area includes, but is not limited to, the above-described process. It is also necessary to trim the first sacrificial layer formed by the deposition process. Dry etching such as deep ion reactive etching (RIDE) can be used, or wet etching (such as using phosphoric acid as an etchant) can be used.

[0050] Furthermore, a dielectric layer 103 is formed above the stacked layer structure 130 in the stepped region. As an example, the dielectric layer 103 can be formed by depositing an oxide, which may be selected from, for example, a silicon oxide-based material. In one embodiment of this application, the dielectric layer 103 may be formed by filling silicon oxide based on TEOS. The dielectric layer 103 may be a multilayer structure, first forming a first sub-film layer with good stepped coverage, such as silicon oxide (SiO2) deposited by high-density plasma (HDP) or silicon oxide deposited by atomic layer deposition (ALD); then continuing to form a second sub-film layer with high filling efficiency, such as silicon oxide based on TEOS (TESO-based SiO2). The density of the first sub-film layer is higher than that of the second sub-film layer, thereby the first sub-film layer has good stepped coverage, while the second sub-film layer has high filling efficiency.

[0051] See Figure 4b and 4c A channel hole is formed in the first longitudinal direction perpendicular to the substrate, penetrating the stacked layer structure. The channel hole has grooves formed at its junctions with multiple gate conductor layers, such as... Figure 4b As shown, a channel hole 31 is first formed by etching through the stacked layer structure 130 penetrating the stepped region. The sidewalls of the plurality of gate conductor layers are exposed in the channel hole 31. High-selectivity wet etching or gas etching can be used. Then, the gate conductor layer 121 is etched in the channel hole 31. The etching depth is controlled by precisely controlling the etching time to form a structure as shown in the figure. Figure 4c The groove 105 is shown. Optionally, the method of forming the groove 105 is not limited to the etching method used in this embodiment; other methods that can form the first groove 105 are also possible.

[0052] Referring to 4d and 4e, an isolation layer is formed on the inner wall of the channel hole. Further, a first isolation layer 141 is formed on the inner wall of the channel hole, and the first isolation layer 141 is located within the groove 105.

[0053] like Figure 4d As shown, an insulating material is first deposited on the inner surface of the channel hole 31, and then the insulating material is etched back to form a shape as shown. Figure 4e The multiple first isolation layers 141 shown.

[0054] Optionally, the insulating material can be partially oxidized, and the oxidation time and amount can be controlled. Specifically, the insulating material outside the groove 105 is oxidized, and the oxidized portion is removed with acid, forming a first isolation layer 141 inside the channel hole, covering the sidewalls of the plurality of gate conductor layers 121. Since the plurality of first isolation layers 141 are located within the first groove 105, they are separated from each other. Optionally, the etching position can be controlled using high-selectivity wet etching or gas etching.

[0055] See Figure 4f A second isolation layer is etched above the dielectric layer to form a contact hole. Specifically, a second isolation layer 108 is formed above the dielectric layer 103, and a contact hole is formed using photolithography. The contact hole and the channel hole 31 are spatially integrated to form a new channel hole.

[0056] See Figure 4g Remove the first sacrificial layer, and fill the space and channel holes formed by removing the first sacrificial layer with conductive material to form a conductive channel; For example, in Figure 4g In this process, the first sacrificial layer 104 is made of a topologically selective film. When phosphoric acid or the like is used as an etchant for wet etching, the topologically selective film material of silicon nitride has an etching rate that is about two to three times that of normal silicon nitride material. Therefore, when the first sacrificial layer 104 is anisotropically etched, the first sacrificial layer 104 can be etched away more quickly in the lateral direction.

[0057] Furthermore, conductive material is filled in the space formed by removing the first sacrificial layer and the contact hole to form a conductive channel 109, which extends to the substrate; wherein, the space formed by removing the first sacrificial layer 104 is replaced by a first interconnect layer 131, and the conductive channel penetrates the first interconnect layer 131 and is electrically connected to the gate conductor layer 121 conductor layer that provides the stepped surface via the first interconnect layer 131.

[0058] Specifically, the filling material can be a conductive material such as tungsten, titanium nitride, or tungsten alloy to form a conductive channel 109. The conductive channel 109 is then subjected to chemical mechanical polishing (CMP) to smooth its upper surface, facilitating subsequent connection between the conductive channel and word lines or control gate select lines.

[0059] In this embodiment, a via 31 penetrating at least a portion of the gate conductor layer is provided. A first isolation layer 141 is formed in the via 31, and the via 31 is filled to form a conductive channel 109. A first connection layer 131 is formed in the space where the first sacrificial layer 104 is removed, connecting the gate conductor layer 121 to the conductive channel. The gate conductor layer 121, which provides a stepped surface and is penetrated by the via 31, can form an electrical connection with the conductive channel 109 through the first connection layer 131. The conductive channel formed by this fabrication method penetrates the gate conductor layer and is interconnected with the gate conductor layer via the first connection layer. In the step of etching to form the via 31, it is not necessary to precisely stop at the top surface of the gate conductor layer, thus reducing the process complexity and difficulty of the conductive channel and improving the reliability of the bit line connection.

[0060] This application provides a method for manufacturing a 3D memory according to a second embodiment of the present invention. Figure 5 A flowchart of the method is shown.

[0061] like Figure 5 As shown: The method for fabricating the conductive channels of the 3D memory in the second embodiment provided may include the following steps: S1: A stacked layer structure with multiple stepped steps is formed on a substrate, a dielectric layer is formed above the stepped steps, and a first sacrificial layer is formed on the top surface of each stepped step; (see...) Figure 6a ); S2: A channel hole is formed in the first longitudinal direction perpendicular to the substrate, penetrating the stacked layer structure of the stepped region. A groove is formed at the junction of the channel hole and the second sacrificial layer (see...). Figure 6b and 6c ); S3: Form an isolation layer on the inner wall of the channel hole (see...) Figure 6d and 6e ); S4: Fill the channel holes to form a third sacrificial layer (see...) Figure 6f ); S5: Replace the second sacrificial layer with the gate conductor layer (see...) Figure 6g ); S6: Etch a second isolation layer above the dielectric layer to form a contact hole (see...) Figure 6h ); S7: Remove the first sacrificial layer and the third sacrificial layer in the channel hole, and fill the space formed by removing the first sacrificial layer and the third sacrificial layer with conductive material to form a conductive channel (see...). Figure 6i and 6j ).

[0062] Figures 6a to 6j Cross-sectional views of various stages of a 3D memory device manufacturing method according to an embodiment of the present invention are shown. The cross-sectional views are along... Figure 2 The AA line in the middle is cut off.

[0063] like Figure 6a As shown, a stacked layer structure with multiple stepped steps is formed on a substrate. The stacked layer structure 130 may include a memory array region (with memory cells) and a stepped step region (with word line interconnects). The stacked layer structure 130 extends from the memory array region to the stepped step region, and the two are adjacent. A dielectric layer 103 is formed above the stacked layer structure 130 in the stepped region, and a first sacrificial layer 104 is formed on the top surface of each stepped step. In the fabrication of 3D memory devices, multiple steps need to be formed using a sacrificial stacked structure (insulating stacked structure) located on the substrate 101. In this case, the stacked layer structure 130 consists of multiple alternately stacked dielectric layers 103 and multiple second sacrificial layers 102. The substrate 101 is, for example, a single-crystal silicon substrate. The second sacrificial layer 102 has a high etching selectivity to the dielectric layer 103, so that the second sacrificial layer 102 can be replaced with a gate conductor layer in subsequent processes. For example, the material of the dielectric layer 103 includes, but is not limited to, silicon oxide, and the material of the second sacrificial layer 102 includes, but is not limited to, silicon nitride. The method for forming the stepped region is known to those skilled in the art and will not be described in detail here.

[0064] Furthermore, a first sacrificial layer 104 is formed on the top surface of the gate conductor layer providing the step surface in the stacked layer structure 130 of the step region. That is, the first sacrificial layer 104 covers multiple second sacrificial layer step surfaces; for example, the first sacrificial layer 104 can be formed on the top surface of each step by one or more deposition processes, including but not limited to atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), or any combination thereof. For example, the first sacrificial layer 104 can be formed by an atomic layer deposition process. The material forming the first sacrificial layer can be a topologically selective silicon nitride (SiN) film (TS-SiN). For example, when wet etching is performed using phosphoric acid or the like as an etchant, the topologically selective silicon nitride film material has an etching rate approximately two to three times that of normal silicon nitride material. This characteristic of the topologically selective silicon nitride film material is beneficial for the formation of subsequent conductive channels.

[0065] It should be noted that the formation of the first sacrificial layer 104 on the top surface of the sacrificial stack structure 136 in the step region includes, but is not limited to, the above-described process. It is also necessary to trim the first sacrificial layer formed by the deposition process. Dry etching, such as deep ion reactive etching (RIDE), can be used, or wet etching (such as using phosphoric acid as an etchant) can be used.

[0066] Furthermore, a dielectric layer 103 is formed over the sacrificial stack structure 136 in the stepped region. As an example, the dielectric layer 103 can be formed by depositing an oxide, which may be selected from, for example, a silicon oxide-based material. In one embodiment of this application, the dielectric layer 103 may be formed by filling silicon oxide based on TEOS. The dielectric layer 103 may be a multilayer structure, first forming a first sublayer with good stepped coverage, such as silicon oxide (SiO2) deposited by high-density plasma (HDP) or silicon oxide deposited by atomic layer deposition (ALD); then forming a second sublayer with high filling efficiency, such as silicon oxide based on TEOS (TESO-based SiO2). The density of the first sublayer is higher than that of the second sublayer, thus the first sublayer has good stepped coverage while the second sublayer has high filling efficiency.

[0067] See Figure 6b and 6c A sacrificial stack structure 136 is formed perpendicular to the first longitudinal direction of the substrate, penetrating the stepped region and extending into the substrate, wherein the channel hole has a groove formed at the junction with the second sacrificial layer 102, such as... Figure 6b As shown, a channel hole 31 is first formed through etching, penetrating the stepped structure and dielectric layer. The sidewalls of the plurality of gate conductor layers are exposed in the channel hole. High-selectivity wet etching or gas etching can be used. Then, the second sacrificial layer 102 is etched in the channel hole 31. The etching depth is controlled by precisely controlling the etching time to form a structure as shown. Figure 6c The groove 105 is shown. Optionally, the method of forming the groove 105 is not limited to the etching method used in this embodiment; other methods that can form the first groove 105 are also possible.

[0068] See Figure 6d and 6e A first isolation layer 141 is formed on the inner wall of the channel hole; like Figure 6d As shown, an insulating material is first deposited on the inner surface of the channel hole 31, and then the insulating material is etched back to form a shape as shown. Figure 6e The multiple first isolation layers 141 shown.

[0069] Optionally, the insulating material can be partially oxidized, and the oxidation time and amount can be controlled. Specifically, the insulating material outside the groove 105 is oxidized, and the oxidized portion is removed with acid, forming a first isolation layer 141 inside the channel hole, covering the sidewalls of the plurality of gate conductor layers. Since the plurality of first isolation layers 141 are located within the first groove 105, they are separated from each other. Optionally, the etching position can be controlled using high-selectivity wet etching or gas etching.

[0070] See Figure 6f The channel hole is filled; using the dielectric layers on both sides of the channel hole as a mask, the channel hole is filled with a third sacrificial layer 106 in a self-aligned manner to form a support pillar. The third sacrificial layer 106 is used to support the dielectric layer 103 during the step of replacing the second sacrificial layer 102 with the gate conductor layers 121, 122, 123. The filling medium may include carbon, polysilicon, silicon nitride, etc. Furthermore, during the filling process, the channel filling process can be controlled to form multiple closed pores 107 in the filling medium to reduce structural stress.

[0071] See 6g, where the second sacrificial layer 102 is replaced with gate conductor layers 121, 122, and 123.

[0072] In this step, for example, anisotropic etching is first performed on the stacked layer structure 130. Anisotropic etching can be performed using dry etching methods, such as ion gun etching, plasma etching, reactive ion etching, or laser ablation. For example, by controlling the etching time, the etching stops near the substrate 101 to form a structure like... Figure 2 Multiple pores 107 are shown. Then, for example, a wet etching process is used to remove the second sacrificial layer 102 through the multiple pores 107, forming a gap between two adjacent dielectric layers 103. Then, conductive material is filled into the pores 107 and the gaps. The conductive material includes, but is not limited to, metallic aluminum. Finally, a back etching process is used to reform the pores 107. The conductive material remaining in the pores 107 constitutes the gate conductor layers 121, 122, and 123. The sidewalls of the multiple gate conductor layers of the stacked layer structure are exposed in the channel holes.

[0073] In this step, the second sacrificial layer 102 is replaced by gate conductor layers 121, 122, and 123. Gate conductor layers 121, 122, and 123, together with dielectric layer 103, form a new stacked layer structure 130. The stacked layer structure 130 formed after replacing the second sacrificial layer 102 with gate conductor layers 121, 122, and 123 corresponds to the aforementioned gate stacked layer structure 120. Since both the first isolation layer 141 and dielectric layer 103 are oxides, the etchant has minimal impact on the first isolation layer 141 and dielectric layer 103 during the removal of the second sacrificial layer 102. The first isolation layer 141 covers the sidewalls of the plurality of gate conductor layers, and the first isolation layer 141 and dielectric layer 103 together surround the gate conductor layers 121, 122, and 123, thereby protecting the gate conductor layers 121, 122, and 123.

[0074] Referring to 6h, a second isolation layer is etched above the dielectric layer to form a contact hole. Specifically, a second isolation layer 108 is formed above the dielectric layer 103, and a contact hole is formed using photolithography. This contact hole and the channel hole 31 are spatially integrated to form a new channel hole.

[0075] Referring to 6i and 6j, the third sacrificial layer 106 in the first sacrificial layer 104 and the channel hole 31 is removed, and the space formed by removing the first sacrificial layer 104 and the third sacrificial layer 106 is filled with conductive material to form a conductive channel 109.

[0076] like Figure 6i The first sacrificial layer 104, located on the top surface of the stepped structure, is made of a topologically selective film material, including alumina and polysilicon. The third sacrificial layer 106 in the channel hole is made of conventional materials such as carbon, polysilicon, and silicon nitride. In this case, phosphoric acid can be used as an etchant to remove the first sacrificial layer 104 by a wet etching process. Since the etching rate of silicon nitride topologically selective film is about two to three times that of conventional SiN, the first sacrificial layer 400 containing silicon nitride topologically selective film is etched away much faster than the third sacrificial layer below it. This accelerates the etching rate, makes the etching of the first sacrificial layer more thorough, and increases the contact area between the gate conductor layer and the first interconnection layer, thereby enhancing the data transmission performance of the 3D memory device subsequently fabricated in this process.

[0077] Furthermore, conductive material is filled into the spaces formed by removing the first and third sacrificial layers and the contact holes to form conductive channels 109 that extend to the substrate. The spaces formed by removing the first sacrificial layer 104 are replaced with a first interconnect layer 131, which is electrically connected to the gate conductor layer 121 providing the stepped surface via the first interconnect layer 131. Specifically, the filling material can be conductive materials such as tungsten, titanium nitride, or tungsten alloys, forming conductive channels 109 that penetrate the stacked structure and the second isolation layer 108. Further, the conductive channels 109 are subjected to chemical mechanical polishing (CMP) to smooth the upper surface of the conductive channels 109, facilitating subsequent processes.

[0078] In this embodiment, a second sacrificial layer is formed on the substrate before the gate conductor layer is formed. The third sacrificial layer of the channel hole plays a supporting role in the entire stacked structure when replacing the second sacrificial layer. The third sacrificial layer is then removed to form a conductive channel. This channel hole integrates the third sacrificial layer that plays a supporting role and the conductive channel that plays a connecting role, requiring fewer etching steps and further reducing the process cost.

[0079] Figure 7 A front plan view of the 3D storage device of the present invention is shown; like Figure 7As shown, the present invention also provides a method for manufacturing a 3D memory device, which, based on the second embodiment of the conductive channel described above, further includes forming a channel post penetrating the stacked layer structure in the memory array region; forming a bit line connected to the top end of the channel post; and forming a word line connected to the top end of the conductive channel, so as to constitute a 3D memory device with full functionality.

[0080] It should be noted that, in order to show the various steps in the method flow more specifically in the attached figure, a certain part is enlarged, showing only one gate conductor layer electrically connected to the conductive channel through the first connection layer. In fact, there are several conductive channels (corresponding to the number of gate conductor layers), and they are electrically connected to other gate conductor layers through the first connection layer at the corresponding position.

[0081] It should be noted that those skilled in the art will understand that the terms "during," "when," and "when…" used herein in relation to circuit operation are not strict terms indicating an action that occurs immediately upon the commencement of a startup action, but rather that there may be one or more small but reasonable delays, such as various transmission delays, between the startup action and the reaction action initiated by it. The terms "approximately" or "substantially" used herein mean that an element value is expected to be close to the declared value or position. However, as is well known in the art, there are always small deviations that make it difficult for the value or position to be strictly the declared value.

[0082] Furthermore, it should be noted that in the text, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, terms such as "comprising," "including," or any variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the stated element.

[0083] The multiple steps in the methods described herein are illustrative only and not intended to be strictly limited in their order, unless otherwise specified. Those skilled in the art can modify the order of the steps to suit actual process conditions. The number of components in the products described herein are illustrative only and not intended to be strictly limited in their value, unless otherwise specified. Those skilled in the art can modify the number of components to suit actual product requirements.

[0084] As described above, these embodiments of the present invention do not exhaustively describe all details, nor do they limit the invention to specific embodiments. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The scope of protection of this invention should be determined by the scope defined in the claims and their equivalents.

Claims

1. A method for fabricating a conductive channel in a 3D memory device, the method comprising: A channel hole is formed in the step region of the 3D memory device, penetrating the stacked layer structure in the 3D memory device, and the sidewalls of the multiple gate conductor layers of the stacked layer structure are exposed in the channel hole; A first isolation layer is formed inside the channel hole, and the first isolation layer covers the sidewalls of the plurality of gate conductor layers; A first interconnect layer is formed on the surface of the gate conductor layer that provides a stepped surface in the plurality of gate conductor layers; as well as The channel holes are filled with a conductive material to form a conductive channel. The conductive channel is separated from the plurality of gate conductor layers by the first isolation layer, and the conductive channel is electrically connected to the gate conductor layer providing the stepped surface via the first connection layer.

2. The method for fabricating a conductive channel according to claim 1, wherein, The conductive channel penetrates the first connecting layer and contacts the sidewall of the first connecting layer.

3. The method for fabricating a conductive channel according to claim 1, wherein, The first connecting layer and the conductive channel are formed simultaneously.

4. The method for fabricating a conductive channel according to claim 1, wherein, The steps for forming the first connection layer include: A first sacrificial layer is formed on the upper surface of the gate conductor layer that provides the stepped surface; and Replace the first sacrificial layer with the first connection layer.

5. The method for fabricating a conductive channel according to claim 4 further includes: The first sacrificial layer is a topologically selective film, and the material of the topologically selective film includes polycrystalline silicon or alumina.

6. The method for fabricating a conductive channel according to claim 4, wherein, The steps to form the first isolation layer include: The sidewalls of the plurality of gate conductor layers are etched through the channel hole to form a groove extending along the periphery of the sidewall of the channel hole; An insulating layer is formed on the sidewall of the channel hole, and the insulating layer fills the groove; and The portion of the insulating layer located on the sidewall of the channel hole is removed by back etching, while the portion of the insulating layer filling the groove is retained.

7. The method for fabricating a conductive channel according to claim 4, wherein, The steps for forming the gate conductor layer in the stacked layer structure include: A dielectric layer and a second sacrificial layer alternately stacked with the dielectric layer are formed on a substrate; and The second sacrificial layer is replaced with the gate conductor layer. Prior to the step of replacing the second sacrificial layer with the gate conductor layer, the first sacrificial layer, the channel hole, and the first isolation layer are formed such that the channel hole penetrates the stacked layer structure in the step region.

8. The method for fabricating a conductive channel according to claim 7, wherein, The steps to form the first isolation layer include: The sidewalls of the plurality of second sacrificial layers are etched through the channel hole to form a groove extending along the periphery of the sidewall of the channel hole; An insulating layer is formed on the sidewall of the channel hole, and the insulating layer fills the groove; and The portion of the insulating layer located on the sidewall of the channel hole is removed by back etching, while the portion of the insulating layer filling the groove is retained.

9. A method for manufacturing a 3D storage device, comprising: A substrate and a stacked layer structure on the substrate are formed, the stacked layer structure including alternately stacked dielectric layers and gate conductor layers, the stacked layer structure including adjacent memory array regions and step regions, the gate conductors and the step regions forming step surfaces; In the storage array region, channel pillars are formed that penetrate the stacked layer structure; A second isolation layer is formed above the stacked layer structure; In the stepped area, a conductive channel is formed through the stacked layer structure and the second isolation layer using the conductive channel fabrication method of any one of claims 1 to 8; Forming a bit line connected to the top end of the channel post; and A word line is formed that connects to the top of the conductive channel.

10. The method for fabricating a 3D memory device according to claim 9, wherein the step of forming the gate conductor layer in the stacked layer structure includes: A dielectric layer and a second sacrificial layer, alternately stacked with the dielectric layer, are formed on a substrate to form a sacrificial stack structure; as well as The second sacrificial layer is replaced with the gate conductor layer. The manufacturing method further includes: Prior to the step of replacing the second sacrificial layer with the gate conductor layer, the channel hole is filled with a third sacrificial layer to form a support pillar; and After replacing the second sacrificial layer with the gate conductor layer, the third sacrificial layer is removed to reform the channel via. The support pillar is used to support the dielectric layer during the step of replacing the second sacrificial layer with the gate conductor layer.

11. The method for manufacturing a 3D storage device according to claim 10, in, The support column includes closed pores.

12. The method for manufacturing a 3D storage device according to any one of claims 10 to 11, wherein, The method of replacing the second sacrificial layer with a gate conductor layer includes: The sacrificial stack structure is anisotropically etched to form gate line gaps; The second sacrificial layer is removed via the gate gap, forming a gap between adjacent dielectric layers in the sacrificial stack structure; and Conductive material is filled into the gaps through the gate line slots to form a gate conductor layer.

13. A 3D storage device, comprising: Substrate; A stacked layer structure comprising alternating stacked dielectric layers and gate conductor layers, the stacked layer structure being located on a substrate, the stacked layer structure comprising adjacent memory array regions and step regions, wherein the gate conductor layers form a step surface in the step regions; A conductive channel extends through the stacked layer structure in the stepped region; A first isolation layer is located between the conductive channel and the plurality of gate conductor layers; A first interconnect layer is located on the surface of the gate conductor layer that provides a stepped surface among the plurality of gate conductor layers; The conductive channel is electrically connected to the gate conductor layer that provides the stepped surface via the first connection layer, and the conductive channel is separated from the other gate conductor layers of the plurality of gate conductor layers by the first isolation layer.

14. The 3D storage device according to claim 13, further comprising: The conductive channel penetrates the first connecting layer and contacts the sidewall of the first connecting layer.

15. The 3D storage device according to claim 13, further comprising: The filling material of the conductive channel includes tungsten, titanium nitride, tungsten alloy, or any combination thereof.

16. The 3D storage device according to claim 13, further comprising: The conductive channel penetrates the stacked layer structure and extends to the substrate.

17. The 3D storage device according to claim 13, further comprising: The material of the gate conductor layer includes any one or a combination of polycrystalline silicon, tungsten, titanium nitride, and tungsten alloys.

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