Three-dimensional memory, fabrication methods, and storage systems

Abstract

A three-dimensional memory, a preparation method and a storage system are disclosed. The preparation method comprises: forming a stack structure comprising a plurality of stacked layers, wherein each stacked layer comprises a gate sacrificial layer; dividing the stack structure into a memory array region arranged in a first direction and a step region, wherein the step region comprises a first region and a second region arranged staggered in a second direction, and the first direction, the second direction and a stacking direction are perpendicular to each other; removing a portion of the uppermost stacked layer in the second region, and forming a second step structure in the second region and a first step structure in the first region which protrudes from the second step structure in the stacking direction; forming a gate line gap penetrating through the stack structure and arranged staggered with the first region, removing a portion of the gate sacrificial layer through the gate line gap to form a sacrificial gap, and filling a conductive material in the sacrificial gap to form a gate layer; and forming a word line contact connected with the gate layer in the first region.

Description

Technical Field

[0001] This application relates to the field of semiconductor devices, and more specifically, to three-dimensional memory, methods for fabricating three-dimensional memory, and memory systems. Background Technology

[0002] The three-dimensional memory includes a stacked structure formed by alternating gate layers and dielectric layers, wherein word line contacts located in the step region of the stacked structure enable electrical connection between the gate layer and external circuitry.

[0003] In conventional three-dimensional memory fabrication methods, in order to achieve effective electrical connection between word line contacts and the gate layer, a thickened portion protruding along the stacking direction is usually provided at the end of the gate layer so that the end of the gate layer will not break down due to the gate layer being too thin during the contact connection with the word line.

[0004] However, with the increasing integration density and stacking number of layers in 3D memory, the depth of the word line contact holes is becoming increasingly deeper, making gate layer breakdown highly susceptible during contact hole formation. Furthermore, excessive thickness also affects the process window for forming the virtual channel structure in the step region. Additionally, filling the over-etched contact holes with conductive material for word line contacts can lead to short circuits between different gate layers (i.e., word line bridging between different layers), thereby causing 3D memory failure.

[0005] Therefore, how to achieve effective electrical connection between word line contacts and gate layer without affecting the performance of three-dimensional memory structure is an urgent problem to be solved. Summary of the Invention

[0006] To address or partially address the aforementioned problems in related technologies, one aspect of this application provides a method for fabricating a three-dimensional memory. The method may include: forming a stacked structure comprising multiple stacked layers, each stacked layer including a gate sacrificial layer; dividing the stacked structure into a memory array region and a step region arranged in a first direction, wherein the step region includes a first region and a second region offset in a second direction, the first direction, the second direction, and the stacking direction being perpendicular to each other; removing a portion of the uppermost stacked layer in the second region and forming a second step structure in the second region; forming a first step structure in the first region that protrudes beyond the second step structure in the stacking direction; forming a gate line gap penetrating the stacked structure and offset from the first region; removing the gate sacrificial layer through the gate line gap to form a sacrificial gap; filling the sacrificial gap with a conductive material to form a gate layer; and forming a word line contact in the first region connected to the gate layer.

[0007] In one embodiment, the gate sacrificial layer includes a first portion located in the first region and a second portion located in the second region. Removing the gate sacrificial layer via the gate line gap to form a sacrificial gap and filling the sacrificial gap with conductive material to form a gate layer includes: removing the second portion and a portion of the first portion via the gate line gap to form the sacrificial gap; filling the sacrificial gap with conductive material to form the gate layer, such that the first step structure is formed as a first step structure, the second step structure is formed as a second step structure, and the remaining gate sacrificial layer is formed as a first dielectric layer, wherein the first step structure includes a plurality of first steps, the uppermost first step includes the first dielectric layer, and the remaining first steps include the gate layer and the first dielectric layer distributed in the first direction; the second step structure includes a plurality of second steps, each second step including the gate layer; and the height of the first step structure protruding from the second step structure in the stacking direction is equal to the thickness of the uppermost first step.

[0008] In one embodiment, the uppermost first step further includes a second dielectric layer located below the first dielectric layer; the remaining first steps also include the second dielectric layer, wherein the second dielectric layer is located below the gate layer and the first dielectric layer. Forming a word line contact connected to the gate layer in the first region includes: forming a filling dielectric layer covering the first step structure and the second step structure; forming an initial contact hole in the first region through the filling dielectric layer and exposing each first step of the first dielectric layer; removing the exposed first dielectric layer and the portion of the second dielectric layer opposite to the exposed first dielectric layer through the initial contact hole to expose the gate layer of the next first step to form a contact hole; and filling the contact hole with a conductive material to form the word line contact communicating with the gate layer.

[0009] In one embodiment, the gate line gap includes a first gate line gap, a second gate line gap, and a third gate line gap. Forming a gate line gap that penetrates the stacked structure and is offset from the first region includes: forming a first gate line gap extending along a first direction in the memory array region and the second region; forming a second gate line gap extending along the first direction in the second region; and forming the third gate line gap extending along the first direction in the memory array region.

[0010] In one embodiment, a wall structure extending along the first direction is formed in the second region; a portion of the wall structure is removed to allow at least one first grid line gap to extend through the wall structure in the first direction; and at least one first grid line gap is filled with a dielectric material to form a first reinforced grid line gap structure.

[0011] In one embodiment, a portion of the wall structure is removed to form at least one second grid line gap in the wall structure; and the at least one second grid line gap is filled with the dielectric material to form a second reinforced grid line gap structure.

[0012] In one embodiment, prior to forming the gate layer, the method further includes: forming a virtual channel structure through the stacked structure in the step region, wherein the virtual channel structure includes a first virtual channel structure, the first virtual channel structure having a strip-shaped profile in an orthographic projection in a plane perpendicular to the stacking direction.

[0013] In one embodiment, filling at least one of the first gate line gaps with a dielectric material to form a first reinforced gate line gap structure includes: filling a portion of the first gate line gap located in the wall structure before forming the gate layer to form a first virtual channel structure; and filling the remaining portion of the first gate line gap with the dielectric material after forming the gate layer to form the first reinforced gate line gap structure.

[0014] In one embodiment, the second gate line gap and the third gate line gap are staggered in the second direction, and the second gate line gap extends intermittently along the first direction.

[0015] In one embodiment, forming an initial contact hole in the first region through the filling medium layer and exposing each of the first steps of the first medium layer includes: the step of forming the initial contact hole stops at the first medium layer of the first step.

[0016] In one embodiment, the storage array region includes a first storage array region and a second storage array region. Dividing the stacked structure into a storage array region and a step region arranged in a first direction includes: in the first direction, the step region is disposed between the first storage array region and the second storage array region.

[0017] Another aspect of this application provides a three-dimensional memory, the memory comprising: a stacked structure including a first stair structure and a second stair structure offset in a second direction, wherein the first stair structure protrudes beyond the second stair structure in the stacking direction; the first stair structure includes a plurality of first steps, the uppermost first step including a first dielectric layer and a second dielectric layer located below the first dielectric layer, the remaining first steps including a gate layer and the first dielectric layer distributed in a first direction, and a second dielectric layer located below the gate layer and the first dielectric layer, word lines contacting and connecting to the gate layer of the corresponding first step, and extending through the first dielectric layer of the next higher first step in the stacking direction, wherein the first direction, the second direction and the stacking direction are perpendicular to each other.

[0018] In one embodiment, the second step structure includes a plurality of second steps, each second step including the gate layer and a second dielectric layer located below the gate layer, wherein the height of the first step structure protruding from the second step structure in the stacking direction is equal to the thickness of the uppermost first step; and the memory further includes a gate line gap structure that extends through the stack structure along the stacking direction and is offset from the first step structure.

[0019] In one embodiment, the stacking structure includes a memory array region and a step region arranged in the first direction, wherein the step region includes a first region having the first step structure and a second region having the second step structure; and the gate line gap structure includes a first gate line gap structure extending along the first direction in the memory array region and the second region.

[0020] In one embodiment, the gate line gap structure further includes: a second gate line gap structure extending intermittently in the second region along the first direction; and a third gate line gap structure extending in the memory array region along the first direction, wherein the first gate line gap structure, the second gate line gap structure, and the third gate line gap structure are staggered from each other in the second direction.

[0021] In one embodiment, the stacked structure further includes a wall structure disposed in the second region and extending along the first direction.

[0022] In one embodiment, the memory further includes: a virtual channel structure disposed in the step area and extending through the stacking structure along the stacking direction, wherein the virtual channel structure includes a first virtual channel structure, and the orthographic projection of the first virtual channel structure in a plane perpendicular to the stacking direction is a strip-shaped outline.

[0023] In one embodiment, the first gate line gap structure includes a first reinforced gate line gap structure, wherein the first reinforced gate line gap structure includes a first gate line gap and a dielectric material filling layer, wherein the first gate line gap extends along the first direction in the memory array region and the second region, the dielectric material filling layer is disposed in a portion of the first gate line gap in the memory array region; and at least one first virtual channel structure is disposed in a portion of the first gate line gap in the second region.

[0024] In one embodiment, the second grid line gap structure includes a second reinforced grid line gap structure disposed in the wall structure and extending in the wall structure along the first direction.

[0025] In another aspect, this application provides a storage system comprising: a controller; and the memory provided in any other aspect of this application, wherein the controller is coupled to the memory and is used to control the memory to store data.

[0026] According to at least one embodiment of the three-dimensional memory and its fabrication method and storage system provided in this application, the stepped region of the stacked structure is divided into a first region and a second region that are staggered, and a gate line gap extending in a first direction is formed in the second region. Because the gate line gap is staggered from the first region, during the process of removing part of the gate sacrificial layer to form the sacrificial gap using etchant in the gate line gap, the etchant cannot penetrate to the ends of the isolated first step in the second direction and the remaining first steps in the first region, wherein the second direction, the first direction, and the stacking direction of the stacked structure are perpendicular to each other. In other words, the etchant in the gate line gap can remove a second portion of the gate sacrificial layer located in the second region and a portion of the first portion of the gate sacrificial layer located in the first region, forming the sacrificial gap. Therefore, after forming the gate layer in the sacrificial gap, a portion of the gate sacrificial layer in the first stepped structure located in the first region can be retained and used as an etch stop layer in the subsequent step of forming word line contact holes, thereby dividing the step of forming word line contact holes into two steps and preventing over-etching during the formation of word line contact holes from causing word line bridging between different gate layers. Attached Figure Description

[0027] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Embodiments of this application are illustrated in the accompanying drawings by way of example rather than limitation, in which the same reference numerals indicate similar elements. Wherein: Figure 1 This is a flowchart of a method for fabricating a three-dimensional memory according to one embodiment of this application; Figures 2A to 10B, Figure 11C These are schematic diagrams illustrating the preparation method according to one embodiment of this application; Figure 11A A partial cross-sectional view of a three-dimensional memory after word line contact is formed, according to one embodiment of this application; Figure 11B It is along Figure 11A A schematic diagram of a partial cross-section taken by line S-S' in the diagram; and Figure 12 This is a schematic diagram of a storage system structure according to one embodiment of this application. Detailed Implementation

[0028] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0029] In the accompanying drawings, the size, dimensions, and shapes of the elements have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not strictly to scale. Furthermore, the order in which the processing steps are described in this application does not necessarily indicate the order in which these processes occur in actual operation, unless otherwise expressly defined or inferred from the context.

[0030] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0031] Additionally, relative terms such as “down” or “bottom” and “up” or “top” may be used herein to describe the relationship between one element and another as shown in the figures. It should be understood that, in addition to the orientations depicted in the figures, relative terms are intended to encompass different orientations of the device. In an exemplary embodiment, when the device in one of the figures is flipped, an element described as being “down” to the other element will be oriented “up” to the other element. Therefore, depending on the specific orientation of the figure, the exemplary term “down” can encompass both “down” and “up” orientations. Similarly, when the device in one of the figures is flipped, an element described as being “below” or “under” the other element will be oriented “above” the other element. Therefore, the exemplary term “below” or “under” can encompass both “up” and “down” orientations.

[0032] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0033] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added to the top surface of the substrate may be patterned or may remain unpatterned. Additionally, the substrate may comprise a wide variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0034] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer may extend over the entire lower or upper layer structure, or may have a extent smaller than that of the lower or upper layer structure. Further, a layer may be a region of a homogeneous or non-homogeneous continuous structure, wherein the non-homogeneous continuous structure has a thickness smaller than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or between any pair of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, and may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may comprise multiple layers.

[0035] As used herein, the term "three-dimensional memory" refers to a semiconductor device having vertically oriented strings of memory cell transistors (referred to herein as "memory strings") on a laterally oriented substrate, such that the memory strings extend in a direction perpendicular to the substrate. As used herein, the term "vertical" means nominally perpendicular to the lateral surface of the substrate.

[0036] Many specific details of this application, such as the structure, materials, dimensions, processing techniques, and methods of the devices, are described below to provide a clearer understanding of the application. However, as those skilled in the art will understand, this application may be implemented without adhering to these specific details.

[0037] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel.

[0038] Figure 1 This is a flowchart of a method 1000 for fabricating a three-dimensional memory according to one embodiment of this application. For example... Figure 1 As shown, this application provides a method 1000 for fabricating a three-dimensional memory, comprising: S1, forming a stacked structure comprising multiple stacked layers, wherein each stacked layer includes a gate sacrificial layer, dividing the stacked structure into a memory array region and a step region arranged in a first direction, wherein the step region includes a first region and a second region staggered in a second direction, the first direction, the second direction and the stacking direction being perpendicular to each other.

[0039] S2, remove a portion of the uppermost stacked layer in the second region and form a second step structure in the second region, and form a first step structure in the first region that protrudes from the second step structure in the stacking direction.

[0040] S3, forming a gate line gap that runs through the stacked structure and is offset from the first region, removing part of the gate sacrificial layer through the gate line gap to form a sacrificial gap, and filling the sacrificial gap with conductive material to form a gate layer.

[0041] S4, a word line contact connected to the gate layer is formed in the first region.

[0042] The following will combine Figures 2A to 11C The specific processes for each step of the above preparation method 1000 are described in detail.

[0043] Step S1

[0044] Figure 2AA top view schematic diagram of the structure formed after forming the laminated structure 200 according to one embodiment of the present application. Figure 2B It is along Figure 2A A schematic diagram of a partial cross-section taken by line N-N' in the diagram.

[0045] like Figure 2A and Figure 2B As shown, step S1 forms a stacked structure comprising multiple stacked layers, wherein each stacked layer includes a gate sacrificial layer, and the stacked structure is divided into a memory array region and a step region arranged in a first direction, wherein the step region includes a first region and a second region staggered in a second direction, and the first direction, the second direction and the stacking direction are perpendicular to each other, and may include, for example,: preparing a substrate 100; and forming a stacked structure 200 on the substrate 100.

[0046] Specifically, such as Figure 2B As shown, in one embodiment of this application, the substrate 100 can be made of any suitable semiconductor material, such as single-crystal silicon (Si), single-crystal germanium (Ge), silicon-germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or gallium arsenide and other group III-V compounds.

[0047] In one embodiment of this application, a substrate 100 for supporting a device structure thereon is formed by sequentially depositing multiple layers made of different materials through a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0048] In one embodiment of this application, the substrate 100 may be a composite substrate, such as including a substrate, a substrate semiconductor layer and a substrate barrier layer formed sequentially.

[0049] The substrate semiconductor layer can be, for example, a polycrystalline silicon layer. Furthermore, well regions formed in the substrate semiconductor layer by doping with N-type or P-type dopants via ion implantation or diffusion processes can be formed. In some embodiments of this application, the well regions can be prepared using the same dopant or different dopants; additionally, the doping concentration of the well regions can be the same or different, and this application does not limit this.

[0050] Furthermore, the substrate barrier layer may be disposed on the outermost side of the substrate 100, and may include a single layer, multiple layers, or a suitable composite layer. Alternatively, when the substrate barrier layer is a composite layer, it may include any one or more of dielectric materials, semiconductor materials, and conductive materials.

[0051] After the substrate 100 is formed, a stacked structure 200 can be formed on one side of the substrate 100.

[0052] Specifically, in one embodiment of this application, multiple thin film deposition processes may be used to form a stacked structure 200 on the surface of the substrate 100. The thin film deposition processes may include, but are not limited to, CVD, PVD, ALD or any combination thereof, and this application does not limit them.

[0053] The stacked structure 200 may include a gate sacrificial layer 210 and a second dielectric layer 220 alternately stacked along the stacking direction (z-direction). In some embodiments, the gate sacrificial layer 210 and the second dielectric layer 220 may each include a first dielectric material and a second dielectric material different from the first dielectric material. Exemplary materials for forming the gate sacrificial layer 210 and the second dielectric layer 220 may include silicon oxide and silicon nitride, respectively. The silicon oxide layer may be used as an isolation stack layer, while the silicon nitride layer may be used as a sacrificial stack layer. The sacrificial stack layer may then be etched away and replaced with a conductive layer comprising a conductive material.

[0054] The gate sacrificial layer 210 and the second dielectric layer 220, which are stacked alternately, can form a plurality of stacked layers (not shown), wherein each stacked layer may include a gate sacrificial layer 210 and a second dielectric layer 220. For example, the uppermost first stacked layer 201 in the second region 02 (which can also be understood as the stacked layer farthest from the substrate 100 in the second region 02) may include a gate sacrificial layer 210 and a second dielectric layer 220.

[0055] Additionally, the stacked structure 200 may also include a spacer layer 202 located at the bottommost point adjacent to the substrate 100. The spacer layer 202 may be formed using a thin film deposition process including but not limited to CVD, PVD, ALD, or any combination thereof. An exemplary material for forming the spacer layer 202 may be a dielectric material such as silicon oxide. Furthermore, the spacer layer 202 may be formed simultaneously with the stacked layers and may be made using the same material as the second dielectric layer 220.

[0056] As the demand for 3D memory storage continues to increase, the size of memory stacks is gradually increasing. To overcome the limitations of traditional processes, dual-stack or multi-stack techniques can be used to form a stacked structure by sequentially stacking multiple sub-stacks along the thickness direction of the stacked structure. Each sub-stack may include multiple alternately stacked insulating layers and gate sacrificial layers. The number of layers in each sub-stack may be the same or different. Since the fabrication process of the dual-stack structure described above is fully or partially applicable to the stacked structure consisting of multiple sub-stacks described herein, related or similar content will not be repeated. However, those skilled in the art will understand that subsequent fabrication processes can be performed based on the multi-stack or dual-stack structure.

[0057] like Figure 2AAs shown, the stacked structure 200 can be divided into a memory array region 12 and a step region 11 arranged in a first direction (X direction). The step region 11 includes a first region 01 and a second region 02 staggered in a second direction (Y direction), wherein the first direction, the second direction, and the stacking direction are perpendicular to each other. In other words, in a plane perpendicular to the stacking direction (which can be understood as the plane containing the X and Y directions), the stacked structure 200 may have a memory array region 12 and a step region 11, wherein the memory array region 12 is used to form a memory array; the step region 11 is used to form a step structure and to connect and conduct the gate layers in the memory array one by one by forming word line contacts, and each memory array region 12 corresponds to at least one step region 11.

[0058] Alternatively, according to some embodiments, at least one stepped area 11 may be disposed in the middle of the storage array area 12, dividing the storage array area 12 into at least two sub-storage array areas. For example, the storage array area 12 may include a first storage array area 12-1 and a second storage array area 12-2. Alternatively, according to some embodiments, at least one stepped area 11 may be disposed on one or more edges of the storage array area 12.

[0059] Step S2

[0060] Figure 3A A partial cross-sectional schematic diagram of a structure formed after removing a portion of the uppermost stacked layer 201 located in the second region 02, according to one embodiment of the present application. Figure 3B A top view schematic diagram of the etching mask layer 03 prepared according to one embodiment of this application. Figure 4 A partial three-dimensional schematic diagram of the structure formed after forming the first step structure 500-1 and the second step structure 500-2 according to one embodiment of the present application. Figure 5A A partial three-dimensional schematic diagram of the structure formed after forming the first step structure 500-1 and the second step structure 500-2 according to one embodiment of the present application. Figure 5B yes Figure 5A A magnified view of a section at point M. Figure 6A A partial cross-sectional schematic diagram of a structure formed after forming a first step structure 500-1 and a second step structure 500-2 in a stepped region 11-1 according to one embodiment of the present application. Figure 6B It is along Figure 6A A schematic diagram of a partial cross-section taken by line S-S' in the diagram.

[0061] like Figures 2B to 6BAs shown, step S2 removes a portion of the uppermost stacked layer in the second region and forms a second step structure in the second region. Forming a first step structure in the first region that protrudes from the second step structure in the stacking direction may include, for example, removing a portion of the uppermost first stacked layer 201 in the second region 02; and forming a second step structure 500-2 in the second region 02, and forming a first step structure 500-1 in the first region 01 that protrudes from the second step structure 500-2 in the stacking direction.

[0062] Specifically, such as Figure 2B and Figure 3A As shown, a portion of the first stacked layer 201 in the second region 02 can be removed by, for example, a dry etching process or a combination of dry and wet etching processes, or by performing other manufacturing processes, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing. In other words, the above-described process can be used to remove at least a portion of the first stacked layer 201 in the second region 02, which may be located in the second region 02 adjacent to the first region 01, to form a first stacked layer 201' isolated in the second direction within the first region 01.

[0063] In addition, combined Figure 3A and Figure 4 The stepped region 11 of the stacked structure 200 may include multiple sub-stepped regions 11-1, wherein each sub-stepped region 11-1 has a different height in the stacking direction. Each sub-stepped region 11-1 may form a first stepped structure 500-1 and a second stepped structure 500-2. Therefore, the above-mentioned removal of a portion of the uppermost first stacked layer 201 in the second region 02 can be understood as the different sub-stepped regions 11-1 of the stacked structure 200 having different stacking heights. Removing a portion of the uppermost first stacked layer 201 in the second region 02 of each sub-stepped region 11-1 forms a first stacked layer 201' isolated in the second direction within the first region 01 of the sub-stepped region 11-1.

[0064] like Figures 2B to 3B As shown, in one embodiment of this application, an etching mask layer 03 may be formed on the top surface of the stacked structure 200. This etching mask layer 03 may be, for example, a photoresist layer. The photoresist layer is formed using a spin coating process or the like, and the stacked structure 200 is patterned using the photoresist layer. The photoresist layer forms an opening 031 that exposes a portion of the first stacked layer 201 in the second region 02. Thus, the photoresist layer can be used as a mask, and any suitable etching process (including any one or a combination of dry etching and wet etching processes) can be used to remove a portion of the first stacked layer 201 in the second region 02, forming a first stacked layer 201' isolated in the second direction within the first region 01.

[0065] Alternatively, the etching mask layer 03 may be a hard mask, which may be a composite layer formed by at least one or any combination of silicon nitride, silicon oxide, silicon carbide and silicon oxynitride, and this application does not limit it.

[0066] like Figure 5A As shown, after forming the first stacked layer 201' isolated in the second direction, a first step structure 500-1 can be formed in the first region 01, and a second step structure 500-2 can be formed in the second region 02. Since the first region 01 includes the first stacked layer 201' isolated in the second direction, the first step structure 500-1 can protrude beyond the second step structure 500-2 in the stacking direction. As shown in 5B, the height h by which the first step structure 500-1 protrudes beyond the second step structure 500-2 in the stacking direction is equal to the thickness of the uppermost first step. In other words, the height h is equal to the thickness of the first stacked layer 201' isolated in the second direction.

[0067] Specifically, in combination Figures 3A to 6B In some embodiments of this application, the first step structure 500-1 and the second step structure 500-2 may be formed simultaneously or in stages, and this application does not limit this. By performing multiple trimming-etching cycles on the edge portions of the stacked structure 200, the stacked structure 200 can have one or more sloping edges and a top (away from substrate 100) dielectric layer pair that is shorter than the bottom (closer to substrate 100) dielectric layer pair. Any suitable etching process (including any one or a combination of dry etching and wet etching processes) can be used in the step structure formation process. Further, a filling dielectric layer 510 can also be formed to cover the step region 11. In addition, multiple chop processes, for example, can be used to form the first step structure 500-1 and the second step structure 500-2.

[0068] refer to Figure 4 and Figure 5AAlternatively, the method for forming the first step structure 500-1 and the second step structure 500-2 may include: covering the surfaces of the first region 01 and the second region 02 with a step region mask (not shown), which may protect the covered portion, such as the portion of the pre-formed wall structure in the second region 02, during the formation of the first step structure 500-1 and the second step structure 500-2. The step region mask may be made of, for example, polysilicon, a high dielectric constant dielectric, titanium nitride, or any other suitable hard mask material. An initial step region mask (not shown) may first be formed in the step region 11 by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof; then, the initial step region mask may be patterned to form openings (not shown) using photolithography, dry etching, and / or wet etching processes; after forming the openings, a process such as a reduction process may be performed on the portion of the step region 11 exposed in the openings to form the first step structure 500-1 and the second step structure 500-2. In addition, the portion of the step area protected by the mask can form a wall structure 430 located in the second region 02.

[0069] The wall structure 430 is located in the second region 02 and extends along the first direction. The wall structure 430 can increase support in the step region 11, reduce stress deformation in the step region 11, and improve the yield and reliability of the three-dimensional storage device. As described above, alternatively, the wall structure 430 can be a portion of the laminated structure 200 that is fully preserved during the process of forming the step structure through processes such as etching trimming. This wall structure 430 can be combined with the laminated structure 200 (e.g., ...). Figure 2B The number of layers and stacking order are the same as shown.

[0070] Furthermore, forming a filler dielectric layer 510 to cover the step region 11 may include forming the filler dielectric layer 510 on the surfaces of the first step structure 500-1 and the second step structure 500-2 through one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The filler dielectric layer 510 may be an oxide or silicon oxide-based material, such as TEOS-based silicon oxide (TESO-based SiO2). Alternatively, the filler dielectric layer 510 may also be a multilayer structure. In addition, the surface of the filler dielectric layer 510 may be further planarized using processes such as chemical mechanical polishing, so that the filler dielectric layer 510 can provide a substantially flat surface for the subsequently generated word line contact holes.

[0071] like Figure 6A and 6BAs shown, through the above process, a first step structure 500-1 and a second step structure 500-2 can be formed in each step region 11-1. The height of the first step structure 500-1 protruding from the second step structure 500-2 in the stacking direction is equal to the thickness of the first stacked layer 201' isolated in the second direction. In other words, the first step structure 500-1 includes a plurality of initial first steps (not shown), wherein the uppermost first initial first step is the first stacked layer 201' isolated in the second direction. The first stacked layer 201' may include a gate sacrificial layer 210' (hereinafter referred to as the first dielectric layer 210') and a second dielectric layer 220' isolated in the second direction.

[0072] Furthermore, the remaining initial first steps 501 of the first step structure 500-1 include a pair of gate sacrificial layers 210 and a second dielectric layer 220 having the same length in a first direction. The second step structure 500-2 includes a plurality of initial second steps (not shown), wherein each initial second step includes a pair of gate sacrificial layers (not shown) and a second dielectric layer (not shown) having the same length in a first direction.

[0073] Figure 7 A top view schematic diagram of the structure formed after forming the gate line gap structure 400, the virtual channel structure 600, and the word line contact 700 according to another embodiment of the preparation method of this application.

[0074] like Figure 7 As shown, before forming the first step structure 500-1 and the second step structure 500-2, the method 1000 for fabricating a three-dimensional memory according to one embodiment of this application further includes a method for forming a channel structure (not shown) and a virtual channel structure 600.

[0075] Specifically, in combination Figure 2B and Figure 7 The channel structure can be formed in the memory array region 12, and the channel structure can penetrate the stacked structure 200 and extend into the substrate 100 along the stacking direction. Forming the channel structure may include, for example, forming a channel hole (not shown) penetrating the stacked structure 200; and sequentially forming a functional layer (not shown) and a channel layer (not shown) on the inner wall of the channel hole.

[0076] The via can be formed by, for example, a dry etching process or a combination of dry and wet etching processes. In addition, other manufacturing processes can be performed, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing. The via can have a cylindrical or columnar shape that extends through the stacked structure 200 and extends into the substrate 100 along the stacking direction.

[0077] Furthermore, after forming a stacked structure using dual-stack or multi-stack technology, the stacked structure may include N sub-stacked structures, and correspondingly, the channel holes may also include N×M sub-channel holes, wherein each sub-stacked structure may include M sub-channel holes, where M≥1 and N≥2. Forming vias in a stacked structure using dual-stack or multi-stack techniques may include: forming a first sub-stacked structure on one side of a substrate and forming M vias penetrating the first sub-stacked structure and extending into the substrate; continuing to form subsequent sub-stacked structures and vias until an Nth sub-stacked structure and M vias located in the Nth sub-stacked structure are formed; then filling the corresponding vias in the N-1 sub-stacked structures other than the Nth sub-stacked structure with a via-filling sacrificial layer; and removing the via-filling sacrificial layer in the N-1 sub-stacked structures based on the M vias of the Nth sub-stacked structure, such that adjacent sub-channels in the N sub-stacked structures are at least partially aligned with each other to obtain M vias.

[0078] After the trench is formed, a functional layer and a trench layer can be formed sequentially in the trench, and a trench plug (not shown) and a trench filling medium layer (not shown) can be formed in the remaining part of the trench. The functional layer includes a barrier layer (not shown), a charge trapping layer (not shown), and a tunneling layer (not shown) sequentially disposed in the trench.

[0079] In one embodiment of this application, a functional layer and a channel layer can be formed in the channel via a thin film deposition process such as CVD, PVD, ALD, or any combination thereof.

[0080] In some embodiments, the functional layer may include an oxide-nitride-oxide (ONO) structure. However, in other embodiments, the functional layer may have a structure different from that of an ONO configuration. The channel layer is capable of transporting the required charge (electrons or holes). According to an exemplary embodiment of this application, the channel layer can be formed on the surface of the tunneling layer by a thin film deposition process such as CVD, PVD, ALD, or any combination thereof.

[0081] In some embodiments, the channel layer may include silicon, such as amorphous silicon, polycrystalline silicon, or monocrystalline silicon. The material of the channel layer includes, but is not limited to, P-type doped polycrystalline silicon or N-type doped polycrystalline silicon. Similar to the vias, the channel layer also extends through the stacked structure 200 along the stacking direction and into the substrate 100.

[0082] In some embodiments of this application, the channel structure may be formed after the first step structure 500-1 and the second step structure 500-2 are formed. In some other embodiments, the channel structure may be formed before the first step structure 500-1 and the second step structure 500-2 are formed. This application does not limit this.

[0083] Furthermore, in one embodiment of this application, a virtual channel structure 600 may be formed in the stacked structure 200, extending through the stacked structure 200 along the stacking direction and reaching the substrate 100. The virtual channel structure 600 can provide structural support for the removal of the gate sacrificial layer during the subsequent formation of the gate layer. The virtual channel structure 600 may include a first virtual channel structure 610 and a second virtual channel structure (not shown). The second virtual channel structure may include a virtual channel via (not shown) and a virtual channel filling dielectric layer (not shown) disposed in the virtual channel via. Its formation process is similar to that of the channel structure and will not be described in detail here.

[0084] like Figure 7 As shown, in one embodiment of this application, the orthographic projection of the first virtual channel structure 610 in a plane perpendicular to the stacking direction (which can be understood as the plane containing the X and Y directions) is a strip-shaped profile. Alternatively, the first virtual channel structure 610 may be disposed in the subsequently formed first gate line gap 411, and the specific formation process will be described in detail below.

[0085] Step S3

[0086] Figure 8A A partial cross-sectional schematic diagram of the structure formed after forming a first step structure 500-1' and a second step structure 500-2' in the step region 11-1 according to one embodiment of the present application. Figure 8B It is along Figure 8A A schematic diagram of a partial cross-section taken by line S-S' in the diagram.

[0087] like Figures 6A to 8B As shown, step S3, which forms a gate line gap that runs through the stacked structure and is offset from the first region, removes the gate sacrificial layer through the gate line gap to form a sacrificial gap, and fills the sacrificial gap with conductive material to form a gate layer, may include, for example, forming a gate line gap 410; and removing the gate sacrificial layer to form a sacrificial gap, and filling the sacrificial gap with conductive material to form a gate layer.

[0088] like Figure 7 As shown, the gate line gap 410 can form the gate line gap structure 400 in subsequent steps. Furthermore, the gate line gap 410 can also be used to form the gate layer 230 (e.g., Figure 8A (As shown). The gate line gap 410 can penetrate the stacked structure 200 along the stacking direction (e.g. Figure 6A (as shown), and set separately from the first area 01.

[0089] In some embodiments of this application, the gate line gap 410 may include a first gate line gap 411, a second gate line gap 412, and a third gate line gap 413. Therefore, a method for forming the gate line gap may include: forming a first gate line gap 411 extending along a first direction in the memory array region 12 and the second region 02; forming a second gate line gap 412 extending along the first direction in the second region 02; and forming a third gate line gap 413 extending along the first direction in the memory array region 12.

[0090] Specifically, in one embodiment of this application, the first gate line gap 411, the second gate line gap 412, and the third gate line gap 413 can all penetrate the stacked structure 200 along the stacking direction (e.g., ...). Figure 6A As shown), and extends to substrate 100 (as shown). Figure 6A (As shown). Alternatively, the first gate line gap 411, the second gate line gap 412, and the third gate line gap 413 can be formed by, for example, a dry etching process or a combination of dry and wet etching processes. The first gate line gap 411, the second gate line gap 412, and the third gate line gap 413 can be formed simultaneously or in stages, and this application does not limit this.

[0091] The first grid line gap 411 can allow the stacked structure 200 (such as...) Figure 6A The memory is divided into multiple memory blocks (as shown). A second gate line gap 412 is distributed in each memory block. Alternatively, the second gate line gap 412 can be configured to extend intermittently along a first direction. Because the second gate line gap 412 is discontinuously distributed, the portion of the stacked structure 200 within each memory block is not completely divided, thus helping to maintain the stability of individual memory blocks. A third gate line gap 413 can also be distributed in each memory block. Furthermore, as another option, the second gate line gap 412 and the third gate line gap 413 can be arranged staggered in a second direction. Because the portions within each memory block divided by the second gate line gap 412 and the third gate line gap 413 are staggered in the second direction, the stability of individual memory blocks in that direction can be increased, stress differences can be eliminated, and the reliability of the three-dimensional memory can be improved.

[0092] Furthermore, in one embodiment of this application, in the method 1000 for fabricating a three-dimensional memory provided in this application, at least one grid line gap 410 may be disposed in the wall structure 430. For example, a portion of the wall structure 430 may be removed so that at least one first grid line gap 411 extends through the wall structure 430 in a first direction; or, a portion of the wall structure 430 may be removed to form at least one second grid line gap 412 in the wall structure 430.

[0093] Removing part of the wall structure 430 can be achieved through, for example, dry etching or a combination of dry and wet etching processes, or other manufacturing processes, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing. At least one gate gap 410 is formed in the wall structure 430, and a reinforced gate gap structure (not shown) can be formed by subsequent filling with a dielectric material, such as a first reinforced gate gap structure 401-1 and a second reinforced gate gap structure 402-1. The reinforced gate gap structure can reduce stress deformation of the 3D memory in the first direction, further increase support in the step region, and improve the yield and reliability of the 3D memory device.

[0094] As an alternative, in forming the gate layer 230 (e.g. Figure 8A Before (as shown), a dielectric material such as silicon oxide can be used as a first virtual channel filling layer (not shown) to fill the portion of the first gate line gap 411 located in the wall structure 430, forming a first virtual channel structure 610. The orthographic projection of the first virtual channel structure 610 in a plane perpendicular to the stacking direction is a strip-shaped profile. During the formation of the gate layer 230, it is necessary to remove part of the gate sacrificial layer 210 (such as...) through the gate line gap 410. Figure 6A (As shown) to form a sacrificial gap (not shown), and fill the sacrificial gap with conductive material to form a gate layer 230. The first virtual channel fill layer is not removed during the removal of part of the gate sacrificial layer. Therefore, by filling the gate gap with the strip-shaped first virtual channel structure, the effect of stress release on the gate gap can be mitigated, and the gate gap can be prevented from twisting and deforming. In addition, the support force of the step region can be increased, thereby significantly improving the yield and reliability of the three-dimensional memory device.

[0095] After forming the gate line gap 410, a portion of the first gate line gap 411, the second gate line gap 412, and the third gate line gap 413 can be used as pathways for providing etchant. The portion of the first gate line gap 411 is the part of the first gate line gap 411 where the first virtual channel structure 610 is not provided. The stacked structure 200 (e.g., ...) is removed using processes such as wet etching. Figure 6A The gate sacrificial layer 210 (as shown) in the diagram Figure 6A (as shown), to form a sacrificial gap.

[0096] like Figure 8A and 8B As shown, after the sacrificial gap is formed, a gate layer 230 can be formed in the sacrificial gap using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. The gate layer 230 can be made of a conductive material, such as any one or a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped crystalline silicon, or silicides.

[0097] Since the gate gap 410 is offset from the first region 01, the etching fluid in the gate gap 410 cannot penetrate into the first stacked layer 201' isolated in the second direction and the ends of the plurality of other initial first steps 501 in the first region 01 during the formation of the sacrificial gap.

[0098] In other words, the etchant in the gate gap 410 can remove a second portion (not shown) of the gate sacrificial layer 210 located in the second region 02, and can remove a portion of the first portion (not shown) of the gate sacrificial layer 210 located in the first region 01, thereby forming a sacrificial gap. This portion may be a part of the first portion that has the same length as the second portion, for example, in the first direction and the same height in the stacking direction.

[0099] Specifically, in combination Figures 6A to 8B In one embodiment of this application, the gate sacrificial layer 210 may include a first portion located in the first region 01 and a second portion located in the second region 02. The second portion of the gate sacrificial layer 210 may be removed via the aforementioned gate line gap 410, and a portion of the first portion of the gate sacrificial layer 210 may be removed to form a sacrificial gap; a conductive material is filled within the sacrificial gap to form a gate layer 230, such that the first step structure 500-1 is formed as a first step structure 500-1', the second step structure 500-2 is formed as a second step structure 500-2', and the remaining gate sacrificial layer 210 is formed as a first dielectric layer 210'.

[0100] Alternatively, a portion of the first part that is removed may be a portion of the first part that has the same length in the first direction and the same height in the stacking direction as the second part.

[0101] like Figure 8A and Figure 8B As shown, the first stepped structure 500-1' includes multiple first steps (not shown), the uppermost first step 501' includes a first dielectric layer 210', and the remaining first steps 501' include a gate layer 230 and a first dielectric layer 210' distributed in a first direction. The second stepped structure 500-2' includes multiple second steps (not shown), each second step including a gate layer 230; furthermore, the height h of the first stepped structure 500-1' protruding from the second stepped structure 500-2' in the stacking direction is equal to the thickness of the uppermost first step 501'.

[0102] Alternatively, the uppermost first step may also include a second dielectric layer 220 located below the first dielectric layer 210'; the remaining first steps 501' may also include a second dielectric layer 220 located below the gate layer 230 and the first dielectric layer 210' distributed in the first direction.

[0103] In addition, combined Figures 7 to 8B Before forming the gate layer 230, the method 1000 for fabricating a three-dimensional memory according to one embodiment of this application further includes forming a barrier layer (not shown) on the inner wall of the sacrificial gap and on the inner sidewalls of the partial first gate gap 411, second gate gap 412, and third gate gap 413 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. Alternatively, the barrier layer may be a high-dielectric-constant dielectric layer. Furthermore, an adhesive layer (e.g., a titanium nitride (TiN) layer, not shown) may be formed between the second dielectric layer 220 and the gate layer 230 or between the dielectric layer and the gate layer 230 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof.

[0104] After the gate layer 230 is formed, a dielectric material layer can be filled in the first gate gap 411, the second gate gap 412, and the third gate gap 413 to form the first gate gap structure 401, the second gate gap structure 402, and the third gate gap structure 403 respectively. Specifically, thin film deposition processes such as CVD, PVD, ALD, or any combination thereof can be used to fill the first gate gap 411, the second gate gap 412, and the third gate gap 413. The dielectric material layer may include a single layer, multiple layers, or a suitable composite layer. Alternatively, when the dielectric material layer is a composite layer, it may include any one or more of dielectric materials, semiconductor materials, and conductive materials.

[0105] After the gate layer 230 is formed, the stacked structure 200 is formed into a stacked structure 200'. The stacked structure 200' includes alternately stacked gate layers 230 and second dielectric layers 220.

[0106] Step S4

[0107] Figure 9A A partial cross-sectional schematic diagram of the structure after forming the initial contact hole 710 according to a preparation method of one embodiment of this application. Figure 9B It is along Figure 9A A schematic diagram of a partial cross-section taken by line S-S' in the diagram. Figure 10A A partial cross-sectional schematic diagram of the structure after forming the contact hole 720 according to one embodiment of the preparation method of this application. Figure 10B It is along Figure 10A A schematic diagram of a partial cross-section taken by line S-S' in the diagram. Figure 11A A partial cross-sectional schematic diagram of the structure after forming the word line contact 700 according to one embodiment of the preparation method of this application. Figure 11B It is along Figure 11A A schematic diagram of a partial cross-section taken by line S-S' in the diagram. Figure 11C A partial cross-sectional schematic diagram of the structure after forming the first step structure 500-1' and the second step structure 500-2' according to one embodiment of the preparation method of this application.

[0108] like Figures 9A to 11C As shown, after forming a filling dielectric layer 510 covering the first step structure 500-1' and the second step structure 500-2', step S4, forming a word line contact connected to the gate layer in the first region, may include, for example,: forming an initial contact hole 710 in the first region 01 that penetrates the filling dielectric layer 510 and exposes the first dielectric layer 210' of each first step in the first step structure 500-1'; removing the exposed first dielectric layer 210' and the portion of the second dielectric layer 220 opposite to the exposed first dielectric layer 210' through the initial contact hole 710 to expose the gate layer 230 of the next first step, to form a contact hole 720; and filling the contact hole 720 with a conductive material to form a word line contact 700 communicating with the exposed gate layer 230.

[0109] Specifically, such as Figure 9A and Figure 9B As shown, deep hole etching processes, such as dry etching processes or a combination of dry and wet etching processes, can be used, or other manufacturing processes, such as patterning processes including photolithography, cleaning and chemical mechanical polishing, can be performed to form an initial contact hole 710 through the filling dielectric layer 510 in the first region 01, wherein the initial contact hole 710 can expose the first dielectric layer 210' of each first step in the first stepped structure 500-1'.

[0110] Alternatively, in the step of forming the initial contact hole 710 described above, the deep etching operation can be stopped at the first dielectric layer 210' of each first step in the first stepped structure 500-1'. Using the first dielectric layer of each first step in the first stepped structure 500-1' as the etching stop layer can increase the etching process window, avoid damage to the gate layer during etching, and improve the performance of the 3D memory.

[0111] Furthermore, the fabrication method for a three-dimensional memory provided in this application divides the step of forming word line contact holes into two steps. First, an initial contact hole is formed by deep hole etching to expose the first dielectric layer of the next higher step. Then, the initial contact hole is etched again to form a contact hole that exposes the gate layer corresponding to the word line contact, which can avoid word line bridging between different gate layers.

[0112] Specifically, such as Figures 9A to 10BAs shown, a dry etching process or a combination of dry and wet etching processes can be used to sequentially remove the exposed first dielectric layer 210' and the portion of the second dielectric layer 220 opposite to the exposed first dielectric layer 210' through the initial contact hole 710, until the gate layer 230 of the next first step is exposed, thereby forming the contact hole 720.

[0113] Then, as Figure 11A As shown, contact holes 720 can be filled with conductive materials using CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof (e.g., Figure 10A (As shown). The conductive material forming the word line contact 700 may include tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), or a combination of two or more of these materials. In some embodiments, when fabricating the word line contact 700, a layer of conductive material (e.g., titanium nitride TiN) may be deposited as a contact layer before depositing another conductive material.

[0114] Furthermore, openings for vias can be formed using dry etching processes or a combination of dry and wet etching processes. Some vias are configured as peripheral contacts, word line contacts 700, or each bit line contact, which electrically contacts the upper end of the corresponding memory cell in the three-dimensional memory and individually addresses the corresponding memory cell. Similar to the via formation process, openings can be created and then filled to form contacts used for interconnection with peripheral devices. These contacts are electrically connected to the aforementioned vias. After forming the interconnect contacts, peripheral circuit chips can be connected to one side of the stack-up structure 200.

[0115] This application provides a method for fabricating a three-dimensional memory that divides the process of forming word line contact holes into two steps. First, an initial contact hole is formed by deep hole etching to expose the first dielectric layer of the next higher step. Then, the initial contact hole is etched again to form a contact hole that exposes the gate layer corresponding to the word line contact, thus avoiding word line bridging between different gate layers. The word line contact formed by this method can achieve effective electrical connection with the gate layer without affecting the structural performance of the three-dimensional memory.

[0116] Combination Figures 11A to 11CAs shown, another aspect of this application also provides a three-dimensional memory 2000. The three-dimensional memory 2000 can be fabricated using any of the above-described fabrication methods. The three-dimensional memory 2000 may include a stacked structure 200' and word line contacts 700, wherein the stacked structure 200' includes a first step structure 500-1' and a second step structure 500-2' staggered in a second direction (Y direction), wherein the first step structure 500-1' protrudes beyond the second step structure 500-2' in the stacking direction (Z direction). The first step structure 500-1' includes a plurality of first steps (not shown), the uppermost first step 501' including a first dielectric layer 210' and a second dielectric layer 220 located below the first dielectric layer 210', and the remaining first steps 501' including a gate layer 230 and a first dielectric layer 210' distributed in a first direction (X direction), and a second dielectric layer 220 located below the gate layer 230 and the first dielectric layer 210'. The word line contact 700 is connected to the gate layer 230 of the corresponding first step and extends through the first dielectric layer 210' of the previous first step in the stacking direction, wherein the first direction, the second direction and the stacking direction are perpendicular to each other.

[0117] According to at least one embodiment of the three-dimensional memory provided in this application, the stepped region of the three-dimensional memory is divided into a first region and a second region that are staggered. A second stepped structure is formed in the second region, and a first stepped structure that protrudes beyond the second stepped structure in the stacking direction is formed in the first region. Each first step in the first stepped structure includes a second dielectric layer. For example, the uppermost first step includes a first dielectric layer and a second dielectric layer located below the first dielectric layer. The remaining first steps include a gate layer and a first dielectric layer distributed in a first direction, and a second dielectric layer located below the gate layer and the first dielectric layer. The word line contact connected to the gate layer of the corresponding first step can extend through the first dielectric layer of the next higher first step in the stacking direction. Therefore, the word line contact can achieve effective electrical connection with the gate layer without affecting the performance of the three-dimensional memory structure.

[0118] In one embodiment of this application, the second step structure 500-2' includes a plurality of second steps (not shown), each second step including a gate layer 230 and a second dielectric layer 220 located below the gate layer 230, wherein the height of the first step structure 500-1' protruding from the second step structure 500-2' in the stacking direction is equal to the thickness of the uppermost first step 201'.

[0119] In addition, such as Figure 7 As shown, the three-dimensional memory 2000 also includes a gate line gap structure 400, which penetrates the stacked structure 200' along the stacking direction and is offset from the first step structure 500-1'.

[0120] Specifically, refer again Figure 7 , Figures 11A to 11C In one embodiment of this application, the stacked structure 200' includes a memory array region 12 and a step region 11 arranged in a first direction, wherein the step region 11 includes a first region 01 having a first step structure 500-1' and a second region 02 having a second step structure 500-2'; and the gate line gap structure 400 includes a first gate line gap structure 401 extending along the first direction in the memory array region 12 and the second region 02.

[0121] According to at least one embodiment of the three-dimensional memory provided in this application, the stepped region of the three-dimensional memory is divided into a first region and a second region that are staggered, and a gate line gap extending in a first direction is formed in the second region. Because the gate line gap is staggered from the first region, during the process of removing part of the gate sacrificial layer to form the sacrificial gap using etchant in the gate line gap, the etchant cannot penetrate to the ends of the isolated first step in the second direction and the remaining first steps in the first region, wherein the second direction, the first direction, and the stacking direction of the stacked structure are perpendicular to each other. In other words, the etchant in the gate line gap can remove a second portion of the gate sacrificial layer located in the second region and a portion of the first portion of the gate sacrificial layer located in the first region, forming the sacrificial gap. Therefore, after forming the gate layer in the sacrificial gap, a portion of the gate sacrificial layer in the first stepped structure located in the first region (formed as a first dielectric layer) can be retained and used as an etch stop layer in the subsequent step of forming word line contact holes, thereby dividing the step of forming word line contact holes into two steps and preventing over-etching during the formation of word line contact holes from causing word line bridging between different gate layers.

[0122] In addition, the gate line gap structure 400 also includes a second gate line gap structure 402 and a third gate line gap structure 403. The second gate line gap structure 402 extends along a first direction in the second region 02, and the third gate line gap structure 403 extends along the first direction in the memory array region 12, wherein the first gate line gap structure 401, the second gate line gap structure 402 and the third gate line gap structure 403 are staggered from each other in the second direction.

[0123] The first gate line gap structure 401 divides the stacked structure 200' into multiple memory blocks. A second gate line gap structure 402 is distributed within each memory block. Alternatively, the second gate line gap structure 402 can be configured to extend intermittently along a first direction. Because the second gate line gap structure 402 is discontinuously distributed, the portion of the stacked structure 200' within each memory block is not completely divided, thus helping to maintain the stability of individual memory blocks. A third gate line gap structure 403 can also be distributed within each memory block. Furthermore, as another option, the second gate line gap structure 402 and the third gate line gap structure 403 can be arranged staggered in a second direction. Because the portions within each memory block divided by the second gate line gap structure 402 and the third gate line gap structure 403 are staggered in the second direction, the stability of individual memory blocks in that direction can be increased, stress differences can be eliminated, and the reliability of the three-dimensional memory can be improved.

[0124] Additionally, as an alternative, the stacked structure 200' also includes a wall structure 430 disposed in the second region 02 and extending along the first direction. The wall structure located in the second region and extending along the first direction can increase support in the step area, reduce stress deformation in the step area, and improve the yield and reliability of the three-dimensional storage device.

[0125] In one embodiment of this application, a virtual channel structure 600 is disposed in the step area 11 and extends through the stacking structure 200' along the stacking direction. The virtual channel structure 600 includes a first virtual channel structure 610 and a second virtual channel structure (not shown). The orthographic projection of the first virtual channel structure 610 in a plane perpendicular to the stacking direction is a strip-shaped outline.

[0126] The first virtual channel structure has a strip-shaped profile projected onto a plane perpendicular to the stacking direction. During the formation of the gate layer, a portion of the gate sacrificial layer needs to be removed through the gate line gap to form a sacrificial gap, and then filled with conductive material to form the gate layer. Since the first virtual channel filler layer is not removed during the partial removal of the gate sacrificial layer, filling the gate line gap with the strip-shaped first virtual channel structure can alleviate the impact of stress release on the gate line gap, prevent distortion of the gate line gap, and increase the support force in the step region, thereby significantly improving the yield and reliability of the 3D memory device.

[0127] Alternatively, the first gate line gap structure 401 includes a first reinforced gate line gap structure 401-1, wherein the first reinforced gate line gap structure 401-1 includes a first gate line gap 411 and a dielectric material filling layer (not shown), wherein the first gate line gap 411 extends along a first direction in the memory array region 12 and the second region 02, the dielectric material filling layer is disposed in the portion of the first gate line gap 411 in the memory array region 12, and at least one first virtual channel structure 610 is disposed in the portion of the first gate line gap 411 in the second region 02. Additionally, the second gate line gap structure 402 includes a second reinforced gate line gap structure 402-1 disposed in the wall structure 430 and extending along the first direction within the wall structure 430. The reinforced gate line gap structure can reduce stress deformation of the three-dimensional memory in the first direction, further increase support in the step region, and improve the yield and reliability of the three-dimensional memory device.

[0128] Since the content and structure described in the preparation method 1000 above can be fully or partially applied to the three-dimensional memory described here, related or similar content will not be repeated.

[0129] Figure 12 This is a schematic diagram of the structure of a storage system 30000 according to one embodiment of this application.

[0130] like Figure 12 As shown, at least one embodiment of another aspect of this application also provides a storage system 30000. The storage system 30000 may include a memory 20000 and a controller 32000. The memory 20000 may be the same as the memory described in any of the embodiments above, and will not be repeated here. The memory 20000 may be a two-dimensional memory or a three-dimensional memory; the following description uses a three-dimensional memory as an example.

[0131] Alternatively, the three-dimensional memory may include at least one of three-dimensional NAND memory and three-dimensional NOR memory.

[0132] The three-dimensional storage system 30000 may include a three-dimensional memory 20000 and a controller 32000. The three-dimensional memory 20000 may be the same as the three-dimensional memory described in any of the embodiments above, and will not be repeated here. The controller 32000 controls the three-dimensional memory 20000 via channel CH, and the three-dimensional memory 20000 can perform operations based on the control of the controller 32000 in response to requests from the host 31000. The three-dimensional memory 20000 receives commands CMD and addresses ADDR from the controller 32000 via channel CH and accesses a region selected from the memory cell array in response to that address. In other words, the three-dimensional memory 20000 can perform internal operations corresponding to commands on the region selected by the address.

[0133] In some embodiments, the three-dimensional storage system can be implemented as a Universal Flash Storage (UFS) device, a Solid State Drive (SSD), a multimedia card in the form of MMC, eMMC, RS-MMC, and Micro MMC, a Secure Digital Card in the form of SD, Mini SD, and Micro SD, a PCMCIA card type storage device, a Peripheral Component Interconnect (PCI) type storage device, a High Speed ​​PCI (PCI-E) type storage device, a Compact Flash (CF) card, a Smart Media Card, or a Memory Stick, etc. The storage system provided in this application, due to the inclusion of the three-dimensional memory provided in this application, has the same beneficial effects as the aforementioned three-dimensional memory, and will not be elaborated upon here.

[0134] Although exemplary methods and structures for fabricating three-dimensional memories have been described herein, it is understood that one or more features may be omitted, substituted, or added to the structure of the three-dimensional memory. Furthermore, the materials of the layers described are merely exemplary.

[0135] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to the technical solutions formed by the selected combination of the above-described technical features, but should also cover other technical solutions formed by any combination of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A method for fabricating a three-dimensional memory, characterized in that, The method includes: A stacked structure comprising multiple stacked layers is formed, wherein each stacked layer includes a gate sacrificial layer, and the stacked structure is divided into a memory array region and a step region arranged in a first direction, wherein the step region includes a first region and a second region staggered in a second direction, and the gate sacrificial layer includes a first portion located in the first region and a second portion located in the second region, wherein the first direction, the second direction and the stacking direction are perpendicular to each other; Remove a portion of the topmost stacked layer in the second region and form a second step structure in the second region, and form a first step structure in the first region that protrudes from the second step structure in the stacking direction; A grid line gap is formed that runs through the stacked structure and is staggered from the first region. The second portion is removed via the gate line gap, and a portion of the first portion is removed to form a sacrificial gap. A conductive material is then filled within the sacrificial gap to form a gate layer, such that the first stepped structure is formed as a first stepped structure, and the remaining gate sacrificial layer is formed as a first dielectric layer. The first stepped structure includes a plurality of first steps, the uppermost first step including the first dielectric layer, and the remaining first steps including the gate layer and the first dielectric layer distributed in the first direction. A word line contact connected to the gate layer is formed in the first region.

2. The method according to claim 1, wherein, The method further includes: By filling the sacrificial gap with the conductive material to form the gate layer, the second step structure is formed into a second step structure. Wherein, the second stepped structure includes a plurality of second steps, each second step including the gate layer; and The height by which the first step structure protrudes from the second step structure in the stacking direction is equal to the thickness of the uppermost first step.

3. The method according to claim 2, wherein, The uppermost first step further includes a second dielectric layer located below the first dielectric layer; the remaining first steps also include the second dielectric layer, wherein the second dielectric layer is located below the gate layer and the first dielectric layer, and forming a word line contact connected to the gate layer in the first region includes: A filling medium layer is formed covering the first stepped structure and the second stepped structure; An initial contact hole is formed in the first region through the filling medium layer, exposing each of the first steps; Through the initial contact hole, the exposed first dielectric layer and the portion of the second dielectric layer opposite to the exposed first dielectric layer are removed until the gate layer of the next first step is exposed to form a contact hole; and The contact hole is filled with a conductive material to form the word line contact that communicates with the gate layer.

4. The method according to claim 1, wherein the gate line gap includes a first gate line gap, a second gate line gap, and a third gate line gap, and forming a gate line gap that penetrates the stacked structure and is offset from the first region includes: Forming the first gate line gap extending along the first direction in the memory array region and the second region; Forming a second gate line gap extending in the second region along the first direction; as well as The third gate line gap is formed, extending along the first direction in the memory array region.

5. The method according to claim 4, wherein, The method further includes: A wall structure extending along the first direction is formed in the second region; Remove a portion of the wall structure so that at least one of the first grid line gaps extends through the wall structure in the first direction; and At least one of the first gate line gaps is filled with a dielectric material to form a first reinforced gate line gap structure.

6. The method according to claim 5, wherein, The method further includes: Remove a portion of the wall structure to form at least one second grid line gap in the wall structure; and The dielectric material is used to fill at least one of the second gate line gaps to form a second reinforced gate line gap structure.

7. The method according to claim 5, wherein, Before forming the gate layer, the method further includes: A virtual channel structure is formed in the stepped area, penetrating the stacked structure. The virtual channel structure includes a first virtual channel structure, the orthographic projection of which in a plane perpendicular to the stacking direction is a strip-shaped profile.

8. The method according to claim 7, wherein, Filling at least one of the first gate line gaps with a dielectric material to form a first reinforced gate line gap structure includes: Before forming the gate layer, the portion of the first gate line gap located in the wall structure is filled to form the first virtual channel structure; and After the gate layer is formed, the dielectric material is filled in the remaining portion of the first gate gap to form the first reinforced gate gap structure.

9. The method according to claim 4, wherein, The second gate line gap and the third gate line gap are staggered in the second direction, and the second gate line gap extends intermittently along the first direction.

10. The method according to claim 3, wherein, The initial contact hole formed in the first region through the filling medium layer and exposing each of the first steps includes: The step of forming the initial contact hole stops at the first dielectric layer of the first step.

11. The method according to any one of claims 1 to 10, wherein, The storage array region includes a first storage array region and a second storage array region. Dividing the stacked structure into a storage array region and a stepped region arranged in a first direction includes: In the first direction, the stepped area is disposed between the first storage array area and the second storage array area.

12. A three-dimensional memory, characterized in that, The memory includes: The stacking structure includes a first step structure and a second step structure that are offset in a second direction, wherein the first step structure protrudes from the second step structure in the stacking direction. The first stepped structure includes a plurality of first steps. The uppermost first step includes a first dielectric layer and a second dielectric layer located below the first dielectric layer. The remaining first steps include a gate layer and the first dielectric layer distributed in a first direction, and a second dielectric layer located below the gate layer and the first dielectric layer. The word line contacts the gate layer of the corresponding first step and extends through the first dielectric layer of the previous first step in the stacking direction, wherein the first direction, the second direction and the stacking direction are perpendicular to each other.

13. The memory according to claim 12, wherein, The second step structure includes a plurality of second steps, each second step including the gate layer and a second dielectric layer located below the gate layer, wherein the height by which the first step structure protrudes from the second step structure in the stacking direction is equal to the thickness of the uppermost first step; and The memory also includes a gate line gap structure that extends through the stacking structure along the stacking direction and is offset from the first step structure.

14. The memory according to claim 13, wherein, The stacked structure includes a storage array region and a stepped region arranged in the first direction, wherein the stepped region includes a first region forming the first stepped structure and a second region forming the second stepped structure; and The gate line gap structure includes a first gate line gap structure extending along the first direction in the memory array region and the second region.

15. The memory according to claim 14, wherein, The gate line gap structure further includes: A second gate line gap structure extends intermittently along the first direction in the second region; and A third gate line gap structure extends along the first direction in the memory array region. The first gate line gap structure, the second gate line gap structure, and the third gate line gap structure are staggered from each other in the second direction.

16. The memory according to claim 15, wherein, The stacked structure also includes a wall structure disposed in the second region and extending along the first direction.

17. The memory according to claim 14, wherein, The memory also includes: A virtual channel structure is disposed in the stepped area and extends through the stacking structure along the stacking direction. The virtual channel structure includes a first virtual channel structure, the orthographic projection of which in a plane perpendicular to the stacking direction is a strip-shaped profile.

18. The memory according to claim 17, wherein, The first gate line gap structure includes a first reinforced gate line gap structure. The first reinforced gate line gap structure includes a first gate line gap and a dielectric material filling layer, wherein the first gate line gap extends along the first direction in the memory array region and the second region, and the dielectric material filling layer is disposed in a portion of the first gate line gap in the memory array region; and At least one of the first virtual channel structures is disposed in a portion of the first gate line gap in the second region.

19. The memory according to claim 16, wherein, The second grid line gap structure includes a second reinforced grid line gap structure disposed in the wall structure and extending in the wall structure along the first direction.

20. A storage system, characterized in that, include: Controller; as well as The memory as described in any one of claims 12 to 19, wherein the controller is coupled to the memory and is used to control the memory to store data.

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