Semiconductor component and method for manufacturing the same, storage system

Abstract

The embodiments of the present application provide a semiconductor component, a manufacturing method thereof and a storage system. The semiconductor component comprises a plurality of memory string channel structures extending into a substrate, each of the memory string channel structures having a functional layer and a channel layer. The manufacturing method comprises: removing part of the substrate and part of the functional layer to expose part of the channel layer; forming a semiconductor layer covering the exposed part of the channel layer, the semiconductor layer having a surface topography adapted to the exposed part of the channel layer; and forming a source contact connected to the semiconductor layer. The semiconductor layer formed in the above scheme has a surface topography adapted to the exposed part of the channel layer, so that the purposes of covering the channel layer and bearing laser damage in an activation process can be achieved without the semiconductor layer necessarily being thick, the difference in longitudinal extension depth of the memory string channel structures in a memory array region can be taken into account more easily, the manufacturing process of the semiconductor component is simplified, and the purpose of increasing the process window of the memory string channel structures is achieved.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing, and more specifically, to semiconductor components and methods of manufacturing thereof, and memory systems. Background Technology

[0002] As the number of stacked layers in 3D NAND increases, the fabrication challenges for 3D NAND array devices become increasingly significant. In one method for manufacturing a 3D NAND structure, multiple array devices comprising multiple NAND memory strings are first formed on a first substrate. Then, an array interconnect layer is formed on the multiple NAND memory strings. Simultaneously, a second substrate is formed, and peripheral devices are formed on the second substrate. A peripheral interconnect layer is then formed on the peripheral devices. Next, the array devices are inverted, and the array interconnect layer and the peripheral interconnect layer are aligned and bonded. Then, the first substrate is removed, and a source layer is formed on the array devices. An N-well pick-up contact is formed on the source layer to bring out the source end. The NPU is then connected to a top metal layer (connected to external circuitry) to form a diode structure, thereby electrically connecting the array devices to external circuitry for signal output.

[0003] However, when the depths of the channel structures in the multiple memory strings formed on the first substrate are uneven, the process of forming the source layer on the array device is difficult and the process window is small. Summary of the Invention

[0004] This application provides semiconductor components, manufacturing methods thereof, and memory systems that can at least partially solve the aforementioned problems existing in the related art.

[0005] One embodiment of this application provides a method for manufacturing a semiconductor device, the semiconductor device including a memory string channel structure having a functional layer and a channel layer extending into a substrate. The manufacturing method includes: removing a portion of the substrate and a portion of the functional layer to expose a portion of the channel layer; and forming a semiconductor layer covering the exposed portion of the channel layer, the semiconductor layer having a surface morphology adapted to the exposed channel layer.

[0006] In some embodiments, the semiconductor component has a memory array region and a step region, a plurality of memory string channel structures are located in the memory array region, and at least two memory string channel structures extend into the substrate by different distances. The removal of a portion of the substrate and a portion of the functional layer to expose a portion of the channel layer includes: removing the substrate located in the memory array region to expose a portion of the functional layer of the plurality of memory string channel structures; and removing a portion of the functional layer of the exposed plurality of memory string channel structures to expose a portion of the channel layer of the plurality of memory string channel structures.

[0007] In some embodiments, forming a semiconductor layer covering the exposed portion of the channel layer includes: forming a semiconductor layer on the surface of a portion of the channel layer of the exposed plurality of memory string channel structures, wherein the surface morphology of the semiconductor is conformal to the surface morphology of the channel layer of at least two memory string channel structures.

[0008] In some embodiments, forming a semiconductor layer covering the exposed portion of the channel layer includes: forming an initial semiconductor layer in the memory array region and the step region, the initial semiconductor layer having a surface morphology conformal to the exposed surfaces of the memory array region and the step region; and removing a portion of the initial semiconductor layer located in the step region while retaining the portion of the initial semiconductor layer located in the memory array region. The retained portion of the initial semiconductor layer constitutes the semiconductor layer.

[0009] In some implementations, before removing the portion of the initial semiconductor layer located in the step region and retaining the portion of the initial semiconductor layer located in the memory array region, the method further includes: thinning the initial semiconductor layer.

[0010] In some implementations, thinning the initial semiconductor layer includes thinning the initial semiconductor layer by an etching process.

[0011] In some embodiments, the thickness of the semiconductor layer ranges from 100 Å to 400 Å.

[0012] In some embodiments, forming an initial semiconductor layer in the memory array region and the step region includes forming the initial semiconductor layer in the memory array region and the step region by means of a furnace tube growth process.

[0013] In some embodiments, the manufacturing method further includes forming a source contact that is connected to the semiconductor layer.

[0014] In some embodiments, forming a source contact portion that is partially connected to the semiconductor layer in the memory array region includes: a doped semiconductor layer; forming an insulating dielectric layer in the memory array region and the step region, the insulating dielectric layer at least covering the semiconductor layer; and forming a source contact portion that penetrates the insulating dielectric layer and is connected to the semiconductor layer.

[0015] In some implementations, the semiconductor layer is a polycrystalline silicon layer.

[0016] Another embodiment of this application provides a semiconductor component, including a stacked structure, a memory string channel structure, and a doped semiconductor layer.

[0017] The stacked structure includes alternating gate conductive layers and insulating layers; a memory string channel structure runs through the stacked structure, and a portion of the channel layer of the memory string channel structure extends to the outside of one side of the stacked structure; a doped semiconductor layer is located on one side of the stacked structure and at least covers and is in direct contact with a portion of the channel layer, and the doped semiconductor layer has a surface morphology adapted to the portion of the channel layer.

[0018] In some embodiments, multiple memory string channel structures are provided, and the channel layers of at least two memory string channel structures extend to different heights on one side of the stacked structure, and the surface morphology of the doped semiconductor layer conforms to the surface morphology of the channel layers of the at least two memory string channel structures.

[0019] In some embodiments, the thickness of the doped semiconductor layer ranges from 100 Å to 400 Å.

[0020] In some implementations, the doped semiconductor layer is formed using a furnace tube growth process.

[0021] In some implementations, the semiconductor component further includes a source contact that is electrically connected to the doped semiconductor layer.

[0022] In some embodiments, the semiconductor component has a memory array region and a step region, with a memory channel structure, a doped semiconductor layer, and a source contact located in the memory array region. The semiconductor component also includes a virtual channel structure and a buffer layer. The virtual channel structure extends through the stacked structure, with a portion of the virtual channel structure extending to the outside of one side of the stacked structure; and the buffer layer is located outside one side of the stacked structure and at least covers the portion of the virtual channel structure extending to the outside of one side of the stacked structure.

[0023] In some embodiments, the semiconductor component further includes a channel contact and a peripheral contact for peripheral circuit connections. The channel contact is located in the stepped region, and the peripheral contact extends through a buffer layer in the stepped region and is connected to the channel contact.

[0024] In some implementations, the doped semiconductor layer is a doped polysilicon layer.

[0025] Another embodiment of this application provides a storage system including a three-dimensional memory and a controller electrically connected to the three-dimensional memory for controlling the three-dimensional memory. The three-dimensional memory includes at least the semiconductor components described above.

[0026] According to one aspect of this application, a method for manufacturing a semiconductor component involves removing the functional layer of a memory string channel structure to expose the channel layer, and then forming a semiconductor layer covering the exposed channel layer. This semiconductor layer has a surface morphology adapted to the exposed channel layer. In other words, the technical solution of this application achieves the goals of covering the channel layer and being fully activated while withstanding laser damage during activation, without requiring a very thick semiconductor layer. Therefore, it is relatively easy to accommodate the differences in the longitudinal extension depth (CH gouging) of the memory string channel structure in the memory array region, thereby simplifying the semiconductor component manufacturing process and increasing the process window of the memory string channel structure. Furthermore, the fully activated semiconductor layer exhibits excellent conductivity, which is beneficial for improving the performance of the semiconductor component. Attached Figure Description

[0027] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Wherein:

[0028] Figures 1A to 1C It is a process diagram of a semiconductor component manufacturing method according to related technologies;

[0029] Figure 2 This is a flowchart illustrating a method for manufacturing a semiconductor component according to an exemplary embodiment of this application;

[0030] Figures 3A to 3H It is based on Figure 2 A schematic diagram of the manufacturing process in the middle; and

[0031] Figure 4 This is a schematic diagram of the structure of a semiconductor component according to an exemplary embodiment of this application; and

[0032] Figure 5A and Figure 5B This is a schematic diagram of the structure of a storage system according to an exemplary embodiment of this application. Detailed Implementation

[0033] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0034] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence.

[0035] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0036] Furthermore, in this text, when describing a part as being "on" another part, such as "on," "above," and "above," the meaning should be interpreted in the broadest possible sense, such that "on" not only means "directly on" something, but also includes the meaning of "on" something with intermediate features or layers in between. Moreover, "above" or "above" does not absolutely mean being above something with respect to the direction of gravity, nor does it only mean "on" something or "above" something, but can also include the meaning of "on" something or "above" something without intermediate features or layers in between (i.e., directly on) something.

[0037] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0038] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0039] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0040] Furthermore, when the term "connection" or "linkage" is used in this application, it may indicate direct or indirect contact between the corresponding components, unless otherwise expressly defined or deduced from the context.

[0041] Figures 1A to 1C A schematic diagram of a manufacturing method for a semiconductor component according to related technologies is shown. It is understood that, in Figures 1A to 1C In the image, only a partial structure of the semiconductor component is shown.

[0042] In a method for manufacturing a semiconductor component in the related art, a stack layer 1 comprising a plurality of vertically alternating gate layers 11 and interlayer insulating layers 12 is first formed on a first substrate. The stack layer 1 includes a memory array region 13 and a step region 14 located outside the memory array region. The memory array region 13 is the core region of the stack layer 1 and includes a memory string channel structure 15 that runs vertically through the memory array region 13. The memory string channel structure 15 includes a semiconductor channel layer 151, a memory dielectric layer 152 disposed around the periphery of the semiconductor channel layer 151, and an isolation layer 153 surrounded by the semiconductor channel layer 151.

[0043] Then, a device layer (not shown) is formed on the second substrate. The device layer can be a complementary metal-oxide-semiconductor (CMOS), static random access memory (SRAM), dynamic random access memory (DRAM), field-programmable gate array (FPGA), central processing unit (CPU), Xpoint chip, or other devices.

[0044] Next, the first substrate and stack layer 1 are inverted and bonded to the device layer.

[0045] Next, the first substrate is removed to expose the storage dielectric layer 152 on top of the storage string channel structure 15. The exposed storage dielectric layer 152 is then removed to expose the semiconductor channel layer 151 on top of the storage string channel structure 15 on top of the stack layer 1. Then, a semiconductor layer 3 is formed on top of the stack layer 1, and the semiconductor layer 3 is connected to the semiconductor channel layer 151 to achieve an electrical connection between the storage string channel structure 15 and the semiconductor layer 3.

[0046] However, when the depths of the multiple memory string channel structures 15 formed on the first substrate are uneven, in order to accommodate the depth differences of the multiple memory string channel structures 15 and the thickness margin of the semiconductor layer 3 in the subsequent chemical mechanical polishing process, it is necessary to first form a very thick semiconductor layer 3 on top of the stack layer 1, for example, with a thickness of approximately 4000 Å, and then use a chemical mechanical polishing process to thin the semiconductor layer 3 of the step region 14. To prevent damage to the semiconductor layer 3 of the memory array region 13 during the chemical mechanical polishing process, an insulating layer 4 is also first formed between the memory array region 13 and the step region 14, such as... Figure 1A As shown. The insulating layer 4 can be made of materials such as oxides, and the thickness of the insulating layer 4 is approximately 5000 to 7000 Å.

[0047] Since the semiconductor layer 3 of the memory array region 13 is covered by the insulating layer 4, the semiconductor layer 3 of the memory array region 13 will not be damaged during the chemical mechanical polishing process to planarize the semiconductor layer 3 of the step region 14 (see reference). Figure 1B and Figure 1C (As shown). In addition, the insulating layer 4 retained on the semiconductor layer 3 of the memory array region 13 can also serve as an isolation layer when forming conductive contacts in subsequent processes.

[0048] The aforementioned approach results in higher costs for semiconductor components. Furthermore, controlling the thickness of the semiconductor layer 3 using chemical mechanical polishing (CMP) is complex, difficult, and has a small, unsustainable process window. This is because if the semiconductor layer 3 is too thick, it may fail to fully activate the subsequent laser activation process; conversely, if it is too thin, it may damage the memory string channel structure 15 during laser activation. Additionally, maintaining consistent extension depths across multiple memory string channel structures 15 places high demands on the fabrication process, further limiting the process window and making it smaller.

[0049] Based on this, an exemplary embodiment of this application provides a method for manufacturing a semiconductor component.

[0050] Figure 2 A flowchart of a method 1000 for manufacturing a semiconductor component 100 according to an exemplary embodiment of this application is shown. Figures 3A to 3H It is based on Figure 2 A schematic diagram of the manufacturing process of method 1000.

[0051] like Figure 3A As shown, the semiconductor component 100 includes a substrate 110 and a stacked layer 120 formed on the substrate 110. The stacked layer 120 includes a plurality of vertically alternating gate conductive layers 121 and dielectric layers 122, as shown in Figure 120. Figure 3A The diagram shows the stack layer 120 after it has been inverted. A peripheral device layer 190 is bonded to the bottom of the stack layer 120.

[0052] In some embodiments, exemplary materials used to form the gate conductive layer 121 and the dielectric layer 122 may include tungsten and silicon oxide, respectively. Optionally, the periphery of the gate conductive layer 121 may also be provided with materials for conductor filling, bonding, or blocking.

[0053] Refer again Figure 3A The stack layer 120 has a memory array region 130 and a step region 150. The stack layer 120 includes multiple memory string channel structures 140 located in the memory array region 130 and extending longitudinally through the stack layer 120. The memory string channel structures 140 may have a general outline shape, such as a cylinder, frustum, or prism. The memory string channel structure 140 may include, for example, a functional layer 142 and a channel layer 141 arranged sequentially from the outside in. Optionally, the functional layer 142 may include, for example, a charge blocking layer, a charge trapping layer, and a tunneling layer arranged sequentially from the outside in. The materials of the charge blocking layer, charge trapping layer, and tunneling layer may sequentially include, for example, silicon oxide, silicon nitride, and silicon oxide, thereby forming a functional layer 142 with an ONO structure. The material of the channel layer 141 may include, for example, a semiconductor material such as silicon (e.g., amorphous silicon, polycrystalline silicon, monocrystalline silicon). The memory string channel structure 140 also includes an isolation layer 143 surrounded by the channel layer 141. Stack layer 120 includes a virtual channel structure 160 located in step area 150 and extending longitudinally through stack layer 120.

[0054] like Figure 2 As shown, the manufacturing method 1000 of this embodiment includes the following steps:

[0055] S110, remove part of the substrate 110 and part of the functional layer 142 to expose part of the channel layer 141;

[0056] S120, forming a semiconductor layer 170 covering the exposed channel layer 141, the semiconductor layer 170 having a surface morphology adapted to the exposed channel layer 141; and

[0057] S130, forming a source contact portion 180 connected to the semiconductor layer 170.

[0058] According to a method 1000 for manufacturing a semiconductor component 100 according to at least one embodiment of this application, after removing a portion of the substrate 110 and a portion of the functional layer 142 to expose a portion of the channel layer 141, a semiconductor layer covering the exposed channel layer is formed, and the semiconductor layer has a surface morphology adapted to the exposed channel layer. In other words, in the technical solution of this application, the purpose of covering the channel layer and resisting laser damage during activation can be achieved without the semiconductor layer being very thick. Therefore, the differences in the longitudinal extension depth (CH gouging) of the memory string channel structure in the memory array region can be more easily taken into account, thereby simplifying the manufacturing process of the semiconductor component and increasing the process window of the memory string channel structure. Moreover, the above solution can also reduce the cost of the semiconductor component and the overall thickness of the semiconductor component.

[0059] It should be understood that the steps shown in preparation method 1000 are not exclusive, and other steps may be performed before, after, or between any of the steps shown. Furthermore, some of the steps may be performed simultaneously or in a manner different from [the steps described]. Figure 2 The execution order is shown below. (Followed by...) Figures 3A to 3H The steps S110 to S130 described above are further described.

[0060] S110

[0061] In some implementations, such as Figure 3A As shown, the semiconductor component 100 also includes a stop layer 115 formed on one side of the substrate 110.

[0062] Therefore, in step S110, a portion of the substrate 110 of the semiconductor component 100 can be removed first to expose the functional layer 142 of the memory string channel structure 140, and then the exposed portion of the functional layer 142 can be removed to expose a portion of the channel layer 141 of the memory string channel structure 140 on top of the stack layer 120.

[0063] In some embodiments, a portion of the substrate 110 of the semiconductor component 100 may be removed using chemical mechanical planarization (CMP) and etching processes (e.g., wet or dry etching processes).

[0064] In some embodiments, a plurality of memory string channel structures 140 extend longitudinally through the stop layer 115 and into the substrate 110, and at least two of the memory string channel structures 140 extend into the substrate 110 by different distances. A method of removing a portion of the substrate 110 includes removing a portion of the substrate 110 located in the memory array region 130 up to the stop layer 115 to expose the top of the functional layer 142 of the memory string channel structure 140 with the shortest extension into the substrate 110, as well as the top and partial sidewalls of the functional layers 142 of the remaining memory string channel structures 140.

[0065] For example, such as Figure 3A As shown, the memory array region 130 includes a first memory array region 131 and a second memory array region 132. The distance that the memory string channel structure 140-2 located in the second memory array region 132 extends to the substrate 110 is greater than the distance that the memory string channel structure 140-1 located in the first memory array region 131 extends to the substrate 110. In other words, the longitudinal depth of the memory string channel structure 140-2 located in the second memory array region 132 is greater than the longitudinal depth of the memory string channel structure 140-1 located in the first memory array region 131. It can be understood that the longitudinal depth here refers to the dimension of the memory string channel structure in a direction approximately perpendicular to the substrate 110. It should be noted that the first memory array region 131 and the second memory array region 132 described above are only illustrative of the uneven distribution of the longitudinal extension depth (CH gouging) of multiple memory channel structures. It should be understood that the different longitudinal extension depths of the memory channel structures are not strictly divided according to regions.

[0066] In some embodiments, the substrate 110 can be removed directly using a wet etching process to expose the top of the functional layer 142-1 of the memory string channel structure 140-1 and the top and part of the sidewalls of the functional layer 142-2 of the memory string channel structure 140-2.

[0067] In some embodiments, substrate 110 includes a base substrate 111 and a buffer layer 113. The base substrate 111 may be, for example, a group III-V compound such as single-crystal silicon (Si), single-crystal germanium (Ge), silicon-germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or gallium arsenide, with a thickness generally between 2000 Å and 3000 Å. The buffer layer 113 may be, for example, a semiconductor material such as polycrystalline silicon, with a thickness generally between 2000 Å and 4000 Å. Optionally, substrate 110 further includes a protective layer 112 located between the base substrate 111 and the buffer layer 113. The protective layer 112 may be, for example, a semiconductor material such as oxide, with a thickness generally between 400 Å and 800 Å. The stop layer 115 may be a semiconductor material such as polycrystalline silicon, with a thickness generally between 100 Å and 400 Å.

[0068] The method of removing substrate 110 includes: removing base substrate 111 or removing base substrate 111 and protective layer 112 up to buffer layer 113; and removing buffer layer 113 located in memory array region 130 up to stop layer 115 to expose the top of functional layer 142 (e.g., functional layer 142-1 of memory string channel structure 140 with the smallest distance extending into buffer layer 113) and the top and sidewalls of functional layer 142 of the remaining memory string channel structures 140 (e.g., functional layer 142-2 of memory string channel structure 140-2).

[0069] It should be noted that the memory string channel structure 140 located in the memory array region 130 and the virtual channel structure 160 located in the step region 150 both extend at least into the buffer layer 113. Therefore, when the buffer layer 113 in the memory array region 130 is removed up to the stop layer 115, the buffer layer 113 in the step region is retained, thereby forming a step-like structure in the transition region between the memory array region 130 and the step region 150, such as... Figure 3B As shown.

[0070] Optionally, when using a wet etching process to remove the buffer layer 113 located in the storage array region 130, a mask can be used to cover the buffer layer 113 located in the step region 150, thereby allowing the buffer layer 113 located in the step region 150 to be retained.

[0071] In some embodiments, an insulating layer 114 is disposed between the buffer layer 113 and the stop layer 115. The insulating layer 114 may be a semiconductor material such as an oxide, and its thickness is approximately between 200 Å and 500 Å. Removing a portion of the functional layer 142 includes removing the portion of the insulating layer 114 located in the memory array region 130 and the portion of the functional layer 142 of the memory string channel structure 140 located on the side of the stop layer 115 near the buffer layer 113, to expose the top of the channel layer 141 of the memory string channel structure 140 with the smallest distance extending into the buffer layer 113 (e.g., channel layer 141-1 of memory string channel structure 140-1) and the top and sidewalls of the channel layers 141 of the remaining memory string channel structures 140 (e.g., channel layer 141-2 of memory string channel structure 140-2).

[0072] For example, after exposing the functional layer 142 of the memory string channel structure 140, an etching process can be used to remove the insulating layer 114 above the stop layer 115 of the memory array region 130 and the functional layer 142 of the memory string channel structure 140 so that a portion of the channel layer 141 of the memory string channel structure 140 is exposed on top of the stack layer 120. Optionally, a portion of the channel layer 141 can also be removed to expose the remaining portion of the channel layer 141.

[0073] It should be noted that the memory array region 130 may also include regions whose longitudinal depth differs from that of memory string channel structures 140-2 and 140-1, or the memory array region 130 may also include regions with a similar gate wire slot structure 133 (see reference). Figure 3B This application does not limit the area of ​​the storage array region 130. This application only uses the example of the storage array region 130 including the first storage array region 131 and the second storage array region 132 for illustration.

[0074] like Figure 3B As shown, when the base substrate 111, protective layer 112, buffer layer 113, insulating layer 114, and functional layer 142-1 of the memory string channel structure 140-1 located in the memory array region 130 are removed to expose the top surface of the channel layer 141-1 on top of the memory string channel structure 140-1, the channel layer 141-2 on the top of the memory string channel structure 140-2 and part of the sidewalls are exposed.

[0075] At this point, as Figure 3B As shown, the exposed surface of the step region 150 is a buffer layer 113, and the exposed surface of the storage array region 130 is a stop layer 115, a functional layer 142-1 and a channel layer 141-1 of the storage string channel structure 140-1, and a functional layer 142-2 and a channel layer 141-2 of the storage string channel structure 140-2.

[0076] S120

[0077] In step S120, a semiconductor layer 170 is formed covering the exposed portion of the channel layer 141, the semiconductor layer 170 having a surface morphology adapted to the exposed channel layer 141.

[0078] It is understandable that the semiconductor layer 170 formed at this time is an undoped semiconductor layer.

[0079] In some embodiments, the semiconductor layer 170 located in the memory array region 130, situated on top of the channel layer 141 of the memory string channel structure 140, has a thickness ranging from approximately 100 Å to 400 Å. Optionally, the thickness of the semiconductor layer 170 ranges from approximately 200 Å to 300 Å. Still alternatively, the thickness of the semiconductor layer 170 is approximately 300 Å.

[0080] In some embodiments, a conformal thin-film deposition process may be used to form the semiconductor layer 170. The thin-film deposition process may include, but is not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof, and this application does not limit it.

[0081] In some embodiments, the material of the semiconductor layer 170 may be, for example, a semiconductor material such as polycrystalline silicon.

[0082] In the above scheme, it has been verified that the thickness range is sufficient to withstand laser damage in subsequent processes. It can achieve the goal of using semiconductor layer 170 to surround part of the exposed channel layer 141 while controlling the overall thickness of semiconductor layer 170 as much as possible, thereby reducing the overall thickness of semiconductor components.

[0083] In some embodiments, the method of forming the semiconductor layer 170 includes the following steps:

[0084] S121. An initial semiconductor layer 170' is formed in the memory array region 130 and the step region 150. The initial semiconductor layer 170' has a surface morphology adapted to the exposed surfaces of the memory array region 130 and the step region 150, such as... Figure 3C As shown;

[0085] S122, Thin the initial semiconductor layer by 170', as follows Figure 3D As shown, and

[0086] S123, Remove the portion of the initial semiconductor layer 170' located in the step region 150 and retain the portion of the initial semiconductor layer 170' located in the memory array region 130, as follows: Figure 3E As shown. The portion of the initial semiconductor layer 170' that is retained constitutes the aforementioned semiconductor layer 170.

[0087] It should be noted that, due to the longitudinal differences in the memory string channel structures 140 of the memory array region 130, the initial semiconductor layer 170' formed in step S121 includes a first initial portion 171' covering the buffer layer 113 located in the step region 150, a second initial portion 172' covering the first memory array region 131 and the second memory array region 132 respectively, and a third initial portion 173'. In some embodiments, the initial semiconductor layer 170' can be formed using a furnace tube growth process. It should be noted here that when the initial semiconductor layer 170' is formed using a furnace tube growth process, if the gap between two adjacent memory string channel structures 140 is large, then the thickness of the grown semiconductor layer 170 should be approximately equal, whether it is the top surface of the channel layer 141 or the top surface of the stop layer 115. However, if the gap between two adjacent memory string channel structures 140 is small, it is possible that the thickness of the initial semiconductor layer 170' grown on the stop layer 115 between adjacent memory string channel structures 140 is greater than the thickness of the initial semiconductor layer 170' grown on the top surface of the channel layer 141. Therefore, the accompanying drawings of this application are merely schematic structural diagrams and should not be used to limit the scope of protection of this application.

[0088] Optionally, in step S122, the initial semiconductor layer 170' can be thinned using a uniform thickness reduction method. Therefore, the thinned initial semiconductor layer 170' also has a surface morphology adapted to the exposed surfaces of the memory array region 130 and the step region 150, such as... Figure 3D As shown. The thinned initial semiconductor layer 170' includes a first portion 171 covering a buffer layer 113 located in the step region 150, a second portion 172 covering a first memory array region 131 and a second memory array region 132, and a third portion 173. The first portion 171 has a first thickness H1, which ranges approximately from 100 Å to 400 Å; the second portion 172 has a second thickness H2, which ranges approximately from 100 Å to 400 Å; and in the third portion 173, the thickness of the retained initial semiconductor layer 170' at the top of the channel layer 141-2 of the memory string channel structure 140-2 is a third thickness H3, which ranges approximately from 100 Å to 400 Å. It can be seen that, due to the differences in the longitudinal direction of the memory string channel structure 140 of the memory array region 130 and the small gap between two adjacent memory string channel structures 140, the thickness of a local location of the third portion 173 of the initial semiconductor layer 170' (e.g., the initial semiconductor layer 170' located above the stop layer 115) may be greater than the first thickness H1 of the first portion 171 and the second thickness H2 of the second portion 172.

[0089] In some embodiments, the thickness of the initial semiconductor layer 170' formed in step S121 is approximately 2 to 4 times the thickness of the initial semiconductor layer 170' after thinning in step S122. That is, the first initial thickness H1' of the first initial portion 171' is approximately 2 to 4 times the first thickness H1, and H1' ranges approximately between 200 Å and 1200 Å; the second initial thickness H2' of the second initial portion 172' is approximately 2 to 4 times the second thickness H2, and H2' ranges approximately between 200 Å and 1200 Å; in the third initial portion 173', the third initial thickness H3' of the initial semiconductor layer 170' located at the top of the channel layer 141-2 of the memory string channel structure 140-2 is approximately 2 to 4 times the third thickness H3, and H3' ranges approximately between 200 Å and 1200 Å.

[0090] It should be noted that when the initial semiconductor layer 170' is formed using the furnace tube growth process, based on the characteristics of the initial semiconductor layer 170' grown by the furnace tube, the third thickness of the third initial portion 173', the first initial thickness H1' of the first initial portion 171', and the second initial thickness H2' of the second initial portion 172' are approximately equal, i.e., H1'≈H2'≈H3'.

[0091] In some embodiments, the initial semiconductor layer 170' can be thinned by an etching process (e.g., wet or dry etching), and the thinned initial semiconductor layer 170' has a first thickness H1, a second thickness H2, and a third thickness H3, as shown in the figure. Figure 3D As shown. The first thickness H1, the second thickness H2, and the third thickness H3 are also approximately equal, that is, H1≈H2≈H3.

[0092] In some embodiments, an initial semiconductor layer with a thickness in the general range of 100 Å to 400 Å may also be formed in step S121. In this case, step S122 may be omitted, and the portion of the initial semiconductor layer 170' located in the step region 150 may be removed directly in step S123 while the portion of the initial semiconductor layer 170' located in the memory array region 130 may be retained.

[0093] Additionally, it should be noted that in some embodiments, a stepped structure is formed in the transition region of the stepped region 150 of the memory array region 130 when the channel layer 141 of the memory string channel structure 140 is exposed in step S110. Therefore, when using the above-described technical solution of first forming the initial semiconductor layer 170' and then thinning the initial semiconductor layer 170', a semiconductor layer is also formed on the sidewall of the stepped structure, resulting in the thickness of the portion of the semiconductor layer 170 located in the transition region of the memory array region 130 being greater than the thickness of the semiconductor layer 170 located at other locations in the memory array region 130. Furthermore, the thickness of the semiconductor layer 170 in the transition region can be reduced in the subsequent laser activation step (see reference). Figure 3F (As shown).

[0094] like Figure 3E As shown, after thinning the initial semiconductor layer 170', the first portion 171 of the initial semiconductor layer 170' located in the step region 150 is removed, thereby retaining the second portion 172 and the third portion 173 of the initial semiconductor layer 170' located in the memory array region 130. Then, the retained initial semiconductor layer 170' (second portion 172 and third portion 173) constitutes the aforementioned semiconductor layer 170.

[0095] In some embodiments, in step S123, the first portion 171 of the initial semiconductor layer 170' located in the step region 150 may be removed by an etching process (e.g., wet or dry etching process).

[0096] In some embodiments of step S121, since the initial semiconductor layer 170' is formed on the sidewall of the stepped structure, the thickness of the portion of the initial semiconductor layer 170' located in the transition region of the step region 150 of the memory array region 130 is greater than the thickness of the initial semiconductor layer 170' located at other locations in the memory array region 130. Therefore, when the first portion 171 of the initial semiconductor layer 170' located in the step region 150 is removed in step S123, a portion of the initial semiconductor layer 170' with a larger thickness is retained in the transition region of the stepped structure located in the memory array region 130. Figure 3E As shown.

[0097] In the above scheme, an initial semiconductor layer covering the step region and the memory array region is first formed, and then a reverse etching process is used to achieve the goal of fully covering the channel layer of the memory string channel structure while removing all the initial semiconductor layers located in the step region. It is evident that, since this application does not employ a mechanical polishing process to remove the initial semiconductor layer located in the step region, the goal of covering the channel layer can be achieved without a very thick initially formed semiconductor layer, thereby reducing the cost of semiconductor components. Furthermore, it can increase the process window of the memory string channel structure and resolve process problems caused by the difference in the vertical depth of the memory string channel structure.

[0098] Furthermore, after removing the first portion 171 of the initial semiconductor layer 170' located in the step region 150 in step S123, and retaining the second portion 172 and the third portion 173 located in the memory array region 130, the second portion 172 and the third portion 173 of the initial semiconductor layer 170' and the buffer layer 113 located in the step region 150 retained in step S110 can together form a relatively flat surface, which is beneficial to subsequent processing.

[0099] S130

[0100] In step S130, a source contact portion 180 is formed that is connected to the semiconductor layer 170.

[0101] In some implementations, step S130 includes the following steps:

[0102] S131, doped semiconductor layer 170, such as Figure 3F As shown;

[0103] S132. An insulating dielectric layer 181 is formed in the memory array region 130 and the step region 150, wherein the insulating dielectric layer 181 at least covers the semiconductor layer 170, such as Figure 3G As shown; and

[0104] S133, A source contact portion 180 is formed that penetrates the insulating dielectric layer 181 and is connected to the semiconductor layer 170, such as Figure 3H As shown.

[0105] like Figures 3F to 3H As shown, the method for forming the source contact 180 connected to the semiconductor layer 170 is detailed below: In step S131, impurity ions (N-type or P-type) are implanted into the semiconductor layer 170 (the second portion 172 and the third portion 173 of the initial semiconductor layer 170'), and a laser with a wavelength of λ is applied to activate the implanted impurities. In step S132, an insulating dielectric layer 181 is formed, which covers the buffer layer 113 located in the step region 150 and the semiconductor layer 170 (i.e., the doped semiconductor layer 174). Next, in step S133, the source contact 180 is formed, which penetrates the insulating dielectric layer 181 and is electrically connected to the doped semiconductor layer 174.

[0106] In the above scheme, the semiconductor layer 170 surrounds the channel layer 141 of the memory string channel structure 140 (channel layer 141-1 of memory string channel structure 140-1 and channel layer 141-2 of memory string channel structure 140-2). Therefore, after ion implantation and laser activation into the semiconductor layer 170, the semiconductor layer 170 is transformed into a doped semiconductor layer 174 (refer to...). Figure 3F As shown, the doped semiconductor layer 174 has electrical conductivity, enabling the conduction of electrical signals between the channel layer 141 of multiple memory string channel structures 140 located in the same memory block and the subsequently formed source contact portion 180.

[0107] In some implementations, such as Figure 3G As shown, an insulating dielectric layer 181 can be formed on the surface of the buffer layer 113 and the doped semiconductor layer 174 using thin film deposition processes such as CVD, PVD, or ALD. The material of the insulating dielectric layer 181 can be, for example, an insulating material such as an oxide. Then, the insulating dielectric layer 181 is planarized using processes such as chemical mechanical polishing, so that the insulating dielectric layer 181 provides a substantially flat upper surface for the memory array region 130 and the step region 150. In the above solution, since the semiconductor layer 170 located in the memory array region 130 and the buffer layer 113 located in the step region 150 together form a relatively flat surface in the aforementioned steps, the purpose of providing a substantially flat upper surface for the memory array region 130 and the step region 150 can be achieved without the insulating dielectric layer 181 having a very thick thickness, thus saving the cost of semiconductor components.

[0108] In some embodiments, forming the source contact 180 in step S133 includes: forming a contact hole 182 that penetrates the insulating dielectric layer 181 and extends to the doped semiconductor layer 174; and filling the contact hole 182 with a conductive material to form the source contact 180. Optionally, the periphery of the source contact 180 may also be provided with a material for conductor filling, bonding, or blocking.

[0109] As an example, multiple such etching processes can be first used to form multiple layers in the insulating dielectric layer 181. Figure 3H The contact hole 182 is shown. The contact hole 182 extends in a direction that is generally perpendicular to the doped semiconductor layer 174.

[0110] like Figure 3H As shown, a conductive material such as iron nitride or tungsten alloy is filled into the contact hole 182 to form the source contact 180. It can be seen that the source contact 180 is electrically connected to the doped semiconductor layer 174, thereby leading out the electrical signal of the storage string channel structure 140.

[0111] In some embodiments, the step area 150 is provided with a plurality of channel contacts 151 that extend longitudinally through the dielectric layer 122 in the stack layer 120 and to the buffer layer 113. The material of the channel contacts 151 can be a conductor material, and the periphery of the channel contacts 151 can also be provided with a material for conductor filling, bonding or blocking.

[0112] In some embodiments, the manufacturing method of this application further includes forming a peripheral contact portion 183 that penetrates the insulating dielectric layer 181 and the buffer layer 113 located in the step region 150 and is connected to the channel contact portion 151 in the step region 150. Optionally, the periphery of the peripheral contact portion 183 may also be provided with a material for conductor filling, bonding or blocking.

[0113] In some embodiments, the peripheral contact 183 and the source contact 180 are formed in the same process. Optionally, multiple contacts such as those formed in the insulating dielectric layer 181 located in the memory array region 130 are formed by etching. Figure 3H As shown in the contact hole 182, a plurality of contacts are formed in the insulating dielectric layer 181 located in the step region 150. Figure 3H The contact hole 184 shown matches the position of the channel contact portion 151. The extending direction of the contact hole 184 is substantially parallel to the extending direction of the contact hole 182, and extends to at least expose the channel contact portion 151. Then, while the contact hole 182 is filled with a conductive material such as iron nitride or tungsten alloy to form the source contact portion 180, the contact hole 184 is filled with a conductive material such as iron nitride or tungsten alloy to form the peripheral contact portion 183.

[0114] In some embodiments, to fully expose the channel contact portion 151, a contact hole 184 with a relatively large width may be formed. Then, an insulating material is deposited on the walls and bottom of the contact hole 184. Next, a portion of the insulating material at the bottom of the contact hole 184 is removed, leaving only a portion of the insulating material on the sidewalls of the contact hole 184 to expose the channel contact portion 151. Then, a conductive material such as iron nitride or tungsten alloy is filled into the gaps formed by the insulating material on the sidewalls of the contact hole 184 to form the peripheral contact portion 183.

[0115] In some embodiments, after forming the peripheral contact 183 and the source contact 180, the manufacturing method of this application further includes forming a metal layer 185 on the surface of the insulating dielectric layer 181, which is electrically connected to the peripheral contact 183 and the source contact 180, respectively. Figure 3H As shown. The material of the metal layer 185 can be, for example, a conductive metal material such as tungsten.

[0116] Another embodiment of this application also provides a semiconductor component 200, such as... Figure 4 As shown, the semiconductor device 200 includes an array device 210 having a memory array region 230 and a step region 250. The array device 210 includes a stacked structure 220, a memory string channel structure 240, a virtual channel structure 260, and a source contact 280. The stacked structure 220 includes alternately stacked gate conductive layers 221 and dielectric layers 222. A doped semiconductor layer 270 and a buffer layer 213 are formed on one side of the stacked structure 220 corresponding to the memory array region 230 and the step region 250, respectively. The memory string channel structure 240 includes a functional layer 242 and a channel layer 241, with the channel layer 241 extending into and directly contacting the doped semiconductor layer 270. The doped semiconductor layer 270 has a surface morphology adapted to a portion of the channel layer 241. The virtual channel structure 260 extends into the buffer layer 213. Optionally, the buffer layer 213 may be a semiconductor material such as polycrystalline silicon, with a thickness approximately between 2000 Å and 4000 Å. The source contact 280 is electrically connected to the doped semiconductor layer 270. Optionally, the periphery of the source contact 280 may also be provided with a material for conductor filling, bonding, or blocking.

[0117] It should be noted that the doped semiconductor layer 270 described above has electrical conductivity and can conduct electrical signals between the channel layer 241 of the storage string channel structure 240 and the source contact portion 280.

[0118] In the above scheme, since the function of the doped semiconductor layer 270 is to conduct electrical signals between the channel layer 241 of the memory string channel structure 240 and the source contact 280, the doped semiconductor layer 270 in the semiconductor component 200 provided in this application has a surface morphology that is adapted to a portion of the channel layer 241. This means that the thickness of the doped semiconductor layer 270 does not need to be very thick to achieve the purpose of covering the channel layer and resisting laser damage during activation. It can also more easily take into account the differences in the longitudinal extension depth (CH gouging) of the memory string channel structure in the memory array region, thereby simplifying the manufacturing process of the semiconductor component 200 and achieving the purpose of increasing the process window of the memory string channel structure 240.

[0119] In some embodiments, the functional layer 242 may include, for example, a charge blocking layer, a charge trapping layer, and a tunneling layer disposed sequentially from the outside in. The materials of the charge blocking layer, the charge trapping layer, and the tunneling layer may sequentially include, for example, silicon oxide, silicon nitride, and silicon oxide, thereby forming a functional layer 242 having an ONO structure. The material of the channel layer 241 may include, for example, a semiconductor material such as silicon (e.g., amorphous silicon, polycrystalline silicon, monocrystalline silicon). The memory string channel structure 240 also includes an isolation layer 243 surrounded by the channel layer 241.

[0120] In some embodiments, the memory array region 230 includes a plurality of memory string channel structures 240, wherein the channel layers 241 of at least two memory string channel structures 240 extend to different heights outside one side of the stacked structure 220. The surface morphology of the doped semiconductor layer 270 is conformal to the surface morphology of the channel layers 241 of the at least two memory string channel structures 240. That is, the depths to which the channel layers 241 of the at least two memory string channel structures 240 extend into the doped semiconductor layer 270 are different, but the thickness of the doped semiconductor layer 270 at the top of the channel layers 241 of the memory string channel structures 240 is approximately equal. The thickness of the doped semiconductor layer 270 at the top of the channel layers 241 of the plurality of memory string channel structures 240 ranges from 100 Å to 400 Å. Optionally, the thickness of the doped semiconductor layer 270 ranges approximately between 200 Å and 300 Å. Further optionally, the approximately thickness of the doped semiconductor layer 270 is 300 Å.

[0121] For example, the memory array region 230 includes a first memory array region 231 and a second memory array region 232. The longitudinal depth of the memory string channel structure 240-2 located in the second memory array region 232 is greater than the longitudinal depth of the memory string channel structure 240-1 located in the first memory array region 231. It is understood that the longitudinal depth here is the depth in a direction approximately perpendicular to the doped semiconductor layer 270. Furthermore, the memory array region 230 may also include regions where the longitudinal depth of several other memory string channel structures differs from the longitudinal depths of memory string channel structures 240-2 and 240-1, or the memory array region 230 may also include regions with a similar gate gap structure 233; this application does not limit this. This application only illustrates the case where the memory array region 230 includes the first memory array region 231 and the second memory array region 232 as an example. Furthermore, the aforementioned first memory array region 231 and second memory array region 232 are merely illustrative of situations where multiple memory channel structures have uneven distribution in their longitudinal extension depth (CH gouging). It should be understood that the different longitudinal extension depths of the storage trench structure are not strictly divided according to regions.

[0122] The doped semiconductor layer 270 includes a first portion 271 and a second portion 272 covering the first memory array region 231 and the second memory array region 232, respectively. Since the longitudinal depth of the memory string channel structure 240-1 in the first memory array region 231 is small, the first portion 271 of the doped semiconductor layer 270 only surrounds the top of the channel layer 241-1 of the memory string channel structure 240-1. Therefore, the first portion 271 of the doped semiconductor layer 270 has a first thickness G1, which is approximately in the range of 100 Å to 400 Å. Because the longitudinal depth of the memory string channel structure 240-2 in the second memory array region 232 is relatively large and the gap between two adjacent memory string channel structures 240-2 is relatively small, the second portion 272 of the doped semiconductor layer 270 not only surrounds the top of the channel layer 241-2 of the memory string channel structure 240-2, but also surrounds part of the sidewall of the channel layer 241-2 of the memory string channel structure 240-2. Therefore, the thickness of the second portion 272 of the doped semiconductor layer 270 is relatively large. However, the thickness of the second portion 272 of the doped semiconductor layer 270 located at the top of the channel layer 241-2 of the memory string channel structure 240-2 is the second thickness G2, and G2 ranges approximately from 100 Å to 400 Å. Optionally, the first thickness G1 and the second thickness G2 are approximately equal.

[0123] It can be seen that, due to the difference in the longitudinal direction of the memory string channel structure 240 of the memory array region 230, the overall thickness of the second portion 272 of the doped semiconductor layer 270 is greater than the overall thickness of the first portion 271. However, despite this, the thickness of the doped semiconductor layer 270 is still within a relatively small range.

[0124] In the above scheme, although the memory string channel structure 240 has the characteristic of being different in the longitudinal direction, within the thickness range defined above, the doped semiconductor layer 270 can achieve the purpose of surrounding part of the exposed channel layer 241, thereby reducing the overall thickness of the semiconductor component.

[0125] In some embodiments, the doped semiconductor layer 270 is formed via a furnace tube growth process. Exemplarily, the method provided in one aspect of this application, such as... Figure 2 Some steps in the semiconductor component manufacturing method 1000 form a doped semiconductor layer 270. Since the contents and structures involved in the manufacturing method 1000 described above are wholly or partially applicable to the doped semiconductor layer 270 described herein, related or similar contents will not be repeated.

[0126] In some embodiments, the doped semiconductor layer 270 is a doped polysilicon layer.

[0127] In some embodiments, the semiconductor component 200 further includes a peripheral device 290 bonded to the array device 210, the peripheral device 290 including at least peripheral circuitry providing electrical signals. The array device 210 also includes a channel contact 251 connected to the peripheral device 290. Optionally, the peripheral device 290 can be a complementary metal-oxide-semiconductor (CMOS), static random access memory (SRAM), dynamic random access memory (DRAM), field-programmable gate array (FPGA), central processing unit (CPU), Xpoint chip, or other similar devices. The array device 210 also includes a peripheral contact 283 that penetrates the buffer layer 213 of the step region 250 and connects to the channel contact 251 in the array device 210. Optionally, the periphery of the peripheral contact 283 may also be provided with a material for conductor filling, bonding, or blocking.

[0128] Optionally, the bottom of the storage string channel structure 240, the bottom of the channel contact portion 251, and the conductive portion 252 located in the step area are each provided with a first bonding interface 215, and the top of the peripheral device 290 is provided with a plurality of second bonding interfaces 291 corresponding to the plurality of first bonding interfaces 215, so as to realize the bonding between the peripheral device 290 and the array device 210.

[0129] For example, the methods provided in one aspect of this application, such as Figure 2Some steps in the semiconductor component manufacturing method 1000 form the source contact 280 and the peripheral contact 283. Since the contents and structures involved in the manufacturing method 1000 described above are wholly or partially applicable to the source contact 280 and the peripheral contact 283 described herein, related or similar contents will not be repeated.

[0130] In some embodiments, the array device 210 further includes an insulating dielectric layer 281 disposed above the upper surface of the buffer layer 213 in the step region 250 and the doped semiconductor layer 270 in the storage array region 230. Optionally, the insulating dielectric layer 281 may be made of an insulating material such as an oxide. The source contact 280 penetrates the insulating dielectric layer 281 and is connected to the doped semiconductor layer 270. The peripheral contact 283 penetrates the insulating dielectric layer 281 and the buffer layer 213 and is connected to the channel contact 251.

[0131] In some embodiments, the semiconductor component 200 further includes a metal layer 285 electrically connected to the peripheral contact 283 and the source contact 280, respectively. The metal layer 285 is disposed on the insulating dielectric layer 281, such as... Figure 4 As shown. The material of the metal layer 285 can be, for example, a conductive metal material such as tungsten.

[0132] Figure 5A and Figure 5B This is a schematic diagram of the structure of a storage system according to an exemplary embodiment of this application. For example... Figure 5A and Figure 5B As shown, the storage system 500 includes a three-dimensional memory 510 and a controller 520. The three-dimensional memory 510 is a semiconductor component 200 as mentioned in the above embodiments, or at least includes a semiconductor component 200 as mentioned in the above embodiments. The controller 520 is electrically connected to the three-dimensional memory 510 and is used to control the three-dimensional memory 510.

[0133] In such Figure 5A In the example shown, the controller 520 and a single three-dimensional memory 510 can be integrated into the memory card. The memory card can include PC cards (PCMCIA, Personal Computer Memory Card International Association), compact flash (CF) cards, smart media (SM) cards, memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), universal flash memory cards (UFS), etc. The memory card may also include a memory card connector 530 that couples the memory card to a host (not shown).

[0134] In such Figure 5BIn another example shown, the controller 520 and multiple three-dimensional memories 510 can be integrated into a solid-state drive (SSD). The SSD may also include an SSD connector 530 that couples the SSD to a host (not shown). In some embodiments, the storage capacity and / or operating speed of the SSD is higher than... Figure 5A The storage capacity and / or operating speed of the memory card shown.

[0135] The above description is merely an illustration of the embodiments of this application and the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A method of manufacturing a semiconductor structure comprising a plurality of memory string channel structures having a functional layer and a channel layer extending into a substrate, at least two of the memory string channel structures extending into the substrate to different distances, wherein, The manufacturing method includes: Removing a portion of the substrate and a portion of the functional layer to expose a portion of the channel layer; and A semiconductor layer is formed covering the exposed portion of the channel layer, the surface morphology of the semiconductor being conformal to the surface morphology of the channel layer of the at least two memory string channel structures.

2. The manufacturing method according to claim 1, wherein, The semiconductor component has a memory array region and a step region, and the plurality of memory string channel structures are located in the memory array region; The removal of a portion of the substrate and a portion of the functional layer to expose a portion of the channel layer includes: Removing the substrate located in the memory array region to expose a portion of the functional layer of the plurality of memory string channel structures; and Remove some functional layers of the exposed plurality of memory string channel structures to expose some channel layers of the plurality of memory string channel structures.

3. The manufacturing method according to claim 2, wherein, The semiconductor layer forming the portion of the exposed channel layer includes: An initial semiconductor layer is formed in the memory array region and the step region, the initial semiconductor layer having a surface morphology conforming to the exposed surfaces of the memory array region and the step region; and Remove the portion of the initial semiconductor layer located in the step region and retain the portion of the initial semiconductor layer located in the memory array region; The retained portion of the initial semiconductor layer constitutes the semiconductor layer.

4. The manufacturing method according to claim 3, wherein, Before removing the portion of the initial semiconductor layer located in the step region and retaining the portion of the initial semiconductor layer located in the memory array region, the method further includes: Thinning of the initial semiconductor layer.

5. The manufacturing method according to claim 4, wherein, Thinning the initial semiconductor layer includes: The initial semiconductor layer is thinned by an etching process.

6. The production method according to claim 1, wherein The thickness of the semiconductor layer ranges from 100 Å to 400 Å.

7. The production method according to claim 3, wherein Forming the initial semiconductor layer in the memory array region and the step region includes: The initial semiconductor layer is formed in the memory array region and the step region using a furnace tube growth process.

8. The production method according to any one of claims 1 to 7, wherein Also includes: A source contact portion is formed that is connected to the semiconductor layer.

9. The manufacturing method according to claim 8, wherein, Forming a source contact portion connected to the semiconductor layer, comprising: Doping the semiconductor layer; An insulating dielectric layer is formed in the storage array region and the step region of the semiconductor component, the insulating dielectric layer at least covering the semiconductor layer; and The source contact portion is formed, which penetrates the insulating dielectric layer and is connected to the semiconductor layer.

10. The production method according to any one of claims 1 to 7, wherein The semiconductor layer is a polycrystalline silicon layer.

11. A semiconductor structure, wherein, include: The stacked structure includes alternating stacked gate conductive layers and insulating layers; Multiple memory string channel structures extend through the stacked structure, and a portion of the channel layers of the multiple memory string channel structures extend to the outside of one side of the stacked structure, wherein at least two of the memory string channel structures have channel layers extending to the outside of one side of the stacked structure at different heights. A doped semiconductor layer is located on one side of the stacked structure and at least covers and is in direct contact with a portion of the channel layer. The surface morphology of the doped semiconductor layer is conformal to the surface morphology of the channel layers of the at least two memory string channel structures.

12. The semiconductor component according to claim 11, wherein The thickness of the doped semiconductor layer ranges from 100 Å to 400 Å.

13. The semiconductor component according to claim 11, wherein The doped semiconductor layer is formed by a furnace tube growth process.

14. The semiconductor component according to any one of claims 11 to 13, wherein Also includes: The source contact is electrically connected to the doped semiconductor layer.

15. The semiconductor component according to claim 14, wherein The semiconductor component has a memory array region and a step region, and the memory string channel structure, the doped semiconductor layer, and the source contact are located in the memory array region; The semiconductor component further includes: A virtual channel structure extends through the stacked structure, and a portion of the virtual channel structure extends to the outside of one side of the stacked structure; as well as A buffer layer is located outside one side of the stacked structure and at least covers the portion of the virtual channel structure extending to the outside of one side of the stacked structure.

16. The semiconductor component according to claim 15, wherein, The semiconductor component further includes: A channel contact portion, located in the stepped area, is used for connection with peripheral circuitry; and The outer contact portion penetrates the buffer layer and connects to the channel contact portion.

17. The semiconductor component according to any one of claims 11 to 13, wherein The doped semiconductor layer is a doped polycrystalline silicon layer.

18. A storage system, characterized by include: A three-dimensional memory, comprising at least the semiconductor component as described in any one of claims 11-17; as well as A controller, electrically connected to the three-dimensional memory, is used to control the three-dimensional memory.

Images