Semiconductor memory devices and manufacturing methods

Abstract

This disclosure relates to semiconductor memory devices and manufacturing methods. A semiconductor device includes: a memory structure on a substrate, wherein the memory structure includes a first word line; a first bit line on the first word line; a second bit line on the first bit line; a memory material on sidewalls of the first and second bit lines; a first control word line along a first side of the memory material, wherein the first control word line is electrically connected to the first word line; a second control word line along a second side of the memory material opposite to the first side; and a second word line on the second bit line, the first control word line, and the second control word line, wherein the second word line is electrically connected to the second control word line.

Description

Technical Field

[0001] This disclosure relates generally to semiconductor memory devices and manufacturing methods. Background Technology

[0002] Semiconductor memories are used in integrated circuits for electronic applications, including, for example, radios, televisions, cellular phones, and personal computing devices. One type of semiconductor memory is resistive random access memory (RRAM), which involves storing values ​​in a material with varying resistance. The resistive material can switch between low-resistance and high-resistance phases to indicate bit codes. Summary of the Invention

[0003] According to one embodiment of this disclosure, a method for manufacturing a semiconductor device is provided, the method comprising: forming a first word line on a substrate; forming a bit line stack, comprising: forming a first bit line on the first word line, wherein the first bit line comprises a first material; forming an insulating layer on the first bit line; and forming a second bit line on the insulating layer, wherein the second bit line comprises the first material; depositing a storage material on the bit line stack, wherein the storage material extends along a first sidewall and a second sidewall of the bit line stack; depositing a conductive material on the storage material, wherein a first portion of the conductive material along the first sidewall is electrically isolated from a second portion of the conductive material along the second sidewall; and forming a second word line on the conductive material, wherein the second word line is electrically connected to a second portion of the conductive material.

[0004] According to another embodiment of this disclosure, a method of manufacturing a semiconductor device is provided, comprising: forming a first word line on a substrate; forming a memory stack on the first word line, wherein each memory stack includes a first sidewall and a second sidewall, wherein forming each memory stack includes: forming a first bit line on at least one first word line; forming a second bit line on the first bit line, wherein the second bit line is electrically isolated from the first bit line; depositing a resistive memory layer along the sidewalls of the first bit line and the sidewalls of the second bit line; and depositing a select layer on the resistive memory layer; forming control word lines on the memory stack, wherein each control word line extends from a first sidewall of a first corresponding memory stack to a second sidewall of a second corresponding memory stack; and forming a second word line on the memory stack and the control word line, wherein each control word line is electrically connected to the first word line or the second word line.

[0005] According to another embodiment of this disclosure, a semiconductor device is provided, comprising: a memory structure on a substrate, wherein the memory structure includes: a first word line; a first bit line on the first word line; a second bit line on the first bit line; a memory material on the sidewalls of the first bit line and the second bit line; a first control word line along a first side of the memory material, wherein the first control word line is electrically connected to the first word line; a second control word line along a second side of the memory material opposite to the first side; and a second word line on the second bit line, the first control word line, and the second control word line, wherein the second word line is electrically connected to the second control word line. Attached Figure Description

[0006] Various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0007] Figure 1A and Figure 1B Plan and cross-sectional views of intermediate steps in manufacturing the first word line of a memory device according to some embodiments are shown.

[0008] Figure 2A , Figure 2B , Figure 3A and Figure 3B Plan and cross-sectional views of intermediate steps in manufacturing a bitline stack of a memory structure according to some embodiments are shown.

[0009] Figure 4A , Figure 4B , Figure 5A and Figure 5B Plan and cross-sectional views of intermediate steps in manufacturing a memory stack according to some embodiments are shown.

[0010] Figure 6A , Figure 6B , Figure 7A and Figure 7B Plan and cross-sectional views of intermediate steps in manufacturing the control word lines of a memory structure according to some embodiments are shown.

[0011] Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11A and Figure 11B Plan and cross-sectional views of intermediate steps in manufacturing the second word line of a memory structure according to some embodiments are shown.

[0012] Figure 12A , Figure 12B and Figure 12C Plan and cross-sectional views of intermediate steps in manufacturing a storage structure according to some embodiments are shown.

[0013] Figure 12D A plan view of a storage array according to some embodiments is shown.

[0014] Figure 13 and Figure 14 A cross-sectional view is shown of an intermediate step in the manufacturing of a storage device according to some embodiments.

[0015] Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A and Figure 17B Plan and cross-sectional views of intermediate steps in manufacturing a storage structure according to some embodiments are shown.

[0016] Figure 18A , Figure 18B , Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figure 21A , Figure 21B , Figure 22A and Figure 22B Plan and cross-sectional views of intermediate steps in manufacturing a storage structure according to some embodiments are shown.

[0017] Figure 23A , Figure 23B , Figure 24A , Figure 24B , Figure 25A , Figure 25B , Figure 26A and Figure 26B Plan and cross-sectional views are shown of intermediate steps in fabricating a bit line stack with electrodes according to some embodiments.

[0018] Figure 27A , Figure 27B and Figure 27C An enlarged cross-sectional view of an electrode according to some embodiments is shown.

[0019] Figure 28A , Figure 28B , Figure 29A and Figure 29B Plan and cross-sectional views are shown of intermediate steps in manufacturing a memory stack with an electrode structure according to some embodiments.

[0020] Figure 30A and Figure 30BPlan and cross-sectional views are shown of intermediate steps in manufacturing control word lines of a memory structure with electrodes according to some embodiments.

[0021] Figure 31A and Figure 31B Plan and cross-sectional views are shown of intermediate steps in manufacturing a second word line with electrodes according to some embodiments.

[0022] Figure 32A and Figure 32B Plan and cross-sectional views are shown of intermediate steps in manufacturing a storage structure with electrodes according to some embodiments.

[0023] Figure 33A and Figure 33B Plan and cross-sectional views are shown of intermediate steps in manufacturing a storage structure with electrodes according to some embodiments. Detailed Implementation

[0024] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples throughout this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0025] In addition, spatially related terms (e.g., "below," "below," "lower than," "above," "upper") may be used in this document to facilitate the description of the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein shall be interpreted accordingly.

[0026] Embodiments will now be described with respect to specific examples, wherein the resistive random access memory (RRAM) device includes an array of memory structures having two vertically stacked bit lines and two vertically stacked word lines. The bit lines may be disposed between the word lines, and the word lines are connected to control word lines extending over the opposite sides of the bit lines. In this manner, each memory structure includes four independently controllable memory cells. In some cases, memory structures such as those described herein can allow for increased cell density of the memory array without increasing the area of ​​the memory array. Furthermore, some embodiments described herein describe memory structures in which each memory cell includes an electrode having a tip, wherein the electrode is connected to the bit line. In some cases, the tip of the electrode induces a more localized electric field during device operation, which allows the physical mechanism of resistive memory to occur in a more localized region near the tip. This can improve device reproducibility, more uniformity of memory cell operation, and more consistent operation of the memory cells.

[0027] Figures 1A to 14 The diagram illustrates a configuration according to some embodiments including a storage structure 250 (see [link]). Figures 12A-12C Semiconductor device 350 (see) Figure 14 The intermediate steps of ). Figures 1A to 12B In this context, the diagram ending with "A" is a plan view showing section A-A' along the corresponding section shown in the diagram ending with "B". Similarly, the diagram ending with "B" shows section B-B' along the corresponding section shown in the diagram ending with "A". For example, Figure 1A It shows Figure 1B The structure shown is in Figure 1B The top-to-bottom plan view of section A-A' is shown, and Figure 1B It shows Figure 1A The structure shown follows Figure 1A The cross-sectional view of section B-B' is shown.

[0028] First turn Figure 1A-Figure 1BAccording to some embodiments, a first word line 103 is formed on a substrate 101. The substrate 101 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (e.g., doped with p-type or n-type dopants) or undoped. The substrate 101 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a semiconductor material layer formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on the substrate, typically a silicon substrate or a glass substrate. Other substrates may also be used, such as multilayer substrates or gradient substrates. In some embodiments, the semiconductor material of the substrate 101 may include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium phosphide indium, and / or gallium arsenide phosphide indium; or combinations thereof.

[0029] Furthermore, substrate 101 may include active devices (not shown separately) formed within and / or on substrate 101, and may include a first metallization layer 102 on the active devices. Those skilled in the art will recognize that active devices may include a variety of active and passive devices, such as transistors, capacitors, resistors, etc., or combinations thereof. Active devices can be used to achieve the desired structural and functional requirements of semiconductor device designs and can be formed using any suitable technique. For example, active devices may include one or more devices, such as diodes, photodiodes, fuses, complementary metal-oxide-semiconductor (CMOS) transistors, fin field-effect transistors (FinFETs), nanostructure (e.g., nanosheets, nanowires, gate-all-around, etc.) field-effect transistors (NSFETs), etc., or combinations thereof.

[0030] A first metallization layer 102 is formed on top of the active device and can connect various active devices to form a functional circuit. In embodiments, the first metallization layer 102 comprises alternating layers of dielectric and conductive materials and can be formed using any suitable technique (e.g., deposition, damascene, dual damascene, etc.). The dielectric layers can be intermetallic dielectric layers (IMDs), and one or more of the dielectric layers can be low-k dielectric materials, non-low-k dielectric materials, oxides, nitrides, polymers, etc., or combinations thereof. In some embodiments, one or more of the dielectric layers can be formed of a material similar to the first dielectric layer 105, as described below.

[0031] The conductive layer may be a metallized pattern and may include conductive features interconnected and embedded in one or more dielectric layers. The conductive features may include multilayer conductive lines, conductive vias, and / or conductive contacts. Conductive vias may be formed in the dielectric layer to electrically connect conductive lines in different layers. The conductive material may include one or more metals, metal alloys, or combinations thereof, and may be deposited using suitable techniques. As a representative example, in Figure 1A-Figure 1B The diagram shows a first metallization layer 102 including a conductive line 111, a dielectric layer 110 covering the conductive line 111, and a conductive via 113 extending through the dielectric layer 110 to electrically connect the conductive line 111. In some embodiments, the conductive line 111 may be part of a logic circuit or another type of circuit. For example, the first metallization layer 102 may have four metallization layers, and the conductive line may be part of a fourth metallization layer, but the first metallization layer 102 may have any suitable number of metallization layers. These are examples; any suitable number of conductive layers, dielectric layers, or conductive vias can be used.

[0032] According to some embodiments, a first word line 103 of the memory structure 250 may be formed on a first metallization layer 102. In some embodiments, the first word line 103 may be electrically connected to the first metallization layer 102 via a conductive via 113. For example, the first word line 103 may be formed by first forming a first dielectric layer 105 on the first metallization layer 102. The first dielectric layer 105 may include one or more dielectric materials, such as doped or undoped silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, doped silicate glass, flowable oxide, other high-k materials, low-k materials, etc., or combinations thereof. In embodiments, the first dielectric layer 105 includes materials such as borosilicate glass (BPSG), but any suitable dielectric may be used, which may include those dielectrics described above for the dielectric layer of the first metallization layer 102. The first dielectric layer 105 may be formed using any suitable process, such as CVD, PVD, PECVD, ALD, etc. In some embodiments, chemical mechanical polishing (CMP), grinding, or other processes are used to planarize the first dielectric layer 105.

[0033] In some embodiments, after the formation of the first dielectric layer 105, a first word line 103 may be formed within the first dielectric layer 105. In this way, the first dielectric layer 105 may surround and isolate the first word line 103. As an example process, the first word line 103 may be formed by forming an opening within the first dielectric layer 105 and depositing a conductive material within the opening. For example, suitable photolithography and etching processes may be used to form the opening. In some embodiments, the conductive material includes an optional liner layer and a conductive filler material above the liner layer. The liner layer may be a diffusion barrier layer, an adhesion layer, etc., and may include one or more layers of titanium, titanium nitride, tantalum, tantalum nitride, molybdenum, ruthenium, rhodium, hafnium, iridium, niobium, rhenium, tungsten, cobalt, aluminum, copper, alloys thereof, oxides thereof, etc., or combinations thereof. The liner layer may be deposited using suitable processes, such as electroplating, CVD, PVD, PECVD, ALD, etc.

[0034] After depositing the liner layer (if present), a conductive filler material is deposited to fill the remaining portion of the opening in the first dielectric layer 105, thereby forming the first word line 103. The conductive filler material may include one or more conductive materials, such as tungsten, cobalt, aluminum, nickel, copper, silver, gold, molybdenum, ruthenium, molybdenum nitride, alloys thereof, or combinations thereof. The conductive filler material can be deposited using suitable processes, such as electroplating, CVD, PVD, PECVD, ALD, etc. In some embodiments, a planarization process (e.g., CMP and / or polishing) may be performed to remove excess conductive material.

[0035] In other embodiments, other techniques may be used to form the first word line 103. For example, the conductive material of the first word line 103 may be deposited on the first metallization layer 102 and then patterned using suitable photolithography and etching techniques to form the first word line 103. Material of the first dielectric layer 105 may then be deposited on the first word line 103. A planarization process may then be performed to remove excess material. These techniques, and all other suitable techniques, are fully intended to be within the scope of this disclosure. In some embodiments, the first word line 103 may be formed having a thickness T1 in the range of about 80 nm to about 180 nm, or a width W1 in the range of about 40 nm to about 80 nm. In some embodiments, adjacent first word lines 103 may be spaced apart by a distance S1 in the range of about 40 nm to about 80 nm. Other shapes, sizes, thicknesses, widths, or distances are also possible, and the first word lines 103 may have a different number or arrangement than those shown.

[0036] In some embodiments, a second dielectric layer 107 may be formed over the first word line 103, and a first via 109 extending through the second dielectric layer 107 to electrically connect to the first word line 103 may be formed. The second dielectric layer 107 may be formed using similar materials and similar processes to those used for the first dielectric layer 105 described above. However, any suitable materials or techniques may be used.

[0037] In some embodiments, the first via 109 may be formed using materials and processes similar to those used for the first word line 103 described above. For example, the first via 109 may be formed by forming an opening in the second dielectric layer 107, filling the opening with a conductive material, and then performing a planarization process to remove excess conductive material. However, any suitable material or technique may be used. In some embodiments, the first via 109 may have a thickness in the range of about 30 nm to about 100 nm, and may have a width or length in the range of about 40 nm to about 80 nm. Other shapes, sizes, thicknesses, widths, lengths, or spacings are also possible, and the first via 109 may have a different number or arrangement than those shown.

[0038] Figures 2A-2B The deposition of a bit line layer 202 according to some embodiments is illustrated. According to some embodiments, the bit line layer 202 is then patterned to form a memory structure 250 (see [link]). Figures 12A-12C The first line 201 and the second line 209 (see) Figures 3A-3B In some embodiments, bit line layer 202 may include a first bit line material, a first adhesion layer 203, an insulating layer 205, a second adhesion layer 207, and a second bit line material. The first bit line material may include a conductive material, such as tungsten, cobalt, aluminum, nickel, copper, silver, gold, alloys thereof, or combinations thereof. The conductive material can be deposited using acceptable processes, such as electroplating, CVD, PVD, PECVD, ALD, etc. However, any suitable material or deposition technique can be used. In some embodiments, the first bit line material may have a thickness in the range of about 30 nm to about 50 nm, but other thicknesses are also possible.

[0039] According to some embodiments, a first adhesion layer 203 may then be deposited on the first wire material to improve adhesion between the first wire material and the overlying insulating layer 205. The first adhesion layer 203 may comprise titanium, titanium nitride, tantalum, tantalum nitride, carbon, or combinations thereof. The first adhesion layer 203 may be deposited using acceptable processes, such as electroplating, CVD, PVD, PECVD, ALD, etc. However, any suitable material or deposition technique may be used. In some embodiments, the first adhesion layer 203 may have a thickness in the range of about 2 nm to about 5 nm, but other thicknesses are also possible.

[0040] According to some embodiments, an insulating layer 205 may then be deposited on the first adhesion layer 203. The insulating layer 205 electrically isolates the first bit line 201 from the second bit line 209 (see [link]). Figures 3A-3B In some embodiments, insulating layer 205 may be a material similar to that previously described for the first dielectric layer 105. For example, insulating layer 205 may be an oxide material, but other materials are also possible. Insulating layer 205 may be deposited using acceptable processes, such as those previously described for the first dielectric layer 105. However, any suitable material or deposition technique may be used. In some embodiments, insulating layer 205 may have a thickness in the range of about 20 nm to about 30 nm, but other thicknesses are also possible.

[0041] According to some embodiments, a second adhesion layer 207 may then be deposited on the insulating layer 205. The second adhesion layer 207 may provide improved adhesion between the insulating layer 205 and the overlying second bit line material. The second adhesion layer 207 may comprise a material similar to that described for the first adhesion layer 203 and may be deposited using a similar process. For example, the second adhesion layer 207 may have a thickness in the range of about 2 nm to about 5 nm, but other thicknesses are also possible.

[0042] According to some embodiments, a second bit line material can then be deposited on the second adhesion layer 207. The second bit line material may include a material similar to that described for the first bit line material and can be deposited using a similar process. For example, the second bit line material may have a thickness in the range of about 30 nm to about 50 nm, but other thicknesses are also possible.

[0043] In some embodiments, a hard mask 210 may be deposited on the bit line layer 202 for use during subsequent patterning steps. The hard mask 210 may be a material such as silicon nitride, silicon oxide, silicon oxynitride, SiCON, SiC, SiOC, or combinations thereof. The hard mask 210 may be deposited using suitable processes, such as CVD, PVD, ALD, etc. In some embodiments, the hard mask 210 may have a thickness in the range of about 5 nm to about 30 nm, but other thicknesses are also possible.

[0044] Figures 3A-3B The diagram illustrates the patterning of bitline layer 202 according to some embodiments to form bitline stack 204. According to some embodiments, bitline stack 204 includes a first bitline 201 formed of a first bitline material and a second bitline 209 formed of a second bitline material. For example, the first bitline 201 and the second bitline 209 can be formed by patterning bitline layer 202 using a suitable photomask and etching process. For example, this can be done on hard mask 210 (see...). Figures 2A-2BA photoresist (not shown) is formed on the hard mask 210 and patterned using an acceptable photolithography technique. The pattern of the photoresist can then be transferred to the hard mask 210 using an acceptable etching process, such as wet etching, dry etching, reactive ion etching (RIE), neutral beam etching (NBE), or a combination thereof. The etching process can be anisotropic. In some embodiments, the photoresist can then be removed using, for example, an ashing process.

[0045] The pattern of hard mask 210 can then be transferred to bit line layer 202 using one or more acceptable etching processes, such as wet etching, dry etching, RIE, NBE, etc., or combinations thereof. The etching process can be anisotropic. In this way, the pattern of hard mask 210 extends through bit line layer 202, patterning a first bit line material to define a first bit line 201, and patterning a second bit line material to define a second bit line 209. In some embodiments, one or more layers of bit line layer 202 can be etched using an etching process different from one or more other layers of bit line layer 202. In some embodiments, hard mask 210 can be removed by an etching process. In other embodiments, hard mask 210 can be removed after patterning the bit line layer. For example, hard mask 210 can be removed using wet etching, dry etching, planarization, etc., or combinations thereof. In other embodiments, hard mask 210 is not removed and remains on bit line stack 204. The following describes... Figures 15A to 17B The process of an embodiment in which the hard mask 210 is not removed is described.

[0046] In this manner, according to some embodiments, a bit line stack 204 can be formed. Each bit line stack 204 includes a first bit line 201 and a second bit line 209. Each first bit line 201 is separated and isolated from the corresponding second bit line 209 by an insulating layer 205. In some embodiments, the bit line stack 204 has a thickness T2 in the range of about 100 nm to about 200 nm. Adjacent bit line stacks 204 may be separated by a distance S2 in the range of 45 nm to about 100 nm. In some embodiments, the bit line stack 204 has a width W2 in the range of about 40 nm to about 80 nm. Other thicknesses, distances, or widths are possible. In some embodiments, the bit line stack 204 may have substantially vertical sidewalls, such as... Figure 3B As shown. In other embodiments, the bit line stack 204 may have sloping sidewalls, tapered sidewalls, convex sidewalls, concave sidewalls, or sidewalls with a profile different from these examples. Figures 3A-3B As shown, in some embodiments, a pair of bit line stacks 204 may be formed between a pair of first vias 109, but other arrangements or configurations of the bit line stacks 204 or the first vias 109 are also possible.

[0047] Figures 4A-4BA storage material 211 and a selection material 213 are shown deposited on a bit line stack 204 according to some embodiments. The storage material 211 can be, for example, a resistive memory material suitable for storing digital values ​​(e.g., 0 or 1), such as resistive random access memory (RRAM or ReRAM) material, PCRAM material, CBRAM material, etc. In some embodiments, the resistance of the storage material 211 can be controlled by applying an appropriate voltage and / or current across the storage material 211. For example, the storage material 211 can be controlled to be in a high-resistance state or a low-resistance state. Depending on the resistance state of the storage material 211, the current flowing through the storage material 211 changes, and a corresponding digital value can be stored. Storage structure 250 (see...) Figures 12A-12C The type and physical mechanism of the storage material 211 may depend on the specific material of the storage material 211. For example, some types of storage materials 211 can be set to a specific resistive state by applying an electric field across the storage material 211 (e.g., by controlling the voltage across the storage material 211), and other types of storage materials 211 can be set to a specific resistive state by heating the storage material 211 (e.g., by controlling the current flowing through the storage material 211).

[0048] In some embodiments, the storage material 211 may include a high-k dielectric material containing metal, such as a metal oxide. The metal may be a transition metal. In some embodiments, the storage material 211 includes HfO. x ZrO x TaO x TiO x VO x NiO x NbO x LaO x CuO x etc., or combinations thereof. In other embodiments, the storage material 211 includes AlO. x SnO x GdO x IGZO, Ag2S, etc., or combinations thereof. In other embodiments, the storage material 211 comprises a chalcogenide material, such as GeS2, GeSe, AgGeSe, GeSbTe, doped GeSbTe (e.g., doped with N, Si, C, Ga, In, etc., or combinations thereof), etc., or combinations thereof. In some embodiments, the storage material 211 may be deposited as a conformal film. The storage material 211 may be deposited by CVD, PVD, ALD, PECVD, etc. These are examples, and other materials or other deposition techniques are possible, and all of these are also considered to be within the scope of this disclosure. In some embodiments, the storage material 211 is deposited on the surface with a thickness ranging from about 5 nm to about 15 nm, but other thicknesses are also possible.

[0049] According to some embodiments, the selected material 213 is then deposited on the storage material 211. In other embodiments, the storage material 211 is patterned prior to the deposition of the selected material 213, as described below. Figures 18A-22B Example embodiments thereof are described. In some embodiments, the selected material 213 is a material exhibiting a bidirectional threshold switching (OTS) effect or a similar effect. In some embodiments, the selected material 213 comprises a chalcogenide material, which includes at least a chalcogenide anion (e.g., selenium, tellurium, etc.) and a positively charged element (e.g., germanium, silicon, phosphorus, arsenic, antimony, bismuth, zinc, nitrogen, boron, carbon, etc.). For example, the chalcogenide material may be GeSb₂Te₅ (GST), but other chalcogenide materials may also be used. In some embodiments, the selected material 213 may be deposited as a conformal film. The selected material 213 may be deposited by CVD, PVD, ALD, PECVD, etc. These are examples, and other materials or other deposition techniques are possible, and all of these are also considered to be within the scope of this disclosure. In some embodiments, the selected material 213 is deposited on the surface at a thickness ranging from about 10 nm to about 30 nm, but other thicknesses are also possible.

[0050] exist Figures 5A-5B In some embodiments, one or more etching processes are performed to remove portions of the storage material 211 and the selection material 213 to form a storage stack 206. According to some embodiments, the one or more etching processes can remove the storage material 211 and the selection material 213 from a horizontal surface, leaving portions of the storage material 211 and the selection material 213 on the sidewalls of the bit line stack 204. In this way, the storage material 211 and the selection material 213 on one bit line stack 204 are isolated from the storage material and selection material 213 on adjacent bit line stacks 204. The bit line stack 204 and the remaining storage material 211 and the selection material 213 form the storage stack 206. The remaining storage material 211 and the selection material 213 may cover some or all of the opposite sidewalls of the first bit line 201, and may cover some or all of the opposite sidewalls of the second bit line 209. In some cases, the storage material 211 retained on the sidewalls of the bit line stack 204 can be considered a "storage spacer," and the selection material 213 retained on the sidewalls of the bit line stack 204 can be considered a "selection spacer." For example... Figure 5B As shown, in some embodiments, the remaining storage material 211 may have an "L-shaped" profile in cross-section. The one or more etching processes may include, for example, wet etching, dry etching, RIE, NBE, or combinations thereof. The etching process may be anisotropic.

[0051] exist Figures 6A-6BIn some embodiments, conductive material 220 is deposited on the memory stack 206. In some embodiments, conductive material 220 may include materials previously deposited for the first word line 103 (see [link to documentation]). Figure 1A-Figure 1B One or more materials similar to those described above. The conductive material 220 may also be deposited using a technique similar to that previously described for the first word line 103. Other materials or techniques are also possible. In some embodiments, a planarization process (e.g., CMP and / or polishing) may be performed to remove excess conductive material 220. After planarization, the top surfaces of the conductive material 220, the second bit line 209, the storage material 211, and the selection material 213 may be substantially flush. In some embodiments, the planarization process may also remove excess portions of the storage material 211 and / or the selection material 213.

[0052] Figures 7A-7B A patterned conductive material 220 is shown to form control word lines 221 according to some embodiments. The conductive material 220 can be patterned, for example, using suitable photolithography and etching techniques (e.g., those previously described). In some embodiments, the control word lines 221 can be formed on top of the first word line 103, such as... Figure 7A As shown. In some embodiments, the width W3 of the control word line 221 may be greater than the width W1 of the first word line 103 (see...). Figure 1A-Figure 1B However, in other embodiments, the width W3 may be approximately equal to or less than the width W1. In some embodiments, the control word line 221 has a width W3 in the range of about 40 nm to about 80 nm, but other widths are possible.

[0053] In some embodiments, some control word lines 221 may extend from the sidewall of one memory stack 206 to the sidewall of an adjacent memory stack 206. In this way, some control word lines 221 may extend on the sidewalls of two adjacent memory stacks 206, and some control word lines 221 may extend on the sidewall of a single memory stack 206. For example, in some embodiments, control word lines 221 located at opposite ends of the first word line 103 may each extend on a single corresponding memory stack 206, and other control word lines 221 along the first word line 103 may each extend on two adjacent memory stacks 206. Other configurations or arrangements are possible. In some embodiments, some control word lines 221 are formed on and electrically connected to the corresponding first word line 103 through the first via 109. Figures 7A-7BAs shown, other control word lines 221 are not formed over the first via 109 and are therefore electrically isolated from the first word line 103. In some embodiments, control word lines 221 formed over the first word line 103 may be alternately connected to or isolated from the first word line 103. In this way, the formation of control word lines 221 allows storage cells 260 on either side of the storage stack 206 (see...) Figures 12C-12D (It) is under control.

[0054] exist Figures 8A-8B In some embodiments, a third dielectric layer 225 is deposited over control word lines 221. The third dielectric layer 225 may extend over and between control word lines 221. In this way, the third dielectric layer 225 may surround and separate the control word lines 221 to isolate them. The third dielectric layer 225 may be a material similar to the first dielectric layer 105 or the second dielectric layer 107, and may be formed using similar techniques. In some embodiments, a planarization process (e.g., CMP and / or polishing) may be performed after the deposition of the third dielectric layer 225. In some embodiments, the third dielectric layer 225 has a thickness in the range of about 15 nm to about 40 nm, but other thicknesses are possible.

[0055] exist Figures 9A-9B In some embodiments, an opening 227 is patterned in the third dielectric layer 225. The opening 227 may expose portions of the control word lines 221. In some embodiments, the opening 227 exposes portions of those control word lines 221 isolated from the first word line 103 (e.g., those control word lines 221 not formed above the first via 109). The opening 227 may be patterned using suitable photolithography and etching techniques. The size of the opening 227 may be larger than, approximately equal to, or smaller than the size of the first via 109.

[0056] exist Figures 10A-10BIn some embodiments, conductive material 231 is deposited over a third dielectric layer 225 and within an opening 227. In some embodiments, the conductive material 231 filling the opening 227 forms a second via 229. In some embodiments, the second via 229 may be electrically connected to some control word lines 221, such as those not electrically connected to the first word line 103. The conductive material 231 may include one or more materials, such as those previously described for the first word line 103, and may be deposited using similar techniques. For example, in some embodiments, the conductive material 231 may include tungsten deposited using CVD, but other materials or deposition techniques are possible. In some embodiments, a planarization process (e.g., CMP and / or polishing) may be performed on the conductive material 231 after deposition. In some embodiments, the conductive material 231 on the third dielectric layer 225 has a thickness in the range of about 30 nm to about 60 nm, but other thicknesses are possible.

[0057] exist Figures 11A-11B In some embodiments, conductive material 231 is patterned to form a second word line 233. The conductive material 231 can be patterned, for example, using suitable photolithography and etching techniques (e.g., those previously described). In some embodiments, the second word line 233 can be formed over the first word line 103 and the control word line 221, such as... Figure 11A As shown. In some embodiments, the width W4 of the second character line 233 may be greater than the width W1 of the first character line 103 (see...). Figure 1A-Figure 1B The width W4 of the second word line 221 may be approximately equal to or less than the width W1 or the width W3. In some embodiments, the second word line 233 has a width W4 in the range of about 40 nm to about 100 nm, but other widths are possible. In some embodiments, adjacent second word lines 233 are separated by a distance S3 in the range of about 40 nm to about 100 nm, but other separation distances are possible.

[0058] In some embodiments, a second word line 233 formed on a second via 229 is electrically connected to a corresponding control word line 221 through the second via 229. For example... Figures 11A-11BAs shown, the second word line 233 is electrically connected to some control word lines 221 through a second via 229, and the first word line 103 is electrically connected to other control word lines 221 through a first via 109. In some embodiments, the control word lines 221 along the second word line 233 may be alternately connected to the corresponding first word line 103 or the second word line 233. In this way, one side of the storage stack 206 may be covered by the control word lines 221 electrically connected to the first word line 103, and the other side of the storage stack 206 may be covered by the control word lines 221 electrically connected to the second word line 233. In other embodiments, the second via 229 may be formed using a separate processing or deposition step compared to the second word line 233.

[0059] exist Figures 12A-12D In some embodiments, a fourth dielectric layer 235 is deposited on the second word line 233 to form a memory structure 250. The fourth dielectric layer 235 may extend on and between the second word line 233. In this way, the fourth dielectric layer 235 may surround and separate the second word line 233 to isolate it. The fourth dielectric layer 235 may be a similar material to the first dielectric layer 105, the second dielectric layer 107, or the third dielectric layer 225, and may be formed using similar techniques. In some embodiments, a planarization process (e.g., CMP and / or polishing) may be performed after the fourth dielectric layer 235 is deposited. After the planarization process is performed, the top surfaces of the fourth dielectric layer 235 and the second word line 233 may be substantially flush.

[0060] Figure 12C It shows something similar to Figure 12B The storage structure 250 shown differs in that various features are labeled for illustrative purposes. For example, Figure 12C A first memory stack 206A and a second memory stack 206B are shown, each including a first bit line 201 (BL1) and a second bit line 209 (BL2), and each having a first control word line 221 (WLC1) on one side and a second control word line 221 (WLC2) on the other side. The first control word line 221 (WLC1) is connected to the first word line 103 (WL1), and the second control word line 221 (WLC2) is connected to the second word line 233 (WL2). Figure 12CAs shown, each memory stack 206 and its adjacent control word lines 221 (WLC1, WLC2) form four memory cells 260A, 260B, 260C, and 260D. For example, memory cells 260B and 260D are formed on top of memory cells 260A and 260C, respectively. Memory cells 260A and 260B are formed on one side of the memory stack 206 and include different regions of the same layer of storage material 211 and selectable material 213 deposited on that side, and memory cells 260C and 260D are formed on the other side of the memory stack 206 and include different regions of the same layer of storage material 211 and selectable material 213 deposited on that side. Using the techniques described herein, separate memory cells 260 can be formed on both sides of the memory stack 206, which can increase the density of memory cells in a memory structure or device.

[0061] The first bit line 201 (BL1), the second bit line 209 (BL2), the first control word line 221 (WLC1), and the second control word line 221 (WLC2) can be used to independently perform read and write operations on each of the four memory cells 260A-D. For example, the memory cells 260A of the first memory stack 206A can be controlled by applying a bias voltage to the first word line 103 (WL1) and the first bit line 201 (BL1). The first word line 103 (WL1) is electrically connected to the first control word line 221 (WLC1) through the first via 109 (VIA1), so biasing the first word line 103 (WL1) allows the first control word line 221 (WLC1) to also be biased. In this way, a corresponding voltage difference is formed across the portions of the storage material 211 and the selection material 213 located between the first bit line 201 (BL1) and the first control word line 221 (WLC1). In some embodiments, applying appropriate bias in this manner allows read and write operations to memory cell 260A to be performed independently of adjacent memory cells 260B-D. Similarly, memory cell 260B can be controlled by applying bias to the second bit line 209 (BL2) and the first word line 103 (WL1), memory cell 260C can be controlled by applying bias to the first bit line 201 (BL1) and the second word line 233 (WL2), and memory cell 260D can be controlled by applying bias to the second bit line 209 (BL2) and the second word line 233 (WL2). In this manner, any memory cell 260 of the memory array 262 (see [link to relevant documentation]) can be controlled by biasing the corresponding first bit line 201 / second bit line 209 and the corresponding word lines 103 / 233. Figure 12D ).

[0062] As described above, in some embodiments, individual word lines (e.g., first word line 103 and second word line 233) are formed as two separate layers above and below control word line 221. In this way, one word line (e.g., first word line 103) can control memory cells 260A-B located on one side of the first bit line 201 / second bit line 209, and another word line (e.g., second word line 233) can control memory cells 260C-D located on the other side of the first bit line 201 / second bit line 209. Therefore, by placing individual word lines in different layers, the number of memory cells 260 can be doubled within the same area without area loss and without the need for dummy cells. Furthermore, by forming separate first bit lines 201 / second bit lines 209, the number of memory cells 260 can be further doubled within the same area without area loss. In this way, in some cases, the techniques described herein can allow the storage density of a memory structure or device to be increased by up to four times. Other configurations or densities are possible.

[0063] Figure 12D An unfolded plan view of a memory array 262 including memory cells 260 according to some embodiments is shown. For clarity, some features are not shown. Figure 12D As shown in the plan view. Figure 12D An example reference section C-C' is also shown, which can correspond to Figure 12C The cross-sectional view shown. The memory array 262 includes a plurality of memory cells 260, which can be independently controlled using corresponding first bit line 201 / second bit line 209 and word lines 103 / 233, as previously described. Memory cell 260B is above and overlaps with corresponding memory cell 260A, and memory cell 260D is above and overlaps with corresponding memory cell 260C. Figure 12DAs shown, memory cells 260 can be arranged in an array of rows and columns. In some embodiments, the first word line 103 and the second word line 233 are parallel, and the first bit line 201 / second bit line 209 is perpendicular to the word lines 103 / 233. Additional memory structures 250 can be further stacked vertically to provide a three-dimensional memory array, thereby increasing device density. In some embodiments, the memory array 262 can be disposed in the back-end process (BEOL) of a semiconductor die. For example, the memory array 262 can be disposed in the interconnect layer of the semiconductor die, for example, over one or more active devices (e.g., transistors, etc.) formed on a semiconductor substrate. For example, the memory array 262 can be disposed over a FinFET device, and the first bit line 201 / second bit line 209 can be parallel to or cover the fins of the FinFET device, and the word lines 103 / 233 can be parallel to or cover the gate structure of the FinFET device. This is an example, and other devices, structures, arrangements, or configurations are possible. In some embodiments, the first word line 103 or the second word line 233 can be combined with conductive lines of logic circuitry within the semiconductor die. This is for the following Figures 13-14 Further description.

[0064] Figure 13 The following is illustrated after further processing according to some embodiments. Figure 12B The cross-sectional view of the structure is shown. Specifically, Figure 13 A second metallization layer 302 is shown formed on memory structure 250 according to some embodiments. The second metallization layer 302 may be formed on second word line 233 to electrically connect the second word line 233 to other functional circuitry. In some embodiments, the second metallization layer 302 may be connected to the first word line 103 or the first metallization layer 102 via vias (not shown). The second metallization layer 302 may, for example, be connected to the first metallization layer 102 (see...). Figure 1A-Figure 1B Similar methods and materials can be used to form it, but other technologies or materials are possible.

[0065] As a representative example Figure 13 The second metallization layer 302 is shown to include a dielectric layer 305 covering the second word line 233, a conductive line 307 covering the dielectric layer 305, and a conductive via 303 extending through the dielectric layer 305 to electrically connect the second word line 233. In some embodiments, the conductive line 307 may be part of a logic circuit or another type of circuit, and the second metallization layer 302 may have any suitable number of conductive layers, dielectric layers, or conductive vias.

[0066] Figure 14 A cross-sectional view of a semiconductor device 350 including a memory structure 250 according to some embodiments is shown. The memory structure 250 may be similar to those previously described for... Figures 12A-12DThe described memory structure 250 or memory array 262. In some embodiments, the semiconductor device 350 includes a first metallization layer 102 and a second metallization layer 302 formed on a substrate 101. The first metallization layer 102, the second metallization layer 302, and the substrate 101 of the semiconductor device 350 may be similar to those previously described for... Figure 1A-Figure 1B and Figure 13 The aforementioned methods can be used to form such structures using similar techniques or materials. In some embodiments, the semiconductor device 350 has a logic region 351 and a storage region 353 on a substrate 101. In some embodiments, a storage structure 250 may be formed between a first metallization layer 102 and a second metallization layer 302 of the semiconductor device 350. For example, in some embodiments, the storage structure 250 may be formed between conductive lines 111 and 307.

[0067] In some cases, the logic region 351 of the semiconductor device 350 includes active devices, passive devices, logic devices, etc. In some embodiments, the memory structure 250 may be formed in the memory region 353 but not in the logic region 351. Therefore, the region of the logic region 351 at or near the same level as the memory structure 250 may be filled with one or more dielectric materials, which may include one or more of the aforementioned dielectric layers, such as dielectric layer 110, first dielectric layer 105, second dielectric layer 107, third dielectric layer 225, dielectric layer 305, etc. For clarity, these and other various dielectric layers are not shown separately.

[0068] Figure 14 The formation of a conductive via 355 is also illustrated, which extends through one or more dielectric materials to connect conductive lines 111 and 307 within logic region 351. The conductive via 355 can be formed, for example, using similar techniques or materials as those used for conductive via 303, but other techniques or materials are possible. In some embodiments, the conductive via 355 can be formed using one or more of the same process steps as forming conductive via 303, but in other embodiments, the conductive via 355 can be formed before or after conductive via 303. By incorporating memory structure 250 into the metallization layer of semiconductor device 350 as described herein, semiconductor device 350 can have greater design flexibility and improved memory density. For example, in some cases, multiple overlapping word lines 103 / 233 and overlapping first bit lines 201 / second bit lines 209 of memory structure 250 can be connected to different metal layers of logic region 351.

[0069] Figures 15A-17B A memory structure 252 is shown according to some embodiments (see [link]). Figure 17BThe intermediate steps of ). Storage structure 252 is similar to Figures 12A-12C The memory structure 250 shown differs in that memory structure 252 includes a portion of hard mask 210 above bit line stack 204. By leaving a portion of hard mask 210 on bit line stack 204, the risk of leakage between second via 229 and second bit line 209 can be reduced or eliminated. In this way, in some cases, including as... Figures 15A-17B The hard mask 210 shown can increase the yield window during processing. Figures 15A-17B The techniques described herein can be applied to other embodiments of this disclosure.

[0070] Figures 15A-15B The formation of a bit line stack 204 according to some embodiments is shown. The bit line stack 204 is similar to Figures 3A-3B Those shown can be formed in a similar manner, except that the patterned hard mask 210 used as an etching mask remains on the bit line stack 204 after the bit line layer 202 is etched. In some embodiments, the portion of the hard mask 210 remaining on the bit line stack 204 has a thickness T3 in the range of about 10 nm to about 30 nm, but other thicknesses are possible.

[0071] exist Figures 16A-16B In some embodiments, storage material 211 and selection material 213 are formed. Storage material 211 and selection material 213 can be similar to... Figures 4A-5B Those shown, and can be formed in a similar manner, differ in that, in addition to the sidewalls of the bitline stack 204, the storage material 211 and the selection material 213 are also deposited on the sidewalls of the hard mask 210. As shown... Figure 16B As shown, it can be used with the previously targeted Figures 5A-5B A similar technique described removes storage material 211 and selects material 213 from a horizontal surface. In this way, a storage stack 206 including a hard mask 210 is formed.

[0072] Figures 17A-17B A memory structure 252, comprising a hard mask 210, is shown according to some embodiments. During the formation... Figures 16A-16B Following the storage stack 206 shown, execution can be performed against... Figures 6A-12B Similar processing steps are described to form the memory structure 252. In some embodiments, the memory stack 206 of the memory structure 252 may have a thickness T4 in the range of about 110 nm to about 230 nm, but other thicknesses are possible. As described above, the presence of the hard mask 210 can improve the electrical isolation between the second via 229 and the second bit line 209 of the memory structure 252. In some embodiments, for example, previously described for... Figures 13-14 The additional processing steps described.

[0073] Figures 18A-22B A memory structure 254 is shown according to some embodiments (see [link]). Figure 22B The intermediate steps of ). Storage structure 254 is similar to Figures 12A-12C The memory structure 250 shown differs from memory structure 254 in that the memory material 211 and the selectable material 213 are sequentially deposited and etched. In this way, a memory material 211 with a substantially constant thickness can be formed on the sidewalls of the bit line stack 204, and therefore, it is not necessary to have, for example, the previously described, [missing information]. Figure 5B The “L-shaped” profile is shown. Furthermore, in some embodiments, the techniques described herein allow the selection material 213 to be formed to generally extend the entire height of the sidewalls of the bitline stack 204. By forming the storage material 211 and the selection material 213 separately as described herein, improved control over the removal of horizontal portions of the storage material 211 or the selection material 213 can be achieved. Figures 18A-22B The techniques described herein can be applied to other embodiments of this disclosure.

[0074] Figures 18A-18B The deposition of storage material 211 according to some embodiments is illustrated. Storage material 211 can be formed, for example, as a cover. Figures 3A-3B The structure shown is a blanket layer. Storage material 211 can be similar to that used for... Figures 4A-4B The aforementioned storage material, and can be formed in a similar manner. Figures 19A-19B In some embodiments, an etching process is performed to remove portions of the storage material 211 from the horizontal surface. The etching process can be similar to that used for... Figures 5A-5B One or more etching processes are described. For example, according to some embodiments, the etching process may leave some portions of the storage material 211 on the sidewalls of the bit line stack 204.

[0075] Figures 20A-20B The deposition of selective material 213 according to some embodiments is shown. Selective material 213 can be formed, for example, as a cover. Figures 19A-19B The blanket-like layer of the structure shown. The choice of material 213 can be similar to that used for… Figures 4A-4B The selected materials can be formed in a similar manner. Figures 21A-21B In some embodiments, an etching process is performed to remove portions of selected material 213 from a horizontal surface to form a storage stack 206. The etching process can be similar to that used for... Figures 5A-5B One or more etching processes are described. For example, according to some embodiments, the etching process may leave some portions of the selected material 213 on the sidewalls of the bit line stack 204 (e.g., on the storage material 211).

[0076] Figures 22A-22BThe formation of a storage structure 254 according to some embodiments is shown. In the formation... Figures 21A-21B Following the storage stack 206 shown, operations can be performed targeting... Figures 6A-12B Similar processing steps are described above to form storage structure 254. In some embodiments, for example, previously performed for... Figures 13-14 The additional processing steps described.

[0077] Figures 23A-32B A memory structure 450 is shown according to some embodiments (see [link]). Figures 32A-32B The intermediate steps of ). Storage structure 450 is similar to that for Figures 12A-12D The described memory structure 250 differs in that the memory structure 450 includes a bit line stack 404 having a first electrode 402 / second electrode 408 protruding from the sidewalls of the bit line stack 404. The first electrode 402 / second electrode 408 can allow for improved device performance, efficiency, and reproducibility, as described in more detail below. In some cases, the first electrode 402 can be considered part of a first bit line 201, and the second electrode 408 can be considered part of a second bit line 209.

[0078] Figures 23A-23B The deposition of bit line layer 401 according to some embodiments is illustrated. According to some embodiments, bit line layer 401 is then patterned to form first bit line 201 and second bit line 209 of memory structure 450 (see [link]). Figures 24A-24B ), and the first electrode 402 and the second electrode 408 of the storage structure 450 (see Figures 26A-26B In some embodiments, bit line layer 401 may include a first bit line material, a first electrode material, a first adhesive layer 203, an insulating layer 205, a second adhesive layer 207, a second electrode material, and a second bit line material. In some embodiments, the first bit line material, the first adhesive layer 203, the insulating layer 205, the second adhesive layer 207, and the second bit line material are the same as those previously used for… Figures 2A-2B Similar materials have been described, and similar techniques can be used for deposition. These various material layers can have properties similar to those previously described. Figures 2A-2B The thickness is similar to that described, or it may have a different thickness than previously described. In some embodiments, a hard mask may be deposited on top of the bit line layer 401. Figures 23A-23B (Not shown in the image) for use during subsequent patterning steps. A hard mask can be similar to that used for... Figures 2A-2B The hard mask 210 is described.

[0079] In some embodiments, a first electrode material is located between a first bit line material and a first adhesion layer 203, and a second electrode material is located between a second adhesion layer 207 and a second bit line material. The first electrode material / second electrode material comprises a conductive material that may differ from the first bit line material / second bit line material. For example, in some embodiments, the first electrode material / second electrode material comprises materials such as ruthenium, tungsten, copper, titanium, titanium nitride, tantalum, tantalum nitride, combinations thereof, etc. The first electrode material / second electrode material can be deposited using suitable techniques, such as electroplating, CVD, PVD, PECVD, ALD, etc. In some embodiments, the first electrode material and the second electrode material may each have a thickness in the range of about 2 nm to about 5 nm, but other thicknesses are possible.

[0080] In some embodiments, the first electrode material / second electrode material is a material that has a lower etching rate than the first bit line material / second bit line material for certain etching processes. In other words, the materials of the first bit line material / second bit line material and the first electrode material / second electrode material can be selected such that a selective etching process can selectively etch the first bit line material / second bit line material relative to the first electrode material / second electrode material. In some embodiments, the selective etching process can selectively etch the material of the first adhesion layer 203 / second adhesion layer 207 relative to the first electrode material / second electrode material. For example, in some embodiments, the first bit line material / second bit line material can be tungsten, and the first electrode material / second electrode material can be ruthenium, but other materials are possible.

[0081] Figures 24A-24B A patterned bitline layer 401 is illustrated according to some embodiments to form a bitline stack 404. The bitline stack 404 can be patterned from the bitline layer 401 using suitable photolithographic masking and etching processes, such as those previously described for patterning the bitline stack 204 (see [link to documentation]). Figures 3A-3BFor example, a hard mask can be patterned over bit line layer 401, and the pattern of the hard mask can then be transferred to bit line layer 401 using one or more acceptable etching processes. In this way, the pattern of the hard mask extends through bit line layer 401, patterning a first bit line material to define a first bit line 201 and patterning a second bit line material to define a second bit line 209. In some embodiments, one or more layers of bit line layer 401 can be etched using an etching process different from one or more other layers of bit line layer 401. In some embodiments, the hard mask can be removed during or after the formation of bit line stack 404. In some embodiments, bit line stack 404 has a thickness T5 in the range of about 100 nm to about 200 nm, but other thicknesses are also possible. In some embodiments, bit line stack 404 has a width W4 in the range of about 40 nm to about 100 nm, but other widths are also possible.

[0082] exist Figures 25A-25B In some embodiments, a first selective etching process is performed on the bit line stack 404 to form a first electrode 402 and a second electrode 408. In some embodiments, the first selective etching process selectively etches the surfaces of the first bit line 201, the second bit line 209, the first adhesion layer 203, and the second adhesion layer 207 relative to the surfaces of the first electrode material and the second electrode material. For example, during the first selective etching process, a first etching rate of the first bit line material / second bit line material may be greater than a second etching rate of the first electrode material / second electrode material. In some embodiments, the ratio of the first etching rate to the second etching rate is in the range of about 10:1 to about 100:1, but other ratios are also possible. In this way, the first selective etching process causes the sidewalls of the first bit line 201 / second bit line 209 and the first adhesion layer 203 / second adhesion layer 207 to be recessed, leaving some portions of the first electrode material and the second electrode material protruding from the sidewalls of the bit line stack 404. After performing the first selective etching process, the remaining portion of the first electrode material forms the first electrode 402, and the remaining portion of the second electrode material forms the second electrode 408.

[0083] In some cases, the first selective etching process can cause the first bit line 201 / second bit line 209 to be recessed by an amount different from that of the first adhesive layer 203 / second adhesive layer 207. In some cases, the first selective etching process can cause the first bit line 201 to be recessed by an amount different from that of the second bit line 209. In some cases, the top surface of the second bit line 209 is etched by the first selective etching process. In some embodiments, a hard mask remains on the second bit line 209 to protect the top surface of the second bit line 209 during the first selective etching process. In some embodiments, the hard mask can be removed after performing the first selective etching process. In other embodiments, the hard mask is not removed, and example embodiments thereof are described below. Figures 33A-33B As shown in the image.

[0084] The first selective etching process may include one or more wet and / or dry etching processes. For example, the first selective etching process may be a plasma etching process that includes chlorine as the process gas, but other process gases, or mixtures of process gases, are also possible. In some embodiments, the first selective etching process may have a process pressure in the range of about 1 mTorr to about 10 mTorr, but other pressures are also possible. In some embodiments, the first selective etching process may use a plasma power in the range of about 40 W to about 800 W, a bias power in the range of about 0 W to about 200 W, or an etching time in the range of about 5 seconds to about 100 seconds. This is an example, and other selective etching processes or process parameters are possible for the first selective etching process.

[0085] exist Figures 26A-26B In some embodiments, a second selective etching process is performed on the bit line stack 404 to recess the sidewalls of the insulating layer 205. In some embodiments, the second selective etching process selectively etches the surfaces of the insulating layer 205 relative to the surfaces of the first bit line 201 / second bit line 209, the first adhesion layer 203 / second adhesion layer 207, and the first electrode 402 / second electrode 408. For example, during the second selective etching process, the insulating layer 205 may be etched at a higher rate than the other layers of the bit line stack 404. The second selective etching process may include one or more wet and / or dry etching processes. For example, the second selective etching process may include wet diluted HF (“dHF”) etching, etc. This is an example, and other selective etching processes are possible for the second selective etching process. In some embodiments, the second selective etching process is not performed.

[0086] In some embodiments, after performing the second selective etching process, the first bit line 201 / second bit line 209 has a width W6, the first electrode 402 / second electrode 408 has a width W7, the first adhesive layer 203 / second adhesive layer 207 has a width W8, and the insulating layer 205 has a width W9. In some cases, the width W6 of the first bit line 201 may be different from the width W6 of the second bit line 209. In some cases, the width W8 of the first adhesive layer 203 may be different from the width W8 of the second adhesive layer 207. In some embodiments, the width W9 of the insulating layer 205 is approximately equal to or less than the width W6 of the first bit line 201 / second bit line 209 and / or the width W8 of the first adhesive layer 203 / second adhesive layer 207. In some cases, the width W7 of the first electrode 402 may be different from the width W7 of the second electrode 408. In some embodiments, the width W7 of the first electrode 402 / second electrode 408 is greater than the width W6 of the first bit line 201 / second bit line 209, the width W8 of the first adhesive layer 203 / second adhesive layer 207, and / or the width W9 of the insulating layer 205. In some embodiments, the width W6 of the first bit line 201 / second bit line 209 is in the range of about 30 nm to about 90 nm, the width W7 of the first electrode 402 / second electrode 408 is in the range of about 40 nm to about 100 nm, the width W8 of the first adhesive layer 203 / second adhesive layer 207 is in the range of about 30 nm to about 90 nm, and the width W9 of the insulating layer 205 is in the range of about 20 nm to about 80 nm. Other widths are also possible.

[0087] The protruding portions (e.g., "ends") of the first electrode 402 / second electrode 408 can be formed with various profiles, which can provide advantages. As an illustrative example, Figures 27A-27C Each showed Figure 26B An enlarged view of region 27 indicated in the image, which includes the protruding portion of the first electrode 402. (See image below.) Figure 27A As shown, the protruding portion of the first electrode 402 can protrude from the first line 201 by a distance L1 ranging from approximately 5 nm to approximately 30 nm, but other distances are also possible. As an example, according to some embodiments, Figure 27A A first electrode 402 with a protruding portion including a flat end is shown. Figure 27B A first electrode 402 with a protruding portion including a rounded (e.g., convex) end is shown, and Figure 27CA first electrode 402 with a protrusion including a stepped and tapered end is shown. These are examples, and the first electrode 402 / second electrode 408 may have protrusions with other profiles (e.g., pointed, tapered, irregular, angled, chamfered, concave) or other shapes or profiles. In some embodiments, the profile of the protrusion can be controlled by controlling parameters of the first selective etching process and / or the second selective etching process. In some cases, the first electrode 402 / second electrode 408 with a relatively narrow end or a tapered end can allow for the formation of a more localized electric field, which can improve device efficiency and reproducibility during operation (explained in more detail below). Although Figures 27A-27C The protruding portion of the first electrode 402 is shown, but this discussion applies to the protruding portions of either the first electrode 402 or the second electrode 408.

[0088] exist Figures 28A-28B In some embodiments, storage material 211 and selection material 213 are deposited on bit line stack 404. Storage material 211 and selection material 213 can be used in conjunction with previously designed materials. Figures 4A-4B The description is similar, and similar techniques can be used for deposition. In some embodiments, storage material 211 and / or selection material 213 are conformally deposited on the bit line stack 404. Figures 29A-29B In some embodiments, one or more etching processes are performed to remove portions of storage material 211 and selected material 213 to form storage stack 406. These one or more etching processes can be similar to those previously performed for... Figures 5A-5B The etching processes described. After one or more etching processes, the bit line stack 404 and the remaining memory material 211 and select material 213 form the memory stack 406. In other embodiments, the memory material 211 and select material 213 may be deposited and etched in separate steps, similar to those described for... Figures 18A-22B The described process.

[0089] Figures 30A-30B The diagram illustrates the formation of a control word line 221 and a third dielectric layer 225 according to some embodiments. The control word line 221 can be similar to that previously described for... Figures 7A-7B The control word line 221 is described and can be formed using similar techniques. For example, the control word line 221 can be formed on the opposite side of the memory stack 406. The third dielectric layer 225 can be similar to that previously described. Figures 8A-8B The third dielectric layer 225 is described and can be formed using similar techniques. For example, the third dielectric layer 225 can be deposited on the memory stack 406 and the control word line 221.

[0090] Figures 31A-31BThe formation of a second word line 233 according to some embodiments is shown. The second word line 233 can be similar to that previously described. Figures 11A-11B The second word line 233 is described, and can be formed in a similar manner. For example, the second word line 223 can be connected to the control word line 221 via the second via 229.

[0091] exist Figures 32A-32B In some embodiments, a fourth dielectric layer 235 is deposited on the second word line 233 to form a memory structure 450 having a first electrode 402 / a second electrode 408. The fourth dielectric layer 235 can be similar to those previously used for... Figures 12A-12D The fourth dielectric layer 235 is described, and can be formed in a similar manner. In some embodiments, the storage structure 450 can be similar to... Figures 12A-12D The memory structure 250 shown differs in that it includes a first electrode 402 / a second electrode 408 and layers within the bit line stack 404 have different widths. (As shown...) Figure 32B As shown, each memory stack 406 and its adjacent control word line 221 form four memory cells 460A, 460B, 460C and 460D.

[0092] Storage unit 460A-D can be used with... Figures 12C-12DThe described memory cells 260A-D are similarly controlled. For example, read and write operations can be performed on a specific memory cell 460 by applying appropriate voltage biases to the corresponding first word line 103, second word line 233, and first bit line 201 / second bit line 209. A first electrode 402 is electrically connected to the first bit line 201, and a second electrode 408 is electrically connected to the second bit line 209. In some cases, during read / write operations, the electric field formed near the ends of the first electrode 402 / second electrode 408 (e.g., near the end of the first electrode) can be larger and / or more localized than the electric field formed near the sidewalls of the first bit line 201 / second bit line 209. Because the first electrode 402 / second electrode 408 is thinner than the first bit line 201 / second bit line 209, and because the ends of the first electrode 402 / second electrode 408 protrude outward from the bit line stack 404, a relatively large electric field can be formed near the ends of the first electrode 402 / second electrode 408. As previously mentioned, for some types of resistive memories, the resistive state of the storage material region within a memory cell can be altered by an electric field. Therefore, within memory cell 460, a relatively large electric field localized near the ends of the first electrode 402 / second electrode 408 can localize the resistance variation region of the storage material 211 near those ends. By promoting the occurrence of the resistance variation region of memory cell 460 near the first electrode 402 / second electrode 408 in this manner, read / write operations on memory cell 460 can be more efficient, reliable, and / or reproducible. Therefore, the embodiments described herein can realize a memory structure 450 with higher density and greater device performance.

[0093] Figures 33A-33B A storage structure 452 according to some embodiments is shown. Storage structure 452 is similar to that for... Figures 23A-32B The described memory structure 450 differs in that the hard mask 210 remains on the bit line stack 404. This is similar to the previous one for... Figures 15A-17B The described embodiment. By leaving some portions of the hard mask 210 on the bit line stack 404, the distance between the second via 229 and the second bit line 209 can be increased, which can reduce the chance of leakage or short circuit.

[0094] The embodiments described herein offer advantages. For example, by utilizing a memory structure with two overlapping bit lines and a shared control word line shared on each side of these two bit lines, the density of the memory array can be increased by up to four times. Furthermore, by using two sets of overlapping word lines connected to the control word line (e.g., a word line above and a word line below the control word line), the density of the memory array can be increased with minimal or no area loss. In this way, in some cases, the density of the memory array can be increased without increasing the overall footprint of the memory array. In some cases, the memory structures described herein can be incorporated into the BEOL layer (e.g., a metallization layer) of the semiconductor device, and thus can be formed at a lower cost and with fewer changes to existing manufacturing processes. In some embodiments, electrodes with protruding ends are formed in the memory cells, which can help localize resistance variation regions in the memory cells. Localizing resistance variation regions in this way can improve the reproducibility of the memory array, reduce variability, and improve operating efficiency. The memory structures and memory arrays described herein can be formed without forming dummy or non-functional memory cells.

[0095] According to one embodiment, a method of manufacturing a semiconductor device includes: forming a first word line on a substrate; forming a bit line stack, including: forming a first bit line on the first word line, wherein the first bit line includes a first material; forming an insulating layer on the first bit line; and forming a second bit line on the insulating layer, wherein the second bit line includes the first material; depositing a storage material on the bit line stack, wherein the storage material extends along a first sidewall and along a second sidewall of the bit line stack; depositing a conductive material on the storage material, wherein a first portion of the conductive material along the first sidewall is electrically isolated from a second portion of the conductive material along the second sidewall; and forming a second word line on the conductive material, wherein the second word line is electrically connected to a second portion of the conductive material. In one embodiment, the method includes: depositing a bidirectional threshold switch (OTS) material on the storage material. In one embodiment, forming the bit line stack includes using a patterned hard mask as an etch mask, and wherein the storage material is deposited on the sidewall of the patterned hard mask. In one embodiment, forming a bit line stack includes: forming a first electrode on a first bit line, wherein the first electrode protrudes from a sidewall of the first bit line; and forming a second electrode over an insulating layer, wherein a second bit line is formed on the second electrode, wherein the second electrode protrudes from a sidewall of the second bit line. In one embodiment, the first electrode and the second electrode comprise a second material different from the first material, wherein forming the bit line stack further includes: performing an etching process that selectively etches the first material relative to the second material. In one embodiment, the first material is tungsten and the second material is ruthenium. In one embodiment, the first word line is electrically connected to a first portion of a conductive material. In one embodiment, forming the bit line stack includes: using an etching process to recess an insulating layer that selectively etches the insulating layer relative to the first material. In one embodiment, the sidewalls of the first bit line, the insulating layer, and the second bit line are coplanar.

[0096] According to one embodiment, a method includes: forming a first word line on a substrate; forming a memory stack on the first word line, wherein each memory stack includes a first sidewall and a second sidewall, wherein forming each memory stack includes: forming a first bit line on at least one first word line; forming a second bit line on the first bit line, wherein the second bit line is electrically isolated from the first bit line; depositing a resistive memory layer along the sidewall of the first bit line and the sidewall of the second bit line; and depositing a select layer on the resistive memory layer; forming control word lines on the memory stack, wherein each control word line extends from a first sidewall of a first corresponding memory stack to a second sidewall of a second corresponding memory stack; and forming a second word line on the memory stack and the control word line, wherein each control word line is electrically connected to either the first word line or the second word line. In one embodiment, forming each memory stack includes: performing at least one etching process to remove horizontal portions of the resistive memory layer and the select layer. In one embodiment, after performing at least one etching process, the resistive memory layer has an "L-shaped" profile. In one embodiment, the first bit line includes a first electrode layer and the second bit line includes a second electrode layer, wherein the first electrode layer and the second electrode layer protrude laterally. In one embodiment, the thicknesses of the first electrode layer and the second electrode layer are in the range of 2 nm to 5 nm. In one embodiment, the first bit line includes a first adhesion layer and the second bit line includes a second adhesion layer. In one embodiment, the second bit line is electrically isolated from the first bit line by an oxide layer.

[0097] According to one embodiment, a semiconductor device includes: a memory structure on a substrate, wherein the memory structure includes a first word line; a first bit line on the first word line; a second bit line on the first bit line; a memory material on sidewalls of the first and second bit lines; a first control word line along a first side of the memory material, wherein the first control word line is electrically connected to the first word line; a second control word line along a second side of the memory material opposite to the first side; and a second word line on the second bit line, the first control word line, and the second control word line, wherein the second word line is electrically connected to the second control word line. In one embodiment, the memory structure includes a first electrode contacting the first bit line and a second electrode contacting the second bit line, wherein the widths of the first and second electrodes are greater than the widths of the first and second bit lines. In one embodiment, the memory structure includes four individual memory cells. In one embodiment, the semiconductor device includes a metallization layer on a substrate, wherein the memory structure is on the metallization layer.

[0098] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0099] Example 1 is a method of manufacturing a semiconductor device, the method comprising: forming a first word line on a substrate; forming a bit line stack, comprising: forming a first bit line on the first word line, wherein the first bit line comprises a first material; forming an insulating layer on the first bit line; and forming a second bit line on the insulating layer, wherein the second bit line comprises the first material; depositing a storage material on the bit line stack, wherein the storage material extends along a first sidewall and a second sidewall of the bit line stack; depositing a conductive material on the storage material, wherein a first portion of the conductive material along the first sidewall is electrically isolated from a second portion of the conductive material along the second sidewall; and forming a second word line on the conductive material, wherein the second word line is electrically connected to a second portion of the conductive material.

[0100] Example 2 is the method of Example 1, further comprising: depositing a bidirectional threshold switch (OTS) material on the storage material.

[0101] Example 3 is the method of Example 1, wherein forming the bit line stack includes: using a patterned hard mask as an etch mask, and wherein the storage material is deposited on the sidewalls of the patterned hard mask.

[0102] Example 4 is the method described in Example 1, wherein forming the bit line stack further includes: forming a first electrode on the first bit line, wherein the first electrode protrudes from a sidewall of the first bit line; and forming a second electrode on the insulating layer, wherein the second bit line is formed on the second electrode, wherein the second electrode protrudes from a sidewall of the second bit line.

[0103] Example 5 is the method of Example 4, wherein the first electrode and the second electrode comprise a second material different from the first material, wherein forming the bit line stack further comprises: performing an etching process that selectively etches the first material relative to the second material.

[0104] Example 6 is the method described in Example 5, wherein the first material is tungsten and the second material is ruthenium.

[0105] Example 7 is the method described in Example 1, wherein the first word line is electrically connected to a first portion of the conductive material.

[0106] Example 8 is the method of Example 1, wherein forming the bit line stack further includes: using an etching process to recess the insulating layer, the etching process selectively etching the insulating layer relative to the first material.

[0107] Example 9 is the method described in Example 1, wherein the sidewalls of the first bit line, the insulating layer, and the second bit line are coplanar.

[0108] Example 10 is a method of manufacturing a semiconductor device, comprising: forming a first word line on a substrate; forming a memory stack on the first word line, wherein each memory stack includes a first sidewall and a second sidewall, wherein forming each memory stack includes: forming a first bit line on at least one first word line; forming a second bit line on the first bit line, wherein the second bit line is electrically isolated from the first bit line; depositing a resistive memory layer along the sidewalls of the first bit line and the sidewalls of the second bit line; and depositing a select layer on the resistive memory layer; forming control word lines on the memory stack, wherein each control word line extends from a first sidewall of a first corresponding memory stack to a second sidewall of a second corresponding memory stack; and forming a second word line on the memory stack and the control word line, wherein each control word line is electrically connected to either the first word line or the second word line.

[0109] Example 11 is the method of Example 10, wherein forming each memory stack further includes performing at least one etching process to remove the horizontal portions of the resistive memory layer and the select layer.

[0110] Example 12 is the method of Example 11, wherein, after performing the at least one etching process, the resistive storage layer has an "L-shaped" profile.

[0111] Example 13 is the method described in Example 10, wherein the first bit line includes a first electrode layer and the second bit line includes a second electrode layer, wherein the first electrode layer and the second electrode layer protrude laterally.

[0112] Example 14 is the method described in Example 13, wherein the thicknesses of the first electrode layer and the second electrode layer are in the range of 2 nm to 5 nm.

[0113] Example 15 is the method of Example 10, wherein the first bit line includes a first adhesive layer and the second bit line includes a second adhesive layer.

[0114] Example 16 is the method described in Example 10, wherein the second bit line is electrically isolated from the first bit line through an oxide layer.

[0115] Example 17 is a semiconductor device comprising: a memory structure on a substrate, wherein the memory structure includes: a first word line; a first bit line on the first word line; a second bit line on the first bit line; a memory material on sidewalls of the first bit line and the second bit line; a first control word line along a first side of the memory material, wherein the first control word line is electrically connected to the first word line; a second control word line along a second side of the memory material opposite to the first side; and a second word line on the second bit line, the first control word line, and the second control word line, wherein the second word line is electrically connected to the second control word line.

[0116] Example 18 is the semiconductor device described in Example 17, wherein the memory structure further includes a first electrode in contact with the first bit line and a second electrode in contact with the second bit line, wherein the widths of the first electrode and the second electrode are greater than the widths of the first bit line and the second bit line.

[0117] Example 19 is the semiconductor device described in Example 17, wherein the memory structure includes four separate memory cells.

[0118] Example 20 is the semiconductor device described in Example 17, further comprising: a plurality of metallization layers on the substrate, wherein the storage structure is on the plurality of metallization layers.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: The first letter line is formed on the substrate; Forming a bitline stack includes: A first position line is formed above the first character line, wherein the first position line comprises a first material; An insulating layer is formed on the first line; and A second bit line is formed on the insulating layer, wherein the second bit line comprises the first material; Storage material is deposited on the bit line stack, wherein the storage material extends along a first sidewall of the bit line stack and along a second sidewall of the bit line stack; A conductive material is deposited on the storage material, wherein a first portion of the conductive material along the first sidewall is electrically isolated from a second portion of the conductive material along the second sidewall; and A second word line is formed on the conductive material, wherein the second word line is electrically connected to a second portion of the conductive material. The formation of the bit line stack further includes: A first electrode is formed on the first bit line, wherein the first electrode protrudes from the sidewall of the first bit line.

2. The method according to claim 1, further comprising: A bidirectional threshold switch (OTS) material is deposited on the storage material.

3. The method according to claim 1, wherein, Forming the bit line stack includes using a patterned hard mask as an etching mask, wherein the storage material is deposited on the sidewalls of the patterned hard mask.

4. The method according to claim 1, wherein, Forming the bit line stack further includes: A second electrode is formed on the insulating layer, wherein a second bit line is formed on the second electrode, and wherein the second electrode protrudes from the sidewall of the second bit line.

5. The method according to claim 4, wherein, The first electrode and the second electrode comprise a second material different from the first material, wherein forming the bit line stack further comprises performing an etching process that selectively etches the first material relative to the second material.

6. The method according to claim 5, wherein, The first material is tungsten and the second material is ruthenium.

7. The method according to claim 1, wherein, The first word line is electrically connected to a first portion of the conductive material.

8. A method for manufacturing a semiconductor device, the method comprising: The first letter line is formed on the substrate; Forming a bitline stack includes: A first position line is formed above the first character line, wherein the first position line comprises a first material; An insulating layer is formed on the first line; and A second bit line is formed on the insulating layer, wherein the second bit line comprises the first material; Storage material is deposited on the bit line stack, wherein the storage material extends along a first sidewall of the bit line stack and along a second sidewall of the bit line stack; A conductive material is deposited on the storage material, wherein a first portion of the conductive material along the first sidewall is electrically isolated from a second portion of the conductive material along the second sidewall; and A second word line is formed on the conductive material, wherein the second word line is electrically connected to a second portion of the conductive material. The formation of the bit line stack further includes: using an etching process to recess the insulating layer, the etching process selectively etching the insulating layer relative to the first material.

9. The method according to claim 8, wherein, The sidewalls of the first bit line, the insulating layer, and the second bit line are coplanar.

10. A method for manufacturing a semiconductor device, comprising: The first letter line is formed on the substrate; A memory stack is formed above the first word line, wherein each memory stack includes a first sidewall and a second sidewall, and forming each memory stack includes: The first line is formed above at least one first letter line; A second bit line is formed on top of the first bit line, wherein the second bit line is electrically isolated from the first bit line; A resistive storage layer is deposited along the sidewalls of the first bit line and the second bit line; and A selection layer is deposited on the resistive storage layer; Control word lines are formed on the memory stacks, wherein each control word line extends from a first sidewall of a first corresponding memory stack to a second sidewall of a second corresponding memory stack; and A second word line is formed above the memory stack and the control word line, wherein each control word line is electrically connected to either the first word line or the second word line. The first bit line includes a first electrode layer, which protrudes laterally.

11. The method according to claim 10, wherein, Forming each memory stack also includes performing at least one etching process to remove the horizontal portions of the resistive memory layer and the select layer.

12. The method according to claim 11, wherein, After performing the at least one etching process, the resistive storage layer has an "L-shaped" profile.

13. The method according to claim 10, wherein, The second bit line includes a second electrode layer that protrudes laterally.

14. The method according to claim 13, wherein, The thicknesses of the first electrode layer and the second electrode layer are in the range of 2 nm to 5 nm.

15. The method according to claim 10, wherein, The first bit line includes a first adhesive layer, and the second bit line includes a second adhesive layer.

16. The method of claim 10, wherein, The second bit line is electrically isolated from the first bit line through an oxide layer.

17. A semiconductor device, comprising: A storage structure, on a substrate, wherein the storage structure comprises: First letter line; The first line is above the first character line; The second line is above the first line; Storage material is located on the sidewalls of the first and second lines; A first control word line is provided along a first side of the storage material, wherein the first control word line is electrically connected to the first word line; The second control word line runs along the second side of the storage material opposite to the first side; and The second word line is located above the second bit line, the first control word line, and the second control word line, wherein the second word line is electrically connected to the second control word line. The storage structure further includes a first electrode that contacts the first bit line, and the width of the first electrode is greater than the width of the first bit line.

18. The semiconductor device according to claim 17, wherein, The storage structure further includes a second electrode that contacts the second bit line, the width of the second electrode being greater than the width of the second bit line.

19. The semiconductor device according to claim 17, wherein, The storage structure comprises four separate storage units.

20. The semiconductor device of claim 17, further comprising: Multiple metallization layers are present on the substrate, wherein the storage structure is present on the multiple metallization layers.

Images