Semiconductor devices with parasitic channel structure

Abstract

This disclosure relates to a semiconductor device having a parasitic channel structure. The disclosure describes a semiconductor device and a method of forming the same. The semiconductor device includes nanostructures on a substrate and source / drain regions in contact with the nanostructures. The semiconductor device also includes a gate structure comprising a first portion and a second portion. The first portion is formed between each nanostructure in the nanostructure. The second portion is formed beneath the bottommost nanostructure of the plurality of nanostructures and extends beneath the top surface of the substrate.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductors, and more particularly to semiconductor devices having a parasitic channel structure. Background Technology

[0002] With advancements in semiconductor technology, the demand for higher storage capacity, faster processing systems, higher performance, and lower costs is increasing. To meet these demands, the semiconductor industry continues to scale down the size of semiconductor devices and has introduced three-dimensional transistors, such as gate all-around field-effect transistors (GAAFETs) and fin field-effect transistors (finFETs). Summary of the Invention

[0003] According to one embodiment of the present disclosure, a semiconductor device is provided, comprising: a plurality of nanostructures on a substrate; a source / drain region in contact with the plurality of nanostructures; and a gate structure comprising: a first portion formed between each of the plurality of nanostructures; and a second portion formed below the bottommost nanostructure of the plurality of nanostructures and extending below the top surface of the substrate.

[0004] According to another embodiment of this disclosure, a semiconductor device is provided, comprising: a plurality of nanostructures on a substrate; a plurality of internal spacers, wherein each internal spacer is formed below a nanostructure among the plurality of nanostructures; and a gate structure comprising: a first portion surrounding each nanostructure among the plurality of nanostructures; and a second portion formed below the bottommost nanostructure among the plurality of nanostructures, wherein the second portion extends below a top surface of the substrate.

[0005] According to another embodiment of this disclosure, a method of forming a semiconductor device is provided, comprising: depositing a first set of semiconductor layers and a second set of semiconductor layers to form a stack of alternating semiconductor layers on a substrate; forming a plurality of spacers on sidewalls of the first set of semiconductor layers; removing the first set of semiconductor layers, wherein a portion of the top surface of the substrate and some portions of the second set of semiconductor layers are exposed between the plurality of spacers; forming an opening by etching the exposed portions of the top surface of the substrate between the plurality of spacers, wherein the opening extends below the top surface of the substrate; and forming a gate structure, comprising: forming a first portion of the gate structure around each of the second set of semiconductor layers; and forming a second portion of the gate structure in the opening. Attached Figure Description

[0006] The various aspects of this disclosure are best understood through the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to standard industry practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0007] Figure 1 This is a flowchart of a method for fabricating a multilayer epitaxial source / drain structure in a semiconductor device according to some embodiments.

[0008] Figures 2A to 2D , Figure 3A , Figure 3B and Figures 4 to 8 Various cross-sectional views of a semiconductor device at various stages of its manufacturing process, according to some embodiments, are shown.

[0009] Figures 9 to 13 Various semiconductor devices incorporating extended gate structures according to some embodiments are shown.

[0010] Exemplary embodiments will now be described with reference to the accompanying drawings. In the drawings, the same reference numerals generally denote the same, functionally similar, and / or structurally similar elements. Detailed Implementation

[0011] The following disclosure provides various embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature can include embodiments where the first and second features are formed in direct contact, and can also include embodiments where an additional feature is provided between the first and second features such that the first and second features do not directly contact each other. Furthermore, reference numerals and / or letters may be repeated in various examples throughout this disclosure. Such repetition, in itself, does not indicate a relationship between the various embodiments and / or configurations discussed.

[0012] In addition, spatially related terms (e.g., "below," "below," "lower than," "above," "upper") may be used herein to facilitate the description of the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein may be interpreted accordingly.

[0013] The abbreviation “FET” used in this article refers to a field-effect transistor. An example of an FET is a metal-oxide-semiconductor field-effect transistor (MOSFET). A MOSFET can be, for example, (i) a planar structure built on the planar surface of a substrate (e.g., a semiconductor wafer), or (ii) a vertical structure.

[0014] As used herein, the term "nominal" refers to the expected or target value (along with a range of values ​​higher and / or lower than the desired value) of a component or process operation characteristic or parameter set during the design phase of a product or process. The range of values ​​is typically due to minor variations in manufacturing processes or tolerances.

[0015] As used herein, the terms “about” and “substantially” indicate a given value that can vary based on a specific technology node associated with the target semiconductor device. In some embodiments, based on a specific technology node, the terms “about” and “substantially” can represent a given value that varies, for example, within 5% (within, for example, ±1%, ±2%, ±3%, ±4%, ±5%), 10% of, 20% of, etc.

[0016] This disclosure provides examples of field-effect transistor (FET) devices (e.g., gate-all-around (GAA) FETs, fin FETs, horizontal or vertical GAA fin FETs, or planar FETs) in semiconductor devices and / or integrated circuits (ICs) and methods of fabricating them.

[0017] GAAFETs and finFETs increase device density and improve device performance. GAAFETs and finFETs consist of a pair of source / drain regions formed on opposite sides of the channel region. As the semiconductor industry continues to scale down the size of semiconductor devices, circuit complexity increases at all device levels. For example, beyond 5nm or 3nm technology nodes, increased source / drain tunneling can increase leakage current and lead to device failure. Short-channel effects can also be a cause of device failure. Semiconductor devices that realize nanostructures (e.g., nanowires and nanosheets) are potential candidates for overcoming short-channel effects. Among these candidates, GAAFETs are able to reduce short-channel effects and enhance carrier mobility, which in turn improves device performance. Further reducing the leakage paths formed under the gate stack and between the source / drain pairs has become increasingly challenging. For example, during the formation of the gate stack, the gate dielectric material and gate electrode are also formed on the top surface of the substrate or fin, resulting in parasitic channels that can serve as leakage paths connecting the source / drain pairs. The leakage current flowing through the parasitic channel can affect the off current and degrade device performance.

[0018] Various embodiments described in this disclosure describe methods for forming a gate stack extending into a region of the substrate with low carrier mobility, which in turn reduces current leakage between a pair of source / drain regions. The extended gate stack can be formed by etching an opening that extends from an upper region of the substrate to a lower region of the substrate with low carrier concentration. The opening may also extend beneath internal spacers located on the side surfaces of the gate stack. The gate stack (including a gate dielectric layer and a gate electrode) can be formed within this opening. The extended gate stack described herein provides various benefits, such as improved device performance and reliability. Benefits may also include (but are not limited to): reduced short-channel effects, reduced subthreshold leakage, and improved device on / off current characteristics. The embodiments described herein use a GAAFET as an example, and these embodiments can be applied to other semiconductor structures, such as finFETs and planar FETs. Furthermore, the embodiments described herein can be used at various technology nodes, such as 14nm, 7nm, 5nm, 3nm, 2nm, and lower technology nodes.

[0019] Figure 1 This is a flowchart of a method 100 for manufacturing a semiconductor device incorporating an extended gate structure, according to some embodiments. For illustrative purposes, reference will be made to manufacturing such a device... Figures 2A to 2D , Figure 3A , Figure 3B and Figures 4 to 8 The example manufacturing process of the semiconductor device 200 shown is described. Figure 1 The operations shown are illustrated. The operations may be performed in a different order depending on the specific application, or some operations may be omitted. It should be noted that method 100 may not produce a complete semiconductor device. Therefore, it should be understood that additional processes may be provided before, during, and after method 100, and some of these other processes are only briefly described herein.

[0020] refer to Figure 1 According to some embodiments, in operation 105, a semiconductor layer is formed on the fin structure of the substrate. For example, as shown in reference... Figures 2A to 2C As shown in the semiconductor device 200, a fin structure 108 having a fin base 108A and a fin top 108B can be formed on a substrate 106. Figure 2B yes Figure 2A The structure in the diagram is viewed in cross section from line AA. Figure 2C yes Figure 2A The structure is shown in a cross-sectional view from line BB. The formation of the fin structure 108 may include forming a fin base 108A and a fin top 108B on the substrate 106. Figures 2A to 2CA semiconductor layer is shown formed in a linear configuration (e.g., having a substantially square cross-section). Alternatively, the semiconductor layer of the semiconductor device 200 may also be formed in a sheet configuration (e.g., having a generally rectangular cross-section), such as... Figure 2D As shown in the image.

[0021] Substrate 106 may be a semiconductor material, such as silicon. In some embodiments, substrate 106 comprises a crystalline silicon substrate (e.g., a wafer). In some embodiments, substrate 106 comprises (i) a basic semiconductor, such as germanium; (ii) a compound semiconductor, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; (iii) an alloy semiconductor, including silicon germanium carbide, silicon germanium, gallium arsenide, gallium phosphide indium phosphide, gallium arsenide indium arsenide, gallium arsenide indium arsenide, gallium arsenide indium arsenide, aluminum arsenide indium, and / or aluminum gallium arsenide; or (iv) a combination of the foregoing. Furthermore, substrate 106 may be doped according to design requirements (e.g., p-type substrate or n-type substrate). In some embodiments, substrate 106 may be doped with a p-type dopant (e.g., boron, indium, aluminum, or gallium) or an n-type dopant (e.g., phosphorus or arsenic).

[0022] The fin structure 108 extends along the x-axis. The fin structure 108 may be part of a substrate and includes a fin base 108A and a fin top 108B disposed on the fin base 108A.

[0023] The fin base 108A may comprise a material similar to that of the substrate 106. The fin base 108A may be formed by photolithographic patterning and etching of the substrate 106. In some embodiments, the fin base 108A may be formed of silicon-germanium with a germanium concentration that gradually decreases from the top surface of the fin base 108A. In some embodiments, the germanium concentration within the fin base 108A is highest at the top surface of the fin base 108A.

[0024] The fin top 108B may include a stack of semiconductor layers. Each semiconductor layer may then be processed to form a channel region beneath the gate structure of the subsequently formed finFET. The fin top 108B may include a first set of semiconductor layers 122 and a second set of semiconductor layers 124 stacked in an alternating configuration. Each of semiconductor layers 122 and 124 may be epitaxially grown on a layer beneath it and may comprise semiconductor materials different from each other. In some embodiments, semiconductor layers 122 and 124 may comprise semiconductor materials similar to or different from the substrate 106. In some embodiments, semiconductor layers 122 and 124 may comprise semiconductor materials with different oxidation rates and / or etch selectivity. In some embodiments, each semiconductor layer 122 may be formed of silicon, and each semiconductor layer 124 may be formed of silicon-germanium. In some embodiments, semiconductor layer 122 may be formed of silicon-germanium, and semiconductor layer 124 may be formed of silicon. Semiconductor layer 122 and / or semiconductor layer 124 may be undoped, or may be in-situ doped using the following during their epitaxial growth process: (i) p-type dopant (e.g., boron, indium, and gallium); and / or (ii) n-type dopant, such as phosphorus and arsenic. For p-type in-situ doping, p-type doping precursors such as diborane, boron trifluoride, and any other p-type doping precursors may be used. For n-type in-situ doping, n-type doping precursors such as phosphine and arsine may be used. Although in Figures 2A to 2C The diagram shows four semiconductor layers 122 and four semiconductor layers 124, but the semiconductor device 200 may have any suitable number of semiconductor layers 122 and 124.

[0025] A sacrificial layer 109 can be formed between the fin base 108A and the stack of semiconductor layers 122 and 124. The sacrificial layer 109 can be formed using the same material as the fin base 108A, but with a different atomic concentration. For example, the fin base 108A can be formed using silicon-germanium with a gradually decreasing germanium concentration, while the sacrificial layer 109 can be formed with a uniform germanium concentration that is substantially the same as the highest level of germanium concentration in the fin base 108A. This difference in germanium concentration can provide a different etch rate for the fin base 108A compared to the sacrificial layer 109.

[0026] Forming the fin base portion 108A and the fin top portion 108B may further include etching the aforementioned material stack by patterned hard mask layers 134 and 136 formed on the aforementioned material stack. In some embodiments, the hard mask layer 134 may be a thin film comprising silicon oxide formed using, for example, a thermal oxidation process. In some embodiments, the hard mask layer 136 may be formed from silicon nitride using, for example, low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD). Etching of the material stack may include dry etching processes, wet etching processes, or combinations thereof. The hard mask layers 134 and 136 may be removed after the formation of the fin structure 108.

[0027] like Figure 2C As shown, the fin top 108B can be formed using a stack of semiconductor layers 122 and 124 with a linear configuration. For example, Figure 2C The sacrificial layer 109 and semiconductor layers 122 and 124 have substantially square cross-sections. In some embodiments, such as Figure 2D As shown, the fin top 108B can be formed using a stack of semiconductor layers 122 and 124 with a sheet-like configuration. For example, Figure 2D The sacrificial layer 109 and semiconductor layers 122 and 124 have substantially rectangular cross-sections. Figure 3A , Figure 3B and Figures 4 to 8 A semiconductor device is shown forming semiconductor layers with a linear configuration, which are then formed into nanowire structures. The method shown in the foregoing figures is also applicable to semiconductor devices having semiconductor layers with a sheet-like configuration, which are then formed into nanosheet structures.

[0028] refer to Figure 1 According to some embodiments, in operation 110, a sacrificial gate structure is formed on the substrate and a semiconductor layer is etched. See also Figure 3A and Figure 3B An STI region 138 can be formed on the substrate 106. The STI region 138 has a first protective liner 138A, a second protective liner 138B, and an insulating layer 138C. Figure 3B yes Figure 3A A cross-sectional view of the semiconductor device 200 as seen from the CC line. In some embodiments, after forming the STI region 138, the hard mask layer 136 remains on the top surface of the hard mask layer 134. In some embodiments, the hard mask layer 136 is removed before forming the STI region 138. Forming the STI region 138 may include: (i) in Figure 2A(ii) depositing a nitride material layer (not shown) for the first protective liner 138A on the structure; (iii) depositing an oxide material layer (not shown) for the second protective liner 138B on the nitride material layer; (iv) depositing an insulating material layer for the insulating layer 138C on the oxide material layer; (v) annealing the insulating material layer for the insulating layer 138C; (v) chemically mechanically polishing (CMP) the nitride material layer, the oxide material layer, and the annealed insulating material layer; and (vi) etching back the polished structure to form Figure 3A The structure is described. Nitride and oxide material layers can be deposited using suitable processes for depositing oxide and nitride materials, such as atomic layer deposition (ALD) and chemical vapor deposition (CVD). These oxide and nitride material layers can prevent annealing of the sidewalls of the fin top 108B during the deposition and annealing of the insulating material for insulating layer 138C. In some embodiments, the insulating material layer for insulating layer 138C may include silicon oxide, silicon nitride, silicon oxynitride, fluorinated glass silicate (FSG), or a low-k dielectric material. In some embodiments, the insulating material layer can be deposited using a CVD process, a high-density plasma (HDP) CVD process, using silane and oxygen as reaction precursors. In some embodiments, the insulating material layer can be formed using a subatmospheric pressure CVD (SACVD) process or a high aspect ratio process (HARP), wherein the process gas may include tetraethoxysilane (TEOS) and / or ozone.

[0029] Polysilicon gate structure 112 is formed on STI region 138, such as Figure 3A and Figure 3BAs shown. The polysilicon gate structure 112 is a sacrificial gate structure and can be replaced in a gate replacement process to form a metal gate structure. In some embodiments, the formation of the polysilicon gate structure 112 may include blanket deposition of a polysilicon material layer and etching of the polysilicon material layer by forming a patterned hard mask layer 116 on the polysilicon material layer. In some embodiments, the polysilicon material layer may be undoped, and the hard mask layer 116 may include an oxide layer and / or a nitride layer. The oxide layer may be formed using a thermal oxidation process, and the nitride layer may be formed by LPCVD or PECVD. The hard mask layer 116 can protect the polysilicon gate structure 112 from subsequent processing steps (e.g., during the formation of spacers 114 and / or source / drain regions). The blanket deposition of the polysilicon material layer may include CVD, physical vapor deposition (PVD), ALD, or any other suitable deposition process. In some embodiments, etching of the deposited polysilicon material layer may include dry etching, wet etching, or a combination thereof. Spacer 114 may be formed on the sidewall of polysilicon gate structure 112. Forming spacer 114 may include blanket deposition of insulating material (e.g., oxide, nitride, and / or silicon carbon oxynitride material) layer, followed by photolithography and etching processes (e.g., reactive ion etching or any other suitable dry etching process using chlorine or fluorine-based etchants).

[0030] The top of the fins can be etched after the polysilicon gate structure 112 is formed. The etching process can remove portions of semiconductor layers 122 and 124 exposed between adjacent polysilicon gate structures 112. The etching process can include a wet etching process using, for example, diluted HF. In some embodiments, one or more etching processes can be used. For example, the etching process can include an etching process for removing silicon material and another etching process for removing silicon-germanium material. During the etching process, the polysilicon gate structure 112 can be protected from etching by spacers 114 and a hard mask layer 116.

[0031] Reference Figure 1 According to some embodiments, in operation 115, an internal spacer structure is formed between semiconductor layers. (See reference...) Figure 4 Some portions of the semiconductor layer 124 can be etched back to form recessed regions, and dielectric material can be deposited in the recessed regions to form internal spacers 127. For example, Figure 4 The semiconductor device 200 shown may include an n-type metal-oxide-semiconductor (NMOS) device, and some portions of the semiconductor layer 124 are etched back.

[0032] Figure 4The semiconductor device 200 shown may include a semiconductor layer 124, a sacrificial layer 109, and a substrate 106 formed using silicon and germanium. In some embodiments, the semiconductor layer 124 may be formed using silicon. When measured from the top surface 106A to the bottom surface 106B of the substrate 106, the substrate 106 may have a gradually decreasing germanium concentration.

[0033] Semiconductor device 200 may also include a p-type metal-oxide-semiconductor (PMOS) device. For simplicity, Figure 5 The PMOS device configuration is not shown. For the PMOS device configuration, the semiconductor layer 124 can be processed to serve as a channel region. The semiconductor layer 122 can be etched back and forth using a suitable etching process, and the internal spacer 127 can be formed between adjacent semiconductor layers 124 using similar deposition and etching processes described below with respect to the etch-back of the semiconductor layer 124 and the formation of the internal spacer 127.

[0034] Semiconductor layer 124 can be etched back and forth using dry etching, wet etching, or a combination thereof. The etch-back process of semiconductor layer 124 can be configured to form non-planar outer surfaces of semiconductor layers 122 and 124. For example, the etching process may include alternating cycles of etching and cleaning processes. The etching process in each cycle may include the use of a gas mixture containing hydrogen fluoride, nitrogen trifluoride, fluorine-based gases, and chlorine-based gases. Figure 4 As shown in the enlarged view 401, semiconductor layer 122 may have a curved convex outer surface 122t, and semiconductor layer 124 may have a curved concave outer surface 124t. In some embodiments, the subsequently formed inner spacer 127 may also have an outer surface 127t that substantially conforms to the contour of the outer surface 124t of semiconductor layer 124.

[0035] Reference Figure 1 According to some embodiments, in operation 120, an epitaxial layer is grown on a substrate, a semiconductor layer, and an internal spacer structure. (See reference...) Figure 5The source / drain structure 502 can be deposited on the substrate 106 and the outer surfaces of the semiconductor layer 122 and the inner spacer 127. In some embodiments, the source / drain structure 502 can be formed by a selective growth process in which semiconductor material is grown on selective surfaces. For example, the source / drain structure 502 can be formed by epitaxially growing crystalline material using exposed portions of the substrate 106 and the semiconductor layer 122 as seed layers. In some embodiments, the substrate 106 and the semiconductor layer 122 are formed of crystalline silicon, and epitaxial deposition methods using self-assembled monolayer (SAM) or selective region ALD can be used to selectively grow crystalline silicon on the exposed surfaces of the substrate 106 and the semiconductor layer 122. The source / drain structure 502 can be formed using suitable deposition methods, such as (i) CVD, including but not limited to LPCVD, atomic layer CVD (ALCVD), ultra-high vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), and any other suitable CVD; (ii) molecular beam epitaxy (MBE); (iii) any suitable epitaxial growth process; or (iv) a combination of the foregoing. In some embodiments, the source / drain structure 502 can be grown by an epitaxial deposition / partial etching process, wherein the epitaxial deposition / partial etching process is repeated at least once. Such a repeated deposition / partial etching process is also referred to as a cyclic deposition etch (CDE) process. In some embodiments, a plasma deposition process using substances such as germane, dichlorosilane, and hydrochloride can be used to deposit the source / drain structure 502 formed of silicon-germanium.

[0036] The crystalline silicon material epitaxially deposited on adjacent semiconductor layers 122 and substrate 106 can expand and merge together to cover the outer surface of the internal spacer 127. The width W of the source / drain structure 502 can be between about 10 nm and about 80 nm, between about 15 nm and about 75 nm, between about 20 nm and about 60 nm, or any suitable size. In some embodiments, the height H of the source / drain structure 502, measured from the top surface 502t to the bottom surface 502b, can be between about 20 nm and about 140 nm, between about 30 nm and about 120 nm, between about 40 nm and about 100 nm, or any suitable size. The source / drain structure 502 can be formed of silicon, silicon germanium, silicon phosphide, any suitable semiconductor material, and / or combinations thereof. In some embodiments, the source / drain structure 502 can be doped with suitable dopants, such as boron and phosphorus.

[0037] Reference Figure 1 According to some embodiments, in operation 125, the nanostructure is released, and openings are formed in the substrate and beneath the internal spacers. (Reference) Figure 6A and Figure 6B Semiconductor layer 124 is removed, exposing portions of semiconductor layer 122 formed between opposing internal spacers 127. The exposed semiconductor layer may be referred to as a nanostructure (e.g., nanowire or nanosheet). In some embodiments, semiconductor layer 122 is removed ( Figure 6A and Figure 6B (not shown in the image), and the semiconductor layer 124 forms a nanostructure. In some embodiments, an interlayer dielectric (ILD) layer 618 is deposited between the spacers 114, and the polysilicon gate structure 112 is removed.

[0038] ILD layer 618 may be disposed on the source / drain structure 502 of the source / drain region and between the spacer 114. ILD layer 618 may include a dielectric material deposited using a deposition method suitable for a flowable dielectric material (e.g., flowable silicon oxide, flowable silicon nitride, flowable silicon oxynitride, flowable silicon carbide, or flowable silicon oxycarbide). For example, flowable CVD (FCVD) may be used to deposit flowable silicon oxide. In some embodiments, the dielectric material is silicon oxide. Other materials and formation methods for ILD layer 618 are within the scope and spirit of this disclosure.

[0039] Following the formation of the ILD layer 618, the polysilicon gate structure 112 and semiconductor layer 124 can be removed using a dry etching process (e.g., reactive ion etching) or a wet etching process, thereby exposing portions of the semiconductor layer 122. The exposed semiconductor layer 122 can be referred to as a nanostructure (e.g., nanowire or nanosheet). Depending on the type of device formed, semiconductor layer 122 can be removed, exposing portions of semiconductor layer 124, which can also be referred to as nanostructures. In some embodiments, the gaseous etchant used in the dry plasma etching process can include hydrogen and free radicals, such as chlorine, fluorine, bromine, or combinations thereof. For example, the gaseous etchant can include hydrogen bromide, hydrogen chloride, or any suitable gaseous etchant. In some embodiments, wet chemical etching can be used. The etchant used in the wet chemical etching process can include ozone mixed with one or more of hydrogen fluoride, hydrogen chloride, hydrogen peroxide, or any suitable chemical etchant. In some embodiments, dry etching can be used followed by a wet etching process.

[0040] After the polysilicon gate structure 112 and semiconductor layer 124 are removed, portions of the top surface 106A of the substrate 106 are exposed between the bottommost opposing internal spacers 127. See also Figure 6B Openings can be formed on these portions of the top surface 106A. For example, opening 602 can be formed in the substrate 106 and below the bottommost opposing inner spacer 127. Figure 6BThe diagram shows a cross-sectional view of an opening 602 that is substantially elliptical in shape, which can be formed using an isotropic etching process. In some embodiments, the etching process used to form the opening 602 can be similar to the etching process used to remove the semiconductor layer 124. For example, a wet chemical etching process using hydrogen chloride can be used to form the opening 602. In some embodiments, the opening 602 can have any suitable shape, such as substantially triangular, substantially rectangular, substantially circular, or any suitable shape. In some embodiments, dry plasma etching with less radio frequency (RF) power can provide more isotropic etching and further extend the opening 602 below the internal spacer 127.

[0041] The atomic concentrations of the semiconductor layer 124 and the substrate 106 can be adjusted to enable controlled etching, thereby forming the nominal shape of the opening 602. In some embodiments, similar materials with different atomic concentrations can be used to form the semiconductor layer 124 and the substrate 106. Different atomic concentrations can result in different etching rates for the semiconductor layer 124 and the substrate 106. Larger differences in atomic concentration can lead to larger differences in etching rates. For example, silicon-germanium material with a germanium atomic concentration of about 10% can be etched much faster than silicon material (e.g., up to 10 times faster). Therefore, increasing or decreasing the germanium concentration can increase or decrease the difference in etching rates between silicon-germanium materials.

[0042] In some embodiments, the upper portion of substrate 106 may have an atomic concentration similar to that of semiconductor layer 124, while the lower portion of substrate 106 may have a lower atomic concentration, such that the etching rate of substrate 106 decreases as the etching process penetrates deeper into substrate 106. This reduced etching rate, resulting from deeper penetration into substrate 106, can facilitate easier control over the etching depth and shape of opening 602. For example, both semiconductor layer 124 and the top portion 610 of substrate 106 can be formed using silicon-germanium material with a similar germanium atomic concentration. The lower portion 620 of substrate 106 can be formed using silicon-germanium with a lower germanium atomic concentration than that of the upper portion 610 and semiconductor layer 124. For example, the germanium concentration of the lower portion 620 may be less than about 5% to about 10% of the germanium concentration of the upper portion 610. In some embodiments, the germanium atomic concentration in substrate 106 gradually decreases when measured from the top surface 106A of substrate 106. In some embodiments, the upper portion 610 may have a greater germanium atom concentration than that of the semiconductor layer 124, and the lower portion 620 may have a lower germanium atom concentration than that of the semiconductor layer 124. In some embodiments, the germanium atom concentration at the top surface 106A of the substrate 106 may be similar to that of the semiconductor layer 124. In some embodiments, the boundary 630 between the upper portion 610 and the lower portion 620 may represent a portion of the substrate 106 containing a germanium concentration similar to that of the semiconductor layer 124. In some embodiments, the substrate 106 has a gradually decreasing atomic concentration, and the boundary 630 may represent a portion of the substrate 106 having a sufficiently low carrier density due to the low atomic concentration, which in turn prevents the formation of leakage current. For example, the atomic concentration at the boundary 630 may be between about 12% and about 18%. In some embodiments, the atomic concentration at the boundary 630 may be about 15%, and the portion of the substrate 106 below the boundary 630 has an atomic concentration of less than about 15%. In some embodiments, the opening 602 may extend vertically (e.g., in the z-direction) to the boundary 630, as... Figure 6B As shown. In some embodiments, the opening 602 may extend beyond the boundary 630 and extend deeper into the substrate 106. In some embodiments, the boundary 630 may be between about 0.2 nm and about 2.0 nm, between about 0.5 nm and about 1.7 nm, between about 0.8 nm and about 1.2 nm, or any suitable size. Extending the opening 602 above the boundary 630 can provide the benefit of reducing the likelihood of leakage current forming due to the reduced carrier density of the substrate 106 below the opening 602.

[0043] refer to Figure 1 According to some embodiments, in operation 130, a gate dielectric layer, a work function layer, and a gate electrode are deposited in the opening and on the nanostructure. (See reference...) Figure 7A gate stack 710 is formed in the opening 602 and on the semiconductor layer 122. The gate stack 710 includes a gate dielectric layer 712, a work function layer 714 and a gate electrode 716.

[0044] A gate dielectric layer 712 may be formed on a semiconductor layer. In some embodiments, the gate dielectric layer 712 may surround an exposed nanostructure-shaped semiconductor layer 122. In some embodiments, the semiconductor layer 122 may be a nanosheet or a nanowire. Forming the gate dielectric layer 712 may include a blanket deposition process of a suitable gate dielectric material layer. In some embodiments, the gate dielectric layer 712 may be formed of a high-k dielectric material (e.g., a dielectric material having a dielectric constant greater than about 3.9). For example, the gate dielectric layer 712 may be formed of hafnium oxide. A work function layer 714 is formed on the gate dielectric layer 712. In some embodiments, each work function layer 714 may include one or more work function metal layers and be formed using the same or different materials and / or thicknesses. The gate dielectric layer 712 and the gate work function layer 714 may each surround the nanostructure-shaped semiconductor layer 122. Depending on the space between adjacent semiconductor layers 122, the semiconductor layer 122 may be surrounded by the gate dielectric layer 712 and the work function layer 714 to fill the space between adjacent semiconductor layers 122. In some embodiments, the gate electrode material subsequently formed may also be formed in the space between adjacent semiconductor layers 122, as shown in enlarged FIG. 750 and described below.

[0045] According to some embodiments, the gate electrode 716 may be formed on the work function layer. A conductive material layer for the gate electrode 716 is formed on the work function layer 714. As shown in enlarged view 750, if the spacing between adjacent semiconductor layers 122 is sufficient to accommodate the thickness of the gate electrode material, the gate electrode 716 can be formed between adjacent semiconductor layers 122 and on the work function layer 714, thereby filling the space between adjacent semiconductor layers 122. The gate electrodes 716 between adjacent semiconductor layers 122 and the gate electrodes 716 formed between spacers 114 are electrically coupled to each other. The conductive material layer for the gate electrode 716 may include suitable conductive materials, such as titanium, silver, aluminum, tungsten, copper, ruthenium, molybdenum, tungsten nitride, cobalt, nickel, titanium carbide, titanium aluminum carbide, manganese, zirconium, metal alloys, and combinations thereof. The gate electrode 716 may be formed by ALD, PVD, CVD, or any other suitable deposition process. The deposition of the gate electrode 716 may continue until the opening between the opposing spacers 114 is filled with the gate electrode 716. Chemical mechanical polishing (CMP) can remove excess gate electrode 716, making the top surface of gate electrode 716 substantially coplanar with the top surface of ILD layer 618. In some embodiments, other structures, such as barrier layers, can be formed. One or more barrier layers can be formed before depositing gate electrode 716. Figure 7 (not shown in the image) to prevent diffusion and oxidation of the gate electrode 716.

[0046] The extended gate stack 710A refers to the portion of the gate stack 710 formed below the bottom semiconductor layer 122 and within the opening 602. The extended gate stack 710A may include a first portion formed between opposing inner sidewalls of the inner spacer 127 and a second portion formed within the opening 602. Both the first and second portions of the extended gate stack 710A are formed directly below the bottom nanostructure, such as the bottom layer of semiconductor layer 122. The second portion of the extended gate stack 710A also extends directly below the bottom inner spacer 127 and outlines the shape of the opening 602. Therefore, the second portion of the extended gate stack 710A can be formed as substantially elliptical, substantially circular, substantially rectangular, or any suitable shape. The extended gate stack 710A may also have a substantially flat bottom surface in contact with the substrate 106. Figure 7 As shown, a leakage path 720 can be formed between a pair of source / drain structures 502, extending through the body of substrate 106. However, because the extended gate stack 710A extends to or below boundary 630, the lower portion 620 of substrate 106 may not provide sufficient carrier concentration to induce leakage current flow, potentially leading to interruptions such as circuit interruption 730.

[0047] Enlarged view 760 shows a portion of the extended gate stack 710A. As shown in enlarged view 760, the gate stack 710A may extend horizontally (e.g., in the x-direction) below the inner spacer 127. In some embodiments, the gate stack 710A contacts the inner sidewall surface and bottom surface of the inner spacer 127. The height of the inner spacer 127 may be referred to as height H1. In some embodiments, height H1 may be between about 3 nm and about 10 nm, between about 5 nm and about 7 nm, or any suitable height. In some embodiments, the extended gate stack 710A may extend into the substrate 106 to height H2 (measured from the bottom surface of the bottommost semiconductor layer 122 to the bottom surface of the extended gate stack 710A). In some embodiments, height H2 may be between about 5 nm and about 15 nm, between about 7 nm and about 13 nm, or between about 9 nm and about 11 nm. The height ratio of height H2 to height H1 may be between about 1.01 and about 3. For example, the ratio can be between about 1.05 and about 2.2, between about 1.3 and about 1.8, and between about 1.4 and about 1.6. In some embodiments, the ratio can be between about 1.01 and about 1.5. A larger height ratio can indicate a deeper extended gate stack 710A, which in turn provides lower leakage current.

[0048] Reference Figure 1According to some embodiments, in operation 135, source / drain contacts and gate contacts are formed. (See also...) Figure 8 Source / drain contacts 804 and gate contacts 806 are formed to provide electrical connections to the source / drain region and the gate electrode, respectively. Specifically, source / drain contacts 804 and gate contacts 806 can be used to connect the source / drain region to the gate electrode and external terminals. Figure 8 Electrical signals are transmitted between (not shown). For example, gate contact 806 can be electrically coupled to gate electrode 716 formed between spacers 114 and adjacent semiconductor layers 122. An additional ILD layer can be formed on the top surface of ILD layer 618. For example, dielectric layer 818 can be formed on ILD layer 618. In some embodiments, dielectric layer 818 can be formed using a material similar to ILD layer 618. Gate contact 806 and source / drain contact 804 can be formed by forming openings in dielectric layer 818, gate electrode 716 and ILD layer 618 and depositing conductive material in these openings. The deposition process can include depositing a metal layer in the openings and performing an annealing process to cause silicide formation of the deposited metal layer. Conductive materials used to form source / drain contact 804 and gate contact 806 can include titanium, aluminum, silver, tungsten, cobalt, copper, ruthenium, zirconium, nickel, titanium nitride, tungsten nitride, metal alloys and / or combinations thereof. The deposition process may include ALD, PVD, CVD, any suitable deposition process, and / or combinations thereof. Gate contact 806 and source / drain contact 804 may be connected to the gate electrode 716 and the third epitaxial layer 902 of the source / drain region, respectively.

[0049] A planarization process can planarize the top surface of the dielectric layer 818, the top surface of the source / drain contact 804, and the top surface of the gate contact 806, making these top surfaces substantially coplanar. In some embodiments, the gate contact 806 may extend into the gate electrode 716. A silicide region may be formed between the source / drain contact 804 and the source / drain structure 502. Figure 8 (not shown in the image) to reduce contact resistance. In some embodiments, the silicide region may include ruthenium silicide, nickel silicide, cobalt silicide, tungsten silicide, tantalum silicide, platinum silicide, erbium silicide, palladium silicide, any suitable silicide material, and / or a combination of the foregoing.

[0050] Back-to-line (BEOL) interconnect structures are formed over source / drain contacts 804 and gate contacts 806. The BEOL interconnect structures can be formed in a dielectric layer 822 deposited on dielectric layer 818. Interconnects can be formed in dielectric layer 822. In some embodiments, the interconnects can be an electrical connection network including vertically extending (e.g., along the z-axis) vias 826 and laterally extending (e.g., along the x-axis) conductors 828. The interconnect structures can provide electrical connections to source / drain contacts 804 and gate contacts 806. In some embodiments, suitable passive and active semiconductor devices (not illustrated for simplicity) can be formed in dielectric layers 818 and 822.

[0051] Figures 9 to 13 Various semiconductor structures incorporating extended gate stacks are shown to reduce leakage current. Figures 9 to 13 Zhongyu Figures 2A to 8 Similar reference numerals in drawings typically indicate elements that are identical, functionally similar, and / or structurally similar.

[0052] Figure 9 A semiconductor structure 900 incorporating an extended gate stack is illustrated according to some embodiments. The semiconductor structure 900 includes a substrate 906 formed using silicon and a semiconductor layer 922 formed using silicon-germanium. The semiconductor layer 922 may be a nanostructure, such as a nanosheet or nanowire. The semiconductor layer 922 can be formed by depositing a semiconductor layer stack comprising alternating layers of silicon and silicon-germanium, removing the silicon material, and exposing the silicon-germanium material. In some embodiments, the silicon material can be removed using a wet chemical etching process with chemical etchants, such as a mixture of ammonium hydroxide and hydrogen peroxide, hydrofluoric acid or a basic wet chemical etchant, and any suitable wet chemical etchant.

[0053] Figure 10 A semiconductor structure 1000 incorporating an extended gate stack is illustrated according to some embodiments. The semiconductor structure 1000 includes a substrate 1006 formed using silicon-germanium and a semiconductor layer 1022. The semiconductor layer 1022 can be a nanostructure, such as a nanosheet or nanowire. The semiconductor layer 1022 can be formed by depositing a semiconductor layer stack comprising alternating layers of silicon and silicon-germanium, removing the silicon material, and exposing the silicon-germanium material. The etching process for removing the silicon material can be similar to that described above. Figure 9 Those described.

[0054] Figure 11A semiconductor structure 1100 incorporating an extended gate stack is illustrated according to some embodiments. The semiconductor structure 1100 includes a substrate 1106 formed using silicon and a semiconductor layer 1122. The semiconductor layer 1122 may be a nanostructure, such as a nanosheet or nanowire. The semiconductor layer 1122 can be formed by depositing a semiconductor layer stack comprising alternating layers of silicon and silicon-germanium, removing the silicon-germanium material, and exposing the silicon material. The etching process for removing the silicon-germanium material can be a wet chemical etching process using a suitable chemical etchant (e.g., a mixture of sulfuric acid, hydrofluoric acid, and ozone, or any suitable wet chemical etchant).

[0055] Figure 12 A semiconductor structure 1200 incorporating an extended gate stack is illustrated according to some embodiments. The semiconductor structure 1200 includes a substrate 1206 formed using germanium and a semiconductor layer 1222. The semiconductor layer 1222 can be a nanostructure, such as a nanosheet or nanowire. The semiconductor layer 1222 can be formed by depositing a semiconductor layer stack comprising alternating layers of germanium and a germanium-tin alloy, removing the germanium-tin alloy, and exposing the germanium material. The etching process for removing the germanium-tin alloy can be a wet chemical etching process or a dry etching process.

[0056] Figure 13 A semiconductor structure 1300 incorporating an extended gate stack is illustrated according to some embodiments. The semiconductor structure 1300 includes a substrate 1306 formed using silicon-germanium and a semiconductor layer 1322. The semiconductor layer 1322 may be a nanostructure, such as a nanosheet or nanowire. The semiconductor layer 1322 can be formed by depositing a semiconductor layer stack comprising alternating layers of silicon-germanium and a germanium-tin alloy, removing the germanium-tin alloy, and exposing the silicon-germanium material. The etching process for removing the germanium-tin alloy can be a wet chemical etching process or a dry etching process.

[0057] Various embodiments described in this disclosure represent methods for forming a gate stack extending into a region of the substrate with low carrier mobility, which in turn reduces current leakage between a pair of source / drain regions. This extended gate stack can be formed by etching an opening extending from an upper region of the substrate into a lower region of the substrate with low carrier concentration. This opening may also extend beneath internal spacers located on the side surfaces of the gate stack. A gate stack including a gate dielectric layer and gate electrodes can be formed within the opening. The extended gate stacks described herein offer various benefits, such as improved device performance and reliability.

[0058] In some embodiments, a semiconductor device includes nanostructures on a substrate and source / drain regions in contact with the nanostructures. The semiconductor device also includes a gate structure comprising a first portion and a second portion. The first portion is formed between each nanostructure in the nanostructure. The second portion is formed beneath the bottommost nanostructure of the plurality of nanostructures and extends beneath the top surface of the substrate.

[0059] In some embodiments, a semiconductor device includes nanostructures and internal spacers on a substrate. Each internal spacer is formed beneath a nanostructure among a plurality of nanostructures. The semiconductor device also includes a gate structure having a first portion and a second portion. The first portion surrounds each of the plurality of nanostructures. The second portion is formed beneath the bottommost nanostructure among the plurality of nanostructures and extends below the top surface of the substrate.

[0060] In some embodiments, a method includes: depositing a first set of semiconductor layers and a second set of semiconductor layers to form a stack of alternating semiconductor layers on a substrate. The method further includes: forming spacers on the sidewalls of the first set of semiconductor layers. The method further includes: removing the first set of semiconductor layers such that a portion of the top surface of the substrate and portions of the second set of semiconductor layers are exposed between a plurality of spacers. The method further includes: forming an opening by etching the exposed portions of the top surface of the substrate between the plurality of spacers, such that the opening extends below the top surface of the substrate. The method further includes: forming a gate structure including a first portion and a second portion. The first portion of the gate structure surrounds each of the second set of semiconductor layers. The second portion of the gate structure is formed in the opening.

[0061] The foregoing disclosure outlines features of several embodiments, enabling those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made therein without departing from the spirit and scope of this disclosure.

[0062] Example 1 is a semiconductor device comprising: a plurality of nanostructures on a substrate; a source / drain region in contact with the plurality of nanostructures; and a gate structure comprising: a first portion formed between each of the plurality of nanostructures; and a second portion formed below the bottommost nanostructure of the plurality of nanostructures and extending below the top surface of the substrate.

[0063] Example 2 is the semiconductor device described in Example 1, further comprising: a plurality of internal spacers, wherein the internal spacers of the plurality of internal spacers are formed between adjacent nanostructures in the plurality of nanostructures.

[0064] Example 3 is the semiconductor device described in Example 2, wherein a second portion of the gate structure is formed below the bottommost inner spacer of the plurality of inner spacers.

[0065] Example 4 is the semiconductor device described in Example 2, wherein a second portion of the gate structure contacts the inner surface of the bottommost inner spacer among the plurality of inner spacers.

[0066] Example 5 is the semiconductor device described in Example 2, wherein a second portion of the gate structure contacts the bottom surface of the bottommost of the plurality of internal spacers.

[0067] Example 6 is the semiconductor device described in Example 2, wherein the ratio of the height of the second portion of the gate structure to the height of the internal spacers among the plurality of internal spacers is between about 1.01 and about 1.5.

[0068] Example 7 is the semiconductor device described in Example 1, wherein the substrate comprises silicon germanium, and the plurality of nanostructures comprise silicon.

[0069] Example 8 is the semiconductor device described in Example 1, wherein the substrate and the plurality of nanostructures comprise germanium.

[0070] Example 9 is the semiconductor device described in Example 1, wherein the cross-section of the second portion of the gate structure comprises an elliptical shape.

[0071] Example 10 is the semiconductor device described in Example 1, wherein the substrate includes a non-uniform germanium atom concentration that decreases from the top surface of the substrate to the bottom surface of the substrate.

[0072] Example 11 is a semiconductor device comprising: a plurality of nanostructures on a substrate; a plurality of internal spacers, wherein each internal spacer is formed below a nanostructure among the plurality of nanostructures; and a gate structure comprising: a first portion surrounding each nanostructure among the plurality of nanostructures; and a second portion formed below the bottommost nanostructure among the plurality of nanostructures, wherein the second portion extends below a top surface of the substrate.

[0073] Example 12 is the semiconductor device described in Example 11, wherein a second portion of the gate structure is in contact with the sidewall surface and bottom surface of the bottommost nanostructure among the plurality of nanostructures.

[0074] Example 13 is the semiconductor device described in Example 11, wherein the ratio of the height of the second portion of the gate structure to the height of the internal spacers among the plurality of internal spacers is between about 1.01 and about 1.5.

[0075] Example 14 is the semiconductor device described in Example 11, wherein the substrate comprises silicon germanium and the plurality of nanostructures comprise silicon.

[0076] Example 15 is the semiconductor device described in Example 11, wherein the substrate includes a non-uniform germanium atom concentration that decreases from the top surface of the substrate to the bottom surface of the substrate.

[0077] Example 16 is a method of forming a semiconductor device, comprising: depositing a first set of semiconductor layers and a second set of semiconductor layers to form a stack of alternating semiconductor layers on a substrate; forming a plurality of spacers on sidewalls of the first set of semiconductor layers; removing the first set of semiconductor layers, wherein a portion of the top surface of the substrate and a portion of the second set of semiconductor layers are exposed between the plurality of spacers; forming an opening by etching the exposed portion of the top surface of the substrate between the plurality of spacers, wherein the opening extends below the top surface of the substrate; and forming a gate structure, comprising: forming a first portion of the gate structure around each of the second set of semiconductor layers; and forming a second portion of the gate structure in the opening.

[0078] Example 17 is the method described in Example 16, wherein depositing the first set of semiconductor layers and the second set of semiconductor layers includes depositing a silicon-germanium layer and a silicon layer, respectively.

[0079] Example 18 is the method of Example 16, wherein forming the opening includes exposing the bottom surface of the bottommost spacer among the plurality of spacers.

[0080] Example 19 is the method described in Example 16, wherein depositing the first set of semiconductor layers and the second set of semiconductor layers includes depositing a germanium layer and a germanium-tin alloy layer, respectively.

[0081] Example 20 is the method of Example 16, wherein forming the opening includes forming an opening with an elliptical cross-section.

Claims

1. A semiconductor device, comprising: Multiple nanostructures on a substrate; Multiple internal spacers, wherein the internal spacers are formed between adjacent nanostructures in the plurality of nanostructures. The source / drain regions are in contact with the plurality of nanostructures; and Gate structure, the gate structure comprising: The first part is formed between each of the plurality of nanostructures; and The second portion is formed below the bottommost nanostructure of the plurality of nanostructures and extends below the top surface of the substrate, wherein the second portion of the gate structure contacts the bottom surface of the bottommost internal spacer of the plurality of internal spacers.

2. The semiconductor device according to claim 1, wherein, The second portion of the gate structure is formed below the bottommost inner spacer among the plurality of inner spacers.

3. The semiconductor device according to claim 1, wherein, The second portion of the gate structure contacts the inner surface of the bottommost inner spacer among the plurality of inner spacers.

4. The semiconductor device according to claim 1, wherein, The ratio of the height of the second portion of the gate structure to the height of the internal spacers among the plurality of internal spacers is between 1.01 and 1.

5.

5. The semiconductor device according to claim 1, wherein, The substrate comprises silicon-germanium, and the plurality of nanostructures comprise silicon.

6. The semiconductor device according to claim 1, wherein, The substrate and the plurality of nanostructures include germanium.

7. The semiconductor device according to claim 1, wherein, The cross-section of the second portion of the gate structure has an elliptical shape.

8. The semiconductor device according to claim 1, wherein, The substrate includes a non-uniform germanium atom concentration that decreases from the top surface of the substrate to the bottom surface of the substrate.

9. A semiconductor device, comprising: Multiple nanostructures are on the substrate; Multiple internal spacers, wherein each internal spacer is formed beneath a nanostructure within the plurality of nanostructures; and Gate structure, including: The first part concerns each of the plurality of nanostructures; and The second portion is formed beneath the bottommost nanostructure of the plurality of nanostructures, wherein the second portion extends beneath the top surface of the substrate, and wherein the second portion of the gate structure contacts the bottom surface of the bottommost internal spacer of the plurality of internal spacers.

10. The semiconductor device according to claim 9, wherein, The second portion of the gate structure is in contact with the sidewall surface and bottom surface of the bottommost nanostructure among the plurality of nanostructures.

11. The semiconductor device according to claim 9, wherein, The ratio of the height of the second portion of the gate structure to the height of the internal spacers among the plurality of internal spacers is between 1.01 and 1.

5.

12. The semiconductor device according to claim 9, wherein, The substrate comprises silicon-germanium, and the plurality of nanostructures comprise silicon.

13. The semiconductor device according to claim 9, wherein, The substrate includes a non-uniform germanium atom concentration that decreases from the top surface of the substrate to the bottom surface of the substrate.

14. A method of forming a semiconductor device, comprising: Deposit a first set of semiconductor layers and a second set of semiconductor layers to form a stack of alternating semiconductor layers on a substrate; Multiple spacers are formed on the sidewalls of the first group of semiconductor layers; Remove the first set of semiconductor layers, wherein a portion of the top surface of the substrate and a portion of the second set of semiconductor layers are exposed between the plurality of spacers; An opening is formed by etching the portion of the top surface of the substrate exposed between the plurality of spacers, wherein the opening extends below the top surface of the substrate; and Forming a gate structure includes: A first portion of the gate structure is formed around each of the second set of semiconductor layers; and A second portion of the gate structure is formed in the opening, wherein the second portion of the gate structure contacts the bottom surface of the bottommost spacer among the plurality of spacers.

15. The method according to claim 14, wherein, Depositing the first set of semiconductor layers and the second set of semiconductor layers includes depositing a silicon-germanium layer and a silicon layer, respectively.

16. The method of claim 14, wherein, Forming the opening includes exposing the bottom surface of the bottommost spacer among the plurality of spacers.

17. The method of claim 14, wherein, Depositing the first set of semiconductor layers and the second set of semiconductor layers includes depositing a germanium layer and a germanium-tin alloy layer, respectively.

18. The method according to claim 14, wherein, Forming the opening includes forming an opening with an elliptical cross-section.

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