An IGBT with NP stack drift region

Abstract

The present invention belongs to the technical field of power semiconductors, and particularly relates to an IGBT with an NP stacked drift region. The present invention sets the voltage-resistant layer of the IGBT to be formed by stacking an N-type drift region (4) and a P-type drift region (5) up and down to form an NP stacked drift region, so that the NP stacked drift region forms a Shockley diode structure inside the device, and the Shockley diode is composed of a PNP transistor (emitter: P+ collector, base: N-type field stop layer, collector: P-type drift region) and an NPN transistor (emitter: N-type carrier storage layer, base: P-type drift region, collector: N-type drift region), thereby achieving a better compromise relationship between on-state voltage drop and off-state loss.

Description

Technical Field

[0001] The present invention belongs to the technical field of power semiconductors, and in particular relates to an IGBT (Insulated gate bipolar transistor) structure with an NP stacked drift region. Background Art

[0002] IGBT is an important power device and is widely used. It pursues a better compromise between on-state voltage drop and turn-off loss. The traditional method of optimizing IGBT on-state voltage drop and turn-off loss mainly changes the gate and cathode structures to enhance cathode side carrier storage, changes the anode structure to reduce anode side carrier accumulation, and changes the withstand voltage layer structure to accelerate the extraction of carriers in the drift region. The change to the withstand voltage layer is mainly achieved by introducing alternating PN strips in the drift region to form a super junction structure. However, the super junction structure has high requirements on the N / P strip charge and is difficult to design and manufacture. Summary of the invention

[0003] The purpose of the present invention is to optimize the on-state voltage drop and turn-off loss of the IGBT and to provide an IGBT with an NP stacked drift region.

[0004] The technical solution of the present invention is: an IGBT with an NP stacked drift region, wherein a half cell comprises a collector structure, a voltage-resistant layer structure, an emitter structure and a gate structure, wherein the voltage-resistant layer structure is located above the collector structure, and the emitter structure and the gate structure are located above the voltage-resistant layer structure:

[0005] The collector structure includes a collector metal 1, a P+ collector region 2 and an N-type field stop layer 3; the lower surface lead-out end of the collector metal 1 is the collector C of the device; the P+ collector region 2 is located on the upper surface of the collector metal 1; the N-type field stop layer 3 is located on the upper surface of the P+ collector region 2;

[0006] The emitter structure includes an N-type carrier storage layer 6, a P-type well region 7, an N-type emitter region 9, a P-type body contact region 8 and an emitter metal 10; the N-type carrier storage layer 6 is located on the upper surface of the voltage-resistant layer structure; the P-type well region 7 is located on the upper surface of the N-type carrier storage layer 6; the N-type emitter region 9 and the P-type body contact region 8 are located on the upper surface of the P-type well region 7; the lower surface of the emitter metal 10 is in contact with the upper surfaces of the N-type emitter region 9 and the P-type body contact region 8 at the same time, and the lead-out end of the upper surface is the emitter E of the device;

[0007] The gate structure is a trench gate structure, which includes an insulating medium 12 and a conductive material 11; the conductive material 11 is located in the insulating medium 12, and its lead end is the gate G of the device; the insulating medium 12 vertically passes through the P-type well region 7 and the N-type carrier storage layer 6 from the device surface, and its side surface is in contact with the N-type carrier storage layer 6, the P-type well region 7, and the N-type emitter region 9;

[0008] It is characterized in that the voltage-resistant layer includes an N-type drift region 4 and a P-type drift region 5, which are stacked up and down to form an NP stacked drift region; the lower surface of the N-type drift region 4 contacts the upper surface of the N-type field stop layer 3, and its upper surface contacts the lower surface of the P-type drift region 5; the upper surface of the P-type drift region simultaneously contacts the lower surface and side surface of the insulating medium 12 and the lower surface of the N-type carrier storage layer 6.

[0009] The beneficial effect of the present invention is that the IGBT with the NP stacked drift region of the present invention achieves a better compromise relationship between the on-state voltage drop and the off-state loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 The IGBT structure of the present invention;

[0011] Figure 2 is the IGBT equivalent circuit of the present invention;

[0012] Figure 3 It is the IGBT equivalent circuit and structure corresponding diagram of the present invention;

[0013] Figure 4 It is a conventional IGBT structure;

[0014] Figure 5 It is a conventional IGBT equivalent circuit; DETAILED DESCRIPTION

[0015] The present invention will be described in detail below with reference to the accompanying drawings.

[0016] like Figure 1 As shown in FIG. 1 , an IGBT structure with an NP stacked drift region according to the present invention is shown in FIG. 1 . Figure 2 shown. Figure 3 Will Figure 2 The equivalent circuit in is mapped into the structure. Figure 4 and Figure 5The conventional IGBT structure and equivalent circuit diagram are shown respectively. It can be seen that the NP stacked drift region of the device of the present invention forms a Shockley diode structure inside the device. This Shockley diode is composed of a PNP transistor (emitter: P+ collector 2, base: N-type field stop layer 3, collector: P-type drift region 5) and an NPN transistor (emitter: N-type carrier storage layer 6, base: P-type drift region 5, collector: N-type drift region 4).

[0017] The working principle of the device of the present invention is as follows:

[0018] During withstand voltage: the device gate is turned off, the emitter is grounded and the collector is connected to a positive potential. At this time, the emitter (N-type carrier storage layer 6) of the NPN transistor in the Shockley diode is in a floating state, so the Shockley diode will not be turned on, and the Shockley diode withstands voltage. The electric field is mainly borne by the junction of the N-type drift region 4 and the P-type drift region 5. Since this junction is far away from the surface of the device, the high electric field is located in the body during withstand voltage, and the electric field at the surface gate structure and the N-type carrier storage layer are both low, so the device can achieve high withstand voltage.

[0019] When forward conducting: the gate of the device is turned on, the emitter is grounded and the collector is connected to a positive potential. At this time, the gate channel is turned on, and the emitter (N-type carrier storage layer 6) of the NPN transistor in the Shockley diode is connected to the N+ emitter 9, and it is no longer floating. Therefore, as the anode voltage increases, the holes injected into the P-type drift region 5 by the P+ anode 2 gradually turn on the NPN transistor (emitter: N-type carrier storage layer 6, base: P-type drift region 5, collector: N-type drift region 4). After the NPN transistor is turned on, electrons are injected into the N-type drift region 4, turning on the PNP transistor (emitter: P+ collector 2, base: N-type field stop layer 3, collector: P-type drift region 5). Finally, the Shockley diode enters the PNPN thyristor conduction mode. Both the N-type drift region 4 and the P-type drift region 5 have a conductivity modulation effect, and the device conduction voltage drops.

[0020] When turned off: the device gate is turned off, the emitter is grounded and the collector is connected to a positive potential. At this time, the gate channel changes from on to off, the emitter (N-type carrier storage layer 6) of the NPN transistor in the Shockley diode is disconnected from the N+ emitter 9, and it re-enters a floating state, and the Shockley diode gradually exits from the PNPN thyristor conduction mode. Since the junction of the voltage-resistant N-type drift region 4 and the P-type drift region 5 is located inside the drift region, the electric field needs to be established here if the device is to withstand voltage. Since there are a large number of hole carriers in the drift region, the concentration near this PN junction needs to be reduced in order to establish an electric field at this PN junction. Therefore, the holes in the P-type drift region have been discharged through the emitter before the electric field is established at the PN junction, and the holes in the N-type drift region are also reduced. Therefore, when the electric field is established, the carriers in the P-type drift region and the N-type drift region have been sharply reduced, and the depletion region is depleted in two directions. Therefore, the electric field in the device is established faster, the voltage rise time is reduced, and the device turn-off loss will be reduced.

Claims

1. An IGBT with an NP stack drift region, wherein a half cell comprises a collector structure, a voltage-resistant layer structure, an emitter structure and a gate structure, wherein the voltage-resistant layer structure is located above the collector structure, and the emitter structure and the gate structure are located above the voltage-resistant layer structure: The collector structure comprises a collector metal (1), a P+ collector region (2) and an N-type field stop layer (3); the lower surface lead-out end of the collector metal (1) is the collector (C) of the device; the P+ collector region (2) is located on the upper surface of the collector metal (1); and the N-type field stop layer (3) is located on the upper surface of the P+ collector region (2); The emitter structure comprises an N-type carrier storage layer (6), a P-type well region (7), an N-type emitter region (9), a P-type body contact region (8) and an emitter metal (10); the N-type carrier storage layer (6) is located on the upper surface of the voltage-resistant layer structure; the P-type well region (7) is located on the upper surface of the N-type carrier storage layer (6); the N-type emitter region (9) and the P-type body contact region (8) are located on the upper surface of the P-type well region (7); the lower surface of the emitter metal (10) is in contact with the upper surfaces of the N-type emitter region (9) and the P-type body contact region (8), and the lead-out end of the upper surface of the emitter metal (10) is the emitter (E) of the device; The gate structure is a trench gate structure, comprising an insulating medium (12) and a conductive material (11); the conductive material (11) is located in the insulating medium (12), and its lead end is the gate (G) of the device; the insulating medium (12) vertically passes through the P-type well region (7) and the N-type carrier storage layer (6) from the surface of the device, and its side surface is in contact with the N-type carrier storage layer (6), the P-type well region (7), and the N-type emitter region (9); It is characterized in that The voltage-resistant layer comprises an N-type drift region (4) and a P-type drift region (5), which are stacked up and down to form an NP stacked drift region; the lower surface of the N-type drift region (4) contacts the upper surface of the N-type field stop layer (3), and the upper surface of the N-type drift region (4) contacts the lower surface of the P-type drift region (5); and the upper surface of the P-type drift region (5) contacts the lower surface and side surface of the insulating medium (12) and the lower surface of the N-type carrier storage layer (6) at the same time.

Images