Method for forming a semiconductor device

Abstract

A method of forming a semiconductor device includes forming a first interlayer dielectric layer over a source region and a drain region of a semiconductor structure; forming a first masking material over the first interlayer dielectric layer; etching a plurality of first openings in the first masking material; filling the first openings with a fill material; etching a second opening in the fill material; filling the second opening with a second masking material; removing the fill material; and etching the first interlayer dielectric layer with the first masking material and the second masking material as an etching mask to form a plurality of third openings in the first interlayer dielectric layer, the third openings exposing portions of the source region and the drain region of the semiconductor structure.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for forming the same, and particularly to the source / drain contacts for forming a fin field-effect transistor. Background Technology

[0002] Semiconductor devices are used in many different electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. The formation of a semiconductor device typically involves depositing layers of insulating or dielectric material, conductive layer, and semiconductor layer sequentially on a semiconductor substrate, and then using photolithography to pattern these material layers to form circuit components and elements on the semiconductor substrate.

[0003] The semiconductor industry has continuously improved the packing density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by constantly shrinking the minimum feature size, enabling the integration of more components into a given area. However, as the minimum feature size shrinks, some additional problems arise that need to be addressed. Summary of the Invention

[0004] One embodiment relates to a method of forming a semiconductor device. The method includes: forming a first inter-layer dielectric (ILD) over a source region and a drain region of a semiconductor structure; forming a first masking material over the first inter-layer dielectric; etching a plurality of first openings in the first masking material; filling the first openings with a filler material; etching a plurality of second openings in the filler material; filling the second openings with a second masking material; removing the filler material; and etching the first inter-layer dielectric using the first and second masking materials as an etching mask to form a plurality of third openings in the first inter-layer dielectric, the third openings exposing portions of the source and drain regions of the semiconductor structure.

[0005] Another embodiment relates to a method for forming a semiconductor device. The method for forming the semiconductor device includes: depositing an inter-layer dielectric layer over a first source / drain region and over a second source / drain region. Dielectric (ILD); forming an etch mask above the interlayer dielectric layer includes: depositing a first mask material above the interlayer dielectric layer; forming a first opening in the first mask material, the first opening extending above the first source / drain region and above the second source / drain region; filling the first opening with a dielectric material; forming a second opening in the dielectric material, the second opening located between the first source / drain region and the second source / drain region; filling the second opening with a second mask material; and etching a first contact opening in the interlayer dielectric layer to expose the first source / drain region, and etching a second contact opening in the interlayer dielectric layer to expose the second source / drain region, wherein an isolation region of the interlayer dielectric layer below the second mask material isolates the first contact opening from the second contact opening.

[0006] Another embodiment relates to a method of forming a semiconductor device. The method of forming the aforementioned semiconductor device includes: forming a plurality of fins protruding from a substrate and extending in a first direction; forming a plurality of gate stacks extending above the fins and extending in a second direction orthogonal to the first direction; forming a plurality of source / drain regions on the fins; depositing an inter-layer dielectric (ILD) layer above the source / drain regions; forming a first patterned mask, including: depositing a sacrificial material above the inter-layer dielectric layer and above the gate stacks; patterning a plurality of openings in the sacrificial material, wherein each opening extends above at least two gate stacks of the gate stacks; depositing a masking material within the openings, the first patterned mask including the masking material; using the first patterned mask to etch the inter-layer dielectric layer to form a plurality of contact openings above the source / drain regions; and filling the contact openings with a conductive material to form a plurality of source / drain contacts. Attached Figure Description

[0007] The following detailed description, in conjunction with the accompanying illustrations, will provide a better understanding of the content disclosed herein. It should be emphasized that, in accordance with industry standard practice, the various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the individual features may be arbitrarily enlarged or reduced for clarity of discussion.

[0008] Figure 1 This illustration shows a perspective view of an intermediate stage in the formation of a Fin Field-Effect Transistor (FinFET) device, according to some embodiments.

[0009] Figure 2 A perspective view illustrating an intermediate stage in the formation of a fin field-effect transistor device according to some embodiments.

[0010] Figure 3 This illustration shows a top view of an intermediate stage in the formation of the source / drain contacts of a fin field-effect transistor device, according to some embodiments.

[0011] Figure 4 This illustration shows a top view of an intermediate stage in the formation of the source / drain contacts of a fin field-effect transistor device, according to some embodiments.

[0012] Figure 5 This illustration shows a top view of an intermediate stage in the formation of the source / drain contacts of a fin field-effect transistor device, according to some embodiments.

[0013] Figure 6 This illustration shows a top view of an intermediate stage in the formation of the source / drain contacts of a fin field-effect transistor device, according to some embodiments.

[0014] Figure 7 This illustration shows a top view of an intermediate stage in the formation of the source / drain contacts of a fin field-effect transistor device, according to some embodiments.

[0015] Figure 8 This illustration shows a top view of an intermediate stage in the formation of the source / drain contacts of a fin field-effect transistor device, according to some embodiments.

[0016] Figure 9 This illustration shows a top view of an intermediate stage in the formation of the source / drain contacts of a fin field-effect transistor device, according to some embodiments.

[0017] Figure 10 This illustration shows a top view of an intermediate stage in the formation of the source / drain contacts of a fin field-effect transistor device, according to some embodiments.

[0018] Figure 11 This illustration shows a top view of an intermediate stage in the formation of the source / drain contacts of a fin field-effect transistor device, according to some embodiments.

[0019] Figure 12 This illustration shows a top view of an intermediate stage in the formation of the source / drain contacts of a fin field-effect transistor device, according to some embodiments.

[0020] Figure 13This illustration shows a top view of an intermediate stage in the formation of the source / drain contacts of a fin field-effect transistor device, according to some embodiments.

[0021] Figure 14 This illustration shows a top view of an intermediate stage in the formation of the source / drain contacts of a fin field-effect transistor device, according to some embodiments.

[0022] Figure 15 This illustration shows a top view of an intermediate stage in the formation of the source / drain contacts of a fin field-effect transistor device, according to some embodiments.

[0023] Figure 16A , Figure 16B and Figure 16C Various views are illustrated according to other embodiments at the intermediate stage of forming the source / drain contacts for a fin field-effect transistor device.

[0024] Figure 17A , Figure 17B and Figure 17C Various views are illustrated at the intermediate stage of forming the source / drain contacts of a fin field-effect transistor device according to other embodiments.

[0025] The reference numerals in the attached figures are explained as follows:

[0026] 10: Wafers

[0027] 20: Base

[0028] 22: Shallow trench isolation zone

[0029] 24: Fins

[0030] 30: Dummy gate stack

[0031] 32: Dummy gate dielectric

[0032] 34: Dummy gate electrode

[0033] 36: Masking layer

[0034] 38: Gate spacer

[0035] 42, 42A, 42B: Epitaxial source / drain regions

[0036] 46: Contact Etching Stop Layer

[0037] 48: First interlayer dielectric

[0038] 52: Gate dielectric layer

[0039] 56: Gate electrode

[0040] 60: Replace gate stack

[0041] 62: Hard mask

[0042] 64: Second interlayer dielectric layer

[0043] 66: Etching Stop Layer

[0044] 68: Hard mask layer

[0045] 70: Opening

[0046] 72: Filler material

[0047] 80: Photoresist structure

[0048] 82: Bottom layer

[0049] 84: Intermediate layer

[0050] 86: Upper level

[0051] 88: Opening

[0052] 90, 90A: Segmented Mask

[0053] 90': Sliced ​​masking material

[0054] 92, 92A, 92B: Contact openings

[0055] 112, 112A, 112B: Source / Drain Contacts

[0056] 112': Contact material

[0057] A1: Angle

[0058] W1, W2, W3, W5: Width

[0059] W4: Cutting width

[0060] WB: Bottom width

[0061] WT1: Top width

[0062] T1, T2, T3, T4, T5: Thickness

[0063] XX, YY: Cross-section Detailed Implementation

[0064] The following disclosure provides numerous different embodiments or examples for implementing various components of the provided patent-claimed invention. Specific examples of components and configurations are described below to simplify the description of embodiments of the invention. Of course, these are merely examples and are not intended to limit the embodiments of the invention. For instance, the following description, referring to a first component being formed on or above a second component, may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, the embodiments of the invention may repeat the numbers and / or letters of element symbols in various examples; this repetition is for simplicity and clarity and does not specify a relationship between the various embodiments and / or configurations discussed.

[0065] Furthermore, spatial relative terms such as "below," "under," "lower than," "below," "above," "above," "above," and similar terms may be used to help describe the relationship between one element or component shown in the figure and another element or component(s). These spatial relative terms are used to cover different orientations of the device in use or operation, other than those depicted in the figure. The device may be rotated (90 degrees or other orientations), and the spatial relative descriptions used herein may be interpreted accordingly.

[0066] This document provides a semiconductor device and a method for forming the same, based on various embodiments. Specifically, it describes the formation of source / drain contacts for a fin field-effect transistor. Openings for the source / drain contacts can be formed, for example, by forming a hard mask over an inter-layer dielectric (ILD). The openings are etched into the hard mask, corresponding to larger areas where the source / drain contacts are formed. These openings in the hard mask are filled with a sacrificial material. The sacrificial material is then patterned, with the pattern corresponding to cuts subsequently formed between the source / drain contacts. The pattern in the sacrificial material is filled with a cut mask material to form a patterned cut mask. Then, using the hard mask as an etching mask, the openings for the source / drain contacts are etched. In some cases, sacrificial materials are used to form a patterned cut mask, resulting in smaller cuts between the source / drain contacts (for example, cuts with a smaller width or a finer pitch). Furthermore, the use of this patterned cut mask can create contact openings with a smaller width near the bottom, improving the filling process for forming the source / drain contacts.

[0067] Throughout the various views and embodiments illustrated in the drawings, similar element symbols are used to represent similar elements. In some illustrated embodiments, the formation of Fin Field-Effect Transistors (FinFETs) is used as an example to explain the concept of the embodiments of the present invention. The illustrated FinFETs can be electrically coupled to operate as, for example, a single transistor or as multiple transistors such as two or more transistors. Other types of transistors, such as planar transistors, Gate-All-Around (GAA) transistors, or similar transistors, can also be applied to the embodiments of the present invention. The embodiments discussed herein are provided to provide examples of how to make or use the subject matter of the embodiments of the present invention, and modifications that can be made while still within the scope of the various embodiments will be readily understood by those skilled in the art. In the following drawings, numbers and / or letters of similar element symbols are used to represent similar components. Although method embodiments are discussed in a particular order, other method embodiments can be implemented in any logical order. Some embodiments discussed herein are presented in the context of fin field-effect transistors formed using a gate-last process. In other embodiments, a gate-first process may be used. Furthermore, some embodiments cover applications in planar devices, such as planar field-effect transistors.

[0068] Figure 1This illustration depicts a perspective view of an intermediate stage in the formation of a fin field-effect transistor structure according to some embodiments. The structure includes a wafer 10, which further includes a substrate 20. The substrate 20 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or a similar substrate, which may be doped (e.g., with a p-type or n-type dopant) or undoped. The substrate 20 may be a wafer, such as a silicon wafer. Generally, a semiconductor-on-insulator substrate is a layer of semiconductor material formed on an insulating layer. This insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is provided on a substrate, typically a silicon or glass substrate. Other substrates may also be used, such as multilayer or gradient substrates. In some embodiments, the semiconductor material of the substrate 20 may include: silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or a combination of the above.

[0069] exist Figure 1The image shows multiple fins 24 formed on the substrate 20. The fins 24 are semiconductor strips, and may also be referred to as "semiconductor fins," "semiconductor strips," or "strips." In some embodiments of the invention, the fins 24 are part of the original substrate 20, and therefore the material of the fins 24 is the same as that of the substrate 20. In some embodiments, the fins 24 are formed by forming trenches through local etching of the substrate 20. The etching can be any suitable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), similar processes, or combinations thereof. The etching can be anisotropic. The fins 24 can be patterned by any method. For example, patterning can be performed using one or more lithography processes, including double-patterning or multi-patterning processes, to pattern the fins 24. Generally, the aforementioned dual or multiple patterning processes combine lithography and self-alignment processes, resulting in a pattern with a smaller pitch than that achievable using, for example, a single, direct lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a lithography process. A plurality of spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels can be used to pattern the fin 24. In some embodiments, a mask (or other layer) may remain on the fin 24. In some embodiments, the fin 24 may be formed using an epitaxial growth process. For example, a dielectric layer may be formed over a top surface of a substrate 20, and trenches may be etched through the dielectric layer to expose the underlying substrate 20. Homoethelic structures may be epitaxially grown in the trenches, and the dielectric layer may be recessed such that the homoethelic structure protrudes from the dielectric layer to form the fin 24. Furthermore, in some embodiments, a heteroepitaxial structure can be used for the fin 24. For example, it can be... Figure 1The fin 24 is recessed, and a material different from the substrate 20 can be epitaxially grown over the recessed fin 24. In such an embodiment, the fin 24 includes both the recessed material and the epitaxially grown material positioned over the recessed material. Therefore, the fin 24 can be formed with a semiconductor material different from the semiconductor material of the substrate 20. According to some embodiments, the fin 24 is formed with the following materials: silicon; germanium; a compound semiconductor including silicon phosphide, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or a combination of the above.

[0070] In another embodiment, a dielectric layer may be formed above a top surface of the substrate 20, and trenches may be etched through the dielectric layer. A heteroepitaxial structure may then be epitaxially grown in the trenches using a material different from that of the substrate 20, and the dielectric layer may be recessed so that the heteroepitaxial structure protrudes from the dielectric layer to form fins 24. In some embodiments of epitaxially growing homoepitaxial or heteroepitaxial structures, the epitaxial growth material may be in-situ doped during growth, thus eliminating the need for prior implantation and subsequent implantation steps, although in-situ and implantation doping can be used together.

[0071] In the above embodiments, the fin 24 can be patterned by any method. For example, patterning can be performed using one or more lithography processes, including dual or multiple patterning processes, to pattern the fin 24. Generally, the aforementioned dual or multiple patterning processes combine lithography with a self-aligned process, resulting in a pattern with a smaller intercept than that achievable using, for example, a single, direct lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a lithography process. A plurality of spacers are formed next to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers or mandrel can then be used to pattern the fin 24.

[0072] like Figure 1As shown, multiple shallow trench isolation (STI) regions 22 are formed between the fins 24. The shallow trench isolation regions 22 may comprise a material, such as an oxide, nitride, or combination thereof, of silicon oxide, and may be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable chemical vapor deposition (FCVD, for example, a CVD-based material deposited in a remote plasma system and post-cured to transform it into another material, such as an oxide), or a combination thereof. Other insulating materials formed using any acceptable process may be used. Once the insulating material is formed, an annealing process may be performed. Although the shallow trench isolation region 22 is illustrated as a single film layer, some embodiments may use multiple film layers. For example, in some embodiments, a liner (not shown) may be formed first along the surfaces of the substrate 20 and the fins 24. Subsequently, a filling material as discussed above can be formed on top of the aforementioned liner.

[0073] After the material for the shallow trench isolation region 22 is formed, a planarization process can be performed to remove the material from the shallow trench isolation region 22 and expose the fins 24. The planarization process can be, for example, chemical mechanical polishing (CMP), etch-back, a combination thereof, or similar methods. The planarization process exposes the fins 24 such that, after the planarization process is completed, the top surface of the fins 24 is flush with the top surface of the shallow trench isolation region 22. In an embodiment where a mask remains on the fins 24, the planarization process can expose or remove the mask such that, after the planarization process is completed, the top surface of the mask or the top surface of the fins 24 is flush with the top surface of the shallow trench isolation region 22, respectively.

[0074] The shallow trench isolation region 22 can be recessed such that the top of the fin 24 protrudes above the remaining portion of the shallow trench isolation region 22. The top surface of the shallow trench isolation region 22 may have a flat surface, a convex surface, a concave surface (such as a dishing surface), or a combination thereof, as shown in the figure. The shallow trench isolation region 22 can be recessed using an acceptable etching process, such as an etching process selective for the material of the shallow trench isolation region 22 (for example, etching the material of the shallow trench isolation region 22 at a faster rate than the material of the fin 24). For example, the etching can be performed using a dry etching process, such as a process using NF3 and NH3 as etching gases. An alternative embodiment of the invention is to perform a wet etching process to recess the shallow trench isolation region 22. For example, an oxide removal method can be used, which may use, for example, diluted hydrofluoric acid (dHF).

[0075] Reference again Figure 1 A plurality of dummy gate stacks 30 are formed on the top surface and sidewalls of the fin 24. Each dummy gate stack 30 may include a dummy gate dielectric 32 and a dummy gate electrode 34 formed above the dummy gate dielectric 32. Each dummy gate stack 30 may also include a masking layer 36 above the dummy gate electrode 34. The masking layer 36 may include one or more layers. The dummy gate stacks 30 may intersect above one or more fins 24 and / or shallow trench isolation regions 22. The dummy gate stacks 30 also have a length direction orthogonal to the length direction of the fin 24.

[0076] The dummy gate dielectric 32 may include, for example, silicon oxide, silicon nitride, combinations thereof, or the like, and may be deposited or thermally grown using acceptable techniques. A dummy gate electrode 34 may be deposited over the dummy gate dielectric 32 and then planarized by, for example, chemical mechanical polishing. A masking layer 36 may be deposited over the dummy gate electrode 34. The dummy gate electrode 34 may be a conductive or non-conductive material and may be selected from a group including: amorphous silicon, polycrystalline silicon, polycrystalline silicon-germanium, metal nitrides, metal silicides, metal oxides, and metals. The dummy gate electrode 34 may be deposited by physical vapor deposition (PVD), chemical vapor deposition, sputtering deposition, or other techniques well known to those skilled in the art for depositing the selected material. The dummy gate electrode 34 may be formed of other materials that have high etch selectivity relative to the etching of the shallow trench isolation region. The masking layer 36 may include, for example, silicon nitride, silicon oxynitride, silicon carbide, the like, or combinations thereof. It should be noted that, for illustrative purposes only, the dummy gate dielectric 32 is depicted as covering the fin 24 and the shallow trench isolation region 22; however, in other embodiments, the dummy gate dielectric 32 may be deposited such that it does not extend to the surface of the shallow trench isolation region 22.

[0077] Next, a plurality of gate spacers 38 are formed on the sidewalls of the dummy gate stack 30. In some embodiments, the gate spacers 38 can be formed by heating oxidation or deposition followed by anisotropic etching. According to some embodiments of the present invention, the gate spacers 38 are formed of, for example, silicon nitride, silicon oxide, silicon carbonitride, silicon oxynitride, silicon oxycarbonitride, or the like, and can have a single-layer structure or a multilayer structure including multiple dielectric layers. After the gate spacers 38 are formed, placement for lightly doped source / drain (LDD) regions (not explicitly shown) can be performed. In some embodiments, after the placement of the lightly doped source / drain regions, one or more layers of gate spacers 38 are formed.

[0078] Please refer to the following: Figure 1According to some embodiments, multiple epitaxial source / drain regions 42 are formed in the fin 24. An etching step (hereinafter referred to as source / drain recess) can be performed to etch the portion of the fin 24 not covered by the dummy gate stack 30 and gate spacer 38. The recess can be anisotropic, so the portion of the fin 24 directly below the dummy gate stack 30 and gate spacer 38 is not etched. The top surface of the recessed fin 24 can be lower than the top surface of the shallow trench isolation region 22, such as... Figure 1 As shown. For example, fin 24 can be etched using a selective etching process, such as NF3 and NH3, HF and NH3, or the like. In other embodiments, fin 24 is not recessed prior to the formation of the epitaxial source / drain region 42.

[0079] According to some embodiments, an epitaxial source / drain region 42 is then formed on the recessed portion of the fin 24. The epitaxial source / drain region 42 can be formed, for example, by selectively growing a semiconductor material from the recessed portion of the fin 24, resulting in... Figure 1 The structure is described. According to some embodiments, the epitaxial source / drain region 42 includes silicon germanium, silicon, silicon carbon, germanium, the like, or combinations thereof. Depending on whether the resulting fin field-effect transistor is a p-type or n-type fin field-effect transistor, p-type or n-type impurities can be simultaneously doped during the epitaxial growth process. For example, when the formed fin field-effect transistor is a p-type fin field-effect transistor, silicon germanium, germanium tin, boron-doped silicon germanium (SiGeB), boron-doped germanium, the like, or combinations thereof can be grown. When the formed fin field-effect transistor is an n-type fin field-effect transistor, silicon phosphorus (SiP), silicon carbide (SiC), phosphorus-doped silicon carbide (SiCP), or the like can be grown. In an alternative embodiment of the present invention, the epitaxial source / drain region 42 is formed of a III-V compound semiconductor, such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, combinations thereof, or multilayer structures thereof. The epitaxial source / drain region 42 may also have a surface raised from the corresponding surface of the fin 24 and may have facets. Subsequent drawings are shown in [reference to figure 1]. Figure 1 The structure formed by the structure, but the embodiments and techniques described herein can be used as shown in Figure 1 The structure or other structure, embodiment or device.

[0080] Figure 1 Several reference cross-sections are further illustrated. Cross-section XX is along the longitudinal axis of fin 24 and the direction of current between, for example, the epitaxial source / drain region 42 of a fin field-effect transistor. Cross-section YY is orthogonal to cross-section XX and extends through the epitaxial source / drain region 42 of the aforementioned fin field-effect transistor. For clarity, subsequent figures refer to these reference cross-sections.

[0081] Transfer to Figure 2 ,exist Figure 1 An interlayer dielectric (ILD) 48 is deposited above the illustrated structure. The interlayer dielectric 48 is formed of a dielectric material that can be deposited by any suitable method, such as chemical vapor deposition, plasma-enhanced chemical vapor deposition (PECVD), or flowable chemical vapor deposition (FCVD). The dielectric material may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulating materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) 46 may be provided between the interlayer dielectric 48 and the epitaxial source / drain region 42 and gate spacer 38. The contact etch stop layer 46 may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, silicon carbide nitride, or the like, which has a different etch rate compared to the material of the upper interlayer dielectric 48. A planarization process, such as a chemical mechanical polishing process or a mechanical grinding process, may be performed to make the top surface of the interlayer dielectric 48 flush. The interlayer dielectric 48 may have a thickness T1 (see...). Figure 3 In some embodiments, the thickness is between about 50 nm and about 80 nm, or it can be other thicknesses.

[0082] According to some embodiments, the dummy gate dielectric 32, dummy gate electrode 34, and masking layer 36 are removed to form a replacement gate stack 60. In some embodiments, an anisotropic dry etching process can be used to remove the dummy gate dielectric 32, dummy gate electrode 34, and masking layer 36. For example, the etching process described above may include a dry etching process using an etching gas that selectively etches the dummy gate dielectric 32, dummy gate electrode 34, and masking layer 36 without etching the first interlayer dielectric 48 or gate spacer 38. In some embodiments, a wet etching process or an oxide removal process can be used. In some embodiments, the dummy gate dielectric 32 is removed from a first region of a die (e.g., a core logic region) leaving the dummy gate dielectric 32 in a second region of the die (e.g., an input / output region). The removal of the dummy gate dielectric 32 and the dummy gate electrode 34 forms a recess that exposes a channel region of a corresponding fin 24. During the removal process, the dummy gate dielectric 32 can be used as an etch stop layer when etching the dummy gate electrode 34. Then, after removing the dummy gate electrode 34, the dummy gate dielectric 32 can be selectively removed or not.

[0083] According to some embodiments, the replacement gate stack 60 includes a gate dielectric layer 52 and a gate electrode 56. The gate dielectric layer 52 is conformally deposited in the aforementioned recess, for example, on the top surface and sidewalls of the fin 24 and on the sidewalls of the gate spacer 38. The gate dielectric layer 52 may also be deposited on the top surface of the first interlayer dielectric layer 48. According to some embodiments, the gate dielectric layer 52 includes silicon oxide, silicon nitride, or a multilayer thereof. In some embodiments, the gate dielectric layer 52 includes a high dielectric constant dielectric material, and in these embodiments, the gate dielectric layer 52 may have a dielectric constant greater than about 7.0, and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, magnesium, barium, titanium, lead, and combinations thereof. Methods for forming the gate dielectric layer 52 may include molecular beam deposition (MBD), atomic layer deposition (ALD), plasma-assisted chemical vapor deposition, similar methods, or combinations thereof. In embodiments where a portion of the dummy gate dielectric 32 remains in the aforementioned recess, the gate dielectric layer 52 comprises the material of the dummy gate dielectric 32 (for example, SiO2).

[0084] Gate electrodes 56 are deposited above the gate dielectric layer 52 and fill the remaining portion of the aforementioned recess. Gate electrodes 56 may comprise a metallic material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. For example, although... Figure 2 The diagram illustrates a single-layer gate electrode 56, which may include any number of liner layers, any number of work function tuning layers, and a filler material. A planarization process, such as chemical mechanical polishing, can be performed to remove excess material from the gate dielectric layer 52 and the gate electrode 56, which lies above the top surface of the first interlayer dielectric 48. The remaining material of the gate electrode 56 and the gate dielectric layer 52 thus form the replacement gate stack 60 of the fabricated fin field-effect transistor. The gate electrode 56 and the gate dielectric layer 52 can be considered together as a "replacement gate stack 60," a "gate stack," or a "gate structure." The replacement gate stack 60 may extend along a channel region of the fin 24.

[0085] The formation of the gate dielectric layer 52 in different regions of wafer 10 can occur simultaneously, with the gate dielectric layer 52 in each region being formed of the same material, and the formation of the gate electrode 56 can occur simultaneously, with the gate electrode 56 in each region being formed of the same material. In some embodiments, the gate dielectric layer 52 in each region can be formed using different processes, allowing the gate dielectric layer 52 to be made of different materials, and / or the gate electrode 56 in each region can be formed using different processes, allowing the gate electrode 56 to be made of different materials. When using different processes, various masking steps can be used to mask and expose appropriate areas.

[0086] Please refer to the following: Figure 2 According to some embodiments, a hard mask 62 may be formed over the replacement gate stack 60. The hard mask 62 may be formed of, for example, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon oxycarbonitrile, the like, or combinations thereof. Forming the hard mask 62 may include recessing the replacement gate stack 60 (including the gate dielectric layer 52 and the corresponding upper gate electrode 56) using one or more etching processes to form recesses, such that the recesses are formed directly above the replacement gate stack 60 and between the portions opposite the gate spacers 38. Figure 2 As shown, the gate spacer 38 is also etched. Then, a dielectric material is filled into the recess, and a planarization process is performed to remove excess dielectric material. The remaining portion of the dielectric material forms a hard mask 62. In some embodiments, before forming the hard mask 62, one or more additional dielectric layers may be formed over the recessed gate electrode 56, which may include, for example, an etch stop layer.

[0087] Figures 3 to 17C The illustration depicts the formation of source / drain contacts 112 according to some embodiments (see [reference]). Figures 16A to 16C )and Figures 17A to 17C Various views of the intermediate stage. Figures 3 to 15 , Figure 16C and Figure 17C The drawing corresponds to the one shown in Figure 1 A cross-sectional view of section YY. Figure 16B and Figure 17B The drawing corresponds to the one shown in Figure 1 A cross-sectional view of section XX. Figure 16A and Figure 17A A plan view is shown. The various views shown in the figures are merely examples; other configurations or arrangements not shown are also considered within the scope of embodiments of the invention.

[0088] exist Figure 3 In this process, a second interlayer dielectric layer 64 is deposited above the first interlayer dielectric layer 48. In some embodiments, the second interlayer dielectric layer 64 is a flowable thin film formed by a flow-through chemical vapor deposition method. In some embodiments, the second interlayer dielectric layer 64 is formed of a dielectric material, such as phosphosilicate glass, borosilicate glass, boron-doped phosphosilicate glass, undoped silicate glass, or the like, and can be deposited by any suitable method, such as chemical vapor deposition, plasma-assisted chemical vapor deposition, or similar methods. The second interlayer dielectric layer 64 may have a thickness T2, which in some embodiments is between about 10 nm and about 20 nm, but may be other thicknesses.

[0089] exist Figure 4 In this process, an etch stop layer 66 is formed above the first interlayer dielectric 48. The etch stop layer 66 may include a dielectric material, such as silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, aluminum oxide, hafnium oxide, similar materials, or combinations thereof, and is compatible with the material of the first interlayer dielectric 48 and the upper filler material 72 (see [link to documentation]). Figure 7 (Comparison) can be performed at different etch rates. In some embodiments, the etch stop layer 66 has a thickness of approximately With the agreement The etch stop layer 66 can be formed by a process such as chemical vapor deposition, atomic layer deposition, or a similar process. In other embodiments, an etch stop layer 66 is not formed over the first interlayer dielectric 48.

[0090] A hard mask layer 68 is formed above the etch stop layer 66. In some embodiments, the hard mask layer 68 may be formed of materials including: a metal (e.g., titanium nitride (TiN), titanium, tantalum nitride, tantalum, a metal-doped carbide (e.g., tungsten carbide (WC)) or the like) and / or a non-metal (e.g., silicon nitride, boron nitride, silicon carbide or the like). In some embodiments, the material composition of the hard mask layer 68 may be determined to provide high etch selectivity relative to the etch stop layer 66, other layers such as the first interlayer dielectric 48, and / or other subsequently formed layers. The hard mask layer 68 may be formed by a process such as chemical vapor deposition, atomic layer deposition, or similar processes. However, any suitable process and materials may be used. In some embodiments, the hard mask layer 68 may have a thickness T3 between about 10 nm and about 50 nm, but may be other thicknesses.

[0091] exist Figure 5 In some embodiments, an opening 70 is formed in the hard mask layer 68. The opening 70 can define a larger area of ​​the wafer 10, where the source / drain contacts 112 (see [link to relevant documentation]) are located. Figures 17A-17C An opening 70 can be formed within this larger region. In this way, the opening 70 can extend over multiple epitaxial source / drain regions 42 in either the X or Y direction. For example, shown in Figure 5 An opening 70 extends in the Y direction above the three epitaxial source / drain regions 42; in other embodiments, an opening 70 may extend above one, two or more of the three epitaxial source / drain regions 42.

[0092] An opening 70 can be formed in the hard mask layer 68 using appropriate optical lithography techniques. For example, a photoresist (e.g., three layers of photoresist or the like) can be formed over the hard mask layer 68 and patterned. This patterned photoresist can then be used as an etch mask to etch the hard mask layer 68. The hard mask layer 68 can be etched using an anisotropic etching process that selectively etches the hard mask layer 68 over the etch stop layer 66. This etching process can be, for example, a suitable dry etching process. In this way, multiple areas of the etch stop layer 66 are exposed through the opening 70. After forming the opening 70, any remaining portions or layers of the photoresist can be removed using, for example, an ashing process or other suitable process.

[0093] exist Figure 6In some embodiments, a filler material 72 is formed over the above structure to fill the opening 70. The filler material 72 may include one or more layers of dielectric material. For example, the filler material 72 may include: oxides, such as silicon oxide, titanium oxide, tantalum oxide, aluminum oxide, other metal oxides or the like; nitrides, such as silicon nitride, silicon oxynitride, metal nitrides or the like; or combinations thereof. The filler material 72 may be formed by a suitable process, such as chemical vapor deposition, flow-through chemical vapor deposition, plasma-assisted chemical vapor deposition, atomic layer deposition, physical vapor deposition, a spin coating process, similar processes or combinations thereof. These or other dielectric materials may be formed by any acceptable process. The filler material 72 may be a different dielectric material from the hard mask layer 68, allowing the filler material 72 to be selectively etched from the hard mask layer 68. In some embodiments, the filler material 72 is silicon oxide formed using flow-through chemical vapor deposition or a low-temperature oxide (for example: an oxide deposited using a process temperature of 200°C or lower). In some cases, the filler material 72 can be annealed after deposition. Other materials can also be used.

[0094] exist Figure 7 In some embodiments, a planarization process is used to remove excess filler material 72. This planarization process removes the filler material 72 from above the hard mask layer 68 and can thin the hard mask layer 68. After the planarization process, the remaining filler material 72 can have a substantially flat surface, which can be approximately flush with the hard mask layer 68. In some cases, a substantially flat surface can improve the formation of smaller components using subsequent optical lithography processes, such as those for... Figures 8 to 11 The illustrated planarization process includes a chemical mechanical polishing process, a grinding process, or a similar process. After planarization, the filler material 72 may have a thickness T4, which is between about 10 nm and about 50 nm, but may be other thicknesses. In some embodiments, the thickness T4 may be approximately the same as the thickness T3 of the hard mask layer 68. In some embodiments, after planarization, the height variation of the combined top surface of the hard mask layer 68 and the filler material 72 may be less than about 50 nm.

[0095] exist Figure 8 In some embodiments, a photoresist structure 80 is formed above the hard mask layer 68 and above the filler material 72, and the photoresist structure 80 is patterned. In response to... Figure 9 As explained, the photoresist structure 80 is used to pattern the filler material 72. For example... Figure 8As shown, the photoresist structure 80 can be a three-layer photoresist, or it can have any number of layers. In some cases, using a three-layer photoresist structure 80 improves the fine cutoff pattern defined by the filler material 72. For example, as shown in Figure 8 The photoresist structure 80 is a three-layer photoresist, comprising a bottom layer 82, an intermediate layer 84 above the bottom layer 82, and a top layer 86 above the intermediate layer 84. The top layer 86 may be formed of a photoresist (e.g., a photosensitive material), which may be an organic material and may be a positive or negative photosensitive material. In some embodiments, the bottom layer 82 is formed of a polymer material and may be a bottom anti-reflective coating (BARC). The intermediate layer 84 may comprise an inorganic material, which may be a nitride (e.g., silicon nitride), an oxide oxynitride (e.g., silicon oxynitride), an oxide (e.g., silicon oxide), the like, or a combination thereof. The intermediate layer 84 may have high etch selectivity relative to the top layer 86 and / or the bottom layer 82. The layers of the photoresist structure 80 may be sequentially deposited using, for example, a spin coating process and / or a suitable deposition process. Although this document discusses a three-layer photoresist structure 80, in other embodiments, the photoresist structure 80 may use a single-layer or double-layer structure (for example, including only a bottom layer 82 and an upper layer 86 without an intermediate layer 84). The type of structure used (for example, single-layer, double-layer, or triple-layer) may depend on the optical lithography process used. For example, in extreme ultraviolet (EUV) lithography, a single-layer or double-layer structure may be used. Figure 8 The photoresist structure 80 described is an example, and the photoresist structure may include other layers, materials, or combinations thereof.

[0096] like Figure 8 As shown, a suitable optical lithography process can be used to pattern the photoresist structure 80. In some embodiments, the patterning includes forming a plurality of openings 88 in the photoresist structure 80, the regions corresponding to the openings 88 being a cut-out mask 90 (see...). Figure 11 The opening 88 is located at the subsequent formation site. In some embodiments, the opening 88 is laterally located (for example, along the YY direction) between adjacent epitaxial source / drain regions 42. In some embodiments, the opening 88 may be formed with a width W1 along the YY direction, which is about 8 nm or greater, but may be other widths. In some embodiments, the opening 88 may be formed with a width along the XX direction, which is about 8 nm or greater, but may be other widths. The opening 88 may have a rectangular, circular, irregular shape, or other shape.

[0097] Subsequently, in order to pattern the intermediate layer 84 using an etching process (not shown separately in the diagram), the upper layer 86 can be used as an etching mask. This etching process can be anisotropic, causing the opening 88 in the upper layer 86 to extend through the intermediate layer 84. Then, in order to pattern the bottom layer 82 using an etching process (not shown separately in the diagram), the intermediate layer 84 can be used as an etching mask. This etching process can be anisotropic, causing the opening 88 in the intermediate layer 84 to extend through the bottom layer 82, while the upper layer 86 may be consumed.

[0098] exist Figure 9 In some embodiments, an etching process is used to extend an opening 88 formed in the photoresist structure 80 through a filler material 72. This etching process can be anisotropic, allowing the opening 88 in the bottom layer 82 to extend through the filler material 72, and the filler material 72 has dimensions approximately the same as (or slightly smaller than) its dimensions in the photoresist structure 80. For example, the opening 88 in the filler material 72 can be formed with a width W2 along the YY direction, which is about 8 nm or greater, but can be other widths. The opening 88 in the filler material 72 can expose an etch stop layer 66. In some embodiments, an opening 88 in the filler material 72 can have an aspect ratio (width / height) between about 0.01 and about 5, but can be other aspect ratios. In some cases, having a relatively small aspect ratio allows for the formation of an opening 88 with a smaller width or finer intercept, which can also reduce the risk of damage once the masking material 90' (see [link to masking material]) is cut into pieces. Figure 10 The stress filling the opening 88. In some embodiments, the opening 88 may have an intercept of about 10 nm or greater, but may be other intercepts.

[0099] In some embodiments, the etching process described above may include a dry etching process followed by a cleaning process. The etching process exhibits high etch selectivity for the filler material 72 relative to the etch stop layer 66. In some embodiments, the dry etching process may involve anisotropic plasma etching with plasma generated at a power between about 5 watts and about 2000 watts, and may be performed at pressures between about 5 mTorr and about 200 mTorr. Other process conditions may be possible. In some embodiments, the dry etching process may use one or more process gases, such as CF4, CH2F2, CHF3, NF3, SF6, C4F6, C4F8, other fluorinated gases, similar gases, or other types of process gases. In some embodiments, the cleaning process may include the use of ozonated deionized water (DIO3), an acid-free photoresist stripper, an ashing process, or the like. In other embodiments, other etching techniques or cleaning processes may be used. During the etching of filler material 72, the intermediate layer 84 may be consumed, and the underlying layer 82 may be consumed at least partially. In embodiments where the underlying layer 82 is not completely consumed during etching of filler material 72, an ashing process may be performed to remove any remaining residue of the underlying layer 82. The structure of the residue is shown in... Figure 9 Cross-sectional view.

[0100] Transfer to Figure 10 A cut-out masking material 90' can be formed over a patterned hard masking layer 68, over a patterned filler material 72, and within an opening 88 in the patterned filler material 72. In some embodiments, the cut-out masking material 90' can be formed from a material including a metal (e.g., titanium nitride (TiN), titanium, tantalum nitride, tantalum, a metal-doped carbide (e.g., tungsten carbide (WC)) or the like) and / or a non-metal (e.g., silicon nitride, boron nitride, silicon carbide or the like). In some embodiments, the material composition of the cut-out masking material 90' can be determined to provide high etch selectivity relative to other layers such as etch stop layer 66, first interlayer dielectric layer 48, etc., and / or relative to other subsequently formed layers. The cut-out masking material 90' can be formed by a process such as chemical vapor deposition, atomic layer deposition, or similar processes. However, any suitable process and material can be used. In some embodiments, the cut-out masking material 90' is the same material as the filler material 72 and can be formed in a similar manner.

[0101] exist Figure 11In some embodiments, a planarization process is used to remove excess cut mask material 90' to form a cut mask 90. ​​The planarization process removes the cut mask material 90' from above the hard mask layer 68 and above the filler material 72, and can thin the hard mask layer 68 or the filler material 72. The planarization process may include a chemical mechanical polishing process, a grinding process, or a similar process. The remaining portion of the cut mask material 90' forms the cut mask 90. ​​After planarization, the cut mask 90 may have a thickness T5, which is between about 5 nm and about 50 nm, but may be other thicknesses. In some embodiments, the thickness T5 may be approximately the same as the thickness T4 of the filler material 72 or the thickness T3 of the hard mask layer 68. The area of ​​the cut mask 90 may have a width W3 along the YY direction, which is about 8 nm or greater, but may be other widths. In some cases, a graphical fill material 72 as described herein can be used to form the area of ​​the cutout mask 90 with a smaller width (for example: W3). The cutout mask 90 can define the cutout in the subsequently formed source / drain contacts 112 (see...). Figures 17A-17C The location between ).

[0102] Figure 12 and Figure 13 According to some embodiments, a graphical hard mask layer 68 and a cutout mask 90 are illustrated as a combined etch mask to form a contact opening 92. Figure 12 The diagram illustrates etching the filler material 72 to form an initial contact opening 92, thereby exposing the etch stop layer 66. The filler material 72 can be removed by the aforementioned etching, thus the filler material 72 can be considered a "sacrificial material". Figure 13 The etching process involves etching the etch stop layer 66, the second interlayer dielectric layer 64, the first interlayer dielectric layer 48, and the contact etch stop layer 46, extending the contact opening 92 into the first interlayer dielectric layer 48 to expose the epitaxial source / drain region 42. (See diagram below.) Figures 12 to 13 As shown, the diced mask 90 defines areas where the first interlayer dielectric layer 48 separates the adjacent contact openings 92, thus affecting the subsequent formation of the source / drain contacts 112 (see [link]). Figures 17A-17C This forms a "cutout". In some cases, the use of the cutout mask 90 described herein allows the cutout to have a smaller cutout width W4 (see [link to documentation]). Figure 15 , Figure 17A and Figure 17C This allows for a smaller separation between the source / drain contacts 112 without increasing the risk of bridging or short circuits. The techniques described herein also achieve wider source / drain contacts 112, which reduces contact resistance and minimizes the effects of process variations. In this way, the density, intercept, yield, and electrical performance of a device can be improved.

[0103] Although the embodiments are illustrated with respect to etching the filler material 72 and the etch stop layer 66, the second interlayer dielectric layer 64, the first interlayer dielectric layer 48, and the contact etch stop layer 46 together in a single etch step, these embodiments are not intended to be limiting. For example, the filler material 72 and one or more underlying layers, or other combinations of film layers, can be etched in a single step using more etch steps, fewer etch steps, or other combinations of etch steps. All of these embodiments are considered to be within the scope of the embodiments of the present invention.

[0104] According to some embodiments, one or more dry etching processes can be used to etch the contact openings 92 shown in Figures 12 and 13, and a wet cleaning process can be followed. The etching process can have high etch selectivity for the etch stop layer 66, the second interlayer dielectric layer 64, the first interlayer dielectric layer 48, and / or the contact etch stop layer 46 relative to the hard mask layer 58 and the cut mask 90. ​​In some embodiments, the dry etching process can have an isotropic plasma etching with plasma generated at a power between about 20 watts and about 2000 watts, and can be performed at a pressure between about 5 mTorr and about 200 mTorr. Other process conditions may be possible. In some embodiments, the dry etching process can use one or more process gases, such as CF4, CH2F2, CHF3, C4F6, C4F8, NF3, O2, Ar, CH3F, He, CO, CO2, COS, other fluorinated gases, similar gases, or other types of process gases. In some embodiments, the above-described wet cleaning process may include the use of diluted hydrofluoric acid, SC-1, SPM, HPM (SC-2), ozone-deionized water, similar agents, or other reagents. In other embodiments, other etching techniques or cleaning processes may be used.

[0105] In some embodiments, the contact opening 92 is formed to have a width WB near the bottom of the contact opening 92, which is greater than the width of the corresponding epitaxial source / drain region 42, such as... Figure 13 As shown. In this way, the source / drain contact 112 can be increased (see...). Figures 17A-17C The contact area between the contact opening 92 and the epitaxial source / drain region 42 can reduce contact resistance. Furthermore, the larger bottom width WB of the contact opening 92 can reduce the effects of process variations on the contact resistance of the source / drain contact 112. In this way, the source / drain contact 112 can be "self-aligned". The width of the contact opening 92 can be controlled by controlling the pattern of the etch mask formed by the patterned hard mask layer 68 and the diced mask 90.

[0106] In some embodiments, the techniques described herein can form a contact opening 92 having a bottom width (for example, bottom width WB) that is approximately equal to or less than a top width (for example, top width WT1). For example, in some embodiments, the contact opening 92 can be formed such that its sidewalls have an angle A1 between approximately 83° and approximately 91°, but may be other angles. By having a nearly vertical profile or a near-bottom tapering profile, the contact opening 92 can be filled more efficiently with the conductive material of the source / drain contacts 112, with a lower chance of voids, incomplete filling, cracking, strain, warping, or other factors that could negatively impact device performance.

[0107] exist Figure 14 and Figure 15 According to some embodiments, source / drain contacts 112 are formed. Please refer to... Figure 14 The hard mask layer 68 and the cut mask 90 can be removed. The hard mask layer 68 and the cut mask 90 can be removed using, for example, a wet etching process using diluted hydrofluoric acid, SC-1, SPM, HPM (SC-2), ozone-deionized water, similar agents, or other reagents. Other removal techniques may also be used. According to some embodiments, a liner (not shown) and a conductive material are formed above the etch stop layer 66 and within the contact opening 92. Figure 14 In this designation, the aforementioned pad and the aforementioned conductive material are collectively designated as contact material 112'. The pad may be, for example, a diffusion barrier layer, an adhesive layer, or the like, and may include a material such as titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may include, for example, copper, copper alloys, silver, gold, tungsten, cobalt, aluminum, nickel, the like, or combinations thereof. A suitable process may be used to form the pad or the conductive material, such as atomic layer deposition, chemical vapor deposition, physical vapor deposition, plating, similar methods, or combinations thereof. In some embodiments, a silicide (not shown in the figures) may be formed at the interface between the epitaxial source / drain region 42 and the contact material 112'.

[0108] exist Figure 15 In some embodiments, a planarization process, such as chemical mechanical polishing, is performed. In some embodiments, the planarization process removes the etch stop layer 66, the second interlayer dielectric layer 64, and the upper portion of the contact material 112'. The remaining pads and the conductive material form source / drain contacts 112. In some embodiments, the planarization process also thins the first interlayer dielectric layer 48. After the planarization process, the top surface of the source / drain contacts 112 can be substantially flush with the top surface of the first interlayer dielectric layer 48. Figure 15As shown, the source / drain contact 112 can be separated by a block width W4 along the YY direction, which is between about 8 nm and about 15 nm, but can be other widths. In some cases, the forming diced mask 90 described herein can achieve a smaller diced width W4 without increasing the risk of bridging or short circuits. It also allows the source / drain contact 112 to have a larger width W5, which can reduce contact resistance and reduce sensitivity to process variations. In some embodiments, the source / drain contact 112 can have a width W5 along the YY direction, which is about 10 nm or greater, but can be other widths.

[0109] Transfer to Figures 16A to 16C and Figure 17A and Figure 17C This shows various views of intermediate steps in forming the source / drain contact 112 according to some embodiments. (Shown...) Figures 16A to 16C and Figure 17A and Figure 17C The structure is similar to that shown in Figures 1 to 15 The structure, apart from the arrangement and dimensions of the epitaxial source / drain regions 42, the diced mask 90, the contact openings 92, and the source / drain contacts 112, is shown in particular. Figures 16A to 16C The structure is similar to that shown in Figure 13 The structure is shown in Figures 17A to 17C The structure is similar to that shown in Figure 15 The structure. Thus, it can be represented in a manner similar to that shown below. Figures 1 to 15 The structure is formed in a way that is shown in Figures 16A to 16C and Figure 17A and Figure 17C The structure. Figure 16A and Figure 17A Show floor plan, Figure 16B and Figure 17B Displays a cross-sectional view along the specified section XX. Figure 16C and Figure 17C Displays a cross-sectional view along the specified section YY.

[0110] Figures 16A to 16C The structure shown after the formation of contact opening 92 is similar to Figure 13 For descriptive purposes, specific contact openings 92A and 92B of contact opening 92 are designated. For example... Figures 16A to 16C As shown, a partial cutout mask 90 extends between the epitaxial source / drain regions 42 to form separate contact openings 92. For example, along section YY, the cutout mask 90A serves as a separator between contact openings 92A and 92B. Contact opening 92A exposes the epitaxial source / drain region 42A, while contact opening 92B exposes the epitaxial source / drain region 42B. Figure 16A and Figure 16CAs shown, the epitaxial source / drain regions 42 have different lengths along the YY direction, and therefore the contact openings 92 can be formed with different widths. Figure 16A As shown, the cutout mask 90 can have different widths along the YY direction (for example, width W3). A single cutout mask 90 can also have multiple widths or different widths than those shown. Figure 16A The shape.

[0111] Figures 17A to 17C The structure shown after the formation of the source / drain contact 112 is similar to Figure 15 .like Figures 17A to 17C As shown, the first interlayer dielectric layer 48 forms a "cutout" that isolates adjacent source / drain contacts 112. For example, along section YY, the first interlayer dielectric layer 48 previously isolated source / drain contacts 112A and source / drain contacts 112B in the region beneath the cutout mask 90A. The use of the cutout mask 90 described herein, as previously described, allows for a smaller cutout width W4. In some embodiments, the source / drain contacts 112 may have a width W6 along the XX direction, which is between about 9 nm and about 18 nm, but may be other widths.

[0112] Although not explicitly stated, it will be readily understood by one of ordinary skill in the art that... Figure 15 or Figures 17A to 17C Further processing steps are performed on the structure. For example, gate contacts may be formed to replace the gate stack 60, or various inter-metal dielectrics (IMDs) and their corresponding metallization may be formed above the first inter-dielectric layer 48.

[0113] The embodiments offer several advantages. The described techniques enable the formation of source / drain contacts with smaller cutouts without increasing the risk of bridging or short circuits. In particular, smaller cutouts can be obtained by using all the block masks described herein to form the cutouts. For example, a filler material with a substantially flat surface can reduce the topographic effect during the photolithography step and allow the pattern of the cutout mask to be formed with a finer intercept. Due to the relatively small thickness of the filler material, the pattern of the cutout mask etched into the filler material has a lower aspect ratio. This low aspect ratio reduces the chance of the filler material warping or cracking due to stress. Furthermore, the techniques described herein are applicable to both forming large-area (e.g., "a group") contact openings and forming small-area (e.g., "a single trench") contact openings. The techniques described herein can also form contact openings with a near-vertical profile or a tapered profile at the bottom, which improves the filling of conductive material when forming source / drain contacts. In this way, the contact resistance of the source / drain contacts can be reduced, and device performance can be improved.

[0114] In some embodiments, a method includes: forming a first inter-layer dielectric (ILD) over a source region and a drain region of a semiconductor structure; forming a first masking material over the first inter-layer dielectric; etching a plurality of first openings in the first masking material; filling the first openings with a filler material; etching a plurality of second openings in the filler material; filling the second openings with a second masking material; removing the filler material; and etching the first inter-layer dielectric using the first masking material and the second masking material as an etching mask to form a plurality of third openings in the first inter-layer dielectric, the third openings exposing portions of the source region and the drain region of the semiconductor structure.

[0115] In one embodiment, the method includes forming an etch stop layer over the first interlayer dielectric layer before forming the first masking material. In one embodiment, the first masking material comprises tungsten carbide. The second masking material comprises tungsten. In one embodiment, the method includes forming a second interlayer dielectric layer over the first interlayer dielectric layer before forming the first masking material. In one embodiment, the filler material comprises a flowable oxide. In one embodiment, the method includes planarizing the filler material before etching the second opening. In one embodiment, the planarized filler material has a thickness in the range of 10 nm to 50 nm. In one embodiment, the method includes: filling the third opening of the first interlayer dielectric layer with a conductive material; and performing a planarization process on the conductive material, the planarization process exposing a top surface of the first interlayer dielectric layer.

[0116] In some embodiments, a method includes: depositing an inter-layer dielectric (ILD) over a first source / drain region and over a second source / drain region; forming an etch mask over the inter-layer dielectric, including: depositing a first mask material over the inter-layer dielectric; forming a first opening in the first mask material, the first opening extending over the first source / drain region and over the second source / drain region; filling the first opening with a dielectric material; forming a second opening in the dielectric material, the second opening being located between the first source / drain region and the second source / drain region; and filling the second opening with a second mask material; and etching a first contact opening in the inter-layer dielectric to expose the first source / drain region, and etching a second contact opening in the inter-layer dielectric to expose the second source / drain region, wherein an isolation region of the inter-layer dielectric below the second mask material isolates the first contact opening from the second contact opening.

[0117] In one embodiment, the method includes depositing an etch stop layer over the interlayer dielectric layer, wherein the etch stop layer is exposed at the first opening in the first masking material. In one embodiment, etching of the first contact opening and the second contact opening removes the dielectric material. In one embodiment, the width of the interlayer dielectric layer near the top of the first contact opening is smaller than its width near the bottom of the first contact opening. In one embodiment, a top surface of the isolation region of the interlayer dielectric layer has a width in the range of 8 nm to 15 nm. In one embodiment, the isolation region of the interlayer dielectric layer has a sidewall corner in the range of 83° to 91°. In one embodiment, the second opening has an aspect ratio (width / height) in the range of 0.01 to 5.

[0118] In some embodiments, a method includes: forming a plurality of fins protruding from a substrate and extending in a first direction; forming a plurality of gate stacks extending above the fins and extending in a second direction orthogonal to the first direction; forming a plurality of source / drain regions on the fins; depositing an inter-layer dielectric (ILD) layer above the source / drain regions; forming a first patterned mask, including: depositing a sacrificial material above the inter-layer dielectric layer and above the gate stacks; patterning a plurality of openings in the sacrificial material, wherein each opening extends above at least two gate stacks of the gate stacks; and depositing a masking material within the openings, the first patterned mask including the masking material; using the first patterned mask to etch the inter-layer dielectric layer to form a plurality of contact openings above the source / drain regions; and filling the contact openings with a conductive material to form a plurality of source / drain contacts.

[0119] In one embodiment, the method includes forming a second patterned mask over the interlayer dielectric layer and over the gate stack, the second patterned mask including a patterned opening, wherein the sacrificial material is deposited within the patterned opening. In one embodiment, a portion of the interlayer dielectric layer extends in the second direction from a first source / drain contact of the source / drain contact to a second source / drain contact of the source / drain contact, wherein the portion of the interlayer dielectric layer has a width in the second direction ranging from 8 nm to 15 nm. In one embodiment, the sacrificial material includes silicon oxide.

[0120] The foregoing outlines features of numerous embodiments, enabling those skilled in the art to better understand the embodiments of the present invention from various aspects. Those skilled in the art will understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art will also understand that these equivalent structures do not depart from the inventive spirit and scope of the embodiments of the present invention. Various changes, substitutions, or modifications can be made to the embodiments of the present invention without departing from the inventive spirit and scope of the embodiments of the present invention.

Claims

1. A method for forming a semiconductor device, comprising: A first interlayer dielectric layer is formed above a source region and a drain region of a semiconductor structure; A first shielding material is formed above the first interlayer dielectric layer; Multiple first openings are etched into the first masking material; The first opening is filled with a filler material; Multiple second openings were etched into the filler material; The second opening is filled with a second masking material; Remove the filler material; as well as The first interlayer dielectric layer is etched using the first masking material and the second masking material as an etching mask to form a plurality of third openings in the first interlayer dielectric layer, the third openings exposing parts of the source region and the drain region of the semiconductor structure.

2. The method for forming a semiconductor device as claimed in claim 1, further comprising: Before forming the first masking material, an etch stop layer is formed above the first interlayer dielectric layer.

3. The method for forming a semiconductor device as claimed in claim 1, wherein the first masking material comprises tungsten carbide.

4. The method of forming a semiconductor device as claimed in claim 1, wherein the second masking material comprises tungsten.

5. The method for forming a semiconductor device as claimed in claim 1, further comprising: Before forming the first masking material, a second interlayer dielectric layer is formed above the first interlayer dielectric layer.

6. The method of forming a semiconductor device as claimed in claim 1, wherein the filling material comprises a flowable oxide.

7. The method for forming a semiconductor device as claimed in claim 1, further comprising: The filler material is planarized before the second opening is etched out.

8. The method of forming a semiconductor device as claimed in claim 7, wherein the planarized filler material has a thickness in the range of 10 nm to 50 nm.

9. The method for forming a semiconductor device as claimed in claim 1, further comprising: The third opening in the first interlayer dielectric layer is filled with a conductive material; as well as A planarization process is performed on the conductive material, which exposes a top surface of the first interlayer dielectric layer.

10. A method for forming a semiconductor device, comprising: An inter-dielectric layer is deposited above a first source / drain region and above a second source / drain region; An etching mask is formed above the interlayer dielectric layer, including: A first masking material is deposited above the interlayer dielectric layer; A first opening is formed in the first masking material, and the first opening extends above the first source / drain region and above the second source / drain region; The first opening is filled with a dielectric material; A second opening is formed in the dielectric material, the second opening being located between the first source / drain region and the second source / drain region; and The second opening is filled with a second masking material; and A first contact opening is etched in the interlayer dielectric layer to expose the first source / drain region, and a second contact opening is etched in the interlayer dielectric layer to expose the second source / drain region, wherein an isolation region of the interlayer dielectric layer under the second masking material isolates the first contact opening from the second contact opening.

11. The method of forming a semiconductor device as claimed in claim 10, further comprising: An etch stop layer is deposited above the interlayer dielectric layer, wherein the etch stop layer is exposed at the first opening in the first masking material.

12. The method of forming a semiconductor device as claimed in claim 10, wherein etching of the first contact opening and the second contact opening removes the dielectric material.

13. The method of forming a semiconductor device as claimed in claim 10, wherein the width of the interlayer dielectric layer near the top of the first contact opening is smaller than the width near the bottom of the first contact opening.

14. The method of forming a semiconductor device as claimed in claim 10, wherein a top surface of the isolation region of the interlayer dielectric layer has a width in the range of 8 nm to 15 nm.

15. The method of forming a semiconductor device as claimed in claim 10, wherein the isolation region of the interlayer dielectric layer has a sidewall angle in the range of 83° to 91°.

16. The method of forming a semiconductor device as claimed in claim 10, wherein the second opening has an aspect ratio (width / height) in the range of 0.01 to 5.

17. A method for forming a semiconductor device, comprising: Multiple fins are formed, the fins protruding from a base and extending in a first direction; Multiple gate stacks are formed, the gate stacks extending above the fins, and the gate stacks extending in a second direction orthogonal to the first direction; Multiple source / drain regions are formed on the fin; A dielectric layer is deposited above the source / drain regions; Forming a first graphical mask includes: A sacrificial material is deposited above the interlayer dielectric layer and above the gate stack; The sacrificial material is patterned with a plurality of openings, each of which extends over at least two gate stacks of the gate stack; and A masking material is deposited within the opening, the first patterned mask including the masking material; A second patterned mask is formed above the interlayer dielectric layer and above the gate stack. The second patterned mask includes a patterned opening, in which the sacrificial material is deposited. The first patterned mask is used to etch the interlayer dielectric layer to form multiple contact openings above the source / drain regions; and The contact opening is filled with a conductive material to form multiple source / drain contacts.

18. The method of forming a semiconductor device as claimed in claim 17, wherein a portion of the interlayer dielectric layer extends in the second direction from a first source / drain contact of the source / drain contact to a second source / drain contact of the source / drain contact, wherein the portion of the interlayer dielectric layer has a width in the second direction, which is in the range of 8 nm to 15 nm.

19. The method of forming a semiconductor device as claimed in claim 17, wherein the sacrificial material comprises silicon oxide.

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