Method for manufacturing laminated substrate, laminated substrate, and light emitting element substrate

Abstract

Provided are a method for manufacturing a laminated substrate, a laminated substrate, and a light emitting element substrate. In the method for manufacturing a laminated substrate, for a laminated substrate having a base layer having a mesa portion with a trapezoidal cross section, the mesa portion having a first inclined surface extending downward from a top surface and outward, and a second inclined surface having a gable-shaped portion extending outward from the top surface, a wiring layer formed on an upper surface of the base layer, and a resist layer formed on an upper surface of the wiring layer and having a shape corresponding to that of the wiring, a portion of the wiring layer not covered by the resist layer is removed using an etching solution to form a wiring, and the wiring is disposed at a position covering the entire area of the gable-shaped portion of the second inclined surface.

Description

Technical Field

[0001] This invention relates to a method for manufacturing a laminated substrate, a laminated substrate, and a light-emitting element substrate. Background Technology

[0002] In image forming apparatuses, the technology described in Patent Document 1 below regarding the structure of light-emitting devices such as latent image forming apparatus and power removal devices for forming latent images is known in the past.

[0003] Patent document 1 describes the following manufacturing method: In the technology of manufacturing thyristors, transistors, etc., for light-emitting element heads, p-type semiconductors and n-type semiconductors are stacked in sequence, and then the parts other than the target shape part are etched (mesa etching) to obtain the target circuit.

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent Application Publication No. 2019-111664 (“0155” to “0174”, Figures 12 to 15) Summary of the Invention

[0007] The problem that the invention aims to solve

[0008] The technical challenge of this invention is to suppress the breakage of metal wiring when manufacturing a laminated substrate having a trapezoidal mesa surface in the presence of an eave-like portion extending outward from the top of the mesa surface, compared to the case where wiring is generated in a portion of the eave-like portion.

[0009] Methods for solving problems

[0010] According to one aspect of this disclosure, a method for manufacturing a multilayer substrate is provided, wherein for the multilayer substrate, an etching solution is used to remove a portion of a wiring layer not covered by a resist layer to form wiring. The multilayer substrate comprises: a base layer having a trapezoidal platform with a first inclined surface extending downwards and outwards from a top surface and a second inclined surface having an eave-like portion extending outwards from the top surface; a wiring layer formed on the upper surface of the base layer; and a resist layer formed on the upper surface of the wiring layer and having a shape corresponding to the shape of the wiring.

[0011] The wiring is positioned over the entire area of ​​the eaves-like portion covering the second slope.

[0012] According to one aspect of this disclosure, a method for manufacturing a multilayer substrate is provided, wherein for the multilayer substrate, an etching solution is used to remove a portion of a wiring layer not covered by a resist layer to form wiring. The multilayer substrate comprises: a base layer having a trapezoidal platform with a first inclined surface extending downwards and outwards from a top surface and a second inclined surface having an eave-like portion extending outwards from the top surface; a wiring layer formed on the upper surface of the base layer; and a resist layer formed on the upper surface of the wiring layer and having a shape corresponding to the shape of the wiring.

[0013] The wiring is positioned away from the eaves-like portion.

[0014] In the method for manufacturing the laminated substrate described in [2], if the distance between the wiring and the eaves-shaped portion is shorter than the thickness of the wiring film, the wiring width may be set to more than twice the thickness of the wiring film.

[0015] In the method for manufacturing the laminated substrate described in [3], if there are second inclined surfaces on both sides of the wiring width direction, the wiring width can be set to more than three times the wiring film thickness.

[0016] According to one aspect of this disclosure, a method for manufacturing a multilayer substrate is provided, wherein for the multilayer substrate, an etching solution is used to remove a portion of a wiring layer not covered by a resist layer to form wiring. The multilayer substrate comprises: a base layer having a trapezoidal platform with a first inclined surface extending downwards and outwards from a top surface and a second inclined surface having an eave-like portion extending outwards from the top surface; a wiring layer formed on the upper surface of the base layer; and a resist layer formed on the upper surface of the wiring layer and having a shape corresponding to the shape of the wiring.

[0017] The wiring is generated in such a way that it overlaps with two or more of the upper edges of the eave-shaped portion and the first inclined surface.

[0018] In the method for manufacturing the laminated substrate described in [5], the first inclined surface may also extend in a direction orthogonal to the second inclined surface.

[0019] In the method for manufacturing the laminated substrate described in [6], an end edge of the top surface may also be formed, the end edge of the top surface extending in a direction inclined relative to the extension direction of the second inclined surface and its orthogonal direction.

[0020] According to one aspect of this disclosure, a laminated substrate is provided, comprising: a base layer having a trapezoidal mesa with a first inclined surface extending downward and outward from a top surface, and a second inclined surface having an eave-like portion extending outward from the top surface; and wiring formed on the upper surface of the base layer, formed by removing a portion of the wiring layer not covered by the resist layer using an etching solution after forming a resist layer, wherein the resist layer is formed on the upper surface of the wiring layer and has a shape corresponding to the wiring shape, and the wiring layer is formed on the upper surface of the base layer.

[0021] The wiring is positioned over the entire area of ​​the eaves-like portion covering the second slope.

[0022] According to one aspect of this disclosure, a laminated substrate is provided, comprising: a base layer having a trapezoidal mesa with a first inclined surface extending downward and outward from a top surface, and a second inclined surface having an eave-like portion extending outward from the top surface; and wiring formed on the upper surface of the base layer, formed by removing a portion of the wiring layer not covered by the resist layer using an etching solution after forming a resist layer, wherein the resist layer is formed on the upper surface of the wiring layer and has a shape corresponding to the wiring shape, and the wiring layer is formed on the upper surface of the base layer.

[0023] The wiring is positioned away from the eaves-like portion.

[0024] According to one aspect of this disclosure, a light-emitting element substrate is provided, comprising: a laminated substrate according to [8] or [9],

[0025] The laminated substrate has a light-emitting portion, and the wiring supplies current to the light-emitting portion.

[0026] Invention Effects

[0027] According to [1], [2], and [5], when manufacturing a laminated substrate having a trapezoidal mesa, when there is an eave-like portion extending outward from the top of the mesa, the breakage of the metal wiring can be suppressed compared to the case where wiring is generated in a portion of the eave-like portion.

[0028] According to [3], it can suppress the breakage of the wiring compared to the case where the wiring width is not more than twice the wiring film thickness.

[0029] According to [4], even if there are second slopes on both sides of the wiring width direction, the breakage of the wiring can be suppressed compared to the case where the wiring width is not more than three times the wiring film thickness.

[0030] According to [6], compared with the case where it does not overlap with the first slope that is orthogonal to the second slope, it is possible to suppress the etching process and the disconnection of the wiring.

[0031] According to [7], compared with the case of not having an inclinedly extended end edge, it is possible to suppress the adverse effects of etching on the second bevel and the breakage of the wiring.

[0032] According to [8], [9], and

[10] , in a laminated substrate having a trapezoidal mesa, when there is an eave-like portion extending outward from the top of the mesa, the disconnection of the metal wiring can be suppressed compared to the case where wiring is provided in a part of the eave-like portion. Attached Figure Description

[0033] Figure 1 This is an overall explanatory diagram of the image forming apparatus of Embodiment 1.

[0034] Figure 2 This is a cross-sectional view of the latent image forming apparatus of Example 1.

[0035] Figure 3 This is a top view of the light-emitting part of Embodiment 1.

[0036] Figure 4 This is an explanatory diagram of the structure of the light-emitting chip in Example 1.

[0037] Figure 5 This is an explanatory diagram of the structure of the signal generation circuit and the wiring (line) structure on the circuit board in Embodiment 1.

[0038] Figure 6 This is an example of an equivalent circuit diagram illustrating the structure of the light-emitting chip in Embodiment 1.

[0039] Figure 7A , Figure 7B , Figure 7C , Figure 7D This is an explanatory diagram of the light-emitting chip in Example 1. Figure 7A It is a top view. Figure 7B yes Figure 7A Sectional view along line VIIB-VIIB, Figure 7C yes Figure 7A Sectional view along line VIIC-VIIC, Figure 7D yes Figure 7A Sectional view along line VIID-VIID.

[0040] Figure 8A , Figure 8B This is an explanatory diagram of the circuit in Example 1. Figure 8A This is an explanatory diagram of the stack-up structure of the first wiring section. Figure 8B This is an explanatory diagram of the stacked structure of the second wiring section.

[0041] Figure 9A , Figure 9B This is an explanatory diagram of the manufacturing method of a laminated substrate. Figure 9A This is an illustration of the state of a substrate without a mesa before etching. Figure 9B yes Figure 9A An explanatory diagram of the substrate after etching.

[0042] Figure 10A , Figure 10B , Figure 10C This is an explanatory diagram of a multilayer substrate with a mesa shape. Figure 10A It is a top view. Figure 10B From Figure 10A The diagram viewed from the XB direction of the arrow. Figure 10C From Figure 10A The diagram is viewed from the direction of arrow XC.

[0043] Figure 11A , Figure 11B This is an illustration of the etching process for the inverted platform section. Figure 11A This is an illustrative diagram showing the state of the face after the membrane has been separated. Figure 11B From Figure 11A An illustration of the state after etching.

[0044] Figure 12A , Figure 12B , Figure 12C This is an illustration of the situation where the inverted platform surface contacts a portion of the target shape. Figure 12A This is an illustration of the state before etching. Figure 12B This is an illustrative diagram showing the state of the wiring layer after film deposition. Figure 12C This is an illustration of the state after etching.

[0045] Figure 13 This is an explanatory diagram illustrating an example of the manufacturing method of the countertop portion of Embodiment 1.

[0046] Figure 14A , Figure 14B , Figure 14C This is an explanatory diagram of another example of the manufacturing method of the countertop portion of Embodiment 1. Figure 14A This is an illustrative diagram showing the state of the wiring layer after film deposition. Figure 14B This is an illustrative diagram showing the state after etching of the wiring layer film thickness. Figure 14C This is an illustration of the state after etching is complete.

[0047] Figure 15A , Figure 15B It is the ratio of wiring to the face of the platform. Figure 14A , Figure 14B , Figure 14C A diagram illustrating the state when the state is closer to the state shown. Figure 15AThis is an illustrative diagram showing the state before etching when one side of the wiring has an inverted face. Figure 15B This is an illustration of the etched state when one side of the wiring has an inverted face.

[0048] Figure 16A , Figure 16B It is the ratio of wiring to the face of the platform. Figure 14A , Figure 14B , Figure 14C A diagram illustrating the state when the state is closer to the state shown. Figure 16A This is an illustrative diagram showing the state before etching when the wiring has inverted facets on both sides. Figure 16B This is an illustration of the etched state when there are inverted facets on both sides of the wiring.

[0049] Figure 17 This diagram illustrates a situation where wiring cannot avoid the inverted face and cannot cover the entire area of ​​the inverted face with wiring.

[0050] Figure 18A , Figure 18B This diagram illustrates a situation where wiring cannot avoid the inverted face and cannot cover the entire area of ​​the inverted face, resulting in an edge that is inclined relative to the inverted face line. Figure 18A This is an illustration of the state before the inclined end edge is formed. Figure 18B This is an illustration of the state in which the inclined end edge has been formed.

[0051] Figure 19 This is an explanatory diagram illustrating another example of the configuration of the light-emitting part in this invention. Detailed Implementation

[0052] Next, specific embodiments of the present invention will be described with reference to the accompanying drawings, but the present invention is not limited to the following embodiments.

[0053] Furthermore, for ease of understanding of the following description, in the accompanying drawings, the front-to-back direction (the width direction of the medium) is set as the X-axis direction, the left-to-right direction (the transmission direction of the medium) is set as the Y-axis direction, and the up-down direction is set as the Z-axis direction. The directions or sides indicated by the arrows X, -X, Y, -Y, Z, and -Z are respectively set as front, back, right, left, top, and bottom, or front side, back side, right side, left side, top side, and bottom side.

[0054] Additionally, in the diagram, arrows marked with "·" in "○" indicate arrows moving from the back of the paper towards the front, while arrows marked with "×" in "○" indicate arrows moving from the front of the paper towards the back.

[0055] Furthermore, in the following description of the use of the accompanying drawings, for ease of understanding, illustrations other than those of the parts required for the description have been appropriately omitted.

[0056]

Example 1

[0057] (Description of the overall structure of printer U in Example 1)

[0058] Figure 1 This is an overall explanatory diagram of the image forming apparatus of Embodiment 1.

[0059] exist Figure 1 In this invention, a printer U, which is an example of an image forming apparatus according to Embodiment 1 of the present invention, includes: a printer body U1; a supply unit U2, which is an example of a supply device for supplying media to the printer body U1; an operation unit UI for user operation; and a trimmer U3, which is an example of a post-processing device for post-processing media discharged from the printer body U1.

[0060] (Description of the marking structure in Example 1)

[0061] exist Figure 1 In this printer, the main body U1 includes: a control unit (example of a control unit) C, which controls the printer U; a communication unit (not shown) that receives image information from a print image server COM, which is an example of an information transmission device connected to the outside of the printer U via a dedicated cable (not shown); a marking unit U1a, which is an example of a recording unit for recording images on a medium; and so on. A personal computer PC, which is an example of an image transmission device for transmitting information about images printed by the printer U, is connected to the print image server COM via a line such as a cable or a LAN (Local Area Network).

[0062] The marking unit U1a has photosensitive elements Py, Pm, Pc, and Pk for yellow (Y), magenta (M), cyan (C), and black (K) as examples of image holding units; and a photosensitive element Po that produces gloss on the image when printing photographic images, etc. The surfaces of the photosensitive elements Py to Po are made of a photosensitive dielectric.

[0063] exist Figure 1 In this embodiment, around the black photoreceptor Pk and along the rotation direction of the photoreceptor Pk, there are provided a charger CCk as an example of a charging unit, an exposure machine LPHk as an example of a latent image forming unit, a developer Gk as an example of a developing unit, a primary transfer roller T1k as an example of a primary transfer unit, and a photoreceptor cleaner CLk as an example of a cleaning unit for an image holding unit.

[0064] Similarly, chargers CCy, CCM, CCc, CCo, exposure units LPHy, LPHm, LPHc, LPHo, developers Gy, Gm, Gc, Go, primary transfer rollers T1y, T1m, T1c, T1o, and photoreceptor cleaners CLy, CLm, CLc, CLo are arranged around other photoreceptors Py, Pm, Pc, and Po.

[0065] At the upper part of the marking section U1a, toner cartridges Ky, Km, Kc, Kk, and Ko, which serve as examples of developer holding units, are detachably supported. Toner cartridges Ky to Ko contain developer to be added to the developer units Gy to Go.

[0066] An intermediate transfer belt B, serving as an example of an intermediate transfer unit and an example of an image holding unit, is disposed below each of the photosensitive elements Py to Po. The intermediate transfer belt B is sandwiched between the photosensitive elements Py to Po and the primary transfer rollers T1y to T1o. The back side of the intermediate transfer belt B is supported by a drive roller Rd, serving as an example of a drive unit; a tension roller Rt, serving as an example of a tension application unit; a stepping roller Rw, serving as an example of a serpentine prevention unit; multiple idler rollers Rf, serving as an example of a driven unit; a support roller T2a, serving as an example of an opposing unit for secondary transfer; multiple retraction rollers R1, serving as an example of a movable unit; and the aforementioned primary transfer rollers T1y to T1o.

[0067] On the surface of the intermediate transfer belt B, a belt cleaner CLB, as an example of a cleaning unit for the intermediate transfer unit, is set near the drive roller Rd.

[0068] As an example of a secondary transfer component, the secondary transfer roller T2b is configured to face the support roller T2a across the intermediate transfer belt B. Additionally, as an example of a contact unit, the contact roller T2c contacts the support roller T2a to apply a voltage to the support roller T2a with a polarity opposite to that of the developer.

[0069] The aforementioned support roller T2a, secondary transfer roller T2b, and contact roller T2c constitute a secondary transfer unit T2, which is an example of a secondary transfer unit in Embodiment 1. The primary transfer rollers T1y to T1o, the intermediate transfer belt B, and the secondary transfer unit T2 constitute transfer devices T1, B, and T2, which are examples of transfer units in Embodiment 1.

[0070] Below the secondary transfer unit T2, a paper feed tray TR1 is provided as an example of a receiving unit. The paper feed tray TR1 receives a recording sheet S, which is an example of a medium. A pickup roller Rp, which is an example of a pickup unit, and a separation roller Rs, which is an example of a separation unit, are provided diagonally above and to the right of the paper feed tray TR1. A transport path SH for transporting the recording sheet S extends from the separation roller Rs. Multiple transport rollers Ra, which are examples of transport units, are provided along the transport path SH, and transport the recording sheet S to the downstream side.

[0071] Downstream of the separating roller Rs, a burr removal device Bt is provided as an example of a unit for removing unwanted portions. The burr removal device Bt clamps the recording sheet S with a predetermined pressure and conveys it downstream to remove unwanted portions, i.e., burrs, from the edges of the recording sheet S.

[0072] A stacking detection device Jk is installed downstream of the burr removal device Bt. The stacking detection device Jk measures the thickness of the passing recording sheet S to detect the overlapping state of multiple recording sheets S, i.e., stacking.

[0073] A correction roller Rc, serving as an example of an attitude correction unit, is provided downstream of the stacking detection device Jk. The correction roller Rc corrects the tilt, or skewing, of the recording sheet S relative to the conveying direction.

[0074] Downstream of the calibration roller Rc, a registration roller Rr is provided as an example of an adjustment unit, which adjusts the time it takes for the recording sheet S to be conveyed to the secondary transfer unit T2. Additionally, downstream of the registration roller Rr, a sheet guide SG1 is provided as an example of a media guiding unit.

[0075] In addition, the supply unit U2 is also equipped with paper supply trays TR2 and TR3, which are similar to the paper supply tray TR1, pickup roller Rp, separation roller Rs, and transfer roller Ra. The transfer path SH from the paper supply trays TR2 and TR3 merges with the transfer path SH of the printer body U1 on the upstream side of the stacking detection device Jk.

[0076] In contrast to the secondary transfer roller T2b, multiple conveyor belts HB, serving as examples of media conveying units, are provided downstream of the recording sheet S in the conveying direction.

[0077] A fixing device F, which serves as an example of a fixing unit, is provided downstream of the conveyor belt HB in the conveying direction of the recording sheet S.

[0078] A curl eliminator Hd, serving as an example of a bend correction unit, is provided on the trimmer U3 downstream of the fixing unit F. The curl eliminator Hd applies pressure to the recording sheet S, thereby correcting the bend, i.e., curl, of the recording sheet S.

[0079] Downstream of the curl eliminator Hd, the conveyor path SH extends toward the discharge tray TRh, which serves as an example of a stacking unit. At the downstream end of the conveyor path SH, a discharge roller Rh, serving as an example of a discharge unit, is located.

[0080] Downstream of the curl eliminator Hd, a reverse path SH2 is formed, which branches off from the transport path SH. A first gate GT1, serving as a transport direction switching unit, is provided at the branch between the transport path SH and the reverse path SH2.

[0081] The reverse path SH2 includes multiple rotating rollers Rb, which serve as examples of conveying units capable of rotating in both directions. A connecting path SH3, serving as an example of a conveying path, is formed upstream of the rotating rollers Rb. This connecting path SH3 branches off from the upstream portion of the reverse path SH2 and merges downstream of the branch of the conveying path SH2 with the branch of the reverse path SH2. A second gate GT2, serving as an example of a conveying direction switching unit, is provided at the branch between the reverse path SH2 and the connecting path SH3.

[0082] Downstream of the aforementioned reversing path SH2, a return path SH4, used to reverse the transport direction of the recording sheet S, is provided below the fixing device F. A return roller Rb, exemplifying a transport unit capable of rotating in both directions, is provided in the return path SH4. Furthermore, a third gate GT3, exemplifying a transport direction switching unit, is provided at the entrance of the return path SH4.

[0083] In addition, the downstream conveying path SH of the return path SH4 merges with the conveying path SH of the paper supply tray TR1.

[0084] (Marking action)

[0085] When the printer U receives image information sent from the personal computer PC via the print image server COM, the image forming operation, i.e., the job, begins. At the start of the job, the photosensitive elements Py to Po and the intermediate transfer belt B rotate.

[0086] The photoreceptors Py to Po are rotated by a drive source (not shown).

[0087] A predetermined voltage is applied to the chargers CCy to CCo to charge the surfaces of the photoreceptors Py to Po.

[0088] As an example of a latent image forming apparatus and as an example of a light emission apparatus, the exposure machines LPHy to LPo output light Ly, Lm, Lc, Lk, and Lo for writing a latent image according to a control signal from the control unit C, and write an electrostatic latent image on the surface of the photoreceptors Py to Po after charging.

[0089] The developers Gy to Go develop the electrostatic latent images on the surfaces of the photoreceptors Py to Po.

[0090] The toner cartridges Ky to Ko supplement the developer consumed during development in the developer units Gy to Go.

[0091] A primary transfer voltage with a polarity opposite to that of the developer is applied to the primary transfer rollers T1y to T1o to transfer the visual image of the surfaces of the photoreceptors Py to Po onto the surface of the intermediate transfer belt B.

[0092] The photoreceptor cleaners CLy to CLo remove and clean the developer residue remaining on the surface of the photoreceptors Py to Po after a single transfer.

[0093] The intermediate transfer belt B transfers and stacks images in the order of O, Y, M, C, K as it passes through the primary transfer area opposite to the photoreceptor Py to Po, and then passes through the secondary transfer area Q4 opposite to the secondary transfer unit T2. Furthermore, in the case of a monochrome image, only one color image is transferred and sent to the secondary transfer area Q4.

[0094] The pickup roller Rp feeds the recording sheet S from the paper feed trays TR1 to TR3 that supply the recording sheet S, based on the size of the received image information, the specification of the recording sheet S, and the size and type of the recording sheet S it contains.

[0095] Separating rollers Rs separate the recording sheets S fed from pick-up rollers Rp one by one.

[0096] The burr removal device Bt applies a predetermined pressure to the passing recording sheet S to remove burrs.

[0097] The stacking detection device Jk detects the stacking of the recording sheet S by detecting the thickness of the passing recording sheet S.

[0098] The correction roller Rc brings the passing recording sheet S into contact with the wall surface (not shown) to correct skew.

[0099] The registration roller Rr transfers the recording sheet S according to the time it takes for the image on the surface of the intermediate transfer belt B to be transferred to the secondary transfer area Q4.

[0100] The sheet guide SG1 guides the recording sheet S, which is fed by the registration roller Rr, to the secondary transfer area Q4.

[0101] The secondary transfer unit T2 applies a predetermined secondary transfer voltage with the same polarity as the polarity of the developer to the support roller T2a via the contact roller T2c, thereby transferring the image of the intermediate transfer belt B onto the recording sheet S.

[0102] The cleaner CLB removes and cleans the developer residue remaining on the surface of the intermediate transfer belt B after the image is transferred in the secondary transfer area Q4.

[0103] The conveyor belt HB holds the recording sheet S, on which the image has been transferred by the secondary transfer unit T2, on its surface and conveys it downstream.

[0104] The fixing apparatus F includes a heating roller Fh, an example of a heating component, and a pressure roller Fp, an example of a pressure component. A heater h, an example of a heat source, is housed in the heating roller Fh. The fixing apparatus F applies pressure and heat to the recording sheet S in the fixing area Q5, which is in contact with the pressure roller Fp via the heating roller Fh, thereby fixing the unfixed image on the surface of the recording sheet S. The heating roller Fh and the pressure roller Fp constitute the fixing apparatus F of Embodiment 1.

[0105] The curl eliminator Hd applies pressure to the recording sheet S that has passed through the fixing device F to remove the curvature, i.e., the curl, of the recording sheet S.

[0106] In the case of double-sided printing, the recording sheet S that has passed through the curl eliminator Hd is conveyed to the reversing path SH2 by the action of the first gate GT1, is turned back in the return path SH4, and is conveyed again to the registration roller Rr through the conveying path SH, thereby performing printing on the second surface.

[0107] The recording sheet S to be discharged to the discharge tray TRh is conveyed on the conveying path SH with the surface on which the image is recorded being discharged, i.e., discharged face up, and discharged to the discharge tray TRh by the discharge roller Rh.

[0108] On the other hand, when the recording sheet S is discharged with the surface containing the image as the bottom surface, i.e., discharged face down, it is temporarily transferred from the transport path SH to the reverse path SH2. Then, after the rear end of the recording sheet S passes through the second gate GT2 in the transport direction, the forward rotation of the return roller Rb stops. Then, the second gate GT2 is switched, the return roller Rb rotates in the reverse direction, and the recording sheet S is conveyed to the discharge tray TRh on the connecting path SH3.

[0109] The discharged recording sheets S are stacked on the discharge tray TRh.

[0110] (Description of the latent image formation apparatus)

[0111] In Example 1, as the exposure machine (printhead) LPHy to LPHo, in response to the requirement of device miniaturization, a recording device using an LED printhead (LPH) is adopted, which arranges multiple light-emitting diodes (LEDs) in the main scanning direction to form an array of light-emitting elements.

[0112] In addition, a light-emitting thyristor coupled in series with a light-emitting diode is used in the light-emitting chip. Multiple light-emitting elements are arranged in a row on the substrate of the light-emitting chip, and a self-scanning light-emitting element array (SLED) is mounted thereon, which is controlled to be lit sequentially. A thyristor is a device having an anode, a cathode, and at least one gate. When a voltage exceeding a certain amount is applied to the gate, it becomes conductive by applying a voltage between the anode and cathode, and maintains the conductive state while a current exceeding the holding current flows between the anode and cathode.

[0113] Figure 2 This is a cross-sectional view of the latent image forming apparatus of Example 1.

[0114] Figure 3 This is a top view of the light-emitting part of Embodiment 1.

[0115] Figure 2 This is a cross-sectional view showing the structure of printheads LPHy to LPHo, which serve as examples of light-emitting element substrates. Printheads LPHy to LPHo include a housing 61 (example of a frame), a light-emitting device 65 (example of a light-emitting part body), and a rod-lens array 64 (example of an optical unit). The light-emitting device 65 includes a light source 63 having multiple light-emitting elements. The rod-lens array 64 exposes the photoreceptors Py to Po by image formation of light emitted from the light source 63 onto the surfaces of the photoreceptors Py to Po.

[0116] The light emitting device 65 includes a circuit board 62, which houses a light source unit 63 and a signal generation circuit 110 for driving the light source unit 63 (see reference). Figure 3 )wait.

[0117] The housing 61 is made of metal, for example, and supports the circuit board 62 and the rod lens array 64. The light-emitting surface of the light-emitting element of the light source 63 is set as the focal surface of the rod lens array 64. In addition, the rod lens array 64 is arranged along the axial direction (main scanning direction) from Py to Po of the photoreceptor.

[0118] (Light emission device 65)

[0119] exist Figure 3In this example, the light source unit 63 has 20 light-emitting chips C1 to C20 on the circuit board 62 as a laminated substrate. Moreover, the light-emitting chips C1 to C20 are configured to be arranged in two rows in an alternating manner in the X direction, which is the main scanning direction.

[0120] In Example 1, the total number of light-emitting chips Ck (C1 to C20) used is 20, but it is not limited to this and can be appropriately changed according to design and specifications.

[0121] The light emitting device 65 includes a signal generation circuit 110 for driving the light source unit 63. The signal generation circuit 110 is, for example, composed of an integrated circuit (IC). Alternatively, the light emitting device 65 may not include the signal generation circuit 110. In this case, the signal generation circuit 110 is located outside the light emitting device 65 and supplies control signals, etc., to the light-emitting chips C1 to C20 via cables or the like. Here, we will assume that the light emitting device 65 includes the signal generation circuit 110 for explanation.

[0122] Figure 4 This is an explanatory diagram of the structure of the light-emitting chip in Example 1.

[0123] Figure 5 This is an explanatory diagram of the structure of the signal generation circuit and the wiring (line) structure on the circuit board in Embodiment 1.

[0124] exist Figure 4 In this example, the light-emitting chip Ck is composed of a semiconductor stack disposed on a semiconductor substrate 80 with a rectangular surface shape. On the surface of the substrate 80, a plurality of light-emitting elements (in Embodiment 1, light-emitting thyristors L1, L2, L3, etc.) are arranged in an alternating manner along a long side.

[0125] In Embodiment 1, the light-emitting thyristors L1 to L20 have: a plurality of first light-emitting portions (first light-emitting thyristors) L1, L3, L5...L19, which are arranged at a certain interval P along a main scanning direction that is a predetermined first direction; and a plurality of second light-emitting portions (second light-emitting thyristors) L2, L4, L6...L20, which are arranged at a certain interval P along the main scanning direction. The second light-emitting thyristors L2, L4...L20, which are light-emitting portions in this embodiment, are arranged at positions offset from the first light-emitting thyristors L1, L3...L19 relative to a sub-scanning direction (an example of a second direction) that intersects the main scanning direction, and are arranged at positions offset by P / 2 relative to the first light-emitting thyristors L1, L3...L19 along the main scanning direction.

[0126] In the following text, let n be a natural number. Sometimes the first light-emitting thyristors L1, L3...L19 are denoted as "first light-emitting thyristor L2n-1", and the second light-emitting thyristors L2, L4...L20 are denoted as "second light-emitting thyristor L2n".

[0127] Furthermore, in Example 1, a configuration consisting of two rows of light-emitting thyristors L1 to L20 is illustrated, but it can also consist of three or more rows. Additionally, the number of light-emitting thyristors is not limited to 20 and can be freely varied according to design, specifications, etc.

[0128] exist Figure 4 , Figure 5 In this substrate 80, the light-emitting chip Ck has multiple terminals (φ1 terminal, φ2 terminal, Vg terminal, VI terminal, φWa terminal, φWb terminal, and φR terminal) serving as pads for acquiring various control signals at both ends along the long side of the substrate 80 surface. Furthermore, these terminals are arranged in the order of φWa terminal, φ1 terminal, VI terminal, and Vg terminal from one end of the substrate 80, and in the order of φR terminal, φWb terminal, and φ2 terminal from the other end of the substrate 80. The light-emitting portion 102 is disposed between the Vg terminal and the φ2 terminal. Additionally, a back electrode (not shown) serving as a Vsub terminal is provided on the back side of the substrate 80.

[0129] Furthermore, as described in, for example, Japanese Patent Application Publication No. 2020-049720, various control signals and terminals are known in the past, so detailed descriptions are omitted.

[0130] (Light-emitting chip Ck)

[0131] Figure 6 This is an example of an equivalent circuit diagram illustrating the structure of the light-emitting chip in Embodiment 1.

[0132] exist Figure 6 In the following description, the components are labeled using widely used circuit symbols. Furthermore, the positions of each terminal (φ1 terminal, φ2 terminal, φWa terminal, φR terminal, VI terminal, and Vg terminal) are... Figure 4 The difference is shown at the left end of the figure for ease of explanation. Furthermore, the Vsub terminal is provided as a back electrode on the back side of the substrate 80.

[0133] Here, in relation to the signal generation circuit 110, taking the light-emitting chip C1 as an example, the light-emitting chip Ck will be described, and the description of other light-emitting chips C2 to C20 will be omitted.

[0134] The light-emitting chip Ck includes light-emitting thyristors L1, L2, L3, etc., transfer thyristors T1, T2, T3, etc., coupling transistors Qt1, Qt2, Qt3, etc., set thyristors W1, W2, W3, etc., and setting transistors Qw1, Qw2, Qw3, etc.

[0135] Furthermore, without distinguishing between light-emitting thyristors L1, L2, L3, etc., they are all referred to as light-emitting thyristor L. The same applies to the others. The transfer thyristor T, coupling transistor Qt, set thyristor W, and set transistor Qw are arranged along the path of light-emitting thyristor L. Figure 4 Arrangement.

[0136] The transfer thyristor T is an example of a transfer element, and the set thyristor W is an example of a set element. In Embodiment 1, the light-emitting device consists of a light-emitting thyristor L, resistors RI1 and RI2, and resistor Rn.

[0137] The light-emitting chip Ck has thyristors RT1 and RT2 for extinguishing. Without distinguishing between thyristors RT1 and RT2, they are all referred to as thyristor RT.

[0138] Furthermore, the LED chip Ck has multiple resistors. Moreover, the resistors are not distinguished by numbers like those used for LED thyristors L1, L2, L3, etc.

[0139] The light-emitting thyristor L, the transfer thyristor T, the set thyristor W, and the extinguishing thyristor RT are thyristors with a pnpn structure. As shown in the transfer thyristor T1, the transfer thyristor T is a four-terminal device with an anode, a first gate Gtf, a second gate Gts, and a cathode. Furthermore, in... Figure 6 In the figure, the first gate Gtf is denoted as (Gtf). The others are the same. Additionally, other equivalent components are not labeled with reference numerals. The others are the same.

[0140] As shown in the set thyristor W1, the set thyristor W is a four-terminal device having an anode, a first gate Gwf, a second gate Gws, and a cathode. On the other hand, as shown in the light-emitting thyristor L1, the light-emitting thyristor L is a three-terminal device having an anode, a gate Gl, and a cathode. Similarly, as shown in the extinguishing thyristor RT1, the extinguishing thyristor RT is a three-terminal device having an anode, a gate Gr, and a cathode.

[0141] The coupled transistor Qt and the set transistor Qw are PNP bipolar transistors. As shown in coupled transistor Qt1, odd-numbered coupled transistor Qts are four-terminal devices with an emitter E, a base B, a first collector Cf, and a second collector Cs. As shown in coupled transistor Qt2, even-numbered coupled transistor Qts are three-terminal devices with an emitter E, a base B, and a collector C. That is, odd-numbered coupled transistor Qts are multi-collector transistors, and even-numbered coupled transistor Qts are single-collector transistors.

[0142] Furthermore, as shown in the setting transistor Qw1, the setting transistor Qw is a three-terminal device with an emitter E, a base B, and a collector C. Therefore, the setting transistor Qw is also a single-collector transistor.

[0143] Furthermore, the light-emitting chip Ck has multiple wirings that connect the aforementioned components.

[0144] The light-emitting chip Ck has a power line 71 connected to the Vg terminal. The power supply voltage Vg is supplied from the power supply voltage supply unit 170 to the power line 71 via the Vg terminal connected by the power line 200b.

[0145] The light-emitting chip Ck includes transmission signal lines 72a and 72b, which are connected to terminals φ1 and φ2 respectively via resistors R1 and R2. Transmission signals φ1 and φ2 are transmitted from the transmission signal generation unit 120 to terminals φ1 and φ2 respectively via transmission signal lines 201 and 202. Additionally, the light-emitting chip Ck includes setting signal lines 73a and 73b connected to terminals φWa and φWb respectively via resistors R3 and R4. Setting signals φWa1 and φWb1 are transmitted from the setting signal generation unit 130 to terminals φWa and φWb respectively via setting signal lines 203a-1 and 203b-1.

[0146] Resistors R1, R2, R3, and R4 are current-limiting resistors used to maintain voltage.

[0147] Furthermore, the light-emitting chip Ck has lighting signal lines 75a and 75b connected to the VI terminal via resistors RI1 and RI2, respectively. A lighting voltage VI is supplied to the VI terminal from the lighting voltage supply unit 150. Lighting signal lines 75a and 75b are examples of lighting voltage lines, and lighting voltage VI is an example of a lighting voltage.

[0148] Furthermore, the light-emitting chip Ck has extinguishing signal lines 76a and 76b connected to the φR terminal via resistors Rr1 and Rr2, respectively. The extinguishing signal generation unit 140 sends an extinguishing signal φR to the φR terminal via the extinguishing signal line 204.

[0149] Furthermore, the light-emitting chip Ck has a Vsub terminal on the back side of the substrate 80. A reference voltage Vsub is supplied to the Vsub terminal from the reference voltage supply section 160 via a power line 200a. The Vsub terminal is an example of a reference voltage line.

[0150] Figure 7A , Figure 7B , Figure 7C , Figure 7D This is an explanatory diagram of the light-emitting chip in Example 1. Figure 7A It is a top view. Figure 7B yes Figure 7A Sectional view along line VIIB-VIIB, Figure 7C yes Figure 7A Sectional view along line VIIC-VIIC, Figure 7D yes Figure 7A Sectional view along line VIID-VIID.

[0151] exist Figure 7A , Figure 7B , Figure 7C , Figure 7D In the light-emitting chip Ck of Embodiment 1, a first wiring 301 extending from the collector (C) of the first setting transistors (examples of the first control element) Qw1, Qw3, etc., is connected to the first light-emitting thyristors L1, L3...L19, respectively. A second wiring 302 extending from the collector (C) of the second setting transistors (examples of the second control element) Qw2, Qw4, etc., is connected to the second light-emitting thyristors L2, L4...L20, respectively.

[0152] exist Figure 7B In this structure, a first wiring 301 is stacked and formed on the substrate 80. Furthermore, an insulating layer 303 is stacked on the surface side of the first wiring 301. That is, the first wiring 301 is a structure that supplies current to the inner side of the stack.

[0153] exist Figure 7C In this configuration, a portion of the second wiring 302 is composed of a metallic material stacked on the surface side of the insulating layer 303, and supplies current to the second light-emitting thyristor L2n. The insulating layer 303 is stacked on the substrate 80. Figure 7D As shown, in Embodiment 1, the second wiring 302 is disposed on the surface side in such a way that it passes between the first light-emitting thyristors L2n-1 and covers a portion of the outer edge of the first light-emitting thyristors L2n-1, and is disposed on the surface side with an insulating layer 303 sandwiched between them so as not to be energized with the electrode portion 304 of the outer edge of the first light-emitting thyristors L2n-1.

[0154] Figure 8A , Figure 8B This is an explanatory diagram of the circuit in Example 1. Figure 8A This is an explanatory diagram of the stack-up structure of the first wiring section. Figure 8B This is an explanatory diagram of the stacked structure of the second wiring section. Figure 8A This illustrates the case where metal wiring is stacked on the gate semiconductor. Figure 8B This illustrates the case where metal wiring is stacked on an insulating film.

[0155] exist Figure 8AIn this design, transistor Qw is a so-called pnp transistor structure. On or above the surface of conductive substrate 80, there are stacked p-type semiconductor 211 that functions as emitter, n-type semiconductor 212 that functions as base, and p-type semiconductor (first layer) 213 that functions as collector. On the surface of p-type semiconductor 213, there are first metal wirings 301 and 302.

[0156] On the other hand, Figure 8B In the second wiring 302, in the portion passing between the first light-emitting thyristor L2n-1, the insulating layer 303 is stacked on the surface of the substrate 80, and the second wiring 302 is stacked on the surface of the insulating layer (second layer) 303.

[0157] (Description of the manufacturing method of the circuit in Example 1)

[0158] Figure 9A , Figure 9B This is an explanatory diagram of the manufacturing method of a laminated substrate. Figure 9A This is an illustration of the state of a substrate without a mesa before etching. Figure 9B yes Figure 9A An explanatory diagram of the substrate after etching.

[0159] A conductor multilayer film (not shown) with a pnpn structure is formed on the surface side of a semiconductor substrate 02. Active components such as transistors and thyristors are formed by processing the semiconductor multilayer film using etching or the like.

[0160] exist Figure 9A , Figure 9B In this example, as a known circuit board manufacturing method, when manufacturing a multilayer substrate 01, after an insulating film layer 03 and a wiring layer 04 are formed on or above the surface of a semiconductor substrate 02, a resist pattern 07 is formed according to the shape of the wiring 06. When etching (wet etching) is performed using an etchant, as shown... Figure 9B As shown, this is the state where part of the wiring 06 remains. At this time, since the liquid etchant erodes the wiring layer 04 to a position inside the end of the resist pattern 07, the resist pattern 07 was previously designed to be one size larger than the shape of the target wiring 06, taking into account the erosion.

[0161] Figure 10A , Figure 10B , Figure 10C This is an explanatory diagram of a multilayer substrate with a mesa shape. Figure 10A It is a top view. Figure 10B From Figure 10A The diagram viewed from the XB direction of the arrow. Figure 10C From Figure 10A The diagram is viewed from the direction of arrow XC.

[0162] exist Figure 10A , Figure 10B , Figure 10C In the case of the light-emitting chip Ck in Example 1, conventionally, when forming the light-emitting thyristor L portion, a mesa 251 with a roughly trapezoidal cross-section is formed, and insulating film layers, metal film layers, etc., are stacked. When the mesa 251 is formed using wet etching, due to crystal orientation, it is generally formed as follows: Figure 10B The tabletop shown is a frontal tabletop (first inclined surface) 252 whose top is not eaves-shaped, and an inverted tabletop (second inclined surface) 253 with an eaves-shaped portion 253a at the top. Furthermore, the tabletop surface, which is usually trapezoidal in cross-section, is not limited to a geometrically precise trapezoidal cross-section, but also includes trapezoidal shapes such as tabletops formed by differential erosion.

[0163] Figure 11A , Figure 11B This is an illustration of the etching process for the inverted platform section. Figure 11A This is an illustrative diagram showing the state of the face after the membrane has been separated. Figure 11B From Figure 11A An illustration of the state after etching.

[0164] exist Figure 11A In cases where a wiring layer (metal film) 254 is formed on the surface of the inverted platform 253 using a sputtering method or similar method, sometimes metal particles do not sufficiently reach and adhere to the portion below the overhang 253a (the protruding portion), resulting in a thinner or coarser wiring layer 254, thus forming voids 06a. When a resist pattern (resist layer) 256 is formed in this state and etching is performed, sometimes the thinner portions are etched more than expected by the etching solution, or the voids become larger due to etching by the etching solution that enters them. Therefore, in certain situations, such as... Figure 11B As shown, wiring section 06 may be broken in the middle.

[0165] Figure 12A , Figure 12B , Figure 12C This is an illustration of the situation where the inverted platform surface contacts a portion of the target shape. Figure 12A This is an illustration of the state before etching. Figure 12B This is an illustrative diagram showing the state of the wiring layer after film deposition. Figure 12C This is an illustration of the state after etching.

[0166] like Figure 12A As shown, when the line 253b of the eaves 253a of the inverted platform 253 contacts a portion of the target shape 261 of the wiring layer 254, after wet etching begins, when the portion under the eaves 253a is exposed to the etching solution, high-speed etching is performed along the voids 06a, etc. Figure 12BAs shown, sometimes a recess 254a is formed on the wiring layer 254 along the line 253b of the inverted surface 253. When further etching is performed from this state, the etchant travels along the recess 254a to the side where the resist pattern 256 was never formed (see Figure 254). Figure 12B Arrow 260) flows in easily, and etching occurs unexpectedly from the recess 254a, sometimes forming a semi-circular portion 261a of metal. When the cut portion 261a is present, it may have an adverse effect on the lifespan of the wiring, resistance value, etc.

[0167] Figure 13 This is an explanatory diagram illustrating an example of the manufacturing method of the countertop portion of Embodiment 1.

[0168] exist Figure 13 In the case of manufacturing the light-emitting chip Ck of Embodiment 1, when the target shape 261 corresponding to the wiring 301, 302 is to cover the inverted platform 253, the target shape 261 to be formed is set to have a width greater than or equal to the width of the inverted platform 253 and to cover the entire area of ​​the line 253b of the inverted platform 253.

[0169] In this condition, before etching, the two ends 253d of the mesa 253 are covered by the wiring layer 254 to prevent the etchant from penetrating from the two ends 253d. Therefore, etching on the mesa 253 portion is suppressed from exceeding expectations. Thus, breakage of the target shape 261 can be suppressed.

[0170] Figure 14A , Figure 14B , Figure 14C This is an explanatory diagram of another example of the manufacturing method of the countertop portion of Embodiment 1. Figure 14A This is an illustrative diagram showing the state of the wiring layer after film deposition. Figure 14B This is an illustrative diagram showing the state after etching of the wiring layer film thickness. Figure 14C This is an illustration of the state after etching is complete.

[0171] like Figure 13 As shown, when the target shape 261 corresponding to wiring 301, 302 cannot cover the entire countertop line 253b, as Figure 14A , Figure 14B , Figure 14C As shown, the target shape 261 is set in a manner that avoids the portion of the inverted table surface line 253b. In Figure 14A , Figure 14B , Figure 14C Specifically, the target shape 261 is configured such that the length La from the outer edge 271 of the resist layer 256 to the end 253d of the inverted surface line 253b (the distance between the wiring and the eaves-like portion) is shorter than the film thickness Lb of the wiring layer 254 (La < Lb). In this configuration, when from... Figure 14A When etching begins in the state described above, the wiring layer 254 is etched in both the direction along the inverted facet line 253b and the thickness direction. Furthermore, when etching an amount Lb of the wiring layer 254 from the outer edge 271 of the resist layer 256, the wiring layer 254 has already been etched beyond the inverted facet 253 in the direction along the inverted facet line 253b, and thereafter, etching continues unaffected by the eaves 253a. Therefore, when... Figure 14A , Figure 14B , Figure 14C When the target shape 261 is set in that way, the breakage of the target shape 261 can be suppressed.

[0172] Figure 15A , Figure 15B It is the ratio of wiring to the face of the platform. Figure 14A , Figure 14B , Figure 14C A diagram illustrating the state when the state is closer to the state shown. Figure 15A This is an illustrative diagram showing the state before etching when one side of the wiring has an inverted face. Figure 15B This is an illustration of the etched state when one side of the wiring has an inverted face.

[0173] exist Figure 15A , Figure 15B In the case where the target shape 261 corresponding to the wiring 301, 302 is set in a way that avoids the portion of the inverted platform line 253b, when the target shape 261 cannot be set as La < Lb, in Embodiment 1, the width Wa of the target shape 261 is set such that the width Wa of the target shape 261 is sufficiently greater than the film thickness Lb. Figure 15A In the case where a chamfered surface line 253b exists on one side of the target shape 261 in the width direction, as an example, the width Wa of the target shape 261 is set to be twice the film thickness Lb. Furthermore, the width Wa is preferably more than twice, and ideally more than three times. Thus, even if a cut portion 261a is generated during etching, by making the width Wa twice the film thickness Lb, the target shape 261 can be easily and fully connected without breaking.

[0174] Figure 16A , Figure 16B It is the ratio of wiring to the face of the platform. Figure 14A , Figure 14B , Figure 14C A diagram illustrating the state when the state is closer to the state shown. Figure 16A This is an illustrative diagram showing the state before etching when the wiring has inverted facets on both sides. Figure 16B This is an illustration of the etched state when there are inverted facets on both sides of the wiring.

[0175] exist Figure 16A , Figure 16B In Embodiment 1, where La < Lb and there are inverted mesa lines 253b on both sides of the target shape 261 in the width direction corresponding to wirings 301 and 302, as an example, the width Wa of the target shape 261 is set to be three times the film thickness Lb. Furthermore, the width Wa is preferably three times or more, and ideally four times or more. Thus, even if the cut portion 261a is generated on both sides in the width direction during etching, by making the width Wa three times the film thickness Lb, the target shape 261 can be easily and sufficiently connected without breaking.

[0176] Figure 17 This diagram illustrates a situation where wiring cannot avoid the inverted face and cannot cover the entire area of ​​the inverted face with wiring.

[0177] exist Figure 17 In the case where the target shape 261 corresponding to wiring 301, 302 cannot avoid the inverted platform 253 and cannot cover the entire area of ​​the inverted platform line 253b, in Embodiment 1, the target shape 261 is arranged such that it overlaps with the inverted platform 253 and two or more positive platform lines 252b. Here, the positive platform line refers to the upper edge of the first slope 252. With this arrangement, more etching is performed in the inverted platform 253 portion than expected, but the etching in the positive platform 252 portion is as expected. Compared to the case with only the inverted platform 253, the overall etching speed is slower. Therefore, it is possible to suppress the breakage of the target shape 261.

[0178] Figure 18A , Figure 18B This diagram illustrates a situation where wiring cannot avoid the inverted platform surface and cannot cover the entire area of ​​the inverted platform surface, resulting in an edge that is inclined relative to the inverted platform surface line. Figure 18A This is an illustration of the state before the inclined end edge is formed. Figure 18B This is an illustration of the state in which the inclined end edge has been formed.

[0179] exist Figure 18A , Figure 18B In the case where the target shape 261 corresponding to the wiring 301, 302 cannot avoid the inverted platform 253 and cannot cover the entire area of ​​the inverted platform line 253b with the target shape 261, in Embodiment 1, an inclined end edge (the end edge of the top surface extending in the inclined direction) 281 is formed on the platform surface 251, which is inclined relative to both the inverted platform line 253b and the line 252b of the main platform 252. By forming the inclined end edge 281 in this way, the inclined end edge 281 becomes a part that, like the main platform 252, does not have an eave 253a. (Comparison) Figure 18A and Figure 18B It can be seen that by forming the inclined end edge 281, in Figure 18BIn the middle, the length of the inverted platform line 253b is shortened to suppress the adverse effects on the etching at the eaves 253a.

[0180] In addition, Figure 18B The illustration shows a case where the angle of inclination of the inclined end edge 281 relative to the chamfered surface line 253b is 45°, but it is not limited to this. The inventors' experiments have confirmed that within an angle range of 10° to 80°, the adverse effects on the eaves 253a are reduced. Therefore, it is not limited to this. Figure 18B The shape of the inclined edge 281 shown is chamfered, but it can also be set as a curved edge or an edge with a gradually changing inclination angle.

[0181] (Modified Example)

[0182] The embodiments of the present invention have been described in detail above, but the present invention is not limited to the above embodiments and various modifications can be made within the scope of the spirit of the present invention as set forth in the claims. The following are examples of modifications of the present invention (H01) to (H08).

[0183] (H01) In the above embodiments, a printer U is shown as an example of an image forming apparatus, but it is not limited to this. For example, it can also be composed of a copier, a fax machine, or a multifunction printer having multiple or all of their functions. In addition, it is not limited to an electrophotographic image forming apparatus, but can also be applied to any image forming apparatus of inkjet, thermal transfer, etc.

[0184] (H02) In the above embodiments, a light-emitting thyristor structure was exemplified as the light-emitting part, but it is not limited to this. For example, the light-emitting part may also be a light-emitting diode. In addition, wiring can also be applied to a structure that supplies current to each light-emitting part, such as the structure described in Japanese Patent Application Publication No. 2020-123603. Furthermore, it is not limited to the structure of an LED head made of light-emitting diodes or the like; for example, it can also be applied to a structure of a multilayer substrate having a vertical cavity surface-emitting laser (VCSEL).

[0185] (H03) In the above embodiments, a case with multiple first light-emitting thyristors L2n-1 and multiple second light-emitting thyristors L2n is described, but it is not limited to this. It can also be applied to a case where there is one first light-emitting thyristor L2n-1 and one second light-emitting thyristor L2n. In addition, the modified examples can be appropriately combined with each other. For example, by combining modified examples (H02) and modified examples (H03), the light-emitting part can be composed of VCSELs, wherein there is one first VCSEL and one second VCSEL.

[0186] (H04) In the above embodiment, a structure in which a wiring 301, 302 is disposed in a light-emitting thyristor L is illustrated, but it is not limited thereto. For example, it can also be applied to the following structure: a wiring branch is connected to multiple light-emitting thyristors, and the lighting and extinguishing of multiple light-emitting thyristors can be controlled simultaneously through a single wiring.

[0187] (H05) In the above embodiments, the first control element (first coupling transistor) and the second control element (second coupling transistor) are shown to be different, but this is not a limitation. For example, it can also be applied to a structure in which the first control element and the second control element are the same, and the same signal is sent to the first wiring and the second wiring.

[0188] Figure 19 This is an explanatory diagram illustrating another example of the configuration of the light-emitting part in this invention.

[0189] (H06) As shown in Example 1, a structure in which the light-emitting thyristors L are arranged in an alternating manner is illustrated, but it is not limited to this. For example, it can also be applied to the following structures: Figure 19 As shown, when the light-emitting thyristors L are densely arranged in a planar shape instead of in an array, the second wiring 302' from the outer peripheral first light-emitting thyristor L1' and the inner second light-emitting thyristor L2' to the second light-emitting thyristor L2' is the same as in Embodiment 1, and is arranged to pass through the first light-emitting thyristor L1'.

[0190] (H07) In the above embodiments, the application of the light-emitting element substrate is exemplified in the case of a printhead used in an image forming apparatus, but it is not limited to this. It can also be applied to light-emitting element arrays used in light transmission. In this case, it can be combined with a light transmission path so that light from the first light-emitting unit and light from the second light-emitting unit are on the same light transmission path, or on different light transmission paths. Furthermore, it can also be applied to a light-emitting substrate used in light measurement. Light-receiving elements that receive light emitted from the first and second light-emitting units can be formed on the same substrate. Additionally, lenses can be added to allow light emitted from the first and second light-emitting units to pass through before reaching an object.

[0191] (H08) In the embodiments, a structure is illustrated in which the light-emitting part is applied to each light-emitting thyristor and the present invention is applied to the wiring of the light-emitting thyristor, but it is not limited thereto. For example, it can also be applied to the wiring of a group of light-emitting elements composed of multiple light-emitting elements, that is, the wiring that connects multiple light-emitting elements together.

Claims

1. A method for manufacturing a multilayer substrate, wherein for the multilayer substrate, an etching solution is used to remove a portion of a wiring layer not covered by a resist layer to form wiring, wherein the multilayer substrate has: The base layer has a trapezoidal platform surface, the platform surface having a first inclined surface extending downward and outward from the top surface and a second inclined surface having an eave-like portion extending outward from the top surface; A wiring layer is formed on the upper surface of the base layer; as well as A resist layer is formed on the upper surface of the wiring layer and has a shape corresponding to the shape of the wiring. Specifically, the wiring is positioned away from the eaves-like portion, and the distance between the wiring and the eaves-like portion is shorter than the thickness of the wiring film. The width of the wiring is set to be more than twice the thickness of the wiring film.

2. The method for manufacturing a laminated substrate according to claim 1, wherein, When there are second slopes on both sides of the wiring width direction, the wiring width is set to more than three times the wiring film thickness.

3. A method for manufacturing a multilayer substrate, wherein for the multilayer substrate, an etching solution is used to remove a portion of the wiring layer not covered by the resist layer to form wiring, wherein the multilayer substrate has: The base layer has a trapezoidal platform surface, the platform surface having a first inclined surface extending downward and outward from the top surface and a second inclined surface having an eave-like portion extending outward from the top surface; A wiring layer is formed on the upper surface of the base layer; as well as A resist layer is formed on the upper surface of the wiring layer and has a shape corresponding to the shape of the wiring. The wiring is generated in such a way that it overlaps with two or more of the upper edges of the eave-shaped portion and the first inclined surface. The first inclined plane extends in a direction orthogonal to the second inclined plane. The top edge of the table surface is formed as follows, wherein the top edge of the table surface extends in a direction inclined relative to the extension direction of the second inclined surface and its orthogonal direction.

4. A laminated substrate comprising: A base layer having a trapezoidal platform, the platform having a first inclined surface extending downward and outward from the top surface and a second inclined surface having an eave-like portion extending outward from the top surface; and The wiring, formed on the upper surface of the substrate, is created by removing the portion of the wiring layer not covered by the resist layer using an etching solution after the resist layer is formed. The resist layer is formed on the upper surface of the wiring layer and has a shape corresponding to the shape of the wiring. in, The wiring is positioned away from the eaves-like portion, and the distance between the wiring and the eaves-like portion is shorter than the thickness of the wiring film, with a wiring width that is more than twice the thickness of the wiring film.

5. A laminated substrate comprising: A base layer having a trapezoidal platform, the platform having a first inclined surface extending downward and outward from the top surface and a second inclined surface having an eave-like portion extending outward from the top surface; and The wiring, formed on the upper surface of the substrate, is created by removing the portion of the wiring layer not covered by the resist layer using an etching solution after the resist layer is formed. The resist layer is formed on the upper surface of the wiring layer and has a shape corresponding to the shape of the wiring. in, The wiring is generated to overlap with two or more of the upper edges of the eaves-like portion and the first slope. The first inclined plane extends in a direction orthogonal to the second inclined plane. The top surface of the table-shaped surface is formed with the following end edge, which extends in a direction inclined relative to the extension direction of the second inclined surface and its orthogonal direction.

6. A light-emitting element substrate, comprising: The laminated substrate according to claim 4 or 5, in, The laminated substrate has a light-emitting portion, and the wiring supplies current to the light-emitting portion.

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