An OLED display panel and a preparation method thereof

Abstract

Embodiments of the present application disclose an OLED display panel and a preparation method thereof. The OLED display panel comprises an array substrate, the array substrate being provided with an auxiliary electrode layer; an anode layer, the anode layer being arranged on the array substrate, the anode layer being provided with an undercut opening, and the auxiliary electrode layer being exposed in the undercut opening; a light-emitting layer, the light-emitting layer being arranged on the anode layer and being partially disconnected in the undercut opening, and covering part of the auxiliary electrode layer in the undercut opening; and a cathode layer, the cathode layer being arranged on the light-emitting layer and covering part of the auxiliary electrode layer in the undercut opening. By arranging the undercut opening in the anode, the cathode is connected with the auxiliary electrode through the undercut opening, so that the problem of IR-drop is improved.

Description

Technical Field

[0001] This invention relates to the field of display panels, and particularly to an OLED display panel and its manufacturing method. Background Technology

[0002] OLED display panel structures include a transparent anode layer, a light-emitting layer, and a metal cathode layer. To increase the transmittance of top emission, the metal cathode is relatively thin, resulting in a large sheet resistance and a significant IR drop, leading to noticeable brightness unevenness in the display panel and severely impacting the display performance of the OLED device. To improve the brightness uniformity, an auxiliary electrode can be installed, connected to the thinner metal cathode. Because the auxiliary electrode has lower resistance and a smaller IR drop, when energized, the impedance and IR drop of the cathode are reduced, thus improving brightness uniformity to some extent. A common method for connecting the auxiliary electrode and the metal cathode is to use an inverted trapezoidal isolation pillar between them. However, this isolation pillar has a large volume, affecting the aperture ratio and encapsulation, and also limits the selection of raw materials, complicates the manufacturing process, and reduces production efficiency.

[0003] In view of this, it is necessary to develop a new type of OLED display panel to solve the problem that existing technologies require the fabrication of isolation pillars to improve IR-drop, which leads to complex manufacturing processes. Summary of the Invention

[0004] The present invention provides an OLED display panel and a method for manufacturing the same, which solves the problem in the prior art that isolation pillars need to be prepared in order to improve IR-drop, resulting in a complex manufacturing process.

[0005] To address the aforementioned technical problems, embodiments of the present invention disclose the following technical solutions:

[0006] On one hand, an OLED display panel is provided, comprising an array substrate having an auxiliary electrode layer thereon; an anode layer disposed on the array substrate; the anode layer comprising, in a vertical direction: a first electrode layer disposed on the array substrate; a reflective film layer disposed on the first electrode layer; a third electrode layer disposed on the reflective film layer; a bottom-cut opening penetrating the first electrode layer, the auxiliary electrode being exposed in the bottom-cut opening; and a through-hole penetrating the reflective film layer and the third electrode layer, the bottom-cut opening communicating with the through-hole, the projection of the through-hole onto the substrate falling into the projection of the bottom-cut opening onto the substrate; the OLED display panel further comprising: a light-emitting layer disposed on the anode layer and partially disconnected in the bottom-cut opening, covering a portion of the auxiliary electrode layer in the bottom-cut opening; and a cathode layer disposed on the light-emitting layer and covering a portion of the auxiliary electrode layer in the bottom-cut opening.

[0007] In addition to one or more of the features disclosed above, or as an alternative, the array substrate includes: a substrate; a buffer layer disposed on the substrate; an active layer disposed on the buffer layer; a gate insulating layer disposed on the active layer; a gate layer disposed on the gate insulating layer; an interlayer dielectric layer disposed on the gate layer; a metal layer disposed on the interlayer dielectric layer; wherein the metal layer includes a source / drain layer and an auxiliary electrode layer disposed at intervals on the same layer, the source / drain layer being connected to the active layer; a passivation layer disposed on the auxiliary electrode and the source / drain layer; a planarization layer disposed on the passivation layer; a first via penetrating the planarization layer and the passivation layer from the side of the planarization layer away from the substrate, the source / drain layer being exposed in the first via; and a second via penetrating the planarization layer and the passivation layer from the side of the planarization layer away from the substrate, spaced apart from the first via, the auxiliary electrode layer being exposed in the second via.

[0008] In addition to one or more of the features disclosed above, or as an alternative, the anode layer includes a first anode layer and a second anode layer disposed at intervals on the same layer; the first anode layer is disposed on the planarization layer and connected to the source and drain electrodes through the first via; the second anode layer is disposed on the planarization layer and covers the sidewall of the second via, the second anode layer having the undercut opening, and the auxiliary electrode layer being exposed in the undercut opening.

[0009] In addition to one or more of the features disclosed above, or alternatively, the reflective film layer and the third electrode layer include a protrusion that projects inwardly from the sidewall of the second via.

[0010] In addition to one or more of the features disclosed above, or alternatively, the cathode layer is continuously disposed on the light-emitting layer and the protrusion.

[0011] In addition to one or more of the features disclosed above, or as an alternative, the metal layer may further include a pad layer disposed at intervals from the source / drain layer and the auxiliary electrode layer in the same layer, wherein the area of ​​the pad layer in the vertical direction is a bonding area.

[0012] On the other hand, a method for fabricating the OLED display panel of the present invention is provided. The method includes the following steps: fabricating an array substrate having an auxiliary electrode; fabricating an anode layer on the array substrate; the step of fabricating the anode layer specifically includes: fabricating a first electrode layer on the array substrate; fabricating a reflective film layer on the first electrode layer and fabricating a third electrode layer on the reflective film layer; fabricating a via hole that extends from the side of the third electrode layer away from the array substrate, through the first electrode layer and the third electrode layer, and to the side of the auxiliary electrode away from the array substrate; fabricating a bottom-cut opening on the first electrode layer, the bottom-cut opening communicating with the via hole, the auxiliary electrode being exposed in the bottom-cut opening; wherein the projection of the via hole on the array substrate falls into the projection of the bottom-cut opening on the array substrate; after the step of fabricating the anode layer, the method further includes: fabricating a light-emitting layer on the anode layer, partially disconnected in the bottom-cut opening, the light-emitting layer covering a portion of the auxiliary electrode layer in the bottom-cut opening; and fabricating a cathode layer on the light-emitting layer, covering a portion of the auxiliary electrode layer in the bottom-cut opening.

[0013] In addition to one or more of the features disclosed above, or as an alternative, the anode layer is etched using a wet etching process to form the via, and the first electrode is etched using oxalic acid to form the undercut opening.

[0014] In addition to one or more of the features disclosed above, or as an alternative, the material of the first electrode layer is an indium zinc oxide thin film; the material of the reflective film layer is one or more of molybdenum, titanium, silver alloy, aluminum alloy or molybdenum titanium alloy; and the material of the third electrode layer is an indium tin oxide thin film.

[0015] In addition to one or more of the features disclosed above, or as an alternative, the specific steps for preparing the light-emitting layer and the cathode layer include: controlling the evaporation angle of the evaporation source to a first set angle, evaporating the light-emitting layer on the anode layer and partially disconnecting it in the undercut opening, with a gap between the light-emitting layer on the auxiliary electrode layer and the light-emitting layer on the anode layer; adjusting the evaporation angle of the evaporation source to a second set angle, evaporating the cathode layer on the light-emitting layer and covering a portion of the auxiliary electrode layer in the undercut opening, with the cathode layer in contact with the exposed auxiliary electrode layer.

[0016] One of the above technical solutions has the following advantages or beneficial effects: by setting an undercut opening in the anode, the cathode is connected to the auxiliary electrode through the undercut opening, thereby improving the IR-drop problem; and the anode includes a first electrode layer, a reflective film layer and a third electrode layer. The first electrode layer is made of indium zinc oxide thin film, the reflective film layer is made of metal, and the third electrode layer is made of indium tin oxide thin film. The undercut opening is formed by etching the first electrode layer with oxalic acid, which is simple to manufacture and can improve production efficiency. Attached Figure Description

[0017] The technical solution and other beneficial effects of the present invention will become apparent from the following detailed description of specific embodiments of the invention, in conjunction with the accompanying drawings.

[0018] Figure 1 This is a schematic diagram of the structure of an OLED display panel provided in an embodiment of the present invention;

[0019] Figure 2 A flowchart illustrating a method for fabricating an OLED display panel according to an embodiment of the present invention;

[0020] Figure 3 This is a schematic diagram of step 1 of the OLED display panel fabrication method provided in an embodiment of the present invention;

[0021] Figure 4 This is a schematic diagram of step 2 of the OLED display panel fabrication method provided in an embodiment of the present invention;

[0022] Figure 5 This is a schematic diagram of step 21 of the OLED display panel fabrication method provided in an embodiment of the present invention;

[0023] Figure 6 This is a schematic diagram of step 3 of the method for preparing an OLED display panel according to an embodiment of the present invention;

[0024] Figure 7 This is a schematic diagram of step 4 of the OLED display panel fabrication method provided in an embodiment of the present invention;

[0025] Figure 8 This is a schematic diagram of step 5 of the OLED display panel fabrication method provided in an embodiment of the present invention.

[0026] Figure label:

[0027] OLED display panel - 100; Array substrate - 10;

[0028] Anode layer -20; Light-emitting layer -30;

[0029] Support layer -40; Cathode layer -50;

[0030] Substrate-110; Light-shielding layer-121;

[0031] Buffer layer -122; Active layer -130;

[0032] Gate insulating layer -140; Gate layer -150;

[0033] Interlayer dielectric layer - 160; Metal layer - 170;

[0034] Passivation layer - 180; Planarization layer - 190;

[0035] Contact hole-161; First via-hole-191;

[0036] Second through hole 192; Protrusion -230;

[0037] Source / drain layer - 171; Auxiliary electrode layer - 172;

[0038] First anode layer -210; Second anode layer -220;

[0039] First electrode layer - 221; Reflective film layer - 222;

[0040] Third electrode layer -223; Through hole -224;

[0041] Bottom cut opening -225; Pad layer -173. Detailed Implementation

[0042] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. In the description of the present invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the accompanying drawings and are only for the convenience of describing the present invention and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention.

[0043] Please see Figure 1 , Figure 1 This is a schematic diagram of the structure of an OLED display panel 100 provided in this embodiment. The OLED display panel 100 includes an array substrate 10, an anode layer 20, a light-emitting layer 30, a pixel definition layer 40, and a cathode layer 50.

[0044] The array substrate 10 includes a substrate 110, a light-shielding layer 121, a buffer layer 122, an active layer 130, a gate insulating layer 140, a gate layer 150, an interlayer dielectric layer 160, a metal layer 170, a passivation layer 180, a planarization layer 190, a contact hole 161, a first via 191, and a second via 192. The substrate 110 can be made of polymer resins such as polyethersulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate (PC), or cellulose acetate propionate (CAP). The light-shielding layer 121 is disposed on the substrate 110, and the buffer layer 122 is disposed on the light-shielding layer 121.

[0045] An active layer 130 is disposed on a buffer layer 122; a gate insulating layer 140 is disposed on the active layer 130, the gate insulating layer 140 comprising an inorganic layer such as silicon oxide or silicon nitride, and may comprise a single layer or multiple layers. A gate layer 150 is disposed on the gate insulating layer 140; an interlayer dielectric layer 160 is disposed on the gate layer 150, the interlayer dielectric layer 160 may comprise an inorganic material or an organic material. The inorganic material may comprise at least one selected from silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide, cerium oxide, and silicon oxynitride. The organic material may comprise at least one selected from acrylic resins, methacrylic resins, polyisoprene, vinyl resins, epoxy resins, urethane resins, cellulose resins, and perylene resins.

[0046] A metal layer 170 is disposed on the interlayer dielectric layer 160. The metal layer 170 includes a source / drain layer 171, an auxiliary electrode layer 172, and a pad layer 173 disposed at intervals within the same layer. The source / drain layer 171 and the auxiliary electrode layer 172 are made of the same material; the material of the source / drain layer 171 and the auxiliary electrode layer 172 can be any one or more of silver, molybdenum, aluminum, and copper. The area of ​​the pad layer 173 in the vertical direction is a bonding area.

[0047] Contact hole 161 extends from the side of interlayer dielectric layer 160 away from substrate 110 to the surface of active layer 130 away from substrate 110, and source / drain layer 171 is connected to active layer 130 through contact hole 161; passivation layer 180 is disposed on auxiliary electrode and source / drain layer 171.

[0048] A planarization layer 190 is disposed on the passivation layer 180. The planarization layer 190 may include organic materials such as acrylic, polyimide (PI), or benzocyclobutene (BCB), and the first planarization layer 190 has a planarization function. A first via 191 penetrates the planarization layer 190 and the passivation layer 180 from the side of the planarization layer 190 away from the substrate 110, and the source / drain layer 171 is exposed in the first via 191. A second via 192 penetrates the planarization layer 190 and the passivation layer 180 from the side of the planarization layer 190 away from the substrate 110, and the auxiliary electrode layer 172 is exposed in the second via 192.

[0049] The anode layer 20 includes a first anode layer 210 and a second anode layer 220 disposed on the same layer at intervals. The first anode layer 210 is disposed on the planarization layer 190 and in a first via 191, and is connected to the source and drain electrodes through the first via 191. The second anode layer 220 is disposed on the planarization layer and in a second via 192, and is connected to the auxiliary electrode layer 172 through the second via 192.

[0050] The first anode layer 210 includes a first electrode layer 221, a reflective film layer 222, and a third electrode layer 223 stacked together.

[0051] The second anode layer 220 includes a first electrode layer 221, a reflective film layer 222, and a third electrode layer 223 stacked together, as well as a through-hole 224 and a bottom-cut opening 225. The first electrode layer 221 is disposed on the planarization layer 190 and covers the sidewall of the second through-hole 192. The bottom-cut opening 225 penetrates the first electrode layer 221, and the auxiliary electrode layer 172 is exposed in the bottom-cut opening 225. The reflective film layer 222 is disposed on the first electrode layer 221, and the third electrode layer 223 is disposed on the reflective film layer 222. The through-hole 224 penetrates the reflective film layer 222 and the third electrode layer 223. The bottom-cut opening 225 communicates with the through-hole 224, and the projection of the through-hole 224 on the substrate 110 falls into the projection of the bottom-cut opening 225 on the substrate 110. The reflective film layer 222 and the third electrode layer 223 include protrusions 230 protruding inward from the sidewall of the second through-hole 192.

[0052] The first electrode layer 221 is made of indium zinc oxide thin film; the reflective film layer 222 is made of one or more of molybdenum, titanium, silver alloy, aluminum alloy or molybdenum titanium alloy; the third electrode layer 223 is made of indium tin oxide thin film.

[0053] A pixel definition layer 40 is disposed on the planarization layer 190 and the anode layer 20. A light-emitting layer 30 is disposed on the pixel definition layer 40 and the anode layer 20, but partially interrupted within the undercut opening 225, and covers a portion of the auxiliary electrode layer 172 within the undercut opening 225. A gap exists between the light-emitting layer 30 on the auxiliary electrode layer 172 and the light-emitting layer 30 on the anode layer 20. Due to the presence of the undercut opening, the light-emitting layer is vapor-deposited and interrupted at the undercut opening.

[0054] Specifically, the light-emitting layer 30 includes a hole injection layer, a hole transport layer, an organic light-emitting layer, an electron injection layer, and an electron transport layer stacked sequentially, wherein the organic light-emitting layer includes at least a red light-emitting layer, a green light-emitting layer, and a blue light-emitting layer.

[0055] The cathode layer 50 is continuously disposed on the light-emitting layer 30 and the protrusion 230, and covers a portion of the auxiliary electrode layer 172 in the undercut opening 225. The cathode layer 50 overlaps with the auxiliary electrode layer 172 through the undercut opening 225, so that the cathode layer 50 and the auxiliary electrode together form a parallel structure, thereby reducing the cathode resistance and improving the current voltage drop of the OLED display panel 100, which is beneficial to improving the brightness uniformity of the OLED display panel 100.

[0056] Due to the presence of the undercut opening, the subsequent light-emitting layer 30 is interrupted at the undercut opening 225, which avoids the continuity of the light-emitting layer 30. This results in the light-emitting layer 30 not covering the part of the auxiliary electrode exposed by the gap, and thus the auxiliary electrode layer 172 is reserved to overlap with the cathode layer 50. This allows the cathode layer 50 to cover the part of the auxiliary electrode layer 172 that is not covered by the light-emitting layer 30, thereby achieving the overlap between the cathode layer 50 and the auxiliary electrode layer 172.

[0057] In this embodiment of the invention, the thickness of the auxiliary electrode layer 172 is greater than the thickness of the cathode layer 50, meaning the cross-sectional area of ​​the auxiliary electrode layer 172 is greater than the cross-sectional area of ​​the cathode layer 50. Since the resistance of a metal is negatively correlated with its cross-sectional area, the resistance of the auxiliary electrode layer 172 is less than the resistance of the cathode layer 50. Furthermore, because the resistance of the parallel structure formed by the two metals is less than the resistance of any single metal, the resistance of the parallel structure formed by the cathode layer 50 and the auxiliary electrode layer 172 is less than the resistance of the auxiliary electrode layer 172. This significantly reduces the cathode resistance of the OLED display panel 100 and improves the current-voltage drop effect of the OLED display panel 100.

[0058] This invention also provides a preparation method for preparing the OLED display panel 100 involved in this invention. Please refer to [link to relevant documentation]. Figure 2 , Figure 2 This is a flowchart of a method for fabricating an OLED display panel 100, which includes steps 1-4.

[0059] Step 1: Prepare an array substrate 10, which has an auxiliary electrode layer 172.

[0060] Please see Figure 3 , Figure 3 This is a schematic diagram of the structure in step 1 of the preparation method.

[0061] Specifically, it includes the following steps:

[0062] A substrate 110 is provided, and the material of the substrate 110 can be a polymer resin, such as polyethersulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate (PC), or cellulose acetate propionate (CAP).

[0063] A light-shielding layer 121 is prepared on the substrate 110, and a buffer layer 122 is prepared on the light-shielding layer 121.

[0064] An active layer 130 is prepared on a buffer layer 122, and a gate insulating layer 140 is prepared on the active layer 130. The gate insulating layer 140 includes an inorganic layer such as silicon oxide or silicon nitride, and may include a single layer or multiple layers.

[0065] A gate layer 150 is fabricated on a gate insulating layer 140, and an interlayer dielectric layer 160 is fabricated on the gate layer 150. The interlayer dielectric layer 160 may comprise an inorganic material or an organic material. The inorganic material may comprise at least one selected from silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide, cerium oxide, and silicon oxynitride. The organic material may comprise at least one selected from acrylic resins, methacrylic resins, polyisoprene, vinyl resins, epoxy resins, urethane resins, cellulose resins, and perylene resins.

[0066] A metal layer 170 is fabricated on the interlayer dielectric layer 160. The metal layer 170 includes a source / drain layer 171, an auxiliary electrode layer 172, and a pad layer 173 disposed at intervals within the same layer. The source / drain layer 171 and the auxiliary electrode layer 172 are made of the same material; the material of the source / drain layer 171 and the auxiliary electrode layer 172 can be any one or more of silver, molybdenum, aluminum, and copper. The area of ​​the pad layer 173 in the vertical direction is a bonding region.

[0067] Contact hole 161 is prepared, which extends from the side of interlayer dielectric layer 160 away from substrate 110 to the surface of active layer 130 away from substrate 110. Source and drain layers 171 are connected to active layer 130 through contact hole 161.

[0068] A passivation layer 180 is prepared on the auxiliary electrode and the source / drain layer 171, and a planarization layer 190 is prepared on the passivation layer 180. The planarization layer 190 may include organic materials such as acrylic, polyimide (PI) or benzocyclobutene (BCB), and the first planarization layer 190 has a planarization function.

[0069] A first via 191 and a second via 192 are fabricated. The first via 191 extends through the planarization layer 190 and the passivation layer 180 from the side of the planarization layer 190 away from the substrate 110, exposing the source / drain layer 171 in the first via 191. The second via 192 extends through the planarization layer 190 and the passivation layer 180 from the side of the planarization layer 190 away from the substrate 110, exposing the auxiliary electrode layer 172 in the second via 192.

[0070] Step 2: Prepare the anode layer 20 on the array substrate 10.

[0071] Please see Figure 4 , Figure 4 This is a schematic diagram of the structure in step 2 of the preparation method.

[0072] Specifically, it includes the following steps:

[0073] A first anode layer 210 is prepared on the planarization layer 190 and in the first via 191. A second anode layer 220 is prepared on the planarization layer 190 and in the second via 192. The first anode layer 210 and the second anode layer 220 are disposed on the same layer at intervals. The first anode layer 210 is connected to the source and drain electrodes through the first via 191, and the second anode layer 220 is connected to the auxiliary electrode layer 172 through the second via 192.

[0074] The specific steps for preparing the first anode layer 210 include:

[0075] A first electrode layer 221 is prepared on the planarization layer 190 and covers the sidewall of the first via 191. The material of the first electrode layer 221 is an indium zinc oxide (IZO) thin film.

[0076] A reflective film layer 222 is prepared on the first electrode layer 221. The material of the reflective film layer 222 is one or more of molybdenum, titanium, silver alloy, aluminum alloy or molybdenum-titanium alloy.

[0077] A third electrode layer 223 is prepared on the reflective film layer 222, and the material of the third electrode layer 223 is an indium tin oxide (ITO) thin film.

[0078] The specific steps for preparing the second anode layer 220 include:

[0079] A first electrode layer 221 is prepared on the planarization layer 190 and covers the sidewall of the second via 192. The material of the first electrode layer 221 is an indium zinc oxide (IZO) thin film.

[0080] A reflective film layer 222 is prepared on the first electrode layer 221. The material of the reflective film layer 222 is one or more of molybdenum, titanium, silver alloy, aluminum alloy or molybdenum-titanium alloy.

[0081] A third electrode layer 223 is prepared on the reflective film layer 222, and the material of the third electrode layer 223 is an indium tin oxide (ITO) thin film.

[0082] A via 224 is fabricated by etching the second anode layer 220 using a wet etching process. The via 224 penetrates the second anode layer 220 and extends from the third electrode layer 223 and the side away from the substrate 110 through the first electrode layer 221, the reflective film layer 222, and the third electrode layer 223, reaching the surface of the auxiliary electrode layer 172 away from the substrate 110. The auxiliary electrode layer 172 is exposed in the via 224.

[0083] It also includes step 21: preparing the pixel definition layer 40 on the first anode layer 210 and the second anode layer 220.

[0084] Please see Figure 5 , Figure 5 This is a schematic diagram of the structure in step 21 of the preparation method.

[0085] After the pixel definition layer 40 is prepared, the OLED display panel 100 is baked at high temperature.

[0086] Step 3: Prepare an undercut opening 225 on the anode layer 20, and expose the auxiliary electrode layer 172 in the undercut opening 225.

[0087] Please see Figure 6 , Figure 6 This is a schematic diagram of the structure in step 3 of the preparation method.

[0088] The first electrode layer 221 is etched with oxalic acid to form an undercut opening 225, which communicates with a through-hole 224. The projection of the through-hole 224 onto the substrate 110 falls within the projection of the undercut opening 225 onto the substrate 110. The reflective film layer 222 and the third electrode layer 223 include protrusions 230 that protrude inward from the sidewall of the second via 192.

[0089] Indium tin oxide (ITO) films will crystallize and transform into crystals after being baked at high temperatures, making them difficult to etch. Oxalic acid has limited etching performance and cannot etch the crystalline state of ITO. Indium zinc oxide (IZO) films are amorphous materials due to their material properties. High temperatures cannot cause their atoms to rearrange and form crystals. Therefore, oxalic acid can etch the first electrode layer 221.

[0090] Step 4: Prepare the light-emitting layer 30 on the pixel definition layer 40 and the anode layer 20, and partially disconnect it in the undercut opening 225.

[0091] Please see Figure 7 , Figure 7 This is a schematic diagram of the structure in step 4 of the preparation method.

[0092] The evaporation angle of the evaporation source is controlled to a first set angle. The evaporation light-emitting layer 30 is partially disconnected on the pixel definition layer 40 and the anode layer 20 and in the bottom cut opening 225, and covers part of the auxiliary electrode layer 172 in the bottom cut opening 225. There is a gap between the light-emitting layer 30 on the auxiliary electrode layer 172 and the light-emitting layer 30 on the anode layer 20.

[0093] Due to the presence of the undercut opening, the light-emitting layer 30 is interrupted at the undercut opening 225, which avoids the continuity of the light-emitting layer 30. This results in the light-emitting layer 30 not covering the part of the auxiliary electrode layer 172 exposed by the gap, and thus the auxiliary electrode layer 172 is reserved to overlap with the cathode layer 50.

[0094] Step 5: Prepare a cathode layer 50 on the light-emitting layer 30 and the protrusion 230, and cover part of the auxiliary electrode layer 17 in the undercut opening 225.

[0095] Please see Figure 8 , Figure 8 This is a schematic diagram of the structure in step 5 of the preparation method.

[0096] The evaporation angle of the evaporation source is adjusted to the second set angle, and the evaporation cathode layer 50 is continuously disposed on the light-emitting layer 30 and the protrusion 230, and covers part of the auxiliary electrode layer 172 in the bottom cut opening 225, so that the cathode layer 50 and the auxiliary electrode layer 172 overlap.

[0097] In other embodiments, the cathode layer 50 can also be prepared by sputtering.

[0098] Utilizing the principle that crystals are not etched by oxalic acid while amorphous materials are easily etched by oxalic acid, the material used in the first electrode layer 221 cannot become crystal after being baked at high temperature, while the material used in the third electrode layer 223 becomes crystal after being baked at high temperature. Oxalic acid is used to etch the first electrode layer 221 to form the undercut opening 225. The manufacturing process is simple and can improve production efficiency.

[0099] The foregoing has provided a detailed description of an OLED display panel and its preparation method according to embodiments of the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the technical solutions and core ideas of the present invention. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An OLED display panel, characterized in that, include: An array substrate having an auxiliary electrode layer; An anode layer is disposed on the array substrate; The anode layer comprises, in the vertical direction: A first electrode layer is disposed on the array substrate; A reflective film layer is disposed on the first electrode layer; A third electrode layer is disposed on the reflective film layer; A through-hole penetrates the first electrode layer, the reflective film layer, and the third electrode layer, and extends to the side of the auxiliary electrode layer away from the array substrate; The bottom cut opening penetrates the first electrode layer, the auxiliary electrode layer is exposed in the bottom cut opening, the bottom cut opening is connected to the through hole, and the projection of the through hole on the array substrate falls into the projection of the bottom cut opening on the array substrate, wherein the reflective film layer and the third electrode layer form an inwardly protruding part above the sidewall of the bottom cut opening; The OLED display panel also includes: A light-emitting layer is disposed on the anode layer and partially interrupted in the bottom cut opening, covering a portion of the auxiliary electrode layer in the bottom cut opening; A cathode layer is disposed on the light-emitting layer and covers a portion of the auxiliary electrode layer in the undercut opening. 2.The OLED display panel of claim 1, wherein, The array substrate includes: substrate; A buffer layer is disposed on the substrate; An active layer is disposed on the buffer layer; A gate insulating layer is disposed on the active layer; A gate layer is disposed on the gate insulating layer; An interlayer dielectric layer is disposed on the gate layer; A metal layer is disposed in the interlayer dielectric layer; wherein the metal layer includes a source / drain layer and an auxiliary electrode layer disposed at intervals in the same layer, and the source / drain layer is connected to the active layer; A passivation layer is disposed on the auxiliary electrode layer and the source / drain electrode layer; A planarization layer is disposed on the passivation layer; A first via extends through the planarization layer and the passivation layer from the side of the planarization layer away from the substrate, and the source and drain layers are exposed in the first via. The second via extends through the planarization layer and the passivation layer from the side of the planarization layer away from the substrate, and is spaced apart from the first via. The auxiliary electrode layer is exposed in the second via. 3.The OLED display panel of claim 2, wherein, The anode layer includes a first anode layer and a second anode layer disposed at intervals in the same layer; The first anode layer is disposed on the planarization layer and is connected to the source and drain layers through the first via; The second anode layer is disposed on the planar layer and covers the sidewall of the second via. The second anode layer has the undercut opening, and the auxiliary electrode layer is exposed in the undercut opening. 4.The OLED display panel of claim 1, wherein, The cathode layer is continuously disposed on the light-emitting layer and the protrusion. 5.The OLED display panel of claim 2, wherein, The metal layer also includes a pad layer that is spaced apart from the source / drain layer and the auxiliary electrode layer in the same layer, and the area of ​​the pad layer in the vertical direction is a bonding area.

6. A manufacturing method for manufacturing the OLED display panel according to claim 1, characterized in that, The preparation method includes the following steps: An array substrate is fabricated, wherein an auxiliary electrode layer is present on the array substrate; An anode layer is fabricated on the array substrate; The steps for preparing the anode layer specifically include: A first electrode layer is fabricated on the array substrate; A reflective film is prepared on the first electrode layer; A third electrode layer is prepared on the reflective film layer; A through-hole is formed, which extends from the side of the third electrode layer away from the array substrate through the first electrode layer, the reflective film layer and the third electrode layer, and extends to the side of the auxiliary electrode layer away from the array substrate; An undercut opening is formed on the first electrode layer, the undercut opening penetrates the first electrode layer, the undercut opening communicates with the through hole, and the auxiliary electrode layer is exposed in the undercut opening; Wherein, the through hole is projected onto the array substrate and falls into the projection of the undercut opening onto the array substrate, and the reflective film layer and the third electrode layer form an inwardly protruding part above the sidewall of the undercut opening; The step of preparing the anode layer further includes: A light-emitting layer is fabricated on the anode layer and partially disconnected in the undercut opening, the light-emitting layer covering a portion of the auxiliary electrode layer in the undercut opening; A cathode layer is prepared on the light-emitting layer and covers a portion of the auxiliary electrode layer in the undercut opening.

7. The preparation method according to claim 6, characterized in that, The first electrode layer is made of indium zinc oxide thin film; the reflective film layer is made of one or more of molybdenum, titanium, silver alloy, aluminum alloy or molybdenum-titanium alloy; and the third electrode layer is made of indium tin oxide thin film.

8. The preparation method according to claim 7, characterized in that, The anode layer is etched using a wet etching process to form the through hole, and the first electrode layer is etched using oxalic acid to form the undercut opening.

9. The preparation method according to claim 6, characterized in that, The specific steps for preparing the light-emitting layer and the cathode layer include: The evaporation angle of the evaporation source is controlled to a first set angle, and the luminescent layer is partially separated on the anode layer and in the bottom cut opening. There is a gap between the luminescent layer on the auxiliary electrode layer and the luminescent layer on the anode layer. The evaporation angle of the evaporation source is adjusted to a second set angle, and a cathode layer is deposited on the light-emitting layer and covers part of the auxiliary electrode layer in the bottom cut opening. The cathode layer is in contact with the exposed auxiliary electrode layer.

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