Input voltage overvoltage and undervoltage protection module, power supply system and chip

Abstract

The application provides an input voltage overvoltage and undervoltage protection module, a power supply system and a chip, comprising: a first comparison unit for comparing a bus voltage detection voltage with an overvoltage protection reference voltage and generating an overvoltage protection signal; a second comparison unit for comparing the detection voltage with an undervoltage protection reference voltage and generating an undervoltage detection signal; an initial state detection comparison unit for generating a first undervoltage protection signal when the undervoltage detection signal is valid in the initial stage of power supply voltage power-on; a power frequency cycle peak value detection comparison unit for generating a second undervoltage protection signal after the undervoltage detection signal is valid for a preset time; and a protection control unit for generating a protection control signal. The application has no requirement for the ripple of the bus voltage, can accurately detect the input voltage and effectively protect the power supply system, and has simple circuit, saves space and cost, has fast response speed in input overvoltage protection, has high accuracy in input undervoltage protection, and also considers the undervoltage response speed of the initial state of the system.

Description

Technical Field

[0001] This invention relates to the field of circuit design, and in particular to an input voltage overvoltage and undervoltage protection module, a power supply system, and a chip. Background Technology

[0002] The power system provides power to various electrical devices. Reducing the impact of input voltage on the power system and maintaining the stable operation of electrical devices are crucial aspects of power management.

[0003] In existing power supply systems, protection against both excessively high and low input voltages is typically achieved by real-time monitoring of the rectified bus voltage. This method is only suitable for power systems with low bus voltage ripple, requiring a sufficiently large electrolytic capacitor at the rectified input and a relatively low system load to reduce ripple voltage across the capacitor. However, large electrolytic capacitors not only increase cost but also occupy space in external circuitry; furthermore, the stringent system load requirements limit the application scope of this monitoring method.

[0004] Therefore, how to provide overvoltage and undervoltage protection for power systems while saving space and cost and expanding the scope of application has become one of the problems that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide an input voltage overvoltage and undervoltage protection module, power supply system and chip to solve the problems of high cost, large external space occupation and small applicability in the prior art.

[0006] To achieve the above and other related objectives, the present invention provides an input voltage overvoltage and undervoltage protection module, the input voltage overvoltage and undervoltage protection module comprising at least:

[0007] The first comparison unit receives the detected voltage of the bus voltage and the overvoltage protection reference voltage, and generates an overvoltage protection signal based on the comparison result between the detected voltage and the overvoltage protection reference voltage.

[0008] The second comparison unit receives the detection voltage and the undervoltage protection reference voltage, and generates an undervoltage detection signal based on the comparison result between the detection voltage and the undervoltage protection reference voltage.

[0009] An initial state detection comparison unit is connected to the output terminal of the second comparison unit and receives the power supply voltage energization signal. In the initial stage of power supply voltage energization, when the undervoltage detection signal is valid, a first undervoltage protection signal is generated.

[0010] A power frequency cycle peak detection and comparison unit is connected to the output terminal of the second comparison unit and receives the power supply voltage energization signal. After the power supply voltage is energized, a second undervoltage protection signal is generated when the effective time of the undervoltage detection signal reaches a preset time.

[0011] The protection control unit is connected to the output terminals of the first comparison unit, the initial state detection comparison unit, and the power frequency cycle peak detection comparison unit, and generates a protection control signal based on the overvoltage protection signal, the first undervoltage protection signal, and the second undervoltage protection signal.

[0012] Optionally, the non-inverting input of the first comparison unit receives the detected voltage, the inverting input receives the overvoltage protection reference voltage, and outputs the overvoltage protection signal.

[0013] Alternatively, the inverting input of the second comparison unit is connected to the detection voltage, the non-inverting input receives the undervoltage protection reference voltage, and the undervoltage detection signal is output.

[0014] Optionally, the protection signal generation unit includes an OR gate and a protection control signal generation circuit;

[0015] The first input terminal of the OR gate is connected to the output terminal of the first comparison unit, the second input terminal is connected to the output terminal of the initial state detection comparison unit, and the third input terminal is connected to the output terminal of the power frequency cycle peak detection comparison unit. The OR gate performs an OR operation on the overvoltage protection signal, the first undervoltage protection signal, and the second undervoltage protection signal.

[0016] The protection control signal generation circuit is connected to the output terminal of the OR gate, and generates the protection control signal based on the output signal of the OR gate.

[0017] Optionally, the input voltage overvoltage and undervoltage protection module further includes a logic control unit and a drive unit; the logic control unit is connected to the output terminal of the protection control unit and generates a switch control signal based on the protection control signal; the drive unit is connected to the output terminal of the logic control unit.

[0018] Alternatively, the initial state detection and comparison unit includes a current source, a first switch, a second switch, a first capacitor, an inverter, and an AND gate;

[0019] One end of the current source is connected to the operating voltage, and the other end is connected to the upper plate of the first capacitor via the first switch; the lower plate of the first capacitor is grounded; the control terminal of the first switch receives the power supply voltage signal.

[0020] The second switch is connected in parallel across the first capacitor, and the control terminal receives the inverted signal of the power supply voltage signal.

[0021] The input terminal of the inverter is connected to the upper plate of the first capacitor, and the output terminal is connected to the first input terminal of the AND gate; the second input terminal of the AND gate receives the undervoltage detection signal and outputs the first undervoltage protection signal.

[0022] Alternatively, the power frequency cycle peak detection and comparison unit includes an oscillator and a counter;

[0023] The input terminal of the oscillator receives the power supply voltage signal and generates an oscillation signal based on the power supply voltage signal.

[0024] The pulse input terminal of the counter is connected to the output terminal of the oscillator, and the reset terminal is connected to the output terminal of the second comparison unit, outputting the second undervoltage protection signal.

[0025] To achieve the above and other related objectives, the present invention provides a power supply system, the power supply system comprising at least:

[0026] The voltage input module receives AC input voltage and converts it into bus voltage;

[0027] The sampling module is connected to the output terminal of the voltage input module to sample the bus voltage and obtain the detection voltage;

[0028] The power supply voltage detection module detects the power supply voltage and outputs a power supply voltage signal.

[0029] The aforementioned input voltage overvoltage and undervoltage protection module is connected to the output terminal of the sampling module and generates a switching control signal based on the detected voltage and the power supply voltage energized signal.

[0030] It also includes a power switch transistor, and the control terminal receives the switch control signal and performs overvoltage and undervoltage protection on the input voltage based on the switch control signal.

[0031] Optionally, the voltage input module includes a rectifier unit and an electrolytic capacitor, wherein the electrolytic capacitor is connected in parallel to the output terminal of the rectifier unit.

[0032] Alternatively, the sampling module includes a first sampling resistor and a second sampling resistor; the first end of the first sampling resistor is connected to the output end of the voltage input module, the second end is connected to the first end of the second sampling resistor and outputs the detection voltage; the second end of the second sampling resistor is grounded.

[0033] To achieve the above and other related objectives, the present invention provides a chip, the chip comprising at least the above-mentioned input voltage overvoltage and undervoltage protection module.

[0034] As described above, the input voltage overvoltage and undervoltage protection module, power supply system, and chip of the present invention have the following beneficial effects:

[0035] 1. The input voltage overvoltage and undervoltage protection module, power supply system and chip of the present invention have no requirements for the ripple of the bus voltage. Regardless of whether there is a capacitor after input rectification and regardless of the load, it can achieve the purpose of accurately detecting the input voltage and realize effective protection of the power supply system.

[0036] 2. The input voltage overvoltage and undervoltage protection module, power supply system and chip of the present invention have simple circuits, which can effectively save space and cost.

[0037] 3. The input voltage overvoltage and undervoltage protection module, power supply system and chip of the present invention do not detect the peak value of the power frequency cycle to improve the response speed during input overvoltage protection; during input undervoltage protection, two situations are dealt with. In the initial state of the system, the peak value of the power frequency cycle is not detected to improve the response speed. After the system is working stably, the peak value of the power frequency cycle is detected to achieve the purpose of input undervoltage protection more accurately and prevent false protection. Attached Figure Description

[0038] Figure 1 The diagram shown is a structural schematic of the input voltage overvoltage and undervoltage protection module of the present invention.

[0039] Figure 2 The diagram shown is a structural schematic of the power supply system of the present invention.

[0040] Figure 3 The diagram shows the structure of a power supply system.

[0041] Component designation explanation

[0042] 1-Input voltage overvoltage and undervoltage protection module; 11-First comparison unit; 12-Second comparison unit; 13-Initial state detection comparison unit; 14-Power frequency cycle peak detection comparison unit; 141-Oscillator; 142-Counter; 15-Protection control unit; 151-Protection control signal generation circuit; 16-Logic control unit; 17-Drive unit; 2-Voltage input module; 3-Sampling module; 4-Voltage input module; 5-Peak hold module; 6-Sampling module; 7-First comparator; 8-Second comparator; 9-Logic control module. Detailed Implementation

[0043] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0044] Please see Figures 1-3 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex. Example

[0045] like Figure 1 As shown, this embodiment provides an input voltage overvoltage and undervoltage protection module 1, which includes:

[0046] The system comprises a first comparison unit 11, a second comparison unit 12, an initial state detection comparison unit 13, a power frequency cycle peak detection comparison unit 14, and a protection control unit 15.

[0047] like Figure 1 As shown, the first comparison unit 11 receives the bus voltage detection voltage DET and the overvoltage protection reference voltage OVP, and generates an overvoltage protection signal based on the comparison result between the detection voltage DET and the overvoltage protection reference voltage OVP.

[0048] Specifically, in this embodiment, the non-inverting input terminal of the first comparison unit 11 receives the detection voltage DET, the inverting input terminal receives the overvoltage protection reference voltage OVP, and outputs the overvoltage protection signal. When the detection voltage DET is greater than the overvoltage protection reference voltage OVP, the overvoltage protection signal is high (valid); when the detection voltage DET is less than the overvoltage protection reference voltage OVP, the overvoltage protection signal is low (invalid).

[0049] like Figure 1 As shown, the second comparison unit 12 receives the detection voltage DET and the undervoltage protection reference voltage UVP, and generates an undervoltage detection signal based on the comparison result between the detection voltage DET and the undervoltage protection reference voltage UVP.

[0050] Specifically, in this embodiment, the inverting input terminal of the second comparison unit 12 is connected to the detection voltage DET, the non-inverting input terminal receives the undervoltage protection reference voltage UVP, and outputs the undervoltage detection signal. When the detection voltage DET is greater than the undervoltage protection reference voltage UVP, the undervoltage detection signal is low (invalid); when the detection voltage DET is less than the undervoltage protection reference voltage UVP, the undervoltage detection signal is high (valid).

[0051] like Figure 1 As shown, the initial state detection comparison unit 13 is connected to the output terminal of the second comparison unit 12 and receives the power supply voltage energization signal PG. In the initial stage of the power supply voltage VDD being energized, when the undervoltage detection signal is valid, a first undervoltage protection signal is generated.

[0052] Specifically, in this embodiment, the initial state detection and comparison unit 13 includes a current source I1, a first switch SW1, a second switch SW2, a first capacitor C1, an inverter U1, and an AND gate U2. One end of the current source I1 is connected to the operating voltage (in this embodiment, the operating voltage is the power supply voltage VDD; however, in actual use, the operating voltage can be set as needed and is not limited to this embodiment), and the other end is connected to the upper plate of the first capacitor C1 via the first switch SW1. The lower plate of the first capacitor C1 is grounded. The control terminal of the first switch SW1 receives the power supply voltage energization signal PG. The second switch SW1 is connected in parallel across the first capacitor C1, and its control terminal receives the inverted signal of the power supply voltage energization signal PG (obtained through the inverter U3). The input terminal of the inverter U1 is connected to the upper plate of the first capacitor C1, and its output terminal is connected to the first input terminal of the AND gate U2. The second input terminal of the AND gate U2 receives the undervoltage detection signal and outputs the first undervoltage protection signal.

[0053] Specifically, when the power supply voltage VDD is energized, the power supply voltage energization signal PG jumps to a high level, the first switch SW1 is turned on, and the second switch SW2 is turned off. Then, the operating voltage slowly charges the first capacitor C1 through the first current source I1 at a set rate. The voltage on the first capacitor C1 slowly rises from zero. At this time, the first input terminal of the AND gate U2 is at a high level (that is, it is in the initial stage of the power supply voltage VDD being energized, and the duration of the initial stage is determined based on the capacitance and charging speed of the first capacitor). At the same time as the first input terminal of the AND gate U2 is at a high level, if the undervoltage detection signal is at a high level (that is, undervoltage is detected), then the AND gate U2 outputs a first undervoltage protection signal at a high level (valid); if the undervoltage detection signal is at a low level (that is, undervoltage is not detected), then the AND gate U2 outputs a first undervoltage protection signal at a low level (invalid).

[0054] It should be noted that any circuit structure that can realize the initial state detection and generate the first undervoltage protection signal of the present invention is applicable to the initial state detection comparison unit of the present invention, and is not limited to this embodiment.

[0055] like Figure 1 As shown, the power frequency cycle peak detection comparison unit 14 is connected to the output terminal of the second comparison unit 12 and receives the power supply voltage energization signal PG. After the power supply voltage VDD is energized, a second undervoltage protection signal is generated when the effective time of the undervoltage detection signal reaches a preset time.

[0056] Specifically, in this embodiment, the power frequency cycle peak detection and comparison unit 14 includes an oscillator 141 and a counter 142. The input terminal of the oscillator 141 receives the power supply voltage signal PG and generates an oscillation signal (pulse signal) based on the power supply voltage signal PG. The pulse input terminal CP of the counter 142 is connected to the output terminal of the oscillator 141, and the reset terminal is connected to the output terminal of the second comparison unit 12, outputting the second undervoltage protection signal.

[0057] Specifically, when the power supply voltage VDD is energized, the power supply voltage energization signal PG jumps to a high level, the oscillator 141 starts generating an oscillation signal, which is input as a counting pulse to the counter 142. The reset terminal RSET of the counter 142 receives the undervoltage detection signal. The counter 142 counts the number of pulses of the oscillation signal. If the undervoltage detection signal is high (i.e., undervoltage is detected), the reset is invalid, the counter 142 maintains the counting state, and outputs the second undervoltage protection signal as high (valid) after the count value reaches a preset value; if the undervoltage detection signal is low (i.e., undervoltage is not detected), the reset is valid, the counter 142 stops counting and resets to zero, and outputs the second undervoltage protection signal as low (invalid).

[0058] It should be noted that any circuit structure capable of realizing the power frequency cycle peak detection and generating the second undervoltage protection signal of the present invention is applicable to the power frequency cycle peak detection comparison unit of the present invention, and is not limited to this embodiment.

[0059] It should be noted that this invention does not detect the peak value of the power frequency cycle during input overvoltage protection to improve response speed; however, it detects the peak value of the power frequency cycle during input undervoltage protection to more accurately achieve the purpose of input undervoltage protection and prevent false protection.

[0060] like Figure 1As shown, the protection control unit 15 is connected to the output terminals of the first comparison unit 11, the initial state detection comparison unit 13 and the power frequency cycle peak detection comparison unit 14, and generates a protection control signal based on the overvoltage protection signal, the first undervoltage protection signal and the second undervoltage protection signal.

[0061] Specifically, in this embodiment, the protection control unit 15 includes an OR gate U4 and a protection control signal generation circuit 151. The first input terminal of the OR gate U4 is connected to the output terminal of the first comparison unit 11, the second input terminal is connected to the output terminal of the initial state detection comparison unit 13, and the third input terminal is connected to the output terminal of the power frequency cycle peak detection comparison unit 14. It performs an OR operation on the overvoltage protection signal, the first undervoltage protection signal, and the second undervoltage protection signal. The protection control signal generation circuit 151 is connected to the output terminal of the OR gate U4 and generates the protection control signal based on the output signal of the OR gate U4.

[0062] Specifically, when any one of the overvoltage protection signal, the first undervoltage protection signal, and the second undervoltage protection signal is valid (corresponding to a high level in this embodiment), the OR gate U4 outputs a high level (valid, i.e., protection measures need to be taken). When all three signals are invalid (corresponding to a low level in this embodiment), the OR gate U4 outputs a low level (invalid, i.e., no protection measures need to be taken). The protection control signal generation circuit 151 generates the protection control signal based on the output signal of the OR gate U4, including but not limited to level conversion, delay, and other processing.

[0063] like Figure 1 As shown, in another implementation of the present invention, the input voltage overvoltage and undervoltage protection module 1 further includes a logic control unit 16, which is connected to the output terminal of the protection control unit 15 and generates a switching control signal based on the protection control signal.

[0064] Specifically, when the protection control signal is valid, the logic control unit 16 outputs a switch control signal to turn off the power switch, thereby achieving overvoltage or undervoltage protection. As an example, the logic control unit 16 also receives control signals such as over-temperature protection to jointly determine the operating state of the power switch, which will not be elaborated upon here.

[0065] It should be noted that the correspondence between the input signals and the polarity of the input terminals of the first comparison unit and the second comparison unit can be set as needed, and the effective level of each signal can also be set as needed. For example, the polarity and level can be adjusted by adding an inverter; any logical relationship that can be realized in this invention is acceptable and is not limited to this embodiment.

[0066] like Figure 1 As shown, in another implementation of the present invention, the input voltage overvoltage and undervoltage protection module 1 further includes a drive unit 17 connected to the output terminal of the logic control unit 16, and the drive unit 17 generates a drive signal GATE for the power switch based on the switch control signal.

[0067] In another implementation of the present invention, the first comparison unit 11, the second comparison unit 12, the initial state detection comparison unit 13, the power frequency cycle peak detection comparison unit 14, the protection control unit 15, the logic control unit 16 and the drive unit 17 are integrated in the same chip, thereby simplifying the peripheral circuit and reducing the cost. Example

[0068] This embodiment provides a chip, which includes the input voltage overvoltage and undervoltage protection module 1 of Embodiment 1. The pins of the chip can be set according to actual design needs, and will not be described in detail here. Example

[0069] like Figure 2 As shown, the present invention also provides a power supply system, the power supply system comprising:

[0070] Input voltage overvoltage and undervoltage protection module 1, voltage input module 2, sampling module 3, power supply voltage detection module and power switch Q1.

[0071] like Figure 2 As shown, the voltage input module 2 receives AC input voltage AC and converts it into bus voltage Vbus.

[0072] Specifically, the voltage input module 2 includes a rectifier unit DB1, which includes two sets of diodes connected in parallel. Each diode set includes two diodes connected in series. The AC input voltage AC is connected between the two diodes in each diode set via a fuse F. The parallel connection of the two diode sets outputs the bus voltage Vbus. As an example, the bus voltage Vbus is the rectified voltage after the sinusoidal voltage is rectified, which is the absolute value of the sinusoidal voltage.

[0073] Specifically, such as Figure 2 As shown, in another implementation of the present invention, the voltage input module 2 further includes an electrolytic capacitor Cin, which is connected in parallel to the output terminal of the rectifier unit DB1 to store the bus voltage Vbus and regulate the bus voltage Vbus.

[0074] It should be noted that in the power supply system of this invention, the electrolytic capacitor Cin is optional and not a necessary component. Including the electrolytic capacitor Cin can further improve the stability of the bus voltage Vbus; omitting the electrolytic capacitor Cin can significantly save costs and facilitate system miniaturization.

[0075] like Figure 2 As shown, the sampling module 3 is connected to the output terminal of the voltage input module 2 to sample the bus voltage Vbus and obtain the detection voltage DET.

[0076] Specifically, in this embodiment, the sampling module 3 includes a first sampling resistor R1 and a second sampling resistor R2. The first terminal of the first sampling resistor R1 is connected to the output terminal of the voltage input module 2, and the second terminal is connected to the first terminal of the second sampling resistor R2; the second terminal of the second sampling resistor R2 is grounded. The first sampling resistor R1 and the second sampling resistor R2 divide the bus voltage Vbus to obtain the detection voltage DET.

[0077] It should be noted that any circuit structure capable of sampling the bus voltage Vbus is applicable to the present invention and is not limited to this embodiment.

[0078] like Figure 2 As shown, the power supply voltage detection module (not shown in the figure) detects the power supply voltage VDD and outputs the power supply voltage signal PG.

[0079] Specifically, in this embodiment, the power supply voltage generation module (not shown in the figure) obtains electrical energy from the bus voltage Vbus and generates a power supply voltage VDD. The power supply voltage detection module (as an example, it is set inside the input voltage overvoltage and undervoltage protection module 1; in actual use, it can also be set outside the input voltage overvoltage and undervoltage protection module 1) detects the power supply voltage VDD. When the power supply voltage VDD is greater than a preset voltage, it is determined that the power supply voltage VDD is energized, and the power supply voltage energization signal PG (high level active in this embodiment) is output.

[0080] like Figure 2 As shown, the input voltage overvoltage and undervoltage protection module 1 is connected to the output terminal of the sampling module 3, and generates a switch control signal GATE based on the detection voltage DET and the power supply voltage PG.

[0081] Specifically, the circuit structure and working principle of the input voltage overvoltage and undervoltage protection module 1 are described in Embodiment 1, and will not be repeated here.

[0082] like Figure 2As shown, the control terminal of the power switch Q1 receives the switch control signal GATE, and performs overvoltage and undervoltage protection on the input voltage based on the switch control signal GATE.

[0083] Specifically, the power switch Q1 is connected in the path from the bus voltage Vbus to ground. The specific connection relationship is determined based on different power supply topologies (including but not limited to BUCK and BOOST structures), which will not be elaborated here. In this embodiment, the power switch Q1 is an NMOS transistor. The drain of the power switch Q1 is connected to the corresponding device according to the specific topology, the source is grounded, and the gate (control terminal) receives the switch control signal GATE. In actual use, the device type of the power switch Q1 can be set as needed and is not limited to this embodiment.

[0084] In one implementation of the present invention, the input voltage overvoltage and undervoltage protection module 1 is an integrated chip, and the voltage input module 2, the sampling module 3 and the power switch Q1 are peripheral devices of the chip, which can greatly simplify the complexity of peripheral devices and further facilitate the miniaturization of the system.

[0085] The power supply system of this invention has no requirements for bus voltage ripple. Regardless of whether there is a capacitor after input rectification or the weight of the load, it can accurately detect the input voltage and achieve effective protection of the power supply system.

[0086] Comparative Example

[0087] like Figure 3 The diagram shows a power supply system including a voltage input module 4, a peak hold module 5, a sampling module 6, a first comparator 7, a second comparator 8, a logic control module 9, and a power switch Q1. The voltage input module 4 includes a rectifier unit DB1 and an electrolytic capacitor Cin; the peak hold module 5 includes a diode D2 and a capacitor C2; and the sampling module 6 includes sampling resistors R3 and R4.

[0088] like Figure 3As shown, the voltage input module 4 converts the AC input voltage AC into a bus voltage Vbus and stabilizes the bus voltage Vbus through the electrolytic capacitor Cin. The peak hold module 5 samples the peak voltage on the electrolytic capacitor Cin, and the sampling module 6 samples the peak voltage. The first comparator 7 and the second comparator 8 generate corresponding undervoltage protection signals and overvoltage protection signals by comparing the sampled peak voltage signal with the undervoltage protection reference voltage UVP and the overvoltage protection reference voltage OVP. Then, the logic control module 9 generates a control signal to control the power switch Q1. The first comparator 7, the second comparator 8, and the logic control module 9 are integrated within the chip. This solution samples the bus voltage Vbus through the peak hold module 5 and then implements overvoltage and undervoltage protection, thereby removing the limitations on the electrolytic capacitor and load, and has a wide range of applications. However, the diode D2 and capacitor C2 in the peak hold module 5 are located outside the chip, increasing the complexity of the peripheral circuitry and hindering system miniaturization. Furthermore, since both overvoltage and undervoltage protection are based on the peak voltage, the response speed of overvoltage protection is slowed down.

[0089] In summary, this invention provides an input voltage overvoltage and undervoltage protection module, a power supply system, and a chip, comprising: a first comparison unit, receiving a detected voltage of the bus voltage and an overvoltage protection reference voltage, and generating an overvoltage protection signal based on the comparison result of the detected voltage and the overvoltage protection reference voltage; a second comparison unit, receiving the detected voltage and the undervoltage protection reference voltage, and generating an undervoltage detection signal based on the comparison result of the detected voltage and the undervoltage protection reference voltage; an initial state detection comparison unit, connected to the output terminal of the second comparison unit, receiving a power supply voltage energization signal, and generating a first undervoltage protection signal when the undervoltage detection signal is valid in the initial stage of power supply voltage energization; a power frequency cycle peak detection comparison unit, connected to the output terminal of the second comparison unit, receiving the power supply voltage energization signal, and generating a second undervoltage protection signal after the undervoltage detection signal has been valid for a preset time after the power supply voltage has been energized; and a protection control unit, connected to the output terminals of the first comparison unit, the initial state detection comparison unit, and the power frequency cycle peak detection comparison unit, and generating a protection control signal based on the overvoltage protection signal, the first undervoltage protection signal, and the second undervoltage protection signal. A logic control unit, connected to the output of the protection control unit, generates a switching control signal based on the protection control signal. The input voltage overvoltage and undervoltage protection module, power supply system, and chip of this invention have no requirements regarding bus voltage ripple. Regardless of whether there is a capacitor after input rectification or the load weight, it can accurately detect the input voltage, achieving effective protection of the power supply system. Furthermore, the circuit is simple, effectively saving space and cost. During input overvoltage protection, the peak value of the power frequency cycle is not detected to improve response speed; during input undervoltage protection, the peak value of the power frequency cycle is detected to more accurately achieve the purpose of input undervoltage protection, preventing false protection, while also considering the undervoltage response speed in the initial state of the system. Therefore, this invention effectively overcomes various shortcomings of the prior art and has high industrial application value.

[0090] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. An input voltage overvoltage and undervoltage protection module, characterized in that, The input voltage overvoltage and undervoltage protection module includes at least: The first comparison unit receives the detected voltage of the bus voltage and the overvoltage protection reference voltage, and generates an overvoltage protection signal based on the comparison result between the detected voltage and the overvoltage protection reference voltage. The second comparison unit receives the detection voltage and the undervoltage protection reference voltage, and generates an undervoltage detection signal based on the comparison result between the detection voltage and the undervoltage protection reference voltage. An initial state detection comparison unit is connected to the output terminal of the second comparison unit and receives the power supply voltage energization signal. In the initial stage of power supply voltage energization, when the undervoltage detection signal is valid, a first undervoltage protection signal is generated. A power frequency cycle peak detection and comparison unit is connected to the output terminal of the second comparison unit and receives the power supply voltage signal. After the power supply voltage is energized, a second undervoltage protection signal is generated when the effective time of the undervoltage detection signal reaches a preset time. The power frequency cycle peak detection and comparison unit includes an oscillator and a counter. The input terminal of the oscillator receives the power supply voltage signal and generates an oscillation signal based on the power supply voltage signal. The pulse input terminal of the counter is connected to the output terminal of the oscillator, and the reset terminal is connected to the output terminal of the second comparison unit to output the second undervoltage protection signal. The protection control unit is connected to the output terminals of the first comparison unit, the initial state detection comparison unit, and the power frequency cycle peak detection comparison unit. When the overvoltage protection signal, the first undervoltage protection signal, or the second undervoltage protection signal is valid, a protection control signal is generated.

2. The input voltage overvoltage and undervoltage protection module according to claim 1, characterized in that: The non-inverting input of the first comparison unit receives the detected voltage, the inverting input receives the overvoltage protection reference voltage, and outputs the overvoltage protection signal.

3. The input voltage overvoltage and undervoltage protection module according to claim 1, characterized in that: The inverting input of the second comparison unit is connected to the detection voltage, the non-inverting input receives the undervoltage protection reference voltage, and the undervoltage detection signal is output.

4. The input voltage overvoltage and undervoltage protection module according to claim 1, characterized in that: The protection signal generation unit includes an OR gate and a protection control signal generation circuit; The first input terminal of the OR gate is connected to the output terminal of the first comparison unit, the second input terminal is connected to the output terminal of the initial state detection comparison unit, and the third input terminal is connected to the output terminal of the power frequency cycle peak detection comparison unit. The OR gate performs an OR operation on the overvoltage protection signal, the first undervoltage protection signal, and the second undervoltage protection signal. The protection control signal generation circuit is connected to the output terminal of the OR gate, and generates the protection control signal based on the output signal of the OR gate.

5. The input voltage overvoltage and undervoltage protection module according to claim 1, characterized in that: The input voltage overvoltage and undervoltage protection module also includes a logic control unit and a drive unit; the logic control unit is connected to the output terminal of the protection control unit and generates a switch control signal based on the protection control signal; the drive unit is connected to the output terminal of the logic control unit.

6. The input voltage overvoltage and undervoltage protection module according to any one of claims 1-5, characterized in that: The initial state detection and comparison unit includes a current source, a first switch, a second switch, a first capacitor, an inverter, and an AND gate; One end of the current source is connected to the operating voltage, and the other end is connected to the upper plate of the first capacitor via the first switch; the lower plate of the first capacitor is grounded; the control terminal of the first switch receives the power supply voltage signal. The second switch is connected in parallel across the first capacitor, and the control terminal receives the inverted signal of the power supply voltage signal. The input terminal of the inverter is connected to the upper plate of the first capacitor, and the output terminal is connected to the first input terminal of the AND gate; the second input terminal of the AND gate receives the undervoltage detection signal and outputs the first undervoltage protection signal.

7. A power supply system, characterized in that, The power supply system includes at least: The voltage input module receives AC input voltage and converts it into bus voltage; The sampling module is connected to the output terminal of the voltage input module to sample the bus voltage and obtain the detection voltage; The power supply voltage detection module detects the power supply voltage and outputs a power supply voltage signal. The input voltage overvoltage and undervoltage protection module as described in any one of claims 1-6 is connected to the output terminal of the sampling module and generates a switch control signal based on the detected voltage and the power supply voltage energized signal. It also includes a power switch transistor, and the control terminal receives the switch control signal and performs overvoltage and undervoltage protection on the input voltage based on the switch control signal.

8. The power supply system according to claim 7, characterized in that: The voltage input module includes a rectifier unit and an electrolytic capacitor, with the electrolytic capacitor connected in parallel to the output terminal of the rectifier unit.

9. The power supply system according to claim 8, characterized in that: The sampling module includes a first sampling resistor and a second sampling resistor; the first end of the first sampling resistor is connected to the output end of the voltage input module, the second end is connected to the first end of the second sampling resistor and outputs the detection voltage; the second end of the second sampling resistor is grounded.

10. A chip, characterized in that, The chip includes at least one of the following: an input voltage overvoltage and undervoltage protection module as described in any one of claims 1-6.

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